Antifuse array structure and memory

Abstract

The embodiment of the present application relates to the field of semiconductor circuit design, in particular to a kind of anti-fuse array structure and memory, comprising: a plurality of anti-fuse integrated structure, in bit line extension direction and word line extension direction arrangement into anti-fuse matrix, bit line extension direction and word line extension direction perpendicular to each other;Each anti-fuse integrated structure is connected with two programming wires and two word lines;In the extension direction of word line, each anti-fuse integrated structure and adjacent anti-fuse integrated structure are connected with same programming wire and word line;In the extension direction of bit line, each anti-fuse integrated structure and adjacent anti-fuse integrated structure are connected on one of programming wire.By providing a new layout mode of anti-fuse array, to realize the same capacity of storage array only needs to occupy smaller layout area, thereby increasing the spacing between anti-fuse memory cells on the basis of original layout area, guarantee the electrical isolation effect of electrical element between anti-fuse memory cells.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit design, and in particular to an antifuse array structure and a memory. Background Technology

[0002] Semiconductor devices are essential for many modern applications. Among semiconductor devices, memory devices, used to store data, play a crucial role. With technological advancements, the capacity of memory devices continues to increase; in other words, the density of memory arrays arranged on substrates is increasing.

[0003] For antifuse memory, as the density of the memory array increases, the spacing between antifuse memory cells decreases, making it difficult to guarantee the electrical isolation effect of electrical components between antifuse memory cells.

[0004] Therefore, there is an urgent need to improve the layout of antifuse array structures to ensure the electrical isolation between electrical components in antifuse memory cells. Summary of the Invention

[0005] This application provides an antifuse array structure and a memory, and provides a new layout method for the antifuse array, so that the memory array of the same capacity only needs to occupy a smaller layout area, thereby increasing the spacing between antifuse memory cells on the basis of the original layout area, and ensuring the electrical isolation effect of electrical components between antifuse memory cells.

[0006] This application provides an antifuse array structure, including: multiple antifuse integrated structures arranged in an antifuse matrix in the bit line extension direction and the word line extension direction, wherein the bit line extension direction and the word line extension direction are perpendicular to each other; each antifuse integrated structure is connected to two programming wires and two word lines; in the word line extension direction, each antifuse integrated structure and its adjacent antifuse integrated structure are connected to the same programming wire and word line; in the bit line extension direction, each antifuse integrated structure and its adjacent antifuse integrated structure are connected to one of the programming wires.

[0007] Each antifuse integrated structure is connected to two programming wires and two word lines. That is, each antifuse integrated structure includes two antifuse memory cells and two switching units. Each antifuse memory cell is connected to a programming wire, and each switching unit is controlled by a word line. As those skilled in the art will know, in an antifuse array, the extension direction of the programming wires is the same as the extension direction of the word lines, i.e., the extension direction of the programming wires is perpendicular to the extension direction of the bit lines. In the bit line extension direction, each antifuse integrated structure shares a programming wire with its adjacent antifuse integrated structure. That is, the same programming wire is used to control one antifuse memory cell in one of two adjacent antifuse integrated structures connected on the same bit line. The two antifuse memory cells belong to two adjacent antifuse integrated structures, thereby reducing the layout length of the antifuse memory array in the bit line extension direction. Based on the original layout area and the same capacity of the memory array, the spacing between the switching units and antifuse memory cells located in the same active area is increased to ensure the electrical isolation effect of the electrical components of the antifuse memory array.

[0008] In addition, multiple antifuse integrated structures connected by the same word line are arranged at equal intervals. That is, in the extension direction of the word line, the spacing between adjacent antifuse integrated structures is equal, avoiding the possibility of adjacent antifuse integrated structures being too close together, which would compromise the overall electrical isolation effect of the antifuse memory array.

[0009] In addition, multiple antifuse integrated structures connected by the same bit line are arranged at equal intervals. That is, in the direction of bit line extension, the spacing between adjacent antifuse integrated structures is equal, avoiding the possibility of adjacent antifuse integrated structures being too close together, which would compromise the overall electrical isolation effect of the antifuse memory array.

[0010] In addition, each antifuse integrated structure includes: a first antifuse storage MOS transistor, a first switching transistor, a second switching transistor, and a second antifuse storage MOS transistor; the gate of the first antifuse storage MOS transistor is connected to a first programming wire; the gate of the first switching transistor is connected to a first word line, one end of its source or drain is connected to the first antifuse storage MOS transistor, and the other end is connected to a bit line; the gate of the second switching transistor is connected to a second word line, one end of its source or drain is connected to the second antifuse storage MOS transistor, and the other end is connected to a bit line; the gate of the second antifuse storage MOS transistor is connected to a second programming wire.

[0011] In addition, in the bit line extension direction, the gate of the second antifuse storage MOS transistor in each antifuse integrated structure is connected to the same programming wire as the gate of the first antifuse storage MOS transistor in the adjacent antifuse integrated structure.

[0012] In addition, the antifuse integrated structure includes: an active region, and a first doped region, a second doped region, a third doped region, a fourth doped region, and a fifth doped region located in the active region; the first doped region is the unused terminal of the first antifuse storage MOS transistor, the second doped region is the common terminal of the first antifuse storage MOS transistor and the first switching transistor, the third doped region is the common terminal of the first switching transistor and the second switching transistor, the fourth doped region is the common terminal of the second switching transistor and the second antifuse storage MOS transistor, and the fifth doped region is the unused terminal of the second antifuse storage MOS transistor; an insulating layer covers the active region, and bit lines are disposed on the insulating layer and electrically connected to the third doped region.

[0013] In addition, in the word line extension direction, the widths of the active regions where the first switching transistor, the second switching transistor, the first antifuse storage MOS transistor, and the second antifuse storage MOS transistor are located are consistent, so as to ensure that the spacing between each active device in the antifuse matrix is ​​the same, and further ensure the electrical isolation effect of each active device in the antifuse matrix.

[0014] In addition, the insulating layer also contains conductive vias that expose the top surface of the third doped region. A conductive layer fills these vias, with one end contacting the third doped region and the other end contacting the bit line. A bit line extension layer connects the bit line and the conductive layer, ensuring the stability of the electrical contact between them and preventing conductive defects in the formed antifuse matrix.

[0015] In addition, conductive vias are located on one side of the connected bit lines, and the bit lines contact the conductive layer through bit line extension layers. Connecting the bit lines and conductive layers through the bit line extension layers ensures the stability of the electrical contact between the bit lines and the conductive layer and prevents conductive defects in the formed antifuse matrix.

[0016] In addition, the gate of the first antifuse storage MOS transistor is disposed on the top surface of the active region between the first doped region and the second doped region, the gate of the first switch transistor is disposed on the top surface of the active region between the second doped region and the third doped region, the gate of the second switch transistor is disposed on the top surface of the active region between the third doped region and the fourth doped region, and the gate of the second antifuse storage MOS transistor is disposed on the top surface of the active region between the fourth doped region and the fifth doped region.

[0017] In addition, the gate of the first antifuse storage MOS transistor is buried in the active region between the first doped region and the second doped region, the gate of the first switch transistor is buried in the active region between the second doped region and the third doped region, the gate of the second switch transistor is buried in the active region between the third doped region and the fourth doped region, and the gate of the second antifuse storage MOS transistor is buried in the active region between the fourth doped region and the fifth doped region.

[0018] Furthermore, the antifuse matrix includes multiple columns of antifuse integrated structures arranged along the word line extension direction. The bit lines connected to the first column of antifuse integrated structures are first virtual bit lines, and the bit lines connected to the last column of antifuse integrated structures are second virtual bit lines. By setting virtual bit lines at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures located at the edges of the matrix is ​​ensured to be consistent with that of the antifuse integrated structures inside the matrix, preventing defects in the edge antifuse memory cells that could lead to malfunctions.

[0019] Furthermore, the antifuse matrix includes multiple rows of antifuse integrated structures arranged along the bit line extension direction. In the first row of antifuse integrated structures, the gate of the first antifuse storage MOS transistor is connected to a first virtual programming wire, and in the last row of antifuse integrated structures, the gate of the second antifuse storage MOS transistor is connected to a second virtual programming wire. By setting virtual programming wires at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures located at the edges of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures inside the matrix, preventing defects in the edge antifuse memory cells that would prevent them from functioning properly.

[0020] Furthermore, in the first row of the antifuse integrated structure, the gate of the first switching transistor is connected to the first virtual word line, and in the last row of the antifuse integrated structure, the gate of the second switching transistor is connected to the second virtual word line. The first dashed programming wire and the second virtual programming wire are located on the outermost side of the antifuse matrix, while the first and second virtual word lines are located on the second outermost side of the antifuse matrix. By setting virtual word lines at the edge of the antifuse matrix, the layout environment of the antifuse integrated structure located at the edge of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structure inside the matrix, preventing defects in the edge antifuse memory cells that would prevent them from functioning properly.

[0021] This application also provides a memory, including a memory array, wherein the memory array adopts the above-described antifuse array structure.

[0022] In the direction of bit line extension, the layout length of the antifuse memory array is reduced. Therefore, based on the original layout area and the memory array with the same capacity, the spacing between the switching unit and the antifuse memory unit located in the same active area is increased to ensure the electrical isolation effect of electrical components in the memory array formed by the antifuse integrated structure. Attached Figure Description

[0023] Figure 1 A circuit diagram of an antifuse integrated structure provided in an embodiment of this application;

[0024] Figure 2 A circuit diagram of an antifuse matrix provided in an embodiment of this application;

[0025] Figure 3A schematic diagram showing the connection of an antifuse storage unit to the same programming wire in an adjacent antifuse integrated structure provided in an embodiment of this application;

[0026] Figure 4 A top view of the layout structure of an antifuse integrated structure provided in an embodiment of this application;

[0027] Figure 5 This is a schematic cross-sectional view of the layout structure of an antifuse integrated structure provided in an embodiment of this application;

[0028] Figure 6 A schematic cross-sectional view of the layout structure of another antifuse integrated structure provided in an embodiment of this application;

[0029] Figure 7 This is a schematic diagram of the layout structure of an antifuse matrix provided in an embodiment of this application;

[0030] Figure 8 This is a schematic diagram of the layout structure of the midline of the antifuse matrix provided in an embodiment of this application;

[0031] Figure 9 This is a schematic diagram of the virtual structure of a memory provided in another embodiment of this application;

[0032] Figure 10 A timing diagram illustrating the programming and reading stages of a memory provided in another embodiment of this application. Detailed Implementation

[0033] For antifuse memory, as the density of the memory array increases, the spacing between antifuse memory cells decreases, making it difficult to guarantee the electrical isolation effect of electrical components between antifuse memory cells.

[0034] One embodiment of this application provides an antifuse array structure and a new layout method for the antifuse array, so that the same capacity storage array only needs to occupy a smaller layout area, thereby increasing the spacing between antifuse storage cells on the basis of the original layout area and ensuring the electrical isolation effect of electrical components between antifuse storage cells.

[0035] Those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Figure 1 This is a circuit diagram of the antifuse integrated structure provided in this embodiment. Figure 2 This is a circuit diagram of the antifuse matrix provided in this embodiment. Figure 3This is a schematic diagram showing the connection of an antifuse storage unit to the same programming wire in the adjacent antifuse integrated structure provided in this embodiment. Figure 4 This is a top view of the layout structure of the antifuse integrated structure provided in this embodiment. Figure 5 This is a schematic cross-sectional view of the layout structure of an antifuse integrated structure provided in this embodiment. Figure 6 This is a cross-sectional schematic diagram of the layout structure of another antifuse integrated structure provided in this embodiment. Figure 7 This is a schematic diagram of the layout structure of the antifuse matrix provided in this embodiment. Figure 8 This is a schematic diagram of the layout structure of the antifuse matrix centerline provided in this embodiment. The following is a more detailed description of the antifuse array structure provided in this embodiment with reference to the accompanying drawings:

[0037] refer to Figure 1 and Figure 2 The antifuse array structure includes:

[0038] Multiple antifuse integrated structure 100 (reference) Figure 1 The antifuse matrix is ​​arranged in the extension directions of bit line BL and word line WL (see reference). Figure 2 The extension directions of bit line BL and word line WL are perpendicular to each other. Each antifuse integrated structure 100 is connected to two programming wires PGM and two word lines WL.

[0039] In the extension direction of the word line WL, each antifuse integrated structure 100 and the adjacent antifuse integrated structure 100 are connected to the same programming wire PGM and word line WL.

[0040] In the direction of bit line WL extension, each antifuse integrated structure 100 and the adjacent antifuse integrated structure 100 are connected to one of the programming wires PGM.

[0041] It should be noted that, Figure 2 This is only a partial schematic diagram of the formed antifuse matrix, used only to illustrate the arrangement of the antifuse matrix in this embodiment of the application, and does not constitute a limitation on the number of bit lines BL, word lines WL, and programming wires PGM. In specific use, the number of corresponding bit lines BL, word lines WL, and programming wires PGM can be selected according to the required storage array capacity; in addition, the values ​​in "<>" are only used to distinguish different bit lines BL, word lines WL, or programming wires PGM, and do not constitute a limitation on this embodiment.

[0042] Each antifuse integrated structure 100 is connected to two programming wires PGM and two word lines WL. That is, each antifuse integrated structure 100 includes two antifuse memory cells and two switching units. Each antifuse memory cell is connected to a programming wire PGM, and each switching unit is controlled by a word line WL. As those skilled in the art will know, in an antifuse array, the extension direction of the programming wire PGM is the same as the extension direction of the word line WL, that is, the extension direction of the programming wire PGM is perpendicular to the extension direction of the bit line BL. Specifically, in the extension direction of the bit line BL, each antifuse integrated structure 100 is connected to its adjacent antifuse integrated structure... The 100 are all connected to one of the programming wires PGM, that is, the same programming wire PGM is used to control one of the two adjacent antifuse integrated structures 100 connected on the same bit line BL, that is, the same programming wire PGM is used to control two antifuse memory cells located in different antifuse integrated structures 100, thereby reducing the layout length of the antifuse memory array in the direction of bit line BL; on the basis of the original layout area and the memory array with the same layout capacity, the spacing between the switching unit and the antifuse memory cell located in the same active area is increased to ensure the electrical isolation effect of the electrical components of the antifuse memory array.

[0043] In one example, refer to Figure 1 Each antifuse integrated structure 100 includes:

[0044] The first antifuse storage MOSFET 101, the first switch MOSFET 111, the second switch MOSFET 112, and the second antifuse storage MOSFET 102.

[0045] The gate of the first antifuse storage MOS transistor 101 is connected to the first programming wire PGM. <1> The gate of the first switching transistor 111 is connected to the first word line WL. <1> One end of the source or drain is connected to the first antifuse storage MOS transistor 101, and the other end is connected to the bit line BL. The gate of the second switch transistor 112 is connected to the second word line WL. <2> One end of the source or drain is connected to the second antifuse storage MOSFET 102, and the other end is connected to the bit line BL. The gate of the second antifuse storage MOSFET 102 is connected to the second programming wire PGM. <2> .

[0046] Specifically, in this example, reference Figure 3 In the direction of bit line BL extension, for any two adjacent antifuse integrated structures 100, the gate of the second switch 112 of one of the antifuse integrated structures 100 is connected to the word line WL. <n-2>The gate of the second antifuse storage MOSFET 102 is connected to the programming wire PGM. <m>The gate of the first antifuse storage MOS transistor 101 in another antifuse integrated structure 100 is connected to the programming wire PGM. <m>The gate of the first switching transistor 111 is connected to the word line WL. <n-1>Along the extension direction of bit line BL, for any two adjacent antifuse integrated structures 100, the first switch 111 and the second switch 112 are connected to bit line BL. <n>superior.

[0047] That is, in the direction of bit line BL extension, the gate of the second antifuse storage MOS transistor 102 of each antifuse integrated structure 100 is connected to the gate of the first antifuse storage MOS transistor 101 of the adjacent antifuse integrated structure 100 via the same programming wire PGM. <m>, where n and m are positive integers greater than or equal to 1.

[0048] It should be noted that in other examples, it can also be configured such that, in the bit line extension direction, the gate of the first antifuse storage MOS transistor of each antifuse integrated structure is connected to the same programming wire as the gate of the second antifuse storage MOS transistor of the adjacent antifuse integrated structure.

[0049] In one example, refer to Figure 4 In the antifuse integrated structure 100, the first antifuse storage MOS transistor 101, the first switch transistor 111, the second switch transistor 112, and the second antifuse storage MOS transistor 102 are disposed in the same active region 200.

[0050] Specifically, refer to Figures 5-6 The antifuse integrated structure 100 includes:

[0051] The active region 200, and the first doped region 212, the second doped region 222, the third doped region 232, the fourth doped region 242 and the fifth doped region 252 located in the active region 200.

[0052] The active region 200 is surrounded by an isolation region 201, and the first doped region 212, the second doped region 222, the third doped region 232, the fourth doped region 242, and the fifth doped region 252 are spaced apart in the extension direction of the bit line BL (in combination with...). Figure 4 ).

[0053] Wherein, the first doped region 212 is the unused terminal of the first antifuse storage MOS transistor 101; the second doped region 222 is the common terminal of the first antifuse storage MOS transistor 101 and the first switching transistor 111; the third doped region 232 is the common terminal of the first switching transistor 111 and the second switching transistor 112; the fourth doped region 242 is the common terminal of the second switching transistor 112 and the second antifuse storage MOS transistor 102; and the fifth doped region 252 is the unused terminal of the second antifuse storage MOS transistor 102.

[0054] The source of the first antifuse storage MOSFET 101 is left unused, and its drain is connected to the drain of the first switching transistor 111. The source of the first switching transistor 111 is connected to the bit line BL, so that when the first switching transistor 111 is turned on, the first antifuse storage MOSFET 101 and the bit line BL are electrically connected. The source of the second antifuse storage MOSFET 102 is left unused, and its drain is connected to the drain of the second switching transistor 112. The source of the second switching transistor 112 is connected to the bit line BL, so that when the second switching transistor 112 is turned on, the second antifuse storage MOSFET 102 and the bit line BL are electrically connected.

[0055] Since the source connections of the first switch transistor 111 and the second switch transistor 112 are the same, the layout area of ​​the antifuse integrated structure 100 can be reduced by sharing the source, that is, by sharing the same doped region between the first switch transistor 111 and the second switch transistor 112.

[0056] For an antifuse memory cell, the antifuse MOSFET is turned on by the programming line PGM to form a memory cell. The word line WL controls the switching transistor to facilitate the writing of stored data to the bit line BL. When the corresponding word line WL is turned on, the antifuse memory cell is electrically connected to the bit line BL. By measuring the discharge rate of the charge on the bit line BL by the antifuse memory cell (after a preset time, by comparing the voltage of the bit line BL with the standard voltage), it can be determined whether the antifuse memory cell has been broken down, thereby obtaining the 1 bit of binary data stored in the antifuse memory cell.

[0057] In a specific example, refer to Figure 5 The gate of the first antifuse storage MOSFET 101 is disposed on the top surface of the active region 200 between the first doped region 212 and the second doped region 222. The gate of the first switch MOSFET 111 is disposed on the top surface of the active region 200 between the second doped region 222 and the third doped region 232. The gate of the second switch MOSFET 112 is disposed on the top surface of the active region 200 between the third doped region 232 and the fourth doped region 242. The gate of the second antifuse storage MOSFET 102 is disposed on the top surface of the active region 200 between the fourth doped region 242 and the fifth doped region 252. In other words, the active regions of the first antifuse storage MOSFET 101, the first switch MOSFET 111, the second switch MOSFET 112, and the second antifuse storage MOSFET 102 are configured using a top-gate configuration.

[0058] In a specific example, refer to Figure 6 The gate of the first antifuse storage MOSFET 101 is buried in the active region 200 between the first doped region 212 and the second doped region 222. The gate of the first switch MOSFET 111 is buried in the active region 200 between the second doped region 222 and the third doped region 232. The gate of the second switch MOSFET 112 is buried in the active region 200 between the third doped region 232 and the fourth doped region 242. The gate of the second antifuse storage MOSFET 102 is buried in the active region 200 between the fourth doped region 242 and the fifth doped region 252. In other words, the active regions of the first antifuse storage MOSFET 101, the first switch MOSFET 111, the second switch MOSFET 112, and the second antifuse storage MOSFET 102 are configured by burying the gate.

[0059] Combination Figure 5 and Figure 6 The antifuse integrated structure 100 also includes: an insulating layer 203 covering the active region 200, and a bit line BL (205) disposed on the insulating layer 203 and electrically connected to the third doped region 232.

[0060] Specifically, the insulating layer 200 has a conductive via (not shown) and a conductive layer 204. The conductive via (not shown) exposes the top surface of the third doped region 232. The conductive layer 204 fills the conductive via (not shown), with one end in contact with the third doped region 232 and the other end in contact with BL (205), so that the bit line is electrically connected to the third doped region 232.

[0061] Additionally, refer to Figure 4 In one example, in the word line extension direction, the widths of the active regions 200 containing the first antifuse storage MOSFET 101, the first switch MOSFET 111, the second switch MOSFET 112, and the second antifuse storage MOSFET 102 are consistent. By ensuring that the widths of the active regions 200 containing the first antifuse storage MOSFET 101, the first switch MOSFET 111, the second switch MOSFET 112, and the second antifuse storage MOSFET 102 are consistent, that is, by ensuring that the spacing between each active device in the antifuse matrix is ​​the same, the electrical isolation effect of each active device in the antifuse matrix is ​​further ensured.

[0062] For the layout diagram of the antifuse matrix, refer to... Figure 6 and Figure 7 The antifuse matrix includes multiple rows of integrated antifuse structures 100 arranged along the word line WL extension direction, and multiple columns of integrated antifuse structures 100 arranged along the bit line BL extension direction. Multiple integrated antifuse structures 100 in each row are spaced apart along the WL extension direction, and multiple integrated antifuse structures 100 in each column are spaced apart along the BL extension direction. Adjacent rows of integrated antifuse structures 100 are staggered, meaning that in the BL extension direction, two adjacent integrated antifuse structures 100 are staggered and located in adjacent columns.

[0063] In this configuration, bit lines BL (205) extend in the BL direction and are connected to alternating antifuse integrated structures 100. Since the conductive layers 204 of the antifuse integrated structures 100 are alternately arranged, i.e., conductive vias (not shown) are located on one side of the connected bit lines BL, in one example, the bit lines BL contact the conductive layers 204 through bit line extension layers 300. Connecting the bit lines BL and the conductive layers through the bit line extension layers 300 ensures the stability of the electrical contact between the bit lines and the conductive layers, preventing conductive defects in the formed antifuse matrix.

[0064] In one example, the antifuse integrated structures 100 connected by the same word line WL are arranged at equal intervals. That is, in the extension direction of the word line WL, the spacing between adjacent antifuse integrated structures 100 is equal, avoiding the possibility of small spacing between adjacent antifuse integrated structures 100, which would compromise the overall electrical isolation effect of the antifuse memory array.

[0065] In one example, the antifuse integrated structures 100 connected by the same bit line BL are arranged at equal intervals. That is, in the extension direction of the bit line BL, the spacing between adjacent antifuse integrated structures 100 is equal, avoiding the possibility of small spacing between adjacent antifuse integrated structures 100, which would compromise the overall electrical isolation effect of the antifuse memory array.

[0066] In one example, the bit line BL connected to the first column of antifuse integrated structures 100 is the first virtual bit line Dummy1, and the bit line BL connected to the last column of antifuse integrated structures 100 is the second virtual bit line Dummy2. By setting virtual bit lines at the edge of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edge of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures inside the matrix, preventing defects in the edge antifuse memory cells that would prevent them from functioning properly.

[0067] In one example, the gate of the first storage MOS transistor 101 in the first row of antifuse integrated structure 100 is connected to the first virtual programming wire Dummy3, and the gate of the second storage MOS transistor in the last row of antifuse integrated structure 100 is connected to the second virtual programming wire Dummy4. By setting virtual programming wires at the edge of the antifuse matrix, the layout environment of the antifuse integrated structure 100 located at the edge of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structure inside the matrix, preventing defects in the edge antifuse memory cells that would prevent them from functioning properly.

[0068] Furthermore, in the first row of antifuse integrated structures 100, the gate of the first switching transistor 111 is connected to the first virtual word line Dummy 5, and in the last row of antifuse integrated structures 100, the gate of the second switching transistor 112 is connected to the second virtual word line Dummy 6. The first dashed programming wire Dummy 3 and the second virtual programming wire Dummy 4 are located on the outermost side of the antifuse matrix, while the first virtual word line Dummy 5 and the second virtual word line Dummy 6 are located on the second outermost side of the antifuse matrix. By setting virtual word lines at the edges of the antifuse matrix, the layout environment of the antifuse integrated structures 100 located at the edges of the antifuse matrix is ​​ensured to be consistent with that of the antifuse integrated structures inside the matrix, preventing defects in the edge antifuse memory cells that would prevent them from functioning properly.

[0069] This application embodiment reduces the layout length of the antifuse memory array in the bit line extension direction. Therefore, based on the original layout area and the memory array with the same capacity, the spacing between the switching unit and the antifuse memory unit located in the same active area is increased to ensure the electrical isolation effect of the electrical components in the memory array formed by the antifuse integrated structure.

[0070] It should be noted that the specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection methods of "drain" replacing "source" and "source" replacing "drain" can be used. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problem proposed in this application, but this does not mean that there are no other units in this embodiment.

[0071] Another embodiment of this application also provides a memory, wherein the memory array uses the antifuse array structure provided in the above embodiment. By using the antifuse array structure provided in the above embodiment as the memory array, the spacing between the switching unit and the antifuse memory unit located in the same active area is increased on the basis of the original memory array with the same layout area and capacity, so as to ensure the electrical isolation effect of the electrical components in the memory array formed by the antifuse integrated structure.

[0072] Figure 9 This is a schematic diagram of the virtual structure of the memory provided in this embodiment. Figure 10 The following is a timing diagram illustrating the programming and reading stages of the memory provided in this embodiment. The memory provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0073] refer to Figure 9 The memory includes: a storage array 403, employing the antifuse array structure provided in the above embodiment; a control unit 401, used to receive a row address signal Row_ADD, a programming enable signal PGM_En, and a word line enable signal WL_En; and a row selection control unit 402, connected to the storage array 403 and the control unit 401, used to generate a programming strobe signal PGM based on the row address signal Row_ADD and the programming enable signal PGM_En. <n 2:0>And, based on the row address signal Row_ADD and the word line enable signal WL_En, generate the word line strobe signal WL. <n:0>The column selection control unit 404 is connected to the memory array 403 and is used to turn on the corresponding bit line WL of the memory array 403 according to the bit line strobe signal (not shown).

[0074] Among them, the programming enable signal PGM_En is used to indicate that the programming wire is on, the word line enable signal WL_En is used to indicate that the bit line is on; the programming strobe signal PGM <n 2:0>Used to activate the programming wire PGM in the corresponding memory array 403; word line strobe signal WL <n:0>Used to turn on the word line WL in the corresponding memory array 403.

[0075] For details, please refer to the following: Figure 10 During the programming phase, the programming enable signal PGM_En and the row address signal Row_ADD are provided to generate the programming strobe signal PGM. <n 2:0>The corresponding antifuse MOSFET is selected and blown to form an antifuse memory cell, and the word line strobe signal WL is used to select it. <n:0>The control switch is turned on, and data is written to the antifuse memory cell via the corresponding bit line BL. During the read phase, the word line enable signal WL_En and the row address signal Row_ADD are provided to generate the word line strobe signal WL. <n:0>To select the corresponding antifuse memory cell and electrically connect it to the bit line BL.

[0076] Controlled by both bit line BL and word line WL, when the corresponding word line WL is activated, the antifuse storage unit is electrically connected to bit line BL. The discharge rate of charge on bit line BL by the antifuse storage unit (after a preset time, by comparing the bit line BL voltage with the standard voltage V) is controlled. REF By comparison, it can be determined whether the antifuse memory cell has been broken down, thereby obtaining the 1 bit of binary data stored in the antifuse memory cell.

[0077] It should be noted that, in this embodiment, the programming wire PGM is connected to two antifuse storage units controlled by different word lines WL, i.e., the programming strobe signal PGM. <n 2:0>The required high-level duration must cover two word line strobe signals WL. <n:0>The high-level period is used to complete the data programming.

[0078] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0079] It should be noted that, in order to highlight the innovative aspects of this application, no units that are not closely related to solving the technical problems proposed in this application are introduced in this embodiment. However, this does not mean that there are no other units in this embodiment. Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application. In practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application. < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / m>

Claims

1. An antifuse array structure, comprising: The application relates to a plurality of anti-fuse integrated structures arranged into an anti-fuse matrix in a bit line extension direction and a word line extension direction, wherein the bit line extension direction and the word line extension direction are perpendicular to each other. Each anti-fuse integrated structure is arranged in a same active region, and the extension direction of the active region is the same as the bit line extension direction. Each anti-fuse integrated structure is connected with two programming wires and two word lines. In the extension direction of the word lines, each anti-fuse integrated structure is connected with adjacent anti-fuse integrated structures to the same programming wires and word lines. In the bit line extension direction, each anti-fuse integrated structure is connected with adjacent anti-fuse integrated structures to one of the programming wires. Each anti-fuse integrated structure comprises a first anti-fuse storage MOS tube, a first switch tube, a second switch tube and a second anti-fuse storage MOS tube. The gate of the first anti-fuse storage MOS tube is connected with a first programming wire. The gate of the first switch tube is connected with a first word line, one end of the source or drain is connected with the first anti-fuse storage MOS tube, and the other end is connected with the bit line. The gate of the second switch tube is connected with a second word line, one end of the source or drain is connected with the second anti-fuse storage MOS tube, and the other end is connected with the bit line. The gate of the second anti-fuse storage MOS tube is connected with a second programming wire. In the bit line extension direction, the gate of the second anti-fuse storage MOS tube of each anti-fuse integrated structure is connected with the gate of the first anti-fuse storage MOS tube of adjacent anti-fuse integrated structures to the same programming wire. A plurality of anti-fuse integrated structures connected by the same word line are arranged at equal intervals.

2. The antifuse array structure of claim 1, wherein, A plurality of anti-fuse integrated structures connected by the same bit line are arranged at equal intervals.

3. The antifuse array structure of claim 1, wherein, The anti-fuse integrated structure comprises:

4. The antifuse array structure of claim 1, wherein, An active region, a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region in the active region. The first doped region is the idle end of the first anti-fuse storage MOS tube, the second doped region is the common end of the first anti-fuse storage MOS tube and the first switch tube, the third doped region is the common end of the first switch tube and the second switch tube, the fourth doped region is the common end of the second switch tube and the second anti-fuse storage MOS tube, and the fifth doped region is the idle end of the second anti-fuse storage MOS tube. An insulating layer covers the active region, and the bit line is arranged on the insulating layer and is electrically connected with the third doped region. In the word line extension direction, the widths of the active regions of the first switch tube, the second switch tube, the first anti-fuse storage MOS tube and the second anti-fuse storage MOS tube are consistent.

5. The antifuse array structure of claim 4, wherein, The insulating layer further comprises a conductive via hole which exposes the top surface of the third doped region.

6. The antifuse array structure of claim 4, wherein, A conductive layer fills the conductive via hole, one end of the conductive layer is in contact with the third doped region, and the other end is in contact with the bit line. The conductive via hole is arranged on one side of the connected bit line, and the bit line is in contact with the conductive layer through a bit line extension layer.

7. The antifuse array structure of claim 6 wherein, ​ 8. The antifuse array structure of claim 4, wherein, The gate of the first antifuse storage MOS transistor is arranged on the top surface of the active region between the first doped region and the second doped region, the gate of the first switch transistor is arranged on the top surface of the active region between the second doped region and the third doped region, the gate of the second switch transistor is arranged on the top surface of the active region between the third doped region and the fourth doped region, and the gate of the second antifuse storage MOS transistor is arranged on the top surface of the active region between the fourth doped region and the fifth doped region.

9. The antifuse array structure of claim 4, wherein, The gate of the first antifuse storage MOS transistor is arranged on the top surface of the active region between the first doped region and the second doped region, the gate of the first switch transistor is arranged on the top surface of the active region between the second doped region and the third doped region, the gate of the second switch transistor is arranged on the top surface of the active region between the third doped region and the fourth doped region, and the gate of the second antifuse storage MOS transistor is arranged on the top surface of the active region between the fourth doped region and the fifth doped region.

10. The antifuse array structure of claim 1, wherein, The antifuse matrix comprises a plurality of columns of the antifuse integrated structure arranged along the direction of extension of the word line, wherein the bit line connected by the first column of the antifuse integrated structure is a first virtual bit line, and the bit line connected by the last column of the antifuse integrated structure is a second virtual bit line.

11. The antifuse array structure of claim 1, wherein, The antifuse matrix comprises a plurality of rows of the antifuse integrated structure arranged along the direction of extension of the bit line, wherein the gate of the first antifuse storage MOS transistor in the first row of the antifuse integrated structure is connected to a first virtual programming conductor, and the gate of the second antifuse storage MOS transistor in the last row of the antifuse integrated structure is connected to a second virtual programming conductor.

12. The antifuse array structure of claim 11, wherein, The gate of the first switch transistor in the first row of the antifuse integrated structure is connected to a first virtual word line, and the gate of the second switch transistor in the last row of the antifuse integrated structure is connected to a second virtual word line; wherein the first virtual programming conductor and the second virtual programming conductor are located at the outermost side of the antifuse matrix, and the first virtual word line and the second virtual word line are located at the next outer side of the antifuse matrix.

13. A memory comprising a memory array, characterized by, The memory array adopts the antifuse array structure of any one of claims 1-12. The memory array adopts the antifuse array structure of any one of claims 1-12.

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