Chip transfer method and display panel
By forming a guiding structure on the chip carrier and utilizing the cooperation of guide posts and limiting through holes, the problem of low precision in the Micro-LED chip transfer process is solved, achieving high-precision and high-yield chip transfer.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-16
- Publication Date
- 2026-04-14
AI Technical Summary
In the process of Micro-LED chip transfer, the chip transfer accuracy is not high, resulting in a loss of yield.
A guiding structure is formed on the chip carrier, including guide posts and limiting through holes. The cooperation of the guide posts and limiting through holes restricts the displacement and tilt of the chip, ensuring that the chip is accurately transferred to the target substrate.
This improved the accuracy and yield of chip transfer, reduced the number of transfers, avoided the decrease in accuracy caused by multiple transfers, and achieved high-precision chip transfer.
Smart Images
Figure CN115832118B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip transfer, and more particularly to chip transfer methods and display panels. Background Technology
[0002] Micro-LED (Micro Light-Emitting Diode) is an emerging display technology. Compared with conventional display technologies, displays based on Micro-LED technology have the characteristics of fast response speed, self-illumination, high contrast, long lifespan, and high photoelectric efficiency.
[0003] In the Micro-LED industry, millions or even tens of millions of LED (Light-Emitting Diode) chips are transferred from a growth substrate to a temporary storage substrate, and then from the temporary storage substrate to a backplane. In traditional chip transfer methods, the chips often need to undergo multiple transfers, resulting in reduced chip precision and yield losses.
[0004] Therefore, improving the chip transfer accuracy during the chip transfer process is an urgent problem to be solved. Summary of the Invention
[0005] In view of the shortcomings of the above-mentioned related technologies, the purpose of this application is to provide a chip transfer method and a display panel, which aims to solve the problem of low chip transfer accuracy during the chip transfer process.
[0006] A chip transfer method includes: providing a chip carrier, wherein a chip is disposed on one side of the chip carrier;
[0007] A guiding structure is formed, the guiding structure including guide posts disposed on the chip and limiting through holes disposed on the chip carrier for the guide posts to pass through;
[0008] The positions of the target substrate and the chip carrier are set such that the side of the chip carrier on which the chip is disposed is directly opposite the side of the target substrate on which the chip is disposed.
[0009] The chip to be transferred is detached from the chip carrier under the cooperation of the guide post and the limiting through hole, and falls onto the target substrate;
[0010] Remove the guide post that has fallen onto the chip on the target substrate.
[0011] The aforementioned chip transfer method pre-forms a guiding structure before the chip detaches from the chip carrier. During the chip's detachment from the chip carrier and its fall onto the target substrate, this guiding structure can, to a certain extent, limit the chip's displacement and / or tilt, effectively controlling the direction and amount of chip descent. Furthermore, in some implementations, the aforementioned chip transfer method can effectively apply selective transfer.
[0012] Optionally, the formation of the guide structure includes:
[0013] The limiting through hole is formed in the area where the chip is disposed on the chip carrier;
[0014] The guide post is formed on the chip, passing through the limiting through hole.
[0015] Optionally, the limiting via is formed in the area on the chip carrier where the chip is disposed, including:
[0016] A first photoresist layer is disposed on the side of the chip carrier where the chip is not located;
[0017] The first photoresist layer is patterned to form a first temporary via corresponding to the position of the chip.
[0018] The first photoresist layer is used as a mask to etch the chip carrier, so that the area of the chip carrier corresponding to the first temporary via is removed, forming the limiting via;
[0019] Remove the first photoresist layer.
[0020] Optionally, forming the guide post through the limiting through-hole on the chip includes:
[0021] A second photoresist layer is disposed on the side of the chip carrier where the chip is not located, and the second photoresist layer fills the limiting through hole;
[0022] The second photoresist layer is patterned so that a second temporary via is formed in the second photoresist layer corresponding to the position of the limiting via. The cross-sectional area of the second temporary via is smaller than the cross-sectional area of the limiting via, and the inner wall of the limiting via is covered by the photoresist layer.
[0023] A preset material is placed in the second temporary through hole to form the guide post;
[0024] Remove the second photoresist layer.
[0025] It is understandable that by first creating a second temporary through-hole using photolithography and then setting a preset material in it to form a guide post, the forming accuracy is high, which is beneficial for the production of the guide post.
[0026] Optionally, the preset material includes a material soluble in the target solvent, and the removal of the guide posts that have fallen onto the chip on the target substrate includes:
[0027] The guide column is dissolved and removed using the target solvent.
[0028] It is understandable that a soluble material is used to form the guide pillars to facilitate removal after the transfer is completed.
[0029] Optionally, setting the position of the target substrate and the chip carrier further includes:
[0030] The distance between the chip on the chip carrier and the target substrate is less than the length of the guide post.
[0031] Understandably, after the chip falls onto the target substrate, some of the guide posts remain in the limiting through holes. That is, throughout the entire process of the chip falling onto the target substrate, the guide posts and the limiting through holes can cooperate to restrict the movement of the chip to a certain extent and ensure the accuracy of the chip during the transfer process.
[0032] Optionally, the chip carrier includes a growth substrate on which the chip is grown, the chip includes an epitaxial layer grown on the growth substrate, the epitaxial layer includes a buffer layer, the buffer layer is in contact with the growth substrate, and the guide post passes through the limiting via on the growth substrate and is connected to the buffer layer.
[0033] The step of detaching the chip to be transferred from the chip carrier under the cooperation of the guide post and the limiting through hole includes:
[0034] Remove the buffer layer between the chip to be transferred and the growth substrate;
[0035] After the step of detaching the chip to be transferred from the chip carrier under the cooperation of the guide post and the limiting through hole, and allowing it to fall onto the target substrate, the method further includes:
[0036] Remove the buffer layer between the chip and the guide post.
[0037] Optionally, the target substrate includes a circuit substrate, and the circuit substrate has a die-bonding region.
[0038] The setting of the target substrate and the chip carrier also includes:
[0039] Align the electrodes of the chip on the chip carrier with the bonding region of the die-bonding area;
[0040] After the step of detaching the chip to be transferred from the chip carrier under the cooperation of the guide post and the limiting through hole, and allowing it to fall onto the target substrate, the method further includes:
[0041] The chip is then bonded to the circuit board.
[0042] Understandably, in some implementation processes, the above-mentioned chip transfer method can realize the direct transfer of chips from the chip growth substrate to the circuit substrate, reducing the number of chip transfers, avoiding the reduction in accuracy caused by multiple transfers, and further ensuring high-precision chip transfer.
[0043] Optionally, before forming the guide structure, the method further includes:
[0044] The chip carrier is thinned to reduce its thickness.
[0045] Understandably, a thinner chip substrate makes it easier to form guiding vias during the chip transfer process.
[0046] Based on the same inventive concept, this application also provides a display panel, the display panel including a light-emitting chip and a circuit substrate, wherein the light-emitting chip is transferred to the die-bonding region of the circuit substrate by the chip transfer method described above.
[0047] The light-emitting chips in the aforementioned display panel are set with high precision and good quality. Furthermore, in some implementation processes, the light-emitting chips of the display panel in this embodiment can be directly transferred from the growth substrate to the circuit substrate, resulting in fewer transfer steps and less impact on the yield of the light-emitting chips. At the same time, fewer transfer steps also ensure the accuracy of chip transfer. Attached Figure Description
[0048] Figure 1 This is a schematic diagram of the basic process of the chip transfer method provided in the embodiments of the present invention;
[0049] Figure 2 This is a schematic diagram of the guiding structure provided in an embodiment of the present invention;
[0050] Figure 3 This is a schematic diagram showing the placement of the target substrate and the chip carrier in an embodiment of the present invention.
[0051] Figure 4 This is a schematic diagram illustrating the chip detachment from the chip carrier board according to an embodiment of the present invention.
[0052] Figure 5 This is a schematic diagram of the chip after the guide posts have been removed, provided in an embodiment of the present invention.
[0053] Figure 6This is another schematic diagram of the guiding structure provided in an embodiment of the present invention;
[0054] Figure 7 This is a schematic diagram of the basic process for forming a guide structure provided in an embodiment of the present invention;
[0055] Figure 8 This is a schematic diagram of the process for forming a limiting through hole provided in an embodiment of the present invention;
[0056] Figure 9 This is a schematic diagram of exposing the first photoresist layer according to an embodiment of the present invention;
[0057] Figure 10 for Figure 9 A schematic diagram of the patterned first photoresist layer;
[0058] Figure 11 for Figure 10 A schematic diagram of etching a chip carrier to form a limiting via;
[0059] Figure 12 This is a schematic diagram of the process for fabricating guide pillars on a chip according to an embodiment of the present invention;
[0060] Figure 13 This is a schematic diagram of a second photoresist layer being disposed on a chip carrier according to an embodiment of the present invention;
[0061] Figure 14 for Figure 13 A schematic diagram of the patterned second photoresist layer;
[0062] Figure 15 In order to be in Figure 14 A schematic diagram showing how a guide column is formed by filling it with a pre-set material.
[0063] Figure 16 This is a schematic diagram of another process for forming a guide structure provided by an embodiment of the present invention;
[0064] Figure 17 This is a schematic diagram of the patterning of the third photoresist layer provided in an embodiment of the present invention;
[0065] Figure 18 for Figure 17 A top-down view;
[0066] Figure 19 for Figure 17 A schematic diagram showing the etching of strip-shaped grooves on a chip carrier substrate;
[0067] Figure 20 for Figure 16 A schematic diagram of the guiding structure formed by the process;
[0068] Figure 21This is a schematic diagram illustrating the distance setting between the chip on the chip carrier and the target substrate provided in an embodiment of the present invention.
[0069] Figure 22 for Figure 21 A schematic diagram of the chip falling onto the target substrate;
[0070] Figure 23 This is a schematic diagram showing the dimensional relationship between the second temporary through hole and the limiting through hole provided in an embodiment of the present invention;
[0071] Figure 24 A schematic diagram illustrating the width setting of the strip groove provided in an embodiment of the present invention;
[0072] Figure 25 A schematic diagram of a chip with guide pillars provided in an embodiment of the present invention;
[0073] Figure 26 This is a schematic diagram illustrating the removal of the buffer layer between the chip and the chip carrier board, provided in an embodiment of the present invention.
[0074] Figure 27 for Figure 26 A schematic diagram of the chip falling onto the target substrate;
[0075] Figure 28 This is a schematic diagram of another structure of a chip with guide pillars provided in an embodiment of the present invention;
[0076] Figure 29 This is a schematic diagram illustrating the direct transfer of a chip from a growth substrate to a circuit substrate according to an embodiment of the present invention.
[0077] Explanation of reference numerals in the attached figures:
[0078] 1-Chip; 11-Buffer layer; 12-N-type semiconductor layer; 13-Active layer; 14-P-type semiconductor layer; 15-Electrode; 2-Guide post; 3-Chip carrier; 31-Growth substrate; 4-Limiting via; 5-Target substrate; 51-Circuit substrate; 61-First photoresist layer; 601-First temporary via; 62-Second photoresist layer; 602-Second temporary via; 63-Third photoresist layer; 603-Strip groove; 7-Mask. Detailed Implementation
[0079] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.
[0080] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0081] During the chip transfer process, there is a problem of low chip transfer accuracy.
[0082] Therefore, this application aims to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in subsequent embodiments.
[0083] Example:
[0084] This embodiment provides a chip transfer method; please refer to [link to relevant documentation]. Figure 1 Chip transfer methods include:
[0085] S101. A chip carrier board is provided, and a chip is provided on one side of the chip carrier board;
[0086] S102, Forming a guiding structure;
[0087] It should be noted that, please refer to Figure 2 As shown, the guiding structure of this embodiment includes a guide post 2 disposed on the chip 1 and a limiting through hole 4 disposed on the chip carrier 3 for the guide post 2 to pass through. In some examples, the limiting through hole 4 exposes a portion of the chip 1 near the chip carrier 3, and the guide post 2 is disposed in the exposed area of the chip 1. There is a gap between the guide post 2 and the inner wall of the limiting through hole 4 so that the guide post 2 can move along the thickness direction of the chip carrier 3 without being obstructed by the chip carrier 3. The guide post 2 is used to cooperate with the limiting through hole 4 to restrict the movement of the chip 1 in the non-thickness direction of the chip carrier 3 after the chip 1 is detached from the chip carrier 3. It should be noted that the "passing through" referred to in this embodiment is not limited to the guide post being longer than the limiting through hole; the guide post may also be no longer than the limiting through hole and be completely within the limiting through hole.
[0088] S103. Set the positions of the target substrate and the chip carrier so that the side of the chip carrier with the chip is directly opposite the side of the target substrate with the chip.
[0089] For example, please see Figure 3 As shown, the target substrate 5 and the chip carrier 3 are positioned directly opposite each other.
[0090] S104. The chip to be transferred is detached from the chip carrier by the cooperation of the guide post and the limiting through hole.
[0091] like Figure 4Since the chip carrier 3 is vertically above the target substrate 5, after the chip 1 detaches from the chip carrier 3 and falls towards the target substrate 5, it is understandable that the movement of the chip is somewhat restricted during its descent towards the target substrate 5 due to the guide post passing through the limiting through hole. During some transfer processes, the cooperation between the guide post and the limiting through hole can, to a certain extent, limit the displacement and / or tilt of the chip, effectively controlling the direction and amount of chip descent. As an example, the target substrate is positioned vertically downwards from the chip carrier. The chip 1 to be transferred can fall vertically to the target substrate 5 under the action of external forces, including gravity. The guide post 2 falls with the chip 1 and, during the descent, cooperates with the limiting through hole 4 to restrict the movement of the chip 1 in non-vertical directions.
[0092] S105, Remove the guide posts from the chip that has fallen onto the target substrate.
[0093] like Figure 5 The guide posts on chip 1 are removed. Understandably, after chip 1 falls onto target substrate 5, the chip carrier is removed.
[0094] In this embodiment of the chip transfer method, the chip does not contact the chip carrier before being peeled off and transferred to the chip carrier. In practical applications, it can selectively detach the chip from the chip carrier, that is, selective transfer can be achieved. In this embodiment, a guide structure is pre-formed before the chip detaches from the chip carrier. During the process of the chip detaching from the chip carrier and falling to the target substrate, the guide structure can limit the displacement and / or tilt of the chip to a certain extent, and effectively control the direction and offset of the chip's fall.
[0095] The chip carrier can be any carrier on which a chip is mounted, including but not limited to growth substrates for growing chips, temporary storage substrates for temporarily storing chips, and transfer substrates for picking up and transferring chips. The chip transfer method of this embodiment accurately transfers the chip from the chip carrier to the target substrate. The target substrate can also be any substrate that receives chips, including but not limited to temporary storage substrates for temporarily storing chips, transfer substrates for picking up and transferring chips, and circuit substrates for setting chips to achieve corresponding functions.
[0096] It is understandable that the chip substrate can be any material with through holes, including but not limited to sapphire, silicon carbide, silicon, gallium arsenide, and other semiconductor materials.
[0097] The chips in this embodiment include, but are not limited to, LED light-emitting chips or any other chips that need to be transferred. For example, LED light-emitting chips include, but are not limited to, Mini-LED (Mini Light-Emitting Diode) chips, Micro-LEDs, etc. For instance, in one example, the LED chip can be a Mini-LED chip; in another example, the LED chip can be a Micro-LED chip.
[0098] In this embodiment, the shape of the guide post and the number of guide posts corresponding to a single chip are not limited. The guide post can be a cylinder, a polygonal prism, etc., and the number of guide posts can be one or more. For example, when a guide post is formed on a single chip, the guide post can be located in the central region of the chip to ensure greater stability during the chip's descent. In another example, see... Figure 6 Two guide posts 2 are provided on the same chip 1, and the two guide posts 2 are symmetrically arranged on both sides of the chip 1.
[0099] See Figure 7 In some implementations, a guide structure is formed, including:
[0100] S201. A limiting through hole is formed in the area where the chip is located on the chip carrier;
[0101] In one example, the limiting via extends along the thickness direction of the chip carrier, and the cross-sectional area of the limiting via is smaller than the area of the chip in contact with the chip carrier, thus exposing the chip.
[0102] S202, Form guide posts through the limiting vias on the chip;
[0103] In other words, in some implementations, a limiting through hole is formed first, and then a guide post is made separately.
[0104] See Figure 8 In some embodiments, a limiting via is formed in the area where the chip is located on the chip carrier, including:
[0105] S2011. A first photoresist layer is provided on the side of the chip carrier where no chip is located;
[0106] S2012. Pattern the first photoresist layer to form a first temporary via corresponding to the position of the chip.
[0107] See Figure 9 As shown, the first photoresist layer 61 is exposed using mask 7. In this example, the first photoresist layer 61 can be a positive photoresist; it is understood that in other examples, a negative photoresist can be selected. Figure 10As shown, the first photoresist layer 61 after exposure is developed, and a first temporary via 601 is formed on the first photoresist layer 61.
[0108] S2013. Using the first photoresist layer as a mask, the chip carrier is etched so that the area of the chip carrier corresponding to the first temporary via is removed to form a limiting via.
[0109] like Figure 11 As shown, a portion of the chip carrier 3 is removed to form a limiting via 4. Exemplarily, the etching of the chip carrier can employ methods including, but not limited to, dry etching, such as reactive ion etching (RIE) and inductively coupled plasma (ICP) etching.
[0110] S2014, Remove the first photoresist layer.
[0111] See Figure 12 In some embodiments, a guide post is formed on the chip through a limiting via, including:
[0112] S2021. A second photoresist layer is provided on the side of the chip carrier where no chip is located;
[0113] As an example, see Figure 13 The thickness of the second photoresist layer 62 is not less than the thickness of the chip carrier 3, and the second photoresist layer 62 fills the limiting via 4. In other examples, the thickness of the second photoresist layer may be less than that of the chip carrier, that is, the second photoresist layer does not completely fill the limiting via, but the length of the final guide post is also reduced accordingly.
[0114] S2022. Pattern the second photoresist layer so that the second photoresist layer forms a second temporary via corresponding to the position of the limiting via.
[0115] For example, see Figure 14 The second temporary via 602 exposes the chip 1. The cross-sectional area of the second temporary via 602 is smaller than the cross-sectional area of the limiting via 4, and the inner wall of the limiting via 4 is covered by the second photoresist layer 62.
[0116] S2023. Set a pre-designed material in the second temporary through hole to form a guide post;
[0117] See Figure 15 In this example, the preset material completely fills the second temporary through hole 602, and the shape of the guide post formed is the same as the internal shape of the second temporary through hole 602.
[0118] S2024, Remove the second photoresist layer.
[0119] In some embodiments, the preset material includes a material soluble in the target solvent, and removing the guide posts that have fallen onto the chip on the target substrate includes:
[0120] The guide column is dissolved and removed using the target solvent.
[0121] In one example, the preset material is a glue material, including polyimide (PI), which can be dissolved by solvents such as ethanol, isopropanol, and methanol. It is understood that since the guide posts will undergo a step of detaching the chip from the chip carrier after formation, the guide posts should not be damaged during this process. For example, if the chip is detached from the chip carrier by laser lift-off, the guide posts should be made of a material that will not be decomposed by laser or damaged in other ways. For instance, in the process of detaching the chip from the chip carrier by laser lift-off, the material of the guide posts can be the polyimide mentioned above.
[0122] It is understood that the methods for forming guide structures are not limited to the examples above; usable guide structures can be formed in any other way. For another example, please see... Figure 16 Another way to form a guide structure includes:
[0123] S301. A third photoresist layer is provided on the side of the chip carrier where no chip is located;
[0124] S302. Pattern the third photoresist layer so that the third photoresist layer forms a strip groove corresponding to the position of the chip, and the strip groove is closed at both ends to form a closed pattern.
[0125] like Figure 17 as well as Figure 18 Taking the closed-end shape of the strip groove 603 as an example, where the shape is annular, the final cross-section of the limiting through hole and the guide post is circular. It can be understood that the closed-end shape of the strip groove 603 can be any other shape, and the subsequent method of forming the guide structure is consistent with the following example.
[0126] For example, the annular development area on the third photoresist layer can be formed by multiple exposures.
[0127] S303. Using the third photoresist layer as a mask, the chip carrier is etched so that the area of the chip carrier corresponding to the strip groove is removed.
[0128] S304, Remove the third photoresist layer;
[0129] Please see Figure 19Using the third photoresist layer 63 as a mask, strip-shaped grooves are also etched on the chip carrier 3, which is equivalent to transferring the pattern on the third photoresist layer 63 onto the chip carrier 3. The outer diameter of the ring on the chip carrier is equal to the inner diameter of the limiting via to be formed, and the inner diameter of the ring is equal to the outer diameter of the guide post to be formed. The ring width is equal to the distance between the guide post and the inner wall of the limiting via. Figure 20 As shown, the guide structure formed through the steps of this example is illustrated. The portion of the chip carrier 3 inside the strip-shaped groove is divided, and the material of this portion of the chip carrier becomes the guide post 2. The guide post 2 has the same thickness as the chip carrier 3, while the outer wall of the strip-shaped groove becomes the inner wall of the limiting through-hole. In this example, by directly utilizing the chip carrier to simultaneously form the limiting through-hole and the guide post, the process complexity and cost of forming the guide structure are reduced.
[0130] In some implementations, the chip substrate is thinned before forming the guide structure to reduce its thickness. Forming the guide structure requires creating a limiting via on the chip substrate, which essentially involves removing a portion of the material. A thinner chip substrate facilitates the formation of the guide structure, reducing the required etching depth during processes such as etching to remove this material, saving time and simplifying the process.
[0131] To further ensure the accuracy of the chip transfer process, the spacing between the target substrate and the chip carrier can be adjusted. In some embodiments, a closer distance between the target substrate and the chip carrier can reduce the degree of potential chip misalignment. In some examples, step S103 above: setting the positions of the target substrate and the chip carrier, further includes:
[0132] S1031, Make the distance between the chip on the chip carrier and the target substrate less than the length of the guide post.
[0133] like Figure 21 The distance between chip 1 on chip carrier 3 and target substrate 5 is selected based on the length of the formed guide post 2. In this example, the length of guide post 2 is h1. When setting the positions of target substrate 5 and chip carrier 3, the distance between chip 1 and target substrate 5 is h2, where h1 is greater than h2. It can be understood that h2 is the distance that chip 1 needs to move when it contacts target substrate 5, which can be the distance between the electrode of chip 1 and the pad in the die-bonding area on target substrate 5.
[0134] like Figure 22In this example, after the chip 1 falls onto the target substrate 5, a portion of the guide post 2 remains in the limiting through hole 4. That is, throughout the entire process of the chip 1 falling onto the target substrate 5, the guide post 2 and the limiting through hole 4 can cooperate to restrict the movement of the chip 1 to a certain extent.
[0135] However, it is understandable that even in some examples where the length of the guide post is no greater than the distance between the chip and the target substrate, the guide post and the limiting via restrict the range of motion of the chip as it falls toward the target substrate before the guide post is completely dislodged from the limiting via. This also guides the chip's descent and can improve the accuracy of chip transfer.
[0136] Furthermore, the preciseness of the chip transfer process can be ensured through a well-coordinated connection between the guide post and the limiting via. In some implementations, the gap between the guide post and the inner wall of the limiting via is no greater than 500nm, such as 100nm, 150nm, 200nm, 250nm, 300nm, 400nm, and 500nm. It is understood that the smaller the gap between the guide post and the chip carrier, the smaller the range of motion of the guide post. Consequently, the space available for the chip to move in other directions during its journey towards the target carrier is also smaller, thus ensuring the precision of chip transfer.
[0137] like Figure 23 In step S2022, by controlling the size of the second temporary via 602 formed by the patterning of the second photoresist layer 62, the gap between the fabricated guide post and the inner wall of the limiting via can be made no greater than 500 nm. Specifically, it is only necessary to ensure that the distance between the inner wall of the second temporary via 602 and the inner wall of the limiting via is no greater than 500 nm, that is, the thickness of the second photoresist layer 62 on the limiting via is no greater than 500 nm.
[0138] like Figure 24 In the aforementioned step S302, by controlling the width of the strip groove 603 etched on the third photoresist layer 63 to be no greater than 500nm, and the width of the strip groove 603 formed after etching the chip carrier based on the third photoresist layer 63 as a mask is also no greater than 500nm, the gap between the made guide post and the inner wall of the limiting through hole is no greater than 500nm.
[0139] In some embodiments, the chip carrier includes a growth substrate for growing the chip, the chip includes an epitaxial layer grown on the growth substrate, the epitaxial layer includes a buffer layer, the buffer layer is in contact with the growth substrate, a limiting via exposes the buffer layer, and a guide post is connected to the buffer layer through the limiting via on the growth substrate.
[0140] The process of detaching the chip to be transferred from the chip carrier board by means of guide posts and limiting through holes includes:
[0141] Remove the buffer layer between the chip to be transferred and the growth substrate;
[0142] After the chip to be transferred is detached from the chip carrier by the cooperation of the guide posts and limiting through holes and falls onto the target substrate, the process also includes:
[0143] Remove the buffer layer between the chip and the guide post.
[0144] As a concrete example, see Figure 25 The chip is a Micro-LED chip, and the chip carrier 3 is a growth substrate for growing the Micro-LED chip. The Micro-LED chip on the growth substrate includes an epitaxial layer and electrodes 15. The epitaxial layer includes, but is not limited to, a buffer layer 11, an N-type semiconductor layer 12, an active layer 13, and a P-type semiconductor layer 14. The active layer 13 may include a quantum well layer, and may also include other structures. In some other examples, the epitaxial layer may optionally include at least one of a reflective layer and a passivation layer. The material and shape of the electrodes are not limited. For example, in one example, the material of the electrodes may include, but is not limited to, at least one of Cr, Ni, Al, Ti, Au, Pt, W, Pb, Rh, Sn, Cu, and Ag. In the above examples, after a limiting via is formed on the chip carrier, the buffer layer of the chip is exposed, and the guide post is connected to the buffer layer.
[0145] The buffer layer can be made of materials including, but not limited to, gallium nitride (GaN). Gallium nitride decomposes into nitrogen gas and metallic gallium at certain temperatures. In practical applications, gallium nitride can be decomposed by irradiating it with a laser, causing it to absorb photon energy and generate heat. When the chip in the example above is detached from the chip carrier using the guide posts and limiting vias, the target laser is used to irradiate the gallium nitride buffer layer. Please refer to [link to relevant documentation]. Figure 26 In this embodiment, the target laser (indicated by arrows in the figure; this example uses a 248nm wavelength laser, but other examples may use different wavelengths) selectively irradiates only the buffer layer 11 connected to the chip carrier 3. The buffer layer 11 between the chip and the chip carrier 3 is almost completely decomposed, while the buffer layer 11 connected to the guide post 2 remains intact. Under the influence of gravity and the impact force of the gas generated by the decomposition of gallium nitride, the chip detaches from the chip carrier 3 and falls towards the target substrate. In other examples, an opaque material can be used to form the guide post, which requires lower precision during selective irradiation of the target laser and reduces the complexity of selective irradiation.
[0146] See Figure 27In the example described above, after the chip is dropped onto the target substrate 5, part of the buffer layer 11 and the guide post 2 remain on the chip, and the guide post 2 and the buffer layer 11 can be removed sequentially. Alternatively, in some other examples, the buffer layer 11 can be removed directly. Due to the removal of the buffer layer 11, the guide post 2 also detaches from the chip at the same time. That is, the steps of removing the buffer layer 11 and the guide post 2 are equivalent to the same step.
[0147] See Figure 28 In another example, when forming the guiding structure, the region of the chip's buffer layer 11 corresponding to the guide post 2 is also removed, exposing the chip body below the chip's epitaxial layer ("below" is a term used with reference to the illustrated direction). The guide post 2 is directly connected to the chip body. Taking the Micro-LED chip structure of the aforementioned example in this embodiment as an example, the guide post 2 is connected to the chip's N-type semiconductor layer 12. In this example, after the chip falls onto the target substrate, the buffer layer has been removed, and only the guide post connected to the chip needs to be removed.
[0148] In some embodiments, the target substrate includes a circuit substrate with a die-bonding region. Positioning the target substrate and the chip carrier further includes aligning the electrodes of the chip on the chip carrier with the bonding area of the die-bonding region. The bonding area includes, but is not limited to, the area of the pads. After the chip to be transferred detaches from the chip carrier with the cooperation of guide posts and limiting vias and falls onto the target substrate, the process further includes bonding the chip to the circuit substrate. In one example, such as... Figure 29 The chip is aligned with the die-bonding area of the circuit substrate 51 and directly transferred from the growth substrate 31 to the circuit substrate 51 without any intermediate transfer process. This chip transfer method in this embodiment achieves direct transfer, and the growth substrate 31 and the circuit substrate 51 do not need to contact each other, which facilitates selective chip transfer. By directly transferring the chip from the growth substrate to the circuit substrate, other intermediate transfer steps are omitted, reducing the number of transfers and having a smaller impact on chip yield. Furthermore, fewer transfers further ensure the accuracy of chip transfer.
[0149] In practical applications, the chip transfer method of this embodiment can be either non-selective or selective. That is, all chips on the chip carrier can be transferred, or only a portion of the chips on the chip carrier can be selectively transferred. It is understood that selective transfer can be achieved simply by selectively detaching the chips from the chip carrier. For example, in the example where the chip carrier is a growth substrate for growing chips and the chips are Micro-LED chips including a buffer layer, a target laser is used to selectively irradiate the portion of the chips that need to be transferred, so that only this portion of the chips detaches from the chip carrier, thus achieving selective transfer.
[0150] In other examples, the chip carrier may also be a temporary storage substrate or a transfer substrate. The chip and this type of chip carrier may be connected by some adhesive material, such as photopolymer adhesive. By irradiating the photopolymer adhesive between the chip and the chip carrier with light, the adhesiveness of the photopolymer adhesive is eliminated, allowing the chip to detach from the chip carrier under the action of gravity. In some even examples, the chip can be detached from the chip carrier directly by external force, such as applying a vertically downward force to the guide posts.
[0151] This embodiment also provides a display panel, which includes a light-emitting chip and a circuit substrate. The light-emitting chip is transferred to the die-bonding area of the circuit substrate using the chip transfer method described above in this embodiment. The display panel of this embodiment has high precision in setting the light-emitting chip and good quality. Furthermore, in some implementations, the light-emitting chip of the display panel of this embodiment can be directly transferred from the growth substrate to the circuit substrate, reducing the number of transfers and minimizing the impact on the yield of the light-emitting chip. At the same time, fewer transfers also ensure the precision of chip transfer.
[0152] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A chip transfer method, characterized in that, include: A chip carrier board is provided, wherein a chip is disposed on one side of the chip carrier board; A guiding structure is formed, the guiding structure including guide posts disposed on the chip and limiting through holes disposed on the chip carrier for the guide posts to pass through; The positions of the target substrate and the chip carrier are set such that the side of the chip carrier on which the chip is disposed is directly opposite the side of the target substrate on which the chip is disposed. The chip to be transferred is detached from the chip carrier under the cooperation of the guide post and the limiting through hole, and falls onto the target substrate; Remove the guide post that has fallen onto the chip on the target substrate.
2. The chip transfer method as described in claim 1, characterized in that, The formation of the guiding structure includes: The limiting through hole is formed in the area where the chip is disposed on the chip carrier; The guide post is formed on the chip, passing through the limiting through hole.
3. The chip transfer method as described in claim 2, characterized in that, The limiting through hole is formed in the area where the chip is disposed on the chip carrier, including: A first photoresist layer is disposed on the side of the chip carrier where the chip is not located; The first photoresist layer is patterned to form a first temporary via corresponding to the position of the chip. The first photoresist layer is used as a mask to etch the chip carrier, so that the area of the chip carrier corresponding to the first temporary via is removed, forming the limiting via; Remove the first photoresist layer.
4. The chip transfer method as described in claim 2, characterized in that, The formation of the guide post through the limiting through hole on the chip includes: A second photoresist layer is disposed on the side of the chip carrier where the chip is not located, and the second photoresist layer fills the limiting through hole; The second photoresist layer is patterned so that a second temporary via is formed in the second photoresist layer corresponding to the position of the limiting via. The cross-sectional area of the second temporary via is smaller than the cross-sectional area of the limiting via, and the inner wall of the limiting via is covered by the photoresist layer. A preset material is placed in the second temporary through hole to form the guide post; Remove the second photoresist layer.
5. The chip transfer method as described in claim 4, characterized in that, The preset material includes a material that can be dissolved by the target solvent, and the removal of the guide posts that have fallen onto the chip on the target substrate includes: The guide column is dissolved and removed using the target solvent.
6. The chip transfer method as described in claim 1, characterized in that, The setting of the target substrate and the chip carrier also includes: The distance between the chip on the chip carrier and the target substrate is less than the length of the guide post.
7. The chip transfer method as described in claim 1, characterized in that, The chip carrier includes a growth substrate on which the chip is grown. The chip includes an epitaxial layer grown on the growth substrate. The epitaxial layer includes a buffer layer. The buffer layer is in contact with the growth substrate. The guide post passes through the limiting through-hole on the growth substrate and is connected to the buffer layer. The step of detaching the chip to be transferred from the chip carrier under the cooperation of the guide post and the limiting through hole includes: Remove the buffer layer between the chip to be transferred and the growth substrate; After the step of detaching the chip to be transferred from the chip carrier under the cooperation of the guide post and the limiting through hole, and allowing it to fall onto the target substrate, the method further includes: Remove the buffer layer between the chip and the guide post.
8. The chip transfer method according to any one of claims 1-7, characterized in that, The target substrate includes a circuit substrate, and the circuit substrate has a die-bonding region. The setting of the target substrate and the chip carrier also includes: Align the electrodes of the chip on the chip carrier with the bonding region of the die-bonding area; After the step of detaching the chip to be transferred from the chip carrier under the cooperation of the guide post and the limiting through hole, and allowing it to fall onto the target substrate, the method further includes: The chip is then bonded to the circuit board.
9. The chip transfer method according to any one of claims 1-7, characterized in that, Before forming the guiding structure, the method further includes: The chip carrier is thinned to reduce its thickness.
10. A display panel, characterized in that, The display panel includes a light-emitting chip and a circuit substrate, wherein the light-emitting chip is transferred to the die-bonding region of the circuit substrate by the chip transfer method according to any one of claims 1-9.
Citation Information
Patent Citations
Chip transfer method and display panel
CN115832117A