A CMOS active polyphase filter with adjustable suppression frequency

Abstract

The present invention discloses a CMOS active multiphase filter with adjustable suppression frequency, comprising four RCRC filter circuits. Each RC filter circuit includes two or more RC filter units connected in series. The output C of the previous RC filter unit in the same RC filter circuit is connected to the input A of the next RC filter unit. The input A of each RC filter unit in each RC filter circuit is connected to the input B of the corresponding RC filter unit in the previous RC filter circuit in parallel. The input A of the four RC filter circuits is respectively connected to the positive input of the I and Q signals and the negative input of the I and Q signals; the output C of the first and second RC filter circuits is connected to the positive output of the signal; and the output C of the third and fourth RC filter circuits is connected to the negative output of the signal. The present invention adds an inverting amplifier to the RC filter network to compensate for signal amplitude loss through the filter network.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment and electronic devices, and in particular to a CMOS active polyphase filter with adjustable suppression frequency for orthogonal signal synthesis. Background Art

[0002] With the rapid development of mobile communications, the exploration and research of RF front-end integrated circuit chips, which are inextricably linked to them, has become a new hotspot. As the core module of RF transceiver systems, the performance of mixers is crucial. Due to issues of image frequencies and image rejection, the development of highly integrated transceivers has become a significant challenge. The emergence of image-rejection mixers offers a solution, furthering the development of low-power and low-cost transceiver chips.

[0003] An image rejection mixer can be considered to consist of a quadrature mixer and an intermediate frequency (IF) 90° coupler. A passive polyphase filter composed of resistors and capacitors is typically used as the 90° coupler. Cascading these filters can expand bandwidth, but this increases signal loss. Furthermore, at lower IFs, traditional polyphase filters exhibit frequency-dependent phase error, making them limited in their ability to suppress IF signals within a bandwidth of approximately 10 MHz. Summary of the Invention

[0004] The object of the present invention is to provide a CMOS active polyphase filter with adjustable suppression frequency.

[0005] The technical solution adopted in the present invention is:

[0006] A CMOS active multiphase filter with adjustable suppression frequency includes four RCRC filter circuits arranged in parallel, each RC filter circuit includes two or more RC filter units connected in series.

[0007] Each RC filter unit has an input terminal A, an input terminal B, and an output terminal C. The output terminal C of the previous stage RC filter unit in the same RC filter circuit is connected to the input terminal A of the next stage RC filter unit. The input terminal A of the first stage RC filter unit in the RC filter circuit is connected to a signal input terminal; the output terminal C of the last stage RC filter unit in the RC filter circuit is connected to the signal output terminal.

[0008] The input terminal A of the first-stage RC filter unit in the four-way RC filter circuit is respectively connected to the positive input terminal of the I-way signal, the positive input terminal of the Q-way signal, the negative input terminal of the I-way signal, and the negative input terminal of the Q-way signal;

[0009] The output terminal C of the last-stage RC filter unit of the first RC filter circuit and the second RC filter circuit is connected to the positive output terminal of the signal; the output terminal C of the last-stage RC filter unit of the third RC filter circuit and the fourth RC filter circuit is connected to the negative output terminal of the signal;

[0010] The input end A of each RC filter unit of each RC filter circuit is connected to the input end B of the RC filter unit of the corresponding stage of the previous RC filter circuit in parallel sequence; the previous RC filter circuit corresponding to the first RC filter circuit is the fourth RC filter circuit.

[0011] That is, the input terminal A of each RC filter unit of the first RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the fourth RC filter circuit;

[0012] The input terminal A of each RC filter unit of the second RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the first RC filter circuit;

[0013] The input terminal A of each RC filter unit of the third RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the second RC filter circuit;

[0014] The input terminal A of each RC filter unit of the fourth RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the third RC filter circuit;

[0015] Furthermore, each RC filter circuit has three RC filter units.

[0016] Furthermore, each RC filter unit includes a resistor R, a first inverter, a first adjustable switched capacitor, and a second adjustable switched capacitor; the input end A of the RC filter unit is respectively connected to the input end of the first inverter and one end of the resistor R, and the output end of the first inverter and the other end of the resistor R are connected to one end of the second adjustable switched capacitor; the input end B of the RC filter unit is connected to the input end D of the first adjustable switched capacitor; the output end E of the first adjustable switched capacitor and the second adjustable switched capacitor are connected to the output end C of the RC filter unit.

[0017] Furthermore, the first adjustable switch capacitor and the second adjustable switch capacitor use the same adjustable switch capacitor, and the adjustable switch capacitor includes four inverter units, each inverter unit includes a second inverter, a first capacitor, a second capacitor, an N-type MOS transistor, and a P-type MOS transistor; one end of the first capacitor of all inverter units is connected to the input terminal D of the adjustable switch capacitor;

[0018] The input end of the second inverter is connected to a control input end and the gate of the N-type MOS transistor, and the output end of the second inverter is connected to the gate of the P-type MOS transistor; the other end of the first capacitor is connected to the source of the N-type MOS transistor and the source of the P-type MOS transistor respectively, the drain of the N-type MOS transistor and the drain of the P-type MOS transistor are connected to one end of the second capacitor, and the other end of the second capacitor is connected to the output end E of the adjustable switch capacitor.

[0019] Furthermore, the first inverter and the second inverter employ an inverting amplifier with the same structure; the inverting amplifier comprises a second N-type MOS transistor and a second P-type MOS transistor, the VDD power supply is connected to the source of the second P-type MOS transistor, and the source of the second N-type MOS transistor is grounded (GND); the input end of the inverting amplifier is respectively connected to the gates of the second N-type MOS transistor and the second P-type MOS transistor, and the drains of the second N-type MOS transistor and the second P-type MOS transistor are connected to the output end of the inverting amplifier.

[0020] Furthermore, optional capacitance values of the adjustable switched capacitor include 60p, 30p, 15p, and 7.5p.

[0021] The present invention adopts the above technical solution to provide an active multi-phase filter with adjustable suppression frequency that has the functions of phase balance and signal loss compensation at a low intermediate frequency. By selecting the value of the adjustable switch capacitor to be 60p, 30p, 15p and 7.5p, the suppression frequency of the multi-phase filter can be changed to 10MHz, 20MHz, 40MHz, and 80MHz. When the suppression frequency is 10MHz, 20MHz, 40MHz, and 80MHz, the phase error of the synthesized orthogonal signal can be maintained within plus or minus 3 degrees within a bandwidth of 8MHz to 40MHz, 16MHz to 80MHz, 30MHz to 165MHz, and 78MHz to 600MHz, respectively, which is a significant improvement over the bandwidth range of the phase error of traditional multi-phase filters. In addition, by adding an inverting amplifier to the RC filter network, the signal amplitude lost through the filter network can be compensated, and compared with traditional multi-phase filters, the access of the post-stage signal amplifier circuit at the output end can be eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments;

[0023] Figure 1 This is a circuit principle block diagram of a CMOS active polyphase filter with adjustable suppression frequency according to the present invention;

[0024] Figure 2 Schematic diagram of the circuit structure of the RC filter unit of the present invention;

[0025] Figure 3 Schematic diagram of the circuit structure of the adjustable switched capacitor of the present invention;

[0026] Figure 4 Schematic diagram of the circuit structure of the inverting amplifier of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0028] like Figures 1 to 4 As shown in FIG1 , the present invention discloses a CMOS active multiphase filter with adjustable suppression frequency, comprising four RCRC filter circuits arranged in parallel, each RC filter circuit comprising two or more RC filter units connected in series.

[0029] Each RC filter unit has an input terminal A, an input terminal B, and an output terminal C. The output terminal C of the previous stage RC filter unit in the same RC filter circuit is connected to the input terminal A of the next stage RC filter unit. The input terminal A of the first stage RC filter unit in the RC filter circuit is connected to a signal input terminal; the output terminal C of the last stage RC filter unit in the RC filter circuit is connected to the signal output terminal.

[0030] The input terminal A of the first-stage RC filter unit in the four-way RC filter circuit is respectively connected to the positive input terminal of the I-way signal, the positive input terminal of the Q-way signal, the negative input terminal of the I-way signal, and the negative input terminal of the Q-way signal;

[0031] The output terminal C of the last-stage RC filter unit of the first RC filter circuit and the second RC filter circuit is connected to the positive output terminal of the signal; the output terminal C of the last-stage RC filter unit of the third RC filter circuit and the fourth RC filter circuit is connected to the negative output terminal of the signal;

[0032] The input end A of each RC filter unit of each RC filter circuit is connected to the input end B of the RC filter unit of the corresponding stage of the previous RC filter circuit in parallel sequence; the previous RC filter circuit corresponding to the first RC filter circuit is the fourth RC filter circuit.

[0033] That is, the input terminal A of each RC filter unit of the first RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the fourth RC filter circuit;

[0034] The input terminal A of each RC filter unit of the second RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the first RC filter circuit;

[0035] The input terminal A of each RC filter unit of the third RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the second RC filter circuit;

[0036] The input terminal A of each RC filter unit of the fourth RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the third RC filter circuit;

[0037] Furthermore, each RC filter circuit has three RC filter units.

[0038] Furthermore, each RC filter unit includes a resistor R, a first inverter, a first adjustable switched capacitor, and a second adjustable switched capacitor; the input end A of the RC filter unit is respectively connected to the input end of the first inverter and one end of the resistor R, and the output end of the first inverter and the other end of the resistor R are connected to one end of the second adjustable switched capacitor; the input end B of the RC filter unit is connected to the input end D of the first adjustable switched capacitor; the output end E of the first adjustable switched capacitor and the second adjustable switched capacitor are connected to the output end C of the RC filter unit.

[0039] Furthermore, the first adjustable switch capacitor and the second adjustable switch capacitor use the same adjustable switch capacitor, and the adjustable switch capacitor includes four inverter units, each inverter unit includes a second inverter, a first capacitor, a second capacitor, an N-type MOS transistor, and a P-type MOS transistor; one end of the first capacitor of all inverter units is connected to the input terminal D of the adjustable switch capacitor;

[0040] The input end of the second inverter is connected to a control input end and the gate of the N-type MOS transistor, and the output end of the second inverter is connected to the gate of the P-type MOS transistor; the other end of the first capacitor is connected to the source of the N-type MOS transistor and the source of the P-type MOS transistor respectively, the drain of the N-type MOS transistor and the drain of the P-type MOS transistor are connected to one end of the second capacitor, and the other end of the second capacitor is connected to the output end E of the adjustable switch capacitor.

[0041] Furthermore, the first inverter and the second inverter employ an inverting amplifier with the same structure; the inverting amplifier comprises a second N-type MOS transistor and a second P-type MOS transistor, the VDD power supply is connected to the source of the second P-type MOS transistor, and the source of the second N-type MOS transistor is grounded (GND); the input end of the inverting amplifier is respectively connected to the gates of the second N-type MOS transistor and the second P-type MOS transistor, and the drains of the second N-type MOS transistor and the second P-type MOS transistor are connected to the output end of the inverting amplifier.

[0042] Furthermore, optional capacitance values of the adjustable switched capacitor include 60p, 30p, 15p, and 7.5p.

[0043] The specific principle of the present invention is described in detail below:

[0044] The circuit diagram of the active multiphase filter with adjustable suppression frequency proposed by the present invention is as follows: Figure 1 As shown, it consists of 12 RC filter units RC11~34, each RC module has three ports A, B, and C; the A end of RC_11 is connected to the B end of RC_14 and the signal input terminal I+, the B end is connected to the A end of RC_12 and the signal input terminal Q+, and the C end is connected to the A end of RC_21 and the B end of RC_24; the B end of RC_12 is connected to the A end of RC_13 and the signal input terminal I-, and the C end is connected to the A end of RC_22 and the B end of RC_21; the B end of RC_13 is connected to the A end of RC_14 and the signal input terminal Q-, and the C end is connected to the A end of RC_23 and the B end of RC_22; the C end of RC_14 Connect the A end of RC_24 and the B end of RC_23; the C end of RC_21 is connected to the A end of RC31 and the B end of RC_34; the C end of RC_22 is connected to the A end of RC_32 and the B end of RC_31; the C end of RC_23 is connected to the A end of RC_33 and the B end of RC_32; the C end of RC_24 is connected to the A end of RC_34 and the B end of RC_33; the C end of RC_31 is connected to the output signal terminal Out+ and the C end of RC_32; the C end of RC_33 is connected to the output signal terminal Out- and the C end of RC_34; therefore, the proposed active multi-phase filter with adjustable suppression frequency is a three-stage cascade structure.

[0045] The circuit structure of each RC filter unit is as follows Figure 2 As shown, it mainly consists of three parts: a resistor, an inverter, and an adjustable switched capacitor. The output of inverter Inverter_1 is connected to one end of resistor R and port A, and the output is connected to the D terminal of adjustable switched capacitor Cvar_1 and the other end of resistor R. The D terminal of adjustable switched capacitor Cvar_2 is connected to port B, and the E terminal is connected to the E terminal of adjustable switched capacitor Cvar_2 and port C. Resistor R serves as the resistor that determines the rejection frequency in the RC filter unit. Inverter_1, together with resistor R, forms an inverting amplifier to provide gain to the signal passing through the filter unit to compensate for transmission signal loss. The adjustable switched capacitor Cvar_1, connected in parallel with the resistor, serves as the capacitor that determines the rejection frequency in the RC filter network, and together with the resistor, determines the rejection image frequency of this stage's circuit. Another adjustable switched capacitor, Cvar_2, connected in series with the resistor, isolates the bias DC in the inverter to prevent it from flowing into the parallel branch of the filter unit. Therefore, the circuit structure of the present invention determines the suppression of the image frequency by selecting and controlling the size of the adjustable switch capacitor, and the introduction of the inverting amplifier active device compensates for signal loss and phase balance, thereby effectively improving the operating bandwidth of the polyphase filter.

[0046] The circuit structure of the adjustable switched capacitor Cvar is as follows: Figure 3As shown, it consists of four inverters Inverter_2 to Inverter_5, two capacitors C1, two capacitors C2, two capacitors C3, two capacitors C4, NMOS transistors N1 to N4, and PMOS transistors P1 to P4. Among them, the sizes of capacitors C1 and C2 are equal, the sizes of capacitors C3 and C4 are equal, the sizes of capacitors C5 and C6 are equal, and the sizes of capacitors C7 and C8 are equal. The gate of MOS transistor N1 is connected to the input terminal and control input terminal of inverter Inverter_2. ON_1, the drain is connected to one end of the capacitor C1 on the right and the drain of the MOS transistor P1, and the source is connected to one end of the capacitor C2 on the left and the source of the MOS transistor P1; the gate of the MOS transistor N2 is connected to the input of the inverter Inverter_3 and the control input terminal ON_2, the drain is connected to one end of the capacitor C3 on the right and the drain of the MOS transistor P2, and the source is connected to one end of the capacitor C4 on the right and the source of the MOS transistor P2; the gate of the MOS transistor N3 is connected to the input of the inverter Inverter_4 and the control input terminal ON _3, the drain is connected to one end of the capacitor C5 on the right and the drain of the MOS transistor P3, the source is connected to one end of the capacitor C6 on the left and the source of the MOS transistor P3; the gate of the MOS transistor N4 is connected to the input end of the inverter Inverter_5 and the control input end ON_4, the drain is connected to one end of the capacitor C7 on the right and the drain of the MOS transistor P4, the source is connected to one end of the capacitor C8 on the left and the source of the MOS transistor P4; the gate of the MOS transistor P1 is connected to the output end of the inverter Inverter_2; the gate of the MOS transistor P2 is connected to the input end of the inverter Inverter_5 and the control input end ON_4. Connect the output terminal of inverter Inverter_3; the gate of MOS transistor P3 is connected to the output terminal of inverter Inverter_4; the gate of MOS transistor P4 is connected to the output terminal of inverter Inverter_5; the other ends of capacitors C1, C3, C5, and C7 are connected to the input signal terminal D; the other ends of capacitors C2, C4, C6, and C8 are connected to the output signal terminal E. By inputting a high level or a low level to the four control input terminals ON_1 to 4, the value of the adjustable switch capacitor Cvar can be obtained as follows:

[0047] Cvar=∑(C 2X-1 ) / twenty one)

[0048] Where X is the control input terminal ON_X for inputting a high level (X is numbered 1, 2, 3, or 4).

[0049] Therefore, the circuit suppression frequency fimge is:

[0050] fimage=2πRCvar (2)

[0051] Where R is the suppression resistor R in the RC filter network, and Cvar is the size of the adjustable switch capacitor.

[0052] In addition, the inverting amplifier composed of the inverter and the resistor has a signal amplification function, and the voltage gain of the RC filter network can be obtained as:

[0053]

[0054] Where Va is the voltage at terminal A, Vc is the voltage at terminal B, ZC is the output impedance at terminal C, R is the suppression resistor R in the RC filter network, and Cvar is the size of the adjustable switch capacitor.

[0055] The circuit structure of the inverting amplifier is shown in the figure below: Figure 4 As shown, it is composed of an NMOS transistor N5 and a PMOS transistor P5; the gate of the MOS transistor P5 is connected to the gate of the MOS transistor N5 and the signal input terminal in, the drain is connected to the drain of the MOS transistor N5 and the signal output terminal out, and the source is connected to the power supply VDD; the source of the MOS transistor N5 is grounded GND.

[0056] The present invention adopts the above technical solution to provide an active multi-phase filter with adjustable suppression frequency that has the functions of phase balance and signal loss compensation at a low intermediate frequency. By selecting the value of the adjustable switch capacitor to be 60p, 30p, 15p and 7.5p, the suppression frequency of the multi-phase filter can be changed to 10MHz, 20MHz, 40MHz, and 80MHz. When the suppression frequency is 10MHz, 20MHz, 40MHz, and 80MHz, the phase error of the synthesized orthogonal signal can be maintained within plus or minus 3 degrees within a bandwidth of 8MHz to 40MHz, 16MHz to 80MHz, 30MHz to 165MHz, and 78MHz to 600MHz, respectively, which is a significant improvement over the bandwidth range of the phase error of traditional multi-phase filters. In addition, by adding an inverting amplifier to the RC filter network, the signal amplitude lost through the filter network can be compensated, and compared with traditional multi-phase filters, the access of the post-stage signal amplifier circuit at the output end can be eliminated.

[0057] Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

Claims

1. A CMOS active polyphase filter with adjustable suppression frequency, characterized in that: It includes four RC filter circuits arranged in parallel, each RC filter circuit includes two or more RC filter units connected in series. Each RC filter unit has an input terminal A, an input terminal B, and an output terminal C. The output terminal C of the previous stage RC filter unit in the same RC filter circuit is connected to the input terminal A of the next stage RC filter unit. The input terminal A of the first stage RC filter unit in the RC filter circuit is connected to a signal input terminal; the output terminal C of the last stage RC filter unit in the RC filter circuit is connected to the signal output terminal. The input terminal A of the first-stage RC filter unit in the four-way RC filter circuit is respectively connected to the positive input terminal of the I-way signal, the positive input terminal of the Q-way signal, the negative input terminal of the I-way signal, and the negative input terminal of the Q-way signal; The output terminals C of the RC filter units of the last stage of the first RC filter circuit and the last stage of the second RC filter circuit are both connected to the positive output terminal of the signal; the output terminals C of the RC filter units of the last stage of the third RC filter circuit and the last stage of the fourth RC filter circuit are both connected to the negative output terminal of the signal; The input terminal A of each RC filter unit of each RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the previous RC filter circuit in parallel sequence; the input terminal A of each RC filter unit of the first RC filter circuit is connected to the input terminal B of the RC filter unit of the corresponding stage of the fourth RC filter circuit; Each RC filter unit includes a resistor R, a first inverter, a first adjustable switched capacitor, and a second adjustable switched capacitor; an input terminal A of the RC filter unit is respectively connected to the input terminal of the first inverter and one end of the resistor R, and an output terminal of the first inverter and the other end of the resistor R are connected to one end of the second adjustable switched capacitor; an input terminal B of the RC filter unit is connected to an input terminal D of the first adjustable switched capacitor; and output terminals E of the first adjustable switched capacitor and the second adjustable switched capacitor are connected to an output terminal C of the RC filter unit; The first adjustable switched capacitor and the second adjustable switched capacitor use the same adjustable switched capacitor. The adjustable switched capacitor includes four inverter units. Each inverter unit includes a second inverter, a first capacitor, a second capacitor, an N-type MOS transistor, and a P-type MOS transistor. One end of the first capacitor of all inverter units is connected to the input terminal D of the adjustable switched capacitor. The input end of the second inverter is connected to a control input end and the gate of the N-type MOS transistor, and the output end of the second inverter is connected to the gate of the P-type MOS transistor; the other end of the first capacitor is connected to the source of the N-type MOS transistor and the source of the P-type MOS transistor respectively, the drain of the N-type MOS transistor and the drain of the P-type MOS transistor are connected to one end of the second capacitor, and the other end of the second capacitor is connected to the output end E of the adjustable switch capacitor.

2. The CMOS active polyphase filter with adjustable suppression frequency according to claim 1, wherein: Each RC filter circuit has three RC filter units.

3. The CMOS active polyphase filter with adjustable suppression frequency according to claim 2, wherein: The first inverter and the second inverter use an inverting amplifier with the same structure; the inverting amplifier includes a second N-type MOS transistor and a second P-type MOS transistor, the VDD power supply is connected to the source of the second P-type MOS transistor, and the source of the second N-type MOS transistor is grounded (GND); the input end of the inverting amplifier is respectively connected to the gate of the second N-type MOS transistor and the second P-type MOS transistor, and the drain of the second N-type MOS transistor and the second P-type MOS transistor is connected to the output end of the inverting amplifier.

4. The CMOS active polyphase filter with adjustable suppression frequency according to claim 1, wherein: The capacitance values of the first adjustable switched capacitor or the second adjustable switched capacitor include 60p, 30p, 15p and 7.5p.

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