Three-dimensional AND flash memory device and manufacturing method thereof

Abstract

The present disclosure provides a three-dimensional AND flash memory device, comprising: a gate stack structure disposed on a dielectric substrate, wherein the gate stack structure comprises a plurality of gate layers and a plurality of insulating layers alternately stacked; a plurality of channel pillars passing through the gate stack structure; a plurality of first conductive pillars and a plurality of second conductive pillars disposed within and electrically connected to the plurality of channel pillars; a plurality of charge storage structures disposed between the plurality of gate layers and the channel pillars; and a plurality of isolation walls embedded in the plurality of gate layers, the plurality of isolation walls enclosing the plurality of charge storage structures on the outer sidewalls of the plurality of second conductive pillars.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a three-dimensional AND flash memory device and a manufacturing method thereof. Background Art

[0002] Non-volatile memory has the advantage of ensuring that stored data persists even after a power outage, and is therefore widely used in personal computers and other electronic devices. Currently, the most commonly used three-dimensional memories include NOR memory and NAND memory. Another type of three-dimensional memory is AND memory, which can be used in multi-dimensional memory arrays, offering high integration and area efficiency, as well as fast operation speeds. Therefore, the development of three-dimensional memory devices has become a trend.

[0003] Public content

[0004] The present disclosure provides a three-dimensional AND flash memory device and a manufacturing method thereof, which can reduce drain-induced gate leakage current.

[0005] One embodiment of the present disclosure provides a three-dimensional AND flash memory device, comprising: a gate stack structure disposed on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked; a plurality of channel pillars extending through the gate stack structure; a plurality of first conductive pillars and a plurality of second conductive pillars disposed within and electrically connected to the plurality of channel pillars; a plurality of charge storage structures disposed between the plurality of gate layers and the channel pillars; and a plurality of isolation walls embedded in the plurality of gate layers, the plurality of isolation walls enclosing the plurality of charge storage structures at the outer edges of the plurality of second conductive pillars.

[0006] One embodiment of the present disclosure provides a three-dimensional AND flash memory device, comprising: a gate stack structure located on a dielectric substrate, wherein the gate stack structure includes multiple gate layers and multiple insulating layers alternately stacked one on another; multiple channel pillars passing through the gate stack structure; multiple source pillars and multiple drain pillars located within and in contact with the multiple channel pillars; and multiple charge storage structures located between the multiple gate layers and the channel pillars, wherein sidewalls of the multiple gate layers do not contact sidewalls of a first portion of the multiple charge storage structures, and the sidewalls of the first portion of the multiple charge storage structures cover the multiple channel pillars in contact with the multiple drain pillars.

[0007] One embodiment of the present disclosure provides a method for manufacturing a three-dimensional AND flash memory device, comprising: forming a stacked structure on a dielectric substrate, wherein the stacked structure includes a plurality of sacrificial layers and a plurality of insulating layers alternately stacked on each other; forming a plurality of channel pillars extending through the stacked structure; forming a plurality of first conductive pillars and a plurality of second conductive pillars within the plurality of channel pillars and electrically connected to the plurality of channel pillars; partially removing the plurality of sacrificial layers to form a plurality of horizontal openings, wherein the unremoved portions of the plurality of sacrificial layers form a plurality of isolation walls; the plurality of isolation walls have a curved shape; forming a plurality of gate layers in the plurality of horizontal openings; and forming a plurality of charge storage structures located between the plurality of gate layers and the channel pillars, the plurality of isolation walls enclosing the plurality of charge storage structures at the outer edges of the plurality of second conductive pillars.

[0008] Based on the above, in the embodiment of the present disclosure, the isolation wall is wrapped around the drain column, so that the gate layer does not overlap with the drain column, thereby reducing the drain-induced gate leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A circuit diagram illustrating a 3D AND flash memory array according to some embodiments is shown.

[0010] Figure 1B A top view of a 3D AND flash memory array is shown in accordance with some embodiments.

[0011] Figure 1C Show Figure 1B A partial 3D view of a simplified portion of the storage array.

[0012] Figure 1D and Figure 1E Show Figure 1C Cross-sectional view of the tangent line I-I'.

[0013] Figure 1F Show Figure 1C 、 Figure 1D and Figure 1E Top view of the tangent line II-II'.

[0014] Figure 1G To follow Figure 1F Schematic cross-section of the midline V-V'.

[0015] Figures 2A to 2I is a schematic cross-sectional view of a three-dimensional AND flash memory device according to an embodiment of the present disclosure. Figure 2D 、 Figure 2E 、 Figure 2G 、 Figure 2H and Figure 2I for Figures 3A to 3E Sectional view along the line IV-IV'.

[0016] Figures 3A to 3E Show Figure 2D 、 Figure 2E 、 Figure 2G 、 Figure 2H and Figure 2I Top view of the tangent line III-III'.

[0017] Figures 4A to 4D 1 is a top view of various memory cells according to an embodiment of the present disclosure.

[0018] Figures 5A to 5C 1 is a top view of various memory arrays according to embodiments of the present disclosure.

[0019] Figure 6 FIG. 4 is a cross-sectional view of a three-dimensional AND flash memory device according to an embodiment of the present disclosure.

[0020] Description of Reference Numerals

[0021] 10: Storage Array

[0022] 12, 112: Charge storage layer

[0023] 14, 114: Tunneling layer

[0024] 16, 116: Channel column

[0025] 16R1: First channel column

[0026] 16R2: Second channel column

[0027] 20: Storage unit

[0028] 24, 124: Insulation filling layer

[0029] 28, 128: Insulation column

[0030] 132a, 136b: Conductor columns

[0031] 32a: Source column / conductor column

[0032] 32b: Drain column / conductor column

[0033] 36, 136: barrier layer

[0034] 38, 138: Gate layer / word line

[0035] 38E: End

[0036] 38W, 40W1, 40W2, 56W: sidewall

[0037] 40, 140: Charge storage structure

[0038] 50, 100: dielectric substrate

[0039] 52, 150: Gate stack structure

[0040] 54, 104: Insulation layer

[0041] 56, 156: Separation Wall

[0042] 60: Arrow

[0043] 102, 102': laminated structure

[0044] 106, 106a: Sacrificial layer

[0045] 108: Opening

[0046] 110: Protective layer

[0047] 112': Storage material layer

[0048] 114': Tunneling material layer

[0049] 116R1, 116R2: channel column

[0050] 116': Channel material layer

[0051] 118: Virtual Column

[0052] 122: Protective cover

[0053] 124: Insulation filling layer

[0054] 130a, 130b: hole

[0055] 133: Separation channel

[0056] 134: Horizontal opening

[0057] 137: Barrier layer

[0058] 138: Gate layer

[0059] AR: Array Area

[0060] A (i) 、A (i+1) : Storage Array

[0061] B、B1、B2、BLOCK、BLOCK (i) 、BLOCK (i+1) : Block

[0062] SP (i) n 、SP (i) n+1 、SP (i+1) n、SP (i+1) n+1 :Source column

[0063] DP (i) n , DP i) n+1 , DP i+1) n , DP (i+1) n+1 :Source column

[0064] BL n BL n+1 : Bit line

[0065] WL (i) m 、WL (i) m+1 、WL (i+1) m 、WL (i+1) m+1 :Word line

[0066] C1: Contact window

[0067] D1: Distance

[0068] L1, L2: length

[0069] SC: ladder structure

[0070] SLT: Dividing Wall

[0071] SR: Step Area

[0072] W1, W2: width

[0073] X, Y, Z: direction

[0074] I-I', II-II', III-III', IV-IV', V-V': tangent line

[0075] S1: length of the first chord

[0076] S2: Length of the second string DETAILED DESCRIPTION

[0077] Figure 1A A circuit diagram illustrating a 3D AND flash memory array according to some embodiments is shown. Figure 1B A top view of a 3D AND flash memory array is shown in accordance with some embodiments. Figure 1C Show Figure 1B A partial 3D view of a simplified portion of the storage array. Figure 1D and Figure 1E Show Figure 1CCross-sectional view of the tangent line I-I'. Figure 1F Show Figure 1C 、 Figure 1D and Figure 1E Top view of the tangent line II-II'. Figure 1G To follow Figure 1F Schematic cross-section of the midline V-V'.

[0078] Figure 1A The vertical AND memory array 10 includes two blocks arranged in rows and columns. (i) With BLOCK (i+1) Schematic diagram of the block. (i) Including storage array A (i) Storage Array A (i) A row (for example, the m+1th row) has a common word line (for example, WL (i) m+1 ) of AND storage cells 20. Storage array A (i) Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i) m+1 ) and coupled to different source columns (eg SP (i) n With SP (i) n+1 ) and the drain column (eg DP (i) n With DP (i) n+1 ), so that the AND memory cell 20 is along a common word line (eg WL (i) m+1 ) are logically arranged into a column.

[0079] Storage array A (i) A row (eg, the nth row) has a common source column (eg, SP (i) n ) and a common drain column (such as DP (i) n ) of AND storage cells 20. Storage array A (i) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i) m+1 With WL (i) m ) and coupled to a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). Therefore, storage array A (i)AND memory cell 20 along a common source column (eg SP (i) n ) and a common drain column (such as DP (i) n ) are logically arranged in a row. In the physical layout, depending on the fabrication method used, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.

[0080] exist Figure 1A In the block BLOCK (i) In the storage array A (i) The AND memory cells 20 in the nth row share a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). The AND storage cells 20 in the n+1th row share a common source column (eg SP (i) n+1 ) with a common drain column (e.g. DP (i) n+1 ).

[0081] Common source column (such as SP (i) n ) is coupled to a common source line (eg, SL n ); a common drain column (eg DP (i) n ) is coupled to a common bit line (eg, BL n ). Common source column (such as SP (i) n+1 ) is coupled to a common source line (eg, SL n+1 ); a common drain column (eg DP (i) n+1 ) is coupled to a common bit line (eg, BL n+1 ).

[0082] Similarly, BLOCK (i+1) Including storage array A (i+1) , which is the same as in the block BLOCK (i) Storage array A in (i) Storage array A (i+1) A row (for example, the m+1th row) has a common word line (for example, WL (i+1) m+1 ) of AND storage cells 20. Storage array A (i+1) Each column (eg, the m+1th column) of AND memory cells 20 corresponds to a common word line (eg, WL (i+1) m+1) and coupled to different source columns (eg SP (i+1) n With SP (i+1) n+1 ) and the drain column (eg DP (i+1) n With DP (i +1) n+1 Storage array A (i+1) A row (eg, the nth row) has a common source column (eg, SP (i+1) n ) and a common drain column (such as DP (i+1) n ) of AND storage cells 20. Storage array A (i+1) Each row (eg, the nth row) of AND storage cells 20 corresponds to a different word line (eg, WL (i+1) n+1 With WL (i+1) m ) and coupled to a common source column (eg SP (i+1) n ) with a common drain column (e.g. DP (i+1) n ). Therefore, storage array A (i+1) AND memory cell 20 along a common source column (eg SP (i +1) n ) and a common drain column (such as DP (i+1) n ) are logically configured into one row.

[0083] BLOCK (i+1) With BLOCK (i) Shared source line (eg SL n With SL n+1 ) and bit lines (such as BL n With BL n+1 ). Therefore, the source line SL n and bit line BL n Coupled to block BLOCK (i) AND storage array A (i) The nth row of AND memory cells 20 is coupled to the block BLOCK (i+1) AND storage array A in (i+1) The nth row of AND memory cells 20. Similarly, the source line SL n+1 and bit line BL n+1 Coupled to block BLOCK (i) AND storage array A (i)The AND memory cell 20 in the n+1th row is coupled to the block BLOCK (i+1) AND storage array A in (i+1) The AND storage unit 20 in the n+1th row.

[0084] Please refer to Figures 1B to 1D The memory array 10 may include multiple blocks, such as block B1 and block B2. A partition wall SLT separates the gate stack structures 52 of two adjacent blocks B1 and B2. The partition wall SLT is made of an insulating material. The insulating material may include an organic insulating material, an inorganic insulating material, or a combination thereof. Each block B1 and B2 may include a gate stack structure 52 disposed on a dielectric substrate 50, a plurality of channel pillars 16, a plurality of first conductive pillars (also referred to as source pillars) 32a, a plurality of second conductive pillars (also referred to as drain pillars) 32b, and a plurality of charge storage structures 40.

[0085] Please refer to Figure 1D The memory array 10 may be disposed on an interconnect structure of a semiconductor die, such as one or more active devices (e.g., transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer formed on a metal interconnect structure on a silicon substrate, such as a silicon oxide layer. The dielectric substrate 50 may include an array region AR and a stepped region SR (e.g., Figure 1B shown).

[0086] Please refer to Figure 1B and Figure 1C The gate stack structure 52 is formed on the dielectric substrate 50 in the array region AR and the step region SR. The gate stack structure 52 includes a plurality of gate layers (also called word lines) 38 vertically stacked on the surface of the dielectric substrate 50 and a plurality of insulating layers 54 (such as Figure 1D and Figure 1E In the Z direction, the gate layers 38 are electrically isolated by an insulating layer 54 disposed between them. The gate layers 38 are electrically isolated from the dielectric substrate 50 (shown in FIG. Figure 1D ) extends in a direction parallel to the surface. Figure 1B As shown, the gate layer 38 in the step region SR may have a step structure SC. Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Figure 1B As shown, the contact window C1 for connecting the gate layer 38 can land at the end of the gate layer 38, thereby connecting each gate layer 38 to each wire.

[0087] Please refer to Figures 1B to 1EThe memory array 10 further includes a plurality of channel pillars 16. The channel pillars 16 continuously extend through the gate stack structure 52 of the array region AR. In some embodiments, the channel pillars 16 may have a ring shape (e.g., Figure 1B As shown in FIG. 1 , the material of the channel pillar 16 may be a semiconductor, such as undoped polysilicon.

[0088] Please refer to Figures 1C to 1E The memory array 10 further includes an insulating filling layer 24, an insulating pillar 28, a plurality of first conductor pillars 32a, and a plurality of second conductor pillars 32b. In this example, the first conductor pillar 32a serves as a source pillar; the second conductor pillar 32b serves as a drain pillar. The first conductor pillar 32a, the second conductor pillar 32b, and the insulating pillar 28 are disposed within the channel pillar 16 and each extend in a direction perpendicular to the gate layer 38 (i.e., the Z direction). The first conductor pillar 32a and the second conductor pillar 32b are separated by the insulating filling layer 24 and the insulating pillar 28. The first conductor pillar 32a and the second conductor pillar 32b are electrically connected to the channel pillar 16. The first conductor pillar 32a and the second conductor pillar 32b include doped polysilicon or metal material. The insulating pillar 28 is, for example, silicon nitride.

[0089] Please refer to Figure 1D and Figure 1E At least a portion of the charge storage structure 40 is disposed between the channel pillar 16 and the multi-layer gate layer 38. The charge storage structure 40 may include a tunneling layer (or a gap-engineered tunneling oxide layer) 14, a charge storage layer 12, and a blocking layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the blocking layer 36. In some embodiments, the tunneling layer 14 and the blocking layer 36 comprise silicon oxide. The charge storage layer 12 comprises silicon nitride, or other materials that can capture charge. In some embodiments, such as Figure 1D As shown, a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), while another portion of the charge storage structure 40 (the blocking layer 36) surrounds the gate layer 38. In other embodiments, such as Figure 1E As shown, the charge storage structure 40 (tunneling layer 14 , charge storage layer 12 and blocking layer 36 ) surrounds the gate layer 38 .

[0090] Please refer to Figure 1FThe charge storage structure 40, channel pillar 16, and source and drain pillars 32a and 32b are surrounded by a gate layer 38 and define a memory cell 20. The memory cell 20 can be operated in a single-bit or dual-bit manner using various operation methods. For example, when a voltage is applied to the source and drain pillars 32a and 32b, electrons can be transferred along the channel pillars 16 and stored in the charge storage structure 40 because the source and drain pillars 32a and 32b are connected to the channel pillar 16, thereby enabling a single-bit operation of the memory cell 20. Furthermore, for operation utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source and drain pillars 32a and 32b. For source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection operations, electrons or holes can be locally trapped in the charge storage structure 40 adjacent to one of the two source pillars 32 a and drain pillars 32 b. This allows the memory cell 20 to operate as a single-level cell (SLC, 1 bit) or a multi-level cell (MLC, greater than or equal to 2 bits).

[0091] When operating, a voltage is applied to the selected word line (gate layer) 38, for example, a voltage higher than the corresponding starting voltage (V th ), the channel region of the channel column 16 intersecting the selected word line 38 is turned on, allowing current to flow from the bit line BL n or BL n+1 (Shown in Figure 1C ) enters the drain column 32b and flows through the conductive channel region to the source column 32a (eg, in the direction indicated by arrow 60), and finally flows to the source line SL n or SL n+1 (Shown in Figure 1C ).

[0092] However, if the gate layer 38 surrounds and covers the drain column 32b, it is easy to cause drain-induced gate leakage current. In the embodiment of the present disclosure, an isolation wall 56 is buried in the gate layer 38, so that the gate layer 38 will not cover the drain column 32b, thereby reducing or avoiding drain-induced gate leakage current.

[0093] Please refer to Figure 1B The gate layer 38 is a sacrificial layer (similar to that shown in FIG. Figure 2GIn the present disclosure, a portion of the plurality of sacrificial layers is left to form a plurality of isolation walls 56 (similar to the one shown in FIG. Figure 2G Multiple isolation walls 156). Each isolation wall 56 extends in the X direction, separating the multiple channel columns 16 in each block B into a first column of channel columns 16R1 and a second column of channel columns 16R2. The isolation wall 56 and the partition wall SLT both extend in the X direction. The partition wall SLT is continuously extended. The isolation wall 56 can be continuously extended or discontinuously extended. The length L1 of the partition wall SLT in the X direction is greater than or equal to the length L2 of the isolation wall 56 in the X direction. Furthermore, the isolation wall 56 and the partition wall SLT have different shapes. From a top view, the partition wall SLT is roughly an elongated rectangle, while the isolation wall 56 has a curved shape, such as Figure 1B shown.

[0094] Figure 1G To follow Figure 1F Schematic diagram of the cross section along the midline V-V'. Figure 1F and Figure 1G , the isolation layer 56 is buried in the plurality of gate layers 38, covering and contacting the plurality of charge storage structures 40 on the outer sidewalls of the plurality of drain pillars 32b, as shown in FIG. Figure 1F The contact range of the isolation barrier 56 with the charge storage structure 40 can be controlled by an etching process.

[0095] In this embodiment (such as Figure 1G As shown in FIG. 4 , the sidewall 56W of the isolation wall 56 contacts the sidewall 40W1 of the charge storage structure 40. Figure 1F As shown, a portion of the charge storage structure 40 contacts the isolation wall 56 and covers the portion of the channel column 16 that contacts the drain column 32b. The portion of the channel column 16 contacts the drain column 32b. Figure 1G As shown, end 38E of gate layer 38 does not extend to the portion of sidewall 40W1 of charge storage structure 40 and does not overlap drain pillar 32b. Sidewall 38W of gate layer 38 does not contact the portion of sidewall 40W1 extending to charge storage structure 40. Gate layer 38 and drain pillar 32 do not overlap. Therefore, the electric field between gate layer 38 and drain pillar 32b is reduced, thereby preventing leakage current between channel pillar 16 and drain pillar 32b.

[0096] In one embodiment, if Figure 1FAs shown, each charge storage structure 40 and each channel column 16 have a first chord length S1 and a second chord length S2, respectively, wherein the first chord length S1 is the chord length of the arc surface where each charge storage structure 40 contacts the adjacent isolation wall 56, and the second chord length S2 is the chord length of the arc surface where each channel column 16 contacts the adjacent drain column 32b. In this embodiment, the first chord length S1 is greater than or equal to the second chord length S2. The first chord length S1 is greater than or equal to the second chord length S2, so that the gate layer 38 and the drain column 32b do not overlap (as shown in FIG. 1 ). Figure 1G as shown) to avoid drain-induced gate leakage current.

[0097] The isolation wall 56 and the partition wall SLT are formed by different methods. Figures 2A to 2I as well as Figures 3A to 3E Detailed description. Figures 2A to 2I is a schematic cross-sectional view of a three-dimensional AND flash memory device according to an embodiment of the present disclosure. Figure 2D 、 Figure 2E 、 Figure 2G 、 Figure 2H and Figure 2I for Figures 3A to 3E Sectional view along the line IV-IV'. Figures 3A to 3E Show Figure 2D 、 Figure 2E 、 Figure 2G 、 Figure 2H and Figure 2I Top view of the tangent line III-III'.

[0098] Please refer to Figure 2A , providing a dielectric substrate 100. The dielectric substrate 100 is, for example, a dielectric layer having a metal interconnect structure formed on a silicon substrate, such as a silicon oxide layer. The dielectric substrate 100 includes an array region AR and a step region SR. A stacked structure 102' is formed on the dielectric substrate 100 in the array region AR and the step region SR. The stacked structure 102' can also be referred to as an insulating stacked structure 102'. In this embodiment, the stacked structure 102' is composed of an insulating layer 104 and a sacrificial layer 106 that are sequentially stacked on the dielectric substrate 100. In other embodiments, the sacrificial layer 106 and the insulating layer 104 are stacked on the dielectric substrate 100 in an opposite order. In addition, in this embodiment, the top layer of the stacked structure 102' is the insulating layer 104. The insulating layer 104 is, for example, a silicon oxide layer. The sacrificial layer 106 is, for example, a silicon nitride layer. In this embodiment, the stacked structure 102 ′ has three pairs of insulating layers 104 and sacrificial layers 106 , but the present disclosure is not limited thereto. In other embodiments, more pairs of insulating layers 104 and sacrificial layers 106 may be formed according to actual needs.

[0099] The stacked structure 102' is patterned to form a stepped structure SC (eg, Figure 3Ashown).

[0100] Next, please refer to Figure 2A and Figure 3A , a plurality of openings 108 are formed in the stacked structure 102' of the array region AR, however, Figure 2A Only a single opening 108 is shown. In this embodiment, the bottom surface of the opening 108 exposes the dielectric substrate 100, but the present disclosure is not limited thereto.

[0101] In other embodiments, when the bottom layer of the stacked structure 102' is the insulating layer 104, the bottom of the opening 108 may be located in the bottom insulating layer 104, that is, the bottom surface of the opening 108 exposes the bottom insulating layer 104 without exposing the dielectric substrate 100. Alternatively, in other embodiments, the bottom of the opening 108 further extends into the dielectric substrate 100. In this embodiment, the opening 108 has a circular shape when viewed from above, but the present disclosure is not limited thereto. In other embodiments, the opening 108 may have other shapes, such as a polygon (not shown). Thereafter, a thermal oxidation process is performed to oxidize the surface of the sidewalls of the sacrificial layer 106 exposed by the opening 108 to form a protective layer (e.g., an oxide layer) 110.

[0102] Please refer to Figure 2B A storage material layer 112', a tunneling material layer 114', and a channel material layer 116' are formed on the stacked structure 102' and within the opening 108. The storage material layer 112' may be, for example, a silicon nitride layer. The tunneling material layer 114' may be, for example, a silicon oxide layer. The channel material layer 116' may be made of a semiconductor material, such as undoped polysilicon.

[0103] Please refer to Figure 2C An etch-back process is then performed to partially remove the storage material layer 112', the tunneling material layer 114', and the channel material layer 116', thereby forming the charge storage layer 112, the tunneling layer 114, and the channel pillar 116. The charge storage layer 112, the tunneling layer 114, and the channel pillar 116 cover at least a portion of the sidewalls of the opening 108, exposing the bottom of the opening 108. The charge storage layer 112, the tunneling layer 114, and the channel pillar 116 may extend through the stacked structure 102'. The channel pillar 116 may be, for example, annular in shape when viewed from above, and may be continuous in its extension direction (e.g., a direction perpendicular to the dielectric substrate 100). In other words, the channel pillar 116 is integral in its extension direction and is not divided into multiple disconnected portions. In some embodiments, the channel pillar 116 may have a circular shape when viewed from above, but the present disclosure is not limited thereto. In other embodiments, the channel pillar 116 may have other shapes (e.g., polygonal) when viewed from above.

[0104] In this embodiment, the charge storage layer 112 and the tunneling layer 114 are formed in the opening 108. In another embodiment, the charge storage layer 112 and the tunneling layer 114 are formed in the horizontal opening 134 during the gate replacement process. Figure 6 As shown, detailed description will be given later.

[0105] Please refer to Figure 2B and Figure 2C , an insulating filling layer 124 is formed above the stacked structure 102' and in the opening 108. The insulating filling layer 124 on the stacked structure 102' is located above the stacked structure 102' and can also be called an insulating cap layer. The material of the insulating filling layer 124 is, for example, silicon oxide. When the insulating filling layer 124 fills the opening 108, before the center of the opening 108 is completely filled and a hole is left, an insulating material different from the insulating filling layer 124, such as silicon nitride, is filled to completely seal the opening 108. The insulating material is etched back to the surface of the insulating filling layer 124 through a dry etching or wet etching process, and the insulating material left in the center of the opening 108 forms an insulating column 128.

[0106] Please refer to Figure 2D A patterning process is performed to form holes 130a and 130b in the insulating filling layer 124. The holes 130a and 130b extend from the top surface of the insulating filling layer 124 to the dielectric substrate 100. The shape of the hole pattern defined by the patterning process can be tangential to the shape of the insulating pillar 128. The shape of the hole pattern defined by the patterning process can also exceed the shape of the insulating pillar 128. Because the etching rate of the insulating pillar 128 is lower than the etching rate of the insulating filling layer 124, the insulating pillar 128 is hardly damaged by the etching and remains.

[0107] Please refer to Figure 3A In some embodiments, dummy pillars 118 are further formed in the step region SR. The dummy pillars 118 can serve as support pillars in the subsequent gate replacement process. The dummy pillars 118 can be formed simultaneously when the charge storage layer 112, the tunneling layer 114, the channel pillars 116, the insulating filling layer 124, and the insulating pillars 128 are formed. The dummy pillars 118 can also be formed separately. The number of dummy pillars 118 can be determined as needed. In some embodiments, the dummy pillars 118 in the step region SR are staggered with each other, and the distance D1 between the dummy pillars 118 in the step region SR is greater than or equal to the distance D2 between the channel pillars 116, and its density is lower than the density of the channel pillars 116 in the array region AR.

[0108] Reference Figure 2D and Figure 3A, a first conductor column 132a and a second conductor column 132b are formed in the holes 130a and 130b. The first conductor column 132a and the second conductor column 132b can serve as a source column and a drain column, respectively, and are electrically connected to the channel column 116, respectively. The first conductor column 132a and the second conductor column 132b can be formed by forming a conductor layer on the insulating filling layer 124 and in the holes 130a and 130b, and then forming it by back etching. The first conductor column 132a and the second conductor column 132b are, for example, doped polysilicon. In this embodiment, the second conductor columns (drain columns) 132b of two adjacent columns are adjacent to each other, and the first conductor columns (source columns) 132a of two adjacent columns are far away from each other. The second conductor column (drain column) 132b is arranged at the place farthest away from the subsequently formed separation channel 133 (such as Figure 3E As shown in FIG. 1 , the remaining sacrificial layer 106 a (ie, the isolation wall 156 ) may help wrap around the second conductive post 132 b .

[0109] The radial dimensions of the first conductive post 132a and the second conductive post 132b may be the same (e.g. Figure 4A and Figure 4C shown) or different (as Figure 4B and Figure 4D In some embodiments, the radial dimension of the first conductive pillar 132a serving as the source pillar may be greater than or equal to the radial dimension of the second conductive pillar 132b serving as the drain pillar (as shown in FIG. Figure 4B and Figure 4D The first conductive pillar 132a and the second conductive pillar 132b can be symmetrically arranged with the center line of the channel pillar 116 as the symmetry axis, and arranged along the Y direction (as shown). Figure 4A and Figure 4B The first conductive pillar 132a and the second conductive pillar 132b can be arranged asymmetrically with the center line of the channel pillar 116 as the symmetry axis, that is, the first conductive pillar 132a is offset from the second conductive pillar 132b (as shown). Figure 4C and Figure 4D shown).

[0110] The line connecting the centers of the first conductive post 132a and the second conductive post 132b may be parallel to the Y direction (e.g., Figure 4A and Figure 4B As shown), that is, perpendicular to the partition wall SLT formed subsequently (as shown Figure 3E ), or an acute angle with the Y direction (as shown Figure 4C and Figure 4D In addition, the channel pillars 116 in two adjacent rows may be staggered with each other (as shown in FIG. Figures 3A to 3E as well as Figure 5A ), or aligned with each other (as shown in Figure 5B and Figure 5CThe different radial dimensions of the first conductive pillars 132a and the second conductive pillars 132b, the asymmetric arrangement, and the staggered arrangement of the channel pillars 116 in two adjacent columns all facilitate subsequent wiring.

[0111] Afterwards, refer to Figures 2E to 2G as well as Figures 3B to 3D , a replacement process is performed to replace the multi-layer sacrificial layer 106 with the multi-layer gate layer 138. First, referring to Figure 2E and Figure 3B The stacked structure 102 is patterned to form a plurality of separation trenches 133 therein. The separation trenches 133 extend along the X direction, dividing the stacked structure 102 into a plurality of blocks B.

[0112] Next, please refer to Figure 2F , an etching process, such as a wet etching process, is performed to remove a portion of the multi-layer sacrificial layer 106. Since the etching solution (such as hot phosphoric acid) used in the etching process is injected into the separation trench 133, the contacted portion of the multi-layer sacrificial layer 106 is removed. Therefore, the multi-layer sacrificial layer 106 closer to the separation trench 133 is removed first, while the multi-layer sacrificial layer 106 farther from the separation trench 133 is removed more slowly. During the etching process, when the multi-layer sacrificial layer 106 between the channel pillar 116 and the separation trench 133 is removed, since the protective layer 110 and the sacrificial layer 106 are made of different materials, the protective layer 110 can serve as an etch stop layer to protect the charge storage layer 112 around the channel pillar 116.

[0113] Please refer to Figure 2G and Figure 3C , the etching process is continued, and most of the multi-layer sacrificial layer 106 is removed by controlling the time mode to form a plurality of horizontal openings 134. The density of the dummy columns 118 in the step region SR is low, so the etching rate is high, and the multi-layer sacrificial layer 106 is completely etched. The density of the channel columns 116 in the array region AR is high, the flow rate of the etching liquid is low, and the etching rate is low. The multi-layer sacrificial layer 106a farthest from the separation channel 133 is left behind to form an isolation wall 156. The remaining isolation wall 156 covers the periphery of the conductor column 132b that is farther away from the separation channel 133. The isolation wall 156 divides the multiple channel columns 116 in each block B into two columns of channel columns 116R1 and 116R2, as shown in FIG. Figure 3C The second conductive pillars (drain pillars) 136 b in the two columns of channel pillars 116R1 and 116R2 are adjacent to the isolation wall 156 , while the first conductive pillars (source pillars) 136 a in the two columns of channel pillars 116R1 and 116R2 are away from the isolation wall 156 .

[0114] In addition to being controlled by the etching time, the size of the remaining isolation wall 156 can also be controlled by adjusting the size and density of the dummy columns 118 in the step area SR and the size and density of the channel columns 116 in the array area AR to control the etching rate of the sacrificial layer 106 in the step area SR and the array area AR.

[0115] Please refer to Figure 2H and Figure 3D The protective layer 110 exposed by the multiple horizontal openings 134 is removed. A portion of the protective layer 110 adjacent to the second conductive pillar (drain pillar) 136b is left between the multi-layer sacrificial layer 106a and the charge storage layer 112. A gate material layer is then formed in the multiple isolation trenches 133 and the multiple horizontal openings 134. An etch-back process is then performed to remove the gate material layer in the multiple isolation trenches 133, thereby forming a multi-layer gate layer 138 in the multiple horizontal openings 134. Furthermore, in other embodiments, a blocking material layer and a barrier material layer are sequentially formed in the isolation trenches 133 and the horizontal openings 134 before forming the multi-layer gate layer 138. The blocking material layer may be made of a high-k material with a dielectric constant greater than or equal to 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or combinations thereof. The barrier material layer is made of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. After the barrier material layer and the barrier material layer undergo an etch-back process, a multi-layer barrier layer 136 and a multi-layer barrier layer 137 are formed within the plurality of horizontal openings 134. The barrier layer 137 is located between the barrier layer 136 and the gate layer 138. The multi-layer barrier layer 136, the tunneling layer 114, and the charge storage layer 112 are collectively referred to as a charge storage structure 140. Thus, a gate stack structure 150 is formed. The gate stack structure 150 is disposed on the dielectric substrate 100 and includes a multi-layer gate layer 138 and a multi-layer insulating layer 104 alternately stacked.

[0116] In another embodiment, the charge storage layer 112 and the tunneling layer 114 are not formed in the opening 108, but are formed during the gate replacement process. The tunneling layer 114 and the charge storage layer 112 are first formed in the horizontal opening 134 before forming the gate layer 138. After forming the charge storage layer 112, the blocking layer 136, the barrier layer 137 and the gate layer 138 are formed. Figure 6 shown.

[0117] Please refer to Figure 2I and Figure 3E, forming a separation wall SLT in the separation trench 133. The method for forming the separation wall SLT includes filling an insulating material on the gate stack structure 150 and in the separation trench 133, and then removing excess insulating material on the gate stack structure 150 through an etch-back process or a planarization process. The insulating material is, for example, silicon oxide or silicon nitride.

[0118] Please refer to Figure 3E Then, a contact window C1 is formed in the stepped region SR. The contact window C1 lands at the end of the gate layer 138 in the stepped region SR and is electrically connected thereto.

[0119] The disclosed embodiment embeds an isolation wall within the gate layer, preventing the gate layer from overlapping the drain pillar. This significantly reduces or prevents drain-induced gate leakage current caused by high reverse bias between the gate and drain in the deselected mode. During the gate replacement process, timing control allows a portion of the sacrificial layer to remain as an isolation wall, eliminating the need for additional process steps.

Claims

1. A three-dimensional AND flash memory device, comprising: A gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked with each other; a plurality of channel pillars extending through the gate stack structure; A plurality of first conductive posts and a plurality of second conductive posts are located in the plurality of channel posts and electrically connected to the plurality of channel posts; a plurality of charge storage structures located between the plurality of gate layers and the channel pillars; as well as A plurality of isolation walls are buried in the plurality of gate layers, and the plurality of isolation walls cover the plurality of charge storage structures on the outer sidewalls of the plurality of second conductive pillars.

2. The 3D AND flash memory device according to claim 1 , wherein each charge storage structure and each channel pillar has a first chord length and a second chord length, wherein the first chord length is the chord length of the arc surface of each charge storage structure in contact with an adjacent isolation wall, and the second chord length is the chord length of the arc surface of each channel pillar in contact with an adjacent second conductive pillar, and the first chord length is greater than or equal to the second chord length. 3 . The three-dimensional AND flash memory device according to claim 1 , wherein the plurality of isolation walls have a curved shape and extend in a first direction to separate the plurality of channel pillars into a first column of channel pillars and a second column of channel pillars. 4 . The three-dimensional AND flash memory device according to claim 3 , further comprising a partition wall extending through the gate stack structure, wherein the partition wall extends in the first direction and has a length greater than a length of the isolation wall. 5 . The three-dimensional AND flash memory device according to claim 4 , wherein a width of the partition wall is greater than a width of the isolation wall.

6. A three-dimensional AND flash memory device, comprising: A gate stack structure is located on a dielectric substrate, wherein the gate stack structure includes a plurality of gate layers and a plurality of insulating layers alternately stacked with each other; A plurality of channel pillars passing through the gate stack structure; A plurality of source columns and a plurality of drain columns are located in the plurality of channel columns and in contact with the plurality of channel columns; as well as A plurality of charge storage structures are located between the plurality of gate layers and the channel pillars, The sidewalls of the multiple gate layers do not contact the sidewalls of the first portions of the multiple charge storage structures, and the sidewalls of the first portions of the multiple charge storage structures cover around the multiple channel pillars that contact the multiple drain pillars. 7 . The three-dimensional AND flash memory device according to claim 6 , wherein a radial dimension of each source pillar is greater than or equal to a radial dimension of each drain pillar. 8 . The three-dimensional AND flash memory device according to claim 6 , wherein the plurality of source pillars are offset from the center of the plurality of drain pillars.

9. A method for manufacturing a three-dimensional AND flash memory device, comprising: forming a stacked structure on a dielectric substrate, wherein the stacked structure comprises a plurality of sacrificial layers and a plurality of insulating layers alternately stacked with each other; forming a plurality of channel pillars extending through the stacked structure; forming a plurality of first conductive posts and a plurality of second conductive posts, which are located within the plurality of channel posts and are electrically connected to the plurality of channel posts; locally removing the plurality of sacrificial layers to form a plurality of horizontal openings, wherein portions of the plurality of sacrificial layers that are not removed form a plurality of isolation walls; The plurality of isolation walls have a curved shape; forming a plurality of gate layers in the plurality of horizontal openings; as well as A plurality of charge storage structures are formed between the plurality of gate layers and the channel pillars, and the plurality of isolation walls cover the plurality of charge storage structures on the outer sidewalls of the plurality of second conductive pillars. 10 . The method for manufacturing a three-dimensional AND flash memory device according to claim 9 , wherein the plurality of isolation walls extend in a first direction and separate the plurality of channel pillars into a first row of channel pillars and a second row of channel pillars.

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