A memory resistance calibration method for in-memory computing

Abstract

The application discloses a memory resistance calibration method for in-memory computing, and belongs to the technical field of semiconductor and in-memory computing. The method utilizes the characteristics of the in-memory computing network, and sets the reference column device to all HRS or LRS according to two different resistance change characteristics of the new memory device. When the reference column device is all HRS or LRS, the error current from HRS or LRS is subtracted from the output current of the working column, and the corrected current is obtained. Finally, the corrected voltage signal is output through the reference resistance. The resistance of the device in the cross-point array of the new memory with different resistance-temperature relationships is corrected by the method, so that the performance of the in-memory computing chip based on the new memory under a wide range of environmental temperatures is ensured.

Description

Technical Field

[0001] This invention belongs to the fields of semiconductor and in-memory computing technology, and specifically relates to a novel method for correcting the external resistance of a memory cross-point matrix. Background Technology

[0002] As modern society becomes increasingly intelligent, numerous in-memory computing applications are emerging in our daily lives. These applications are ubiquitous in various production and living environments. For example, cars use intelligent cameras to monitor road conditions and assist driving; outdoor devices employ facial and voice recognition for convenience; and centralized data centers conduct large-scale neural network calculations to research various problems. Currently, many chips specifically designed to accelerate in-memory computing have been developed, and research is underway on in-memory computing chips utilizing various emerging memory technologies, such as resistive random access memory (RRAM), phase-change memory (PCM), and electrochemical memory (ECRAM). These new memory devices possess non-volatile storage capabilities, allowing them to leverage their integrated in-memory computing advantages. Compared to traditional metal-oxide-semiconductor field-effect transistor (MOSFET) devices, they typically offer higher integration density and lower power consumption per unit area. Therefore, when applied to in-memory computing chips, they exhibit superior computing power and energy efficiency compared to traditional MOSFET-based chips.

[0003] However, when these in-memory computing chips based on novel memory devices are actually applied in people's production and daily life, they face the problem of a wide operating temperature range. These devices typically use a combination of Ohm's law and Kirchhoff's laws to solve the core matrix-vector product problem in in-memory computing. Therefore, the performance of in-memory computing chips based on these devices is affected by the resistance of the device. The resistance of novel memory devices is usually affected by temperature, and their target operating environment is not always at room temperature. For example, in automotive and computer room environments, the chip operating temperature is usually relatively high. In contrast, in environments such as outdoors in winter, the North and South Poles, and outer space, the operating temperature is relatively low. Many smart devices operating in such environments may experience performance degradation or even failure.

[0004] The inherent resistance-temperature characteristics of some novel memory devices present new challenges to solving this problem. For example, resistive random access memory (RRRAM), when in its high-resistivity (HRS) state, exhibits a conductivity mechanism similar to that of a semiconductor, with its resistance increasing with temperature. Conversely, when in its low-resistivity (LRS) state, its conductivity mechanism resembles that of a metal, with its resistance decreasing with temperature. When an RRAM array is used as a weight matrix in an in-memory computing network, the resistance state of its internal components is unpredictable. Therefore, changes in external temperature pose additional challenges to the resistance correction of such an array. Solving this problem could drive the development of in-memory computing chips based on novel memory devices, thereby further promoting the intelligent transformation of modern society. Summary of the Invention

[0005] This invention proposes a resistance correction method applied to the outside of a novel memory cross-point array, which corrects the resistance of devices in the novel memory cross-point array with different resistance-temperature relationships, thereby ensuring the performance of the in-memory computing chip based on the novel memory under a wide range of ambient temperatures.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A memory resistance calibration method for in-memory computing includes the following steps:

[0008] 1) In the cross-dot matrix formed by memory, a column of devices is set as a reference column. All devices in the reference column are set to high resistance state HRS or low resistance state LRS. One or more columns of devices in the memory cross-dot matrix that are turned on are defined as working columns. All devices in the working column and the reference column are turned on at the same time.

[0009] 2) Connect a clamping circuit to the end of both the working column and the reference column to clamp the potentials on the working column and the reference column at the reference voltage V. ref ;

[0010] 3) The current output in the reference column is scaled using a current mirror. The input of the current mirror is the output current of the reference column, and the output of the current mirror is connected to the output of the working column. The output current of the working column is subtracted from the output current of the reference column to complete the first stage of correction and obtain the correction current.

[0011] 4) The correction current is scaled using a current mirror, and then converted into a voltage signal through a reference resistor. When all reference column resistors are LRS, the reference resistor is set to HRS; when all reference column resistors are HRS, the reference resistor is set to LRS, completing the second-stage correction and finally obtaining the corrected voltage signal.

[0012] Furthermore, the scaling factor n1 in step 3) is obtained according to the following formula: n1 = N HRS / N+1 / 2 (when all devices in the reference column are set to high resistance (HRS)), or n1 = N LRS / N+1 / 2 (when all devices in the reference column are set to low resistance (LRS)), where N HRS N represents the number of weights with a value of 0 in the weight network of the algorithm used. LRS N represents the number of weights with a value of 1 in the weight network of the algorithm used, and N is the total number of weights.

[0013] Furthermore, the scaling factor n2 in step 4) is obtained according to the following formula:

[0014]

[0015]

[0016] Where V range This refers to the highest voltage across the reference resistor, V. read N is the highest value of the word line input voltage when performing calculations using the cross-matrix. col This refers to the number of devices in the bit lines of the cross-dot matrix that are in operation; ratio is the on / off ratio of a single memory; the correction current is scaled by a current mirror to avoid the device's resistance drifting due to electrical stress caused by an excessively high potential difference across the reference resistor.

[0017] The memory described herein has the characteristic of storing information using resistance. This includes, but is not limited to, phase-change memory (PCM), resistive RAM (ReRAM) (including metal oxide-based or oxygen-vacancy-based ReRAM and filament-based ReRAM), conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), ferroelectric transistor RAM (Fe-TRAM), magnetoresistive RAM (MRAM) (including write-in-place non-volatile MRAM (NVMRAM) and spin-transfer torque (STT) memory), magnetic tunnel junction (MTJ), electrochemical RAM (ECRAM), or other devices or circuits capable of storing information using resistance.

[0018] The clamping circuit consists of an operational amplifier and a PMOS transistor. The source of the PMOS transistor is connected to the working column and the reference column, the drain of the PMOS transistor is connected to a current mirror, the gate of the PMOS transistor is connected to the output of the operational amplifier, the negative input of the operational amplifier is connected to the working column and the reference column, and the positive input of the operational amplifier is connected to a reference voltage.

[0019] The function of the current mirror should be to scale the current output in the reference column according to a certain ratio, including but not limited to the basic current mirror, the common source cascode current mirror, the active current mirror, etc.

[0020] The reference resistor is the same as the memory in the cross-dot matrix.

[0021] The technical principle of this invention is:

[0022] Leveraging the characteristics of in-memory computing networks: While weights in in-memory computing networks can be negative, resistance, as a physical quantity, is only positive. Therefore, when writing the weights of an in-memory computing network into a new type of memory, two new memories are typically used. One memory stores either the resistance value (HRS) or resistance value (LRS), while the other stores different resistance values. The difference in their conductances represents the weight. For example, a weight of 0.2 in the network is represented as 0.3-0.1 (corresponding to HRS) or 1 (corresponding to LRS)-0.8; a weight of -0.3 is represented as 0.1 (corresponding to HRS)-0.4 or 0.7-1 (corresponding to LRS). It is evident that weights represented in this way will always have either an HRS or LRS, depending on the fixed storage state used. Since the ratio of positive to negative weights in the network is typically close to 1:1, this method ensures that nearly half of the devices in the new memory array containing the weight matrix have resistance states at HRS or LRS. When all reference column devices are set to HRS, half of the error current from HRS is subtracted from the output current of the working column. At this point, the distortion in the HRS portion is corrected for most columns, and most of the error in the resulting current originates from LRS. The reference resistor used here is LRS. Since it is the same type of device as the devices in the array, it exhibits the same resistance change characteristics. Passing the aforementioned current through this reference resistor further corrects the distortion in the LRS portion, ultimately outputting a corrected voltage signal. This ensures the performance of the in-memory computing chip based on the new memory across a wide range of ambient temperatures. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the memory resistance calibration method calculated in memory according to the present invention;

[0024] Figure 2 This is a schematic diagram illustrating the chip's recognition capability in its uncorrected operating state.

[0025] Figure 3 This is a schematic diagram illustrating the chip recognition capability of the present invention. Detailed Implementation

[0026] To further illustrate the functionality of this circuit, examples and results for actual correction methods are provided.

[0027] refer to Figure 1 The novel cross-dot matrix of the memory consists of multiple word lines (horizontal lines in the diagram) and bit lines (vertical lines in the diagram), with novel memory cells positioned at the intersections of the word lines and bit lines. This memory device has a 1T1R structure, meaning one transistor and one resistive random access memory (RRAM) are connected in series. This structure can store signal states through resistance values. The novel cross-dot matrix contains a reference column, where all devices are set to HRS (High-Resistance Spectrum). When a working column in the matrix is ​​activated, the reference column is simultaneously activated.

[0028] A clamping circuit composed of an operational amplifier and a PMOS transistor is connected to the ends of the working column and the reference column in the cross-point matrix, respectively, to clamp the potentials on these two columns to the reference voltage V. ref This reference voltage is used to generate a relative negative voltage; for example, when the global reference voltage is 1V, a voltage of 0.5V is equivalent to -0.5V in this chip.

[0029] The PMOS source is connected to the lead of the working or reference column in the cross-point matrix, the drain is connected to the next stage circuit, and the gate is connected to the output of the operational amplifier. The negative input of the operational amplifier is connected to the lead of the working or reference column in the cross-point matrix, and the positive input is connected to the reference voltage of the entire circuit.

[0030] A current mirror is used to scale the current output in the reference column. Specifically, the input to the current mirror is the output current of the reference column, and the output of the current mirror is connected to the output of the working column. This current mirror is a basic current mirror. The current scaling factor n1 of the reference column is N. HRS / N+1 / 2, where N HRS Let N be the number of weights with a value of 0 in the algorithm network, and let N be the total number of weights. Typically, N... HRS The value of / N+1 / 2 is close to 1 / 2. Subtracting the output current of the reference column from the output current of the working column yields the correction current.

[0031] The aforementioned correction current is then scaled by a current mirror and converted into a voltage signal via a reference resistor (LRS) in a low-resistance state. When the cross-matrix circuit is operating, both the working column and the reference column should be enabled simultaneously. After a signal is input to the word lines of the array, the voltage at the V-axis of this cross-matrix is... out The voltage signal is read as the correction result and finally the corrected voltage signal is output.

[0032] This invention takes an RRAM array as an example. The RRAM's LRS is 10K ohms, HRS is 100K ohms, and its size is 512×10¹. The resistance weights in the reference column are set to HRS, and the reference resistors in the correction circuit are set to LRS. In the correction circuit, n1 is set to 0.5, and n2 is set to 0.04. At this time, the maximum output voltage of the Vout port is 1V, which is neither too large to change the device state nor too small to be difficult to measure. After subtracting the HRS error current, which accounts for about half of the total weights, the correction current is obtained. The weight matrix for recognizing the handwritten digit set (MNIST) was written into the array. Without applying a resistance correction circuit and with the weights written at temperatures ranging from 240K to 390K, the accuracy of the network in recognizing the handwritten digit set was investigated for various possible temperature environments the chip might be in (e.g., chip operating temperature 315K, ambient temperature 263K, approximating low-power outdoor operation in winter; chip operating temperature 413K, ambient temperature 300K, approximating operation in a computer room; chip operating temperature 513K, ambient temperature 513K, approximating operation in special environments such as volcanoes or specific factory buildings). The results are shown in […]. Figure 2 As can be seen, in many working environments (red indicates low recognition accuracy), the chip's recognition capability is greatly affected. Figure 3 The results of the correction method proposed in the specific embodiment of the present invention show that, using the correction method provided by the present invention, the performance degradation of the in-memory computing chip under various environments has been significantly improved.

[0033] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A memory resistance calibration method for in-memory computing, comprising the following steps: 1) In the cross-dot matrix formed by memory, a column of devices is set as a reference column. All devices in the reference column are set to high resistance state HRS or low resistance state LRS. One or more columns of devices in the memory cross-dot matrix that are turned on are defined as working columns. All devices in the working column and the reference column are turned on at the same time. 2) Connect a clamping circuit to the end of the working column and the reference column respectively to clamp the potentials on the working column and the reference column to the reference voltage Vref; 3) The current output in the reference column is scaled using a current mirror. The input of the current mirror is the output current of the reference column, and the output of the current mirror is connected to the output of the working column. The output current of the working column is subtracted from the output current of the reference column scaled by the current mirror to complete the first stage of correction and obtain the correction current. 4) Use another current mirror to scale the correction current, and then convert the correction current into a voltage signal through a reference resistor. When all the reference column resistors are LRS, the reference resistor is set to HRS; when all the reference column resistors are HRS, the reference resistor is set to LRS, completing the second stage of correction, and finally obtaining the corrected voltage signal.

2. The memory resistance calibration method for in-memory computing as described in claim 1, characterized in that, In step 3), the scaling factor n1 is: when all devices in the reference column are set to the high-resistance state (HRS), n1 = N. HRS / N + 1 / 2; or, when all devices in the reference column are set to low resistance (LRS), n1 = N LRS / N + 1 / 2, where N HRS N represents the number of weights with a value of 0 in the weight network of the algorithm used. LRS N represents the number of weights with a value of 1 in the weight network of the algorithm used, and N is the total number of weights.

3. The memory resistance calibration method for in-memory computing as described in claim 1, characterized in that, In step 4), the scaling factor n2 is obtained using the following formula: Where V range This refers to the highest voltage across the reference resistor, V. read N is the highest value of the word line input voltage when performing calculations using the cross-matrix. col This refers to the number of devices in the bit lines of the cross-dot matrix that are in operation; ratio is the on / off ratio of a single memory; the correction current is scaled by a current mirror to avoid the device's resistance drifting due to electrical stress caused by an excessively high potential difference across the reference resistor.

4. The memory resistance calibration method for in-memory computing as described in claim 1, characterized in that, The memory is a phase change memory, resistive RAM, conductive bridge RAM, ferroelectric RAM, ferroelectric transistor RAM, magnetoresistive RAM, magnetic tunnel junction, or electrochemical memory.

5. The memory resistance calibration method for in-memory computing as described in claim 1, characterized in that, The clamping circuit consists of an operational amplifier and a PMOS transistor. The source of the PMOS transistor is connected to the working column and the reference column, the drain of the PMOS transistor is connected to a current mirror, the gate of the PMOS transistor is connected to the output of the operational amplifier, the negative input of the operational amplifier is connected to the working column and the reference column, and the positive input of the operational amplifier is connected to a reference voltage.

6. The memory resistance calibration method for in-memory computing as described in claim 1, characterized in that, The current mirror can be a basic current mirror, a common-source cascode current mirror, or an active current mirror.

7. The memory resistance calibration method for in-memory computing as described in claim 1, characterized in that, The reference resistor is the same as the memory in the cross-dot matrix.

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