Inductor, electronic device and manufacturing method thereof
By designing a multilayer inductor unit stacking structure and electrical connection components, the problems of insufficient space utilization and integration of existing thin-film inductors are solved, realizing an inductor with high integration, low resistance and adjustability, suitable for a variety of electronic devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICROPOLYMER SEMICON (JIANGSU) CO LTD
- Filing Date
- 2022-12-29
- Publication Date
- 2026-05-29
Smart Images
Figure CN115841906B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to integrated circuits and methods of manufacturing thereof, and more specifically, to an inductor and methods of manufacturing thereof. Background Technology
[0002] With the development of integrated circuit manufacturing technology, it has been applied to the production of inductor components. As installed electronic devices become increasingly functional and highly integrated, inductors need to improve in terms of high integration, high Q, and low resistance to adapt to the integration requirements of semiconductor components. Most existing thin-film inductors on the market are based on a single-layer thin-film spiral structure, while some high-parameter inductors are implemented using a stacked structure. These structures lack adjustability and cannot easily adjust inductor parameters according to device requirements. Therefore, for independent power inductors, how to improve vertical utilization, extend planar inductors to three dimensions, and simultaneously improve inductor performance, integration, and adjustability has become an urgent problem to be solved.
[0003] This disclosure addresses the aforementioned technical problems by designing a novel inductor structure and manufacturing method. This method is compatible with existing integrated circuit processes, avoiding the shortcomings of existing planar inductors and multilayer structures, such as insufficient space utilization, integration density, and adjustability. Furthermore, it improves the flexibility of inductor adjustment while reducing inductor size, miniaturization, increasing capacity, lower resistance, reliability, and lower cost. Summary of the Invention
[0004] A brief overview of this disclosure is provided below to offer a basic understanding of certain aspects of it. It should be understood that this overview is not an exhaustive summary of the disclosure. It is not intended to identify key or essential parts of the disclosure, nor is it intended to limit its scope. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.
[0005] According to one aspect of this disclosure, an inductor is provided, comprising:
[0006] An inductor comprising multiple stacked inductor units, each inductor unit including a conductive layer, the conductive layers of each inductor unit being isolated from each other by a dielectric layer; a core via penetrating the stacked structure is included within the core via, and a magnetic core is included in the core via; a cut extending to the core via is formed in a portion of the stacked structure of multiple inductor units, and the conductive layer of each inductor unit is formed as an inductor coil; the projection of the inductor coil of each upper inductor unit onto the upper surface of the substrate falls within the range of the projection of the inductor coil of the lower inductor unit onto the upper surface of the substrate, thereby forming a stepped shape at the beginning and end of the inductor coils of the multiple inductor units, the stepped shape exposing a portion of the conductive layer at the beginning and end of the inductor coils of each inductor unit; and an electrical connection assembly is formed on the portion of the conductive layer of each inductor unit exposed from the stepped shape, connecting the multiple inductor units in series.
[0007] Furthermore, the magnetic core through-hole also includes a dielectric material surrounding the magnetic core to isolate the magnetic core from the surrounding area.
[0008] Furthermore, a planarization insulating layer is formed on the stacked structure of multiple inductor units, through-holes are formed in the planarization insulating layer, and the electrical connection components are formed in the through-holes.
[0009] Furthermore, the dielectric layer is selected from silicon oxide layer, silicon oxide / silicon nitride layer, silicon oxide / silicon nitride / silicon oxide layer, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, ruthenium oxide, and combinations thereof.
[0010] Furthermore, the conductive layer is selected from metals or highly doped semiconductor materials.
[0011] Furthermore, the electrical connection assembly connects the inductor coils of each inductor unit end to end, thereby connecting multiple inductor units in series.
[0012] Furthermore, the electrical connection components of the conductive layer of the bottommost inductor unit and the conductive layer of the topmost inductor unit are respectively connected to external interconnects.
[0013] Furthermore, during the formation of the slits, the conductive layer of each of the inductor units is formed as a spiral inductor coil surrounding the magnetic core.
[0014] According to another aspect of this disclosure, a method for manufacturing an inductor is provided, characterized by comprising:
[0015] S1: Provide a substrate;
[0016] S2: Multiple alternating stacks of dielectric / conductive layers are formed on the substrate;
[0017] S3: Photolithography and etching of the plurality of alternating stacks to divide the plurality of alternating stacks into a plurality of inductor structures, each inductor structure including the plurality of alternating stacks, forming a magnetic core via inside each inductor structure, and forming a cut extending to the magnetic core via in a portion of the plurality of alternating stacks in each inductor structure, forming each conductive layer in the plurality of alternating stacks of each inductor structure into an inductor coil;
[0018] S4: Forming a stepped alternating stack, wherein the beginning and end of the inductor coils in the plurality of alternating stacks of each inductor structure are formed into a stepped shape, the stepped shape exposing a portion of the conductive layer at the beginning and end of the inductor coils of each alternating stack; and
[0019] S5: Forming a magnetic core and electrical connection components, depositing insulating material on the stepped alternating stack, forming a magnetic core through photolithography, etching, and deposition processes, and forming electrical connection components on the partially conductive layers at the head and tail of the inductor coils exposed by the stepped alternating stack, connecting multiple inductor coils in each inductor structure in series.
[0020] Furthermore, in step S5, after depositing the insulating material, a planarization process is performed to form contact holes and magnetic core deposition holes through photolithography and etching. Then, magnetic core material is deposited in the magnetic core deposition holes, and conductive material is deposited in the contact holes to form the electrical connection assembly between the magnetic core and each conductive layer. The remaining insulating material after etching the magnetic core deposition holes surrounds the magnetic core, thus isolating the magnetic core from the surrounding area.
[0021] Furthermore, it also includes step S6, the process of forming interconnections, forming interconnections between electrical connection components of inductor coils and external interconnections, connecting each inductor coil end to end, and connecting the electrical connection components of the lowest conductive layer and the highest conductive layer in the inductor structure to external interconnections respectively.
[0022] Furthermore, in step S3, when forming the cut, each conductive layer in the plurality of alternating stacks in each inductor structure is formed into a spiral inductor coil surrounding the magnetic core.
[0023] According to another aspect of this disclosure, an inductor assembly is provided, including a plurality of inductors as described in this disclosure, the plurality of inductors being arranged at intervals on the substrate.
[0024] According to another aspect of this disclosure, an electronic device is provided, including the inductor group of this disclosure.
[0025] The solution disclosed herein can help achieve at least the following effects: the inductor manufacturing process of this disclosure is simple, compatible with existing integrated circuit processes, the inductance value is easy to adjust, the product has high integration, good compatibility, low production cost, good packaging convenience, and is easy to achieve miniaturization, high power density, low resistance, and high Q. Attached Figure Description
[0026] The specific details of this disclosure are described below with reference to the accompanying drawings, which will facilitate a more readily understanding of the above and other objects, features, and advantages of this disclosure. The drawings are merely for illustrating the principles of this disclosure. The dimensions and relative positions of the elements are not necessarily drawn to scale in the drawings.
[0027] Figure 1 A schematic diagram showing the inductor assembly of this disclosure;
[0028] Figure 2 A perspective view of the inductor structure according to the first embodiment of this disclosure is shown;
[0029] Figure 3 A perspective view of the inductor structure according to the first embodiment of this disclosure is shown;
[0030] Figure 4 A flowchart illustrating the inductor fabrication method of this disclosure is shown;
[0031] Figure 5 A perspective view of the inductor structure according to the second embodiment of this disclosure is shown. Detailed Implementation
[0032] Exemplary aspects of this disclosure will be described below with reference to the accompanying drawings. For clarity and brevity, not all features implementing this disclosure are described in the specification. However, it should be understood that many disclosure-specific decisions can be made in developing any such implementation of this disclosure to achieve the developer's specific goals, and these decisions may vary depending on the specific implementation of this disclosure.
[0033] It should also be noted that, in order to avoid obscuring the contents of this disclosure with unnecessary details, only the device structure closely related to the solution according to this disclosure is shown in the accompanying drawings, while other details that are not closely related to this disclosure are omitted.
[0034] It should be understood that this disclosure is not limited to the described embodiments by virtue of the following description with reference to the accompanying drawings. In this document, features may be substituted or borrowed between different embodiments where feasible, and one or more features may be omitted in one embodiment.
[0035] First Implementation Plan
[0036] Figure 1-3 A first embodiment of the inductor structure of this disclosure is shown, wherein the same reference numerals denote the same components.
[0037] Figure 1 This is a schematic diagram of the inductor group in this embodiment. Figure 2 This is a perspective view of the inductor structure according to this embodiment. Figure 1 As can be seen, an inductor group is formed on a substrate 10, including N inductors 20 arranged at intervals (two inductors are shown as an example in the figure), where N is a natural number, and the N inductors 20 can be arranged in a matrix on the substrate. For example, N can be set to 5000, but those skilled in the art should understand that the number of inductors can be flexibly set according to actual needs, and no specific limitation is imposed in this disclosure. The substrate can be, for example, a single crystal / polycrystalline silicon substrate (Si), a silicon-on-insulator (SOI) substrate, a compound substrate of group III-V elements, a glass substrate, a ceramic substrate, or any other substrate material compatible with the semiconductor process. The following description uses a silicon substrate as an example.
[0038] Figure 2 for Figure 1 A perspective view of a single inductor 20, by Figure 2 It can be seen that a stacked structure of multiple dielectric / conductive layers is formed on the silicon substrate 10.
[0039] Each inductor 20 may include M stacked inductor units, where M is a natural number. For example, M can be set to more than 100, but those skilled in the art should understand that the number of inductor units can be flexibly set according to actual needs, and no specific limitation is imposed in this disclosure. Each inductor unit includes an inductor coil formed by a conductive layer, and the inductor coils formed by the conductive layers of each inductor unit are isolated from each other by a dielectric layer.
[0040] The inductor unit stacked in the inductor 20 that is closest to the substrate is defined as the first inductor unit L1, the next closest is defined as the second inductor unit L2, and the inductor unit that is farthest from the substrate is defined as the Mth inductor unit Lm.
[0041] This disclosure involves forming multiple stacked dielectric and conductive layers on a substrate 100 to form inductor units L1-Lm, specifically forming a multilayer thin film (MIMIMI…) of dielectric layer 1011 / conductive layer 1021 / dielectric layer 1012 / conductive layer 1022 / dielectric layer 1013 / conductive layer 1023…dielectric layer 101m / conductive layer 102m. Figure 2An exemplary diagram illustrates a structure of eight inductor cells, wherein a dielectric layer is used to isolate the conductive layers of adjacent inductor cells, and the conductive layers subsequently form the inductor coil of each inductor cell. Optionally, a buffer layer 1000 is formed on the substrate 100.
[0042] like Figure 2 As shown, the stacked structure formed by multiple inductor units includes a through-hole 200 that penetrates the stacked structure. The through-hole 200 contains a magnetic core 201 made of a magnetic material with high permeability and low loss, and the magnetic core 201 is isolated from the surrounding area by an insulating material. Figure 2 The insulating material is not shown in the perspective view. Figure 3 The diagram shows an insulating material 400 surrounding the magnetic core 201, isolating the core from its surroundings. A cutout 300 extending to the through-hole 200 of the magnetic core is formed in a portion of the stacked structure, partially disconnecting the conductive layer and the dielectric layer for isolation of each inductor unit. This allows the conductive layer of each inductor unit to be formed as an inductor coil. The beginnings and ends of the inductor coils of multiple inductor units are formed in a stepped shape, exposing portions of the conductive layer at the beginning and end of the inductor coils of each inductor unit. Through-holes are present in the insulating layer 400 covering the conductive layer of each inductor unit (see [reference]). Figure 3 As shown, conductive material is filled into the through-hole to form electrical connection components 1021A, 1021B, 1022A, 1022B, 1023A, 1023B, ..., 102mA, 102mB, so that each conductive layer is spirally connected upwards. Specifically, component 1021A is connected to the external interconnect, component 1021B is connected to 1022A, component 1022B is connected to 1023A, component 1023B is connected to 1024A, ..., component 102mB is connected to the external interconnect. The electrical connection components connect the inductor coils of each inductor unit end to end, forming a spiral connection structure layer by layer, thereby connecting multiple inductor units in series.
[0043] For the materials of the dielectric layer used for isolation and the conductive layer of the inductor unit, the dielectric layer is preferably a silicon oxide layer, a silicon oxide / silicon nitride layer, a silicon oxide / silicon nitride / silicon oxide layer, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, or ruthenium oxide, etc. The conductive layer is preferably a metal or a highly doped semiconductor material, such as low-voltage highly doped polycrystalline silicon, tungsten, etc. Preferably, the doping concentration of the highly doped semiconductor material can be 1e18 / cm. 3 -9e19 / cm 3The conductive material used to fill the vias for forming electrical interconnects can be selected from one or more alloys of heavily doped polycrystalline silicon, titanium / titanium nitride, aluminum, tungsten, copper, nickel, gold, palladium, silver, platinum, rhodium, cobalt, tin, and lead. The thickness of the dielectric and conductive layers can be between 1 nm and 90,000 nm, and the specific thickness can be selected according to the actual needs of the inductor product to adjust inductance, resistance, etc. The thicknesses of the dielectric and conductive layers can be the same or different.
[0044] See Figure 2 As shown, the first inductor unit L1 is composed of a first conductive layer 1021, the second inductor unit L2 is composed of a second conductive layer 1022, and the Mth inductor unit Lm is composed of an mth conductive layer 102m. To form a layer-by-layer spiral interconnected structure, starting from the first inductor unit L1 to the Mth inductor unit Lm, the projection of the conductive layer of each upper inductor unit onto the upper surface of the substrate falls within the range of the projection of the conductive layer of the lower inductor unit onto the upper surface of the substrate. This forms a stepped shape at the beginning and end of the inductor coils of multiple inductor units, exposing a portion of the conductive layer at the beginning and end of the inductor coils of each inductor unit. Electrical connection components 1021A, 1021B, 1022A, 1022B, 1023A, 1023B, ..., 102mA, 102mB are formed on the portion of each conductive layer exposed from the stepped shape, so that the conductive layers are connected end to end, forming a layer-by-layer spiral interconnected structure, thereby connecting the first inductor unit L1 to the Mth inductor unit Lm in series.
[0045] Furthermore, since N inductors 20 are formed on a substrate 10 at intervals, the desired inductance value can be obtained more conveniently by adjusting the connection relationship between each inductor 20 and the external interconnection components 1021A and 102mB.
[0046] It is understood that the selection of materials for each conductive layer and dielectric layer, as well as the setting of their thicknesses, are specifically chosen based on the specific parameter requirements of the inductor. Although this disclosure provides illustrative examples of the materials and thicknesses, it does not imply any specific limitations. The main purpose of this disclosure is to achieve an independent inductor compatible with integrated circuit technology through the design of the inductor structure, with easily controllable product uniformity, low production costs, and convenient packaging. The inductor structure of this disclosure can be widely used in microcircuits with high reliability requirements, such as multi-chip packaging, communication base stations, electric vehicles, high-end medical devices, optical communications, and aerospace, with a broad application market.
[0047] Second Implementation Plan
[0048] The second embodiment of the inductor disclosed herein is essentially the same as the first embodiment, except that in the first embodiment, the conductive layer of each inductor unit is partially disconnected through a cut 300 to serve as an inductor coil, while in the second embodiment, see [link to relevant documentation]. Figure 5 As shown, when forming the notch 300, the conductive layer of each inductor unit in the stacked structure is also etched to form a spiral inductor coil around the magnetic core 201. Then, the spiral inductor coils of multiple inductor units are connected end to end, thereby connecting the first inductor unit L1 to the Mth inductor unit Lm in series to form inductor 20.
[0049] Third Implementation Plan
[0050] Figure 4 A third embodiment of the inductor manufacturing method disclosed herein is shown.
[0051] like Figure 4 As shown, in step S1, a substrate 10 is first provided, the specific material of which is the same as in the first embodiment. Then, in step S2, multiple alternating layers are formed on the substrate, namely, a stack of conductive layers serving as the inductor coils of the subsequent multiple inductor units L1-Lm and dielectric layers used to isolate the conductive layers. Specifically, multiple alternating stacks of dielectric / conductive layers are deposited on the upper surface of the substrate.
[0052] Then, in step S3, in order to form a plurality of inductors 20, a magnetic core via 200 for each inductor 20, and an inductor coil for each inductor unit L1-Lm on the substrate 10, specifically, photolithography and etching are performed on the substrate 10 comprising a plurality of alternating layers to divide the alternating layers into a plurality of stacked structures. Each stacked structure comprises a plurality of alternating layers of dielectric / conductive layers, and each stacked structure corresponds to the structure of one inductor 20, thereby separating the plurality of inductors 20. A magnetic core via 200 is formed inside the stacked structure of each inductor 20, and a cut 300 extending to the magnetic core via 200 is formed in a portion of the stacked structure of each inductor 20, so that the alternating layers of dielectric / conductive layers in the stacked structure of each inductor are partially broken, thereby forming each conductive layer as Figure 2 The inductor coil shown above, including the segmentation step, the step of forming the magnetic core through hole, and the step of forming the notch, can be completed in one photolithography and etching step, or it can be completed separately through multiple photolithography and etching steps.
[0053] Furthermore, the conductive layer of the inductor coil can be Figure 2 The shape shown can also be Figure 5The spiral inductor coil shown is formed by etching multiple alternating conductive layers in the stacked structure of each inductor structure to form a spiral inductor coil around the magnetic core 201 when the notch 300 is etched. Then, the multiple alternating spiral inductor coils are connected end to end, thereby connecting the first inductor unit L1 to the Mth inductor unit Lm in each inductor 20 in series to form the inductor 20.
[0054] Then, in step S4, a process of forming a stepped alternating stack is performed. Specifically, a first photoresist layer is formed on the inductor coil formed on the Mth conductive layer farthest from the substrate. The first photoresist layer is patterned, and a portion of the first photoresist layer is removed to expose a portion of the conductive layer at the beginning and end of the inductor coil of the Lmth inductor unit. Then, the alternating stack of the Lmth inductor unit is etched using the patterned first photoresist layer to expose a portion of the conductive layer at the beginning and end of the inductor coil of the Lm-1th inductor unit. Subsequently, the first photoresist layer is laterally recessed stepwise, so that the coverage area of the first photoresist layer on the beginning and end of the inductor coil of the lower inductor unit is gradually reduced. The gradually reduced first photoresist layer is used to etch a stepped shape on the beginning and end of the inductor coil of the inductor unit. Each stepped shape exposes a portion of the conductive layer at the beginning and end of the corresponding inductor coil. Finally, the first photoresist layer is removed.
[0055] Then, in step S5, the process of forming the magnetic core and electrical connection components is carried out. Specifically, an insulating material 400 is deposited on the substrate. The insulating material can be a low-k material, such as TEOS. Then, a planarization process is performed, and contact holes and magnetic core deposition holes are formed by photolithography and etching. The magnetic core deposition holes are used for subsequent deposition of the magnetic core 201. In order to retain the deposited insulating material around the magnetic core 201 to form isolation, the diameter of the magnetic core deposition holes is smaller than the magnetic core via 200 formed in step S3. Then, magnetic core material is deposited in the magnetic core deposition holes, and conductive material is deposited in the contact holes to form the electrical connection components of the magnetic core 201 and each conductive layer. The remaining TEOS in the magnetic core via 200 after etching the magnetic core deposition holes is isolated from the surrounding area.
[0056] Finally, step S6, the interconnection process, specifically, forms the interconnections between the electrical connection components of the inductor coils and external interconnections, see [link to relevant documentation]. Figure 2As shown, the inductor coils of each layer are connected in series to form a spiral connection layer by layer. Specifically, the electrical connection component 1021A of the L1 inductor unit is connected to the external interconnect, component 1021B is connected to 1022A, component 1022B is connected to 1023A, component 1023B is connected to 1024A, ..., and the electrical connection component 102mB of the Lm inductor unit is connected to the external interconnect. Through the external interconnect, multiple inductors 20 on the substrate can be electrically connected, thereby making it easier to obtain the desired inductance value.
[0057] Finally, proceed to step S7, cutting and separating the individual inductor groups. It is understandable that, depending on the specific needs, during cutting, instead of separating the individual inductor groups, a portion of the inductor groups can be electrically combined and then cut and separated as a module unit.
[0058] Fourth Implementation Plan
[0059] A fourth embodiment of this disclosure provides an electronic device that may include the inductor array described in the above embodiments. Examples of such electronic devices include transimpedance amplifiers (TIAs), optical transceiver units (ROSA / TOSA), synchronous fiber optic networks (SONET), and broadband test equipment.
[0060] The foregoing description of this disclosure in conjunction with specific implementation schemes is exemplary and not intended to limit the scope of protection of this disclosure. Those skilled in the art can make various modifications and variations to this disclosure based on its spirit and principles, and such modifications and variations are also within the scope of this disclosure.
Claims
1. An inductor, characterized in that, include: An inductor formed by stacking multiple inductor units, each of the inductor units including a conductive layer, the conductive layers of each inductor unit being isolated from each other by a dielectric layer, and the conductive layers of each inductor unit and the dielectric layer between the conductive layers of each inductor unit being formed on a substrate. The stacked structure of multiple inductor units includes a core through-hole that runs through the stacked structure, and the core through-hole contains a magnetic core. A cutout extending to a magnetic core through-hole is formed in a part of a stacked structure of multiple inductor units, and the conductive layer of each inductor unit is formed as an inductor coil. The projection of the inductor coil of each upper-layer inductor unit onto the upper surface of the substrate falls within the range of the projection of the inductor coil of the lower-layer inductor unit onto the upper surface of the substrate, thereby forming a stepped shape at the beginning and end of the inductor coils of multiple inductor units. This stepped shape exposes a portion of the conductive layer at the beginning and end of the inductor coils of each inductor unit. Electrical connection components are formed on the partial conductive layer of each of the inductor units exposed in a stepped manner, thereby connecting multiple inductor units in series.
2. The inductor of claim 1, wherein the through-hole in the core further includes a dielectric material surrounding the core to isolate the core from the surrounding area.
3. The inductor as claimed in claim 1, wherein a planarization insulating layer is formed on a stacked structure of multiple inductor units, a through-hole is formed in the planarization insulating layer, and the electrical connection assembly is formed in the through-hole.
4. The inductor of claim 1, wherein the dielectric layer is selected from silicon oxide layer, silicon oxide / silicon nitride layer, silicon oxide / silicon nitride / silicon oxide layer, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, ruthenium oxide, and combinations thereof.
5. The inductor of claim 1, wherein the conductive layer is selected from metal or highly doped semiconductor material.
6. The inductor of claim 3, wherein the electrical connection assembly connects the inductor coils of each of the inductor units end to end, thereby connecting multiple inductor units in series.
7. The inductor of claim 6, wherein the electrical connection components of the conductive layer of the lowest inductor unit and the conductive layer of the highest inductor unit are respectively connected to external interconnects.
8. The inductor of claim 1, wherein, when forming the cut, the conductive layer of each of the inductor units is formed as a spiral inductor coil surrounding the magnetic core.
9. A method for manufacturing an inductor, characterized in that, include: S1: Provide a substrate; S2: Multiple alternating stacks of dielectric / conductive layers are formed on the substrate; S3: Photolithography and etching of the plurality of alternating stacks to divide the plurality of alternating stacks into a plurality of inductor structures, each inductor structure including the plurality of alternating stacks, forming a magnetic core via inside each inductor structure, and forming a cut extending to the magnetic core via in a portion of the plurality of alternating stacks in each inductor structure, forming each conductive layer in the plurality of alternating stacks of each inductor structure into an inductor coil; S4: Forming a stepped alternating stack, forming the head and tail of the inductor coil in the plurality of alternating stacks of each inductor structure into a stepped shape, the stepped shape exposing part of the conductive layer of the head and tail of the inductor coil of each alternating stack; as well as S5: Forming a magnetic core and electrical connection components, depositing insulating material on the stepped alternating stack, forming a magnetic core through photolithography, etching, and deposition processes, and forming electrical connection components on the partially conductive layers at the head and tail of the inductor coils exposed by the stepped alternating stack, connecting multiple inductor coils in each inductor structure in series.
10. The manufacturing method of claim 9, in step S5, after depositing insulating material, a planarization process is performed, and contact holes and magnetic core deposition holes are formed by photolithography and etching. Then, magnetic core material is deposited in the magnetic core deposition holes, and conductive material is deposited in the contact holes to form the electrical connection assembly of the magnetic core and each conductive layer. The remaining insulating material after etching the magnetic core deposition holes surrounds the magnetic core, thereby isolating the magnetic core from the surrounding area.
11. The manufacturing method of claim 9, further comprising step S6, a process of forming interconnections, forming interconnections between electrical connection components of inductor coils and external interconnections, connecting each inductor coil end to end, and connecting the electrical connection components of the lowest conductive layer and the highest conductive layer of the inductor structure to external interconnections respectively.
12. The manufacturing method of claim 9, wherein in step S3, when forming the slit, each conductive layer of the plurality of alternating stacks in each inductor structure is formed as a spiral inductor coil surrounding the magnetic core.
13. An inductor array comprising a plurality of the inductors of any one of claims 1-8, the plurality of inductors being spaced apart on the substrate.
14. An electronic device comprising the inductor assembly of claim 13.