Semiconductor Structure and Preparation Method

Abstract

The present application provides a semiconductor structure and a manufacturing method thereof. A plurality of memory cells arranged in a staggered manner are disposed on a substrate. The memory cell includes an odd number of vertical transistors, a connection pad connected to one end of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad. Among them, the channel material of the vertical transistor includes single-crystalline semiconductor. The odd number of vertical transistors provides a larger write current for the magnetic tunnel junction, and the channel material of each vertical transistor is single-crystalline semiconductor, which can further improve the write current of the vertical transistor, thereby improving the driving ability of the memory cell and being applicable to high-density magnetic random access memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a preparation method thereof. Background Art

[0002] Magnetoresistive Random Access Memory (MRAM for short) has the high read / write ability of static random access memory and the high integration of dynamic random access memory, and can be written repeatedly infinitely.

[0003] Currently, by combining MTJ (Magnetic Tunnel Junction) with transistors, the capacity of MRAM is increased, expanding the capacity of MRAM from the MB range to the GB range. However, the driving current of the transistor is small, making it difficult for the transistor to drive the MARM memory array. Summary of the Invention

[0004] This application provides a semiconductor structure and a preparation method thereof, aiming to provide a semiconductor structure with stronger driving ability, which is applicable to high-density magnetoresistive random access memory.

[0005] An embodiment of this application provides a semiconductor structure, including:

[0006] A plurality of storage units arranged in a staggered manner on a substrate, where each storage unit includes an odd number of vertical transistors, a connection pad connected to one end of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad;

[0007] Among them, the channel material of the vertical transistor includes single-crystal semiconductor.

[0008] In one embodiment, the single-crystal semiconductor includes single-crystalline silicon or single-crystalline germanium.

[0009] In one embodiment, the vertical transistors of the plurality of storage units are arranged in a staggered array structure on the substrate.

[0010] In one embodiment, a single connection pad is connected to one end of three vertical transistors.

[0011] In one embodiment, the cross-section of the vertical transistor in the direction of the substrate surface is circular, and the cross-section of the connection pad in the direction of the substrate surface is triangular, and the vertices of the triangle are respectively located at the midpoint of the circular cross-section.

[0012] In one embodiment, the projection of the magnetic tunnel junction on the substrate is located inside the projection of the connection pad on the substrate.

[0013] In one embodiment, the vertical transistors in adjacent two rows of storage units are located in three consecutive rows of the array structure.

[0014] In one embodiment, the semiconductor structure further includes:

[0015] A plurality of word lines arranged at intervals, and the extending direction of the word lines is the same as one of the side length directions of the triangle.

[0016] In one embodiment, the word line includes a gate electrode portion and a wire portion;

[0017] The gate electrode portion is connected to the channel of the vertical transistor in a single memory cell, and the wire portion is connected to a plurality of gate electrode portions.

[0018] In one embodiment, the projections of the gate electrode portion and the connection pad on the substrate surface coincide.

[0019] In one embodiment, the gate electrode portion and the wire portion are formed in the same etching step.

[0020] In one embodiment, the width of the word line portion is less than the pitch between the vertical transistors.

[0021] Another embodiment of the present application provides a method for manufacturing a semiconductor structure, including:

[0022] Providing a substrate, and forming a plurality of vertical transistors on the substrate; wherein, the channel material of the vertical transistor includes single-crystal semiconductor;

[0023] Forming a plurality of connection pads above the plurality of vertical transistors away from the substrate, so that the projection of one connection pad on the substrate overlaps with the projections of an odd number of vertical transistors;

[0024] Forming a magnetic tunnel junction above each connection pad away from the vertical transistor.

[0025] In one embodiment, forming a plurality of vertical transistors on the substrate specifically includes:

[0026] Forming a common source electrode plate on the substrate;

[0027] Forming a plurality of vertical channels arranged in an array on the common source electrode plate;

[0028] Forming a gate electrode portion connecting an odd number of vertical channels and a wire portion connecting the gate electrode portions on the common source electrode plate;

[0029] Forming a drain electrode plate on the surface of each vertical channel away from the common source electrode plate.

[0030] In one embodiment, forming a gate electrode portion connecting an odd number of vertical channels and a wire portion connecting the gate electrode portions on the common source electrode plate specifically includes:

[0031] Depositing a metal material on the surface of the common source electrode plate away from the substrate to form a gate electrode plate;

[0032] Form a plurality of triangular mask patterns on the gate electrode plate, and make the projections of the three vertical channels on the mask pattern located inside the triangular mask pattern;

[0033] Form a plurality of strip-shaped mask patterns on the gate electrode plate, and make the strip-shaped mask patterns overlap with the triangular mask patterns;

[0034] Etch the gate electrode plate to form a gate electrode portion and a wire portion connecting the gate electrode portions.

[0035] The semiconductor structure and manufacturing method provided by the embodiments of the present application. The semiconductor structure includes a plurality of cross-arranged memory cells. Each memory cell includes an odd number of vertical transistors, a connection pad, and a magnetic tunnel junction. One end of the odd number of vertical transistors is connected to the connection pad, and a magnetic tunnel junction is provided on the connection pad. The odd number of vertical transistors is used to provide a write current when writing data to or reading data from the magnetic tunnel junction. Since an odd number of vertical transistors are used, a larger write current can be provided for the magnetic tunnel junction. Among them, the channel material of each vertical transistor is single-crystalline semiconductor, which can further increase the write current of the vertical transistor, thereby improving the driving ability of the memory cell and being applicable to high-density magnetic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0037] Figure 1 It is a top view of the semiconductor structure provided by an embodiment of the present application;

[0038] Figure 2 It is a top view of the semiconductor structure provided by another embodiment of the present application;

[0039] Figure 3 For Figure 2 It is a position relationship diagram of the word line, vertical transistor, and connection pad provided by the shown embodiment;

[0040] Figure 4 And Figure 5 It is a process diagram for preparing the channel of the vertical transistor provided by an embodiment of the present application;

[0041] Figure 6 And Figure 7 It is a process diagram for preparing the word line provided by an embodiment of the present application;

[0042] Figure 8 、 Figure 9 And Figure 10 It is a process diagram for preparing the word line provided by an embodiment of the present application;

[0043] Figure 11 This is a process diagram for preparing a connection pad, a magnetic tunnel junction, and a bit line provided in an embodiment of the present application.

[0044] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0045] Here, exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] As Figures 1 to 3 shown, an embodiment of the present application provides a semiconductor structure, including a substrate 400 and a plurality of memory cells disposed on the substrate 400.

[0047] In an embodiment of the present application, the substrate 400 is a semiconductor substrate, for example, it can be a Si substrate, a Ge substrate, a SiGe substrate, a SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc. It can also be a stacked structure, such as Si / SiGe, etc. It can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. In this embodiment, the substrate 400 can be a single-crystalline silicon substrate for supporting the device structure thereon.

[0048] Among them, the plurality of memory cells are arranged in a staggered manner on the substrate 400. Among them, the plurality of memory cells being arranged in a staggered manner can mean that the memory cells in adjacent two rows or adjacent two columns are arranged staggeredly, as Figure 1 shown, or it can also mean that the memory cells in adjacent two rows or adjacent two columns are arranged oppositely, as Figure 2 shown.

[0049] The memory cell includes an odd number of vertical transistors 110, a connection pad 120, and a magnetic tunnel junction 130. That is, each memory cell may include 3 vertical transistors 110, 5 vertical transistors 110, … or 2n - 1 vertical transistors 110, where n is a positive integer.

[0050] Among them, the connection pad 120 is connected to one end of the odd number of vertical transistors 110, and a magnetic tunnel junction 130 is located on a connection pad 120, so that the odd number of vertical transistors 110 are connected to a magnetic tunnel junction 130 through the connection pad 120.

[0051] The vertical transistor includes a source electrode, a drain electrode, a gate electrode, and a channel. Multiple vertical transistors can share a source plate 111 to simplify the manufacturing process. Specifically, as shown in Figure 4 As shown, a source plate 111 is formed on the substrate 400. The source plate 111 is the source electrode of each vertical transistor. The material of the source plate 111 can be indium tin metal oxide (ITO), molybdenum (Mo), aluminum (Al), titanium aluminum alloy (Ti / Al), etc.

[0052] A plurality of channels 112 are formed on the source plate 111, and a plurality of word lines 200 arranged at intervals are formed around the channels 113. Among them, an isolation layer 501 is also provided between the source plate 111 and the word line 200. The isolation layer 501 is used to isolate the source plate 111 and the word line 200. The material of the isolation layer 501 can be silicon oxide. The material of the channel 112 can include single crystal semiconductors. The single crystal semiconductor can be, for example, single crystal silicon or single crystal germanium, to improve the conductivity of the vertical transistor, so that the vertical transistor 110 can provide a larger write current and improve the driving ability of the memory cell. A drain electrode is formed on each channel 112. Then, a channel 112, the word line 200 where the channel 112 is located, the source plate 111, and the drain electrode on the channel 112 form a vertical transistor. The word line 200 where the channel is located is the gate electrode of the vertical transistor.

[0053] One end of the channel 112 in contact with the source plate 111 is called the bottom end of the channel 112, and the end opposite to the bottom end is called the top end of the channel 112. Then, the drain electrode of the vertical transistor is formed at the top end of the channel 112. Dielectric layers 113 are formed between the channel 112 and the word line 200, between the channel 112 and the source plate 111, and between the channel 112 and the drain electrode. The material of the dielectric layer 113 includes high-k oxides, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium oxynitride (HfON), etc.

[0054] Above an odd number of vertical transistors 110, a connection pad 120 is formed such that one end of the odd number of vertical transistors 110 is connected to one connection pad 120. On each connection pad 120, a magnetic tunnel junction 130 is formed such that the odd number of vertical transistors 110 is connected to one magnetic tunnel junction 130 through the connection pad 120.

[0055] In one embodiment, referring to Figure 3 , a single connection pad 120 is connected to one end of three vertical transistors 110. The cross-section of the vertical transistor 110 in the direction of the surface of the substrate 400 is circular, and the cross-section of the connection pad 120 in the direction of the surface of the substrate 400 is triangular, and the vertices of the triangle are respectively located at the midpoints of the circular cross-sections. That is, the vertex a of the triangle is located at the midpoint of the circular cross-section of the first vertical transistor 110, the vertex b of the triangle is located at the midpoint of the circular cross-section of the second vertical transistor 110, and the vertex c of the triangle is located at the midpoint of the circular cross-section of the third vertical transistor 110 to achieve the mutual connection between the connection pad 120 and the three vertical transistors 110. The projection of the magnetic tunnel junction 130 on the substrate 400 is located inside the projection of the connection pad 120 on the substrate 400 to achieve the connection between one magnetic tunnel junction 130 and one connection pad 120.

[0056] By making the projection of the connection pad 120 on the substrate 400 triangular and making the midpoints of the circular cross-sections of the three vertical transistors 110 located at the three vertices of the triangle, the area of the triangular connection pad 120 is larger, and the area of the magnetic tunnel junction 130 located on the connection pad 120 on the substrate 400 can also be larger.

[0057] In one embodiment, the vertical transistors 110 in adjacent two rows of memory cells are located in three consecutive rows of the array structure. That is, three consecutive rows in the vertical transistor 110 array are sequentially labeled as the (i - 1)-th row, the i-th row, and the (i + 1)-th row. Two consecutive rows in the memory cell array are sequentially labeled as the (j - 1)-th row and the j-th row. The vertical transistors 110 in the memory cells of the (j - 1)-th row are located in the (i - 1)-th row and the i-th row of the vertical transistor 110 array, and the vertical transistors 110 in the memory cells of the j-th row are located in the i-th row and the (i + 1)-th row of the vertical transistor 110 array. By setting like this, the pattern layout of the semiconductor is more uniform, which is beneficial to the fabrication of the semiconductor.

[0058] In one embodiment, the semiconductor structure further includes a plurality of word lines 200, the plurality of word lines 200 are arranged at intervals, and the extending direction of the word lines 200 is the same as one of the side length directions of the triangle. As Figure 3As shown, the extending direction of the word line 200 is along the straight line passing through point d and point e. The projection of the connection pad 120 on the substrate 400 is triangle abc, and the straight line passing through point d and point e is parallel to the straight line passing through point a and point c. By such an arrangement, the distance between two adjacent word lines 200 is relatively large, which can simplify the patterning process of the word line 200.

[0059] In one embodiment, the word line 200 includes a gate electrode portion 201 and a wire portion 202. The gate electrode portion 201 is connected to the channel of the vertical transistor 110 in a single memory cell, and the wire portion 202 is connected to multiple gate electrode portions 201. The projections of the gate electrode portion 201 and the connection pad 120 on the surface of the substrate 400 coincide. That is, when the projection of the gate electrode portion is a triangle, the projection of the connection pad 120 is also a triangle, and the two triangles have the same size, and the gate electrode portion is directly below the connection pad 120.

[0060] In one embodiment, the gate electrode portion 201 and the wire portion 202 are formed in the same etching step. By such an arrangement, the connection between the gate electrode portion and the wire portion 202 can be achieved through one-step etching, and there is no need to fabricate connection holes.

[0061] In one embodiment, the width d1 of the word line 200 portion is less than the pitch d2 between the vertical transistors 110. By such an arrangement, the interval between two word lines 200 is relatively large, which can simplify the patterning process of the word line 200.

[0062] A magnetic tunnel junction 130 is formed above the connection pad 120. The magnetic tunnel junction 130 includes a fixed layer, an insulating layer, and a free layer stacked in sequence. The magnetization direction of the fixed layer is fixed, while the magnetization direction of the free layer is easily changed under the action of a magnetic field or a spin-polarized current. The insulating layer is used to isolate the fixed layer and the free layer. The materials of the fixed layer and the free layer can be the same or different materials. For example, they can be iron (Fe), cobalt (Co), nickel (Ni), or their alloys. The thicknesses of the fixed layer and the free layer can be the same or different, the sizes can be the same or different, and the shapes can be the same or different. For example, they can be cylindrical or square-columnar.

[0063] When current flows from the fixed layer into the free layer, the magnetization direction of the free layer is parallel to the magnetization direction of the fixed layer, and the resistance of the magnetic tunnel junction is small, and the memory cell completes writing data "0". When the current flows from the free layer to the fixed layer, the magnetization direction of the free layer is antiparallel to the magnetization direction of the fixed layer, and the resistance of the magnetic tunnel junction is large, and the memory cell completes writing data "1".

[0064] Multiple bit lines 300 can also be formed on the magnetic tunnel junction 130 to improve the problem of relatively high resistance of the embedded bit lines. The direction in which the word line 200 extends is referred to as the first direction, and the direction in which the bit line 300 extends is referred to as the second direction. Then, multiple bit lines 300 extending along the second direction are formed on the magnetic tunnel junction 130. Each bit line 300 can be connected to multiple magnetic tunnel junctions 130, and the first direction and the second direction can be perpendicular. Then, by applying voltages to the word line 200 and the bit line 300, currents are generated and then magnetic fields are generated to change the magnetization direction of the free layer, so as to realize the reading and writing of the magnetic random access memory.

[0065] For a semiconductor structure provided by the present application, compared with a single vertical transistor 110 driving a magnetic tunnel junction 130, a memory cell in which an odd number of vertical transistors 110 drive a magnetic tunnel junction 130 has a greater driving ability. Among them, the channel material of the vertical transistor 110 includes single-crystal semiconductor, and the vertical transistor 110 has higher conductivity to improve the driving ability of the vertical transistor 110, and the driving ability of the memory cell can be further improved.

[0066] Another embodiment of the present application provides a manufacturing method of a semiconductor structure, including:

[0067] S51: Provide a substrate 400, and form multiple vertical transistors 110 on the substrate 400.

[0068] Among them, the substrate 400 is a semiconductor substrate, and a source electrode plate 111 is formed on the substrate 400, as Figure 4 shown. Specifically, a conductive material is deposited on the substrate 400 by using an atomic layer deposition method or a chemical vapor deposition method, etc. For example, it can be indium tin metal oxide (ITO), molybdenum (Mo), aluminum (Al), titanium-aluminum alloy (Ti / Al), etc. A planarization process is performed on the deposited conductive material to form the source electrode plate 111 on the substrate 400. Referring to Figure 4 and Figure 5 , a single-crystal semiconductor material, such as single-crystalline silicon or single-crystalline germanium, is deposited on the source electrode plate 111, and a planarization process is performed on the deposited semiconductor material to form a channel layer on the isolation layer. The channel layer is etched to form multiple vertical channels 112. Referring to Figure 6 , a high-k dielectric layer 113, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium oxynitride (HfON), etc., is formed outside the channel 112.

[0069] Then, continue to refer to Figure 6, deposit a dielectric material, such as silicon oxide, silicon nitride, etc., on the source electrode plate 111, and perform a planarization process on the deposited dielectric material to form an isolation layer 501 on the source electrode plate 111. Then, form spaced-apart word lines 200 on the isolation layer 501. First, deposit a metal material on the isolation layer 501. The metal material can be, for example, tungsten (W), molybdenum (Mo), etc., and perform a planarization process on the metal material to form a word line plate 200' on the isolation layer 501.

[0070] Form a plurality of triangular mask patterns on the gate electrode plate, and make the projections of the three vertical channels on the mask pattern located inside the triangular mask pattern. Form a plurality of strip-shaped mask patterns on the gate electrode plate, and make the strip-shaped mask patterns overlap with the triangular mask patterns. Use the mask pattern as a mask to etch the gate electrode plate to form word lines, and obtain Figures 7 to 9 the structure of Figure 7 is the top view of the word line, Figure 8 is the cross-sectional view at the position of the i-th row of vertical transistors, Figure 9 is the cross-sectional view at the position of the (i + 1)-th row of vertical transistors.

[0071] When patterning on the gate electrode plate, a conventional patterning process can be used, or a more precise self-aligned double patterning technology (Self-aligned Double Patterning, abbreviated as: SADP) or self-aligned quadruple patterning technology (Self-aligned Quadruple Patterning, abbreviated as: SAQP) can be used.

[0072] Subsequently, deposit a dielectric material on the surface of the word line 200 to form a covering layer 502 for the purpose of protecting the word line 200. Then, form a drain on the channel 112. Each channel 112 has a corresponding drain. The method of forming the drain can be to remove a part of the single-crystal semiconductor material at the top of the channel 112 to form a groove in the channel 112, and fill the groove with a conductive material to form the drain. Another method of forming the drain can be to deposit a conductive material on the channel 112 and the covering layer 502, and then remove the conductive material on the covering layer 502 to form a drain on the channel 112.

[0073] S52. Form a plurality of connection pads 120 above the plurality of vertical transistors 110 away from the substrate 400, so that the projection of one connection pad 120 on the substrate 400 overlaps with the projections of an odd number of vertical transistors 110.

[0074] Among them, a metal layer is formed above a plurality of vertical transistors 110 away from the substrate 400, a mask pattern is formed on the metal layer, and the projections of an odd number of vertical transistors 110 on the mask pattern are located inside the mask pattern. Then, the metal layer is etched with the mask pattern as a shield to obtain the connection pads 120, as Figure 10 shown, so as to realize the connection between the drains of an odd number of vertical transistors 110 and the connection pads 120.

[0075] S53. A magnetic tunnel junction 130 is formed above each connection pad 120 away from the vertical transistor 110.

[0076] A dielectric material, such as an oxide, is deposited above the connection pads 120 and the covering layer 502 to form a dielectric layer 503 covering the connection pads 120. Then, a fixed layer 131, an insulating layer 132, and a free layer 133 are sequentially formed on the dielectric layer 503. The fixed layer 131 is in contact with the upper part of the connection pad 120. Here, the end of the fixed layer 131 in contact with the connection pad 120 is called the upper part of the connection pad 120.

[0077] Specifically, two directions parallel to the substrate 400 are respectively called the X direction and the Y direction. A fixed layer plate, an insulating layer plate, and a free layer plate are sequentially formed on the dielectric layer 503, and the fixed layer plate, the insulating layer plate, and the free layer plate are patterned in both the X direction and the Y direction to obtain the sequentially stacked fixed layer 131, insulating layer 132, and free layer 133.

[0078] For example, a third photoresist layer is formed on the free layer plate. The third photoresist layer includes a plurality of strip-shaped structures arranged at intervals in the X direction. A third mask layer is formed on the sidewalls of the third photoresist layer. The third photoresist layer is removed, and with the third mask layer as a shield, the free layer plate, the insulating layer plate, and the fixed layer plate are etched until the connection pads 120, so that the free layer plate, the insulating layer plate, and the fixed layer plate include a plurality of strip-shaped structures in the X direction, and the strip-shaped structures extend in the Y direction. The third mask layer is removed. Subsequently, a fourth photoresist layer is respectively formed on the plurality of strip-shaped structures. The fourth photoresist layer includes a plurality of strip-shaped structures in the Y direction, and the size of the strip-shaped structures in the X direction is the same as the size of the third mask layer in the X direction. A fourth mask layer is formed on the sidewalls of the fourth photoresist layer. The third photoresist layer is removed and with the fourth mask layer as a shield, the free layer plate, the insulating layer plate, and the fixed layer plate are etched to the connection pads 120, so as to form a magnetic tunnel junction on each connection pad 120, that is, the sequentially stacked fixed layer 131, insulating layer 132, and free layer 133, as Figure 11 shown.

[0079] Continue to refer to Figure 11, multiple bit lines 300 can be formed on the magnetic tunnel junction 113 to improve the problem of relatively high resistance of the buried bit lines. The direction in which the word line 200 extends is referred to as the first direction, and the direction in which the bit line 300 extends is referred to as the second direction. Then, multiple bit lines 300 extending in the second direction are formed on the magnetic tunnel junction 113. Each bit line 300 can be connected to multiple magnetic tunnel junctions 113, and the first direction and the second direction can be perpendicular. Then, by applying voltages to the word line 200 and the bit line 300, a current is generated and thus a magnetic field is generated to change the magnetization direction of the free layer 133 to realize the read and write of the magnetic random access memory.

[0080] In the above technical solution, multiple vertical transistors 110 are formed on the substrate 400, and multiple connection pads 120 are formed above the multiple vertical transistors 110 away from the substrate 400, so that one connection pad 120 is connected to an odd number of vertical transistors 110. A magnetic tunnel junction 130 is formed above each connection pad 120 away from the vertical transistor 110, so as to realize that an odd number of vertical transistors 110 are connected to one magnetic tunnel junction 130 through the connection pad 120. The odd number of vertical transistors 110 provide a write current for one magnetic tunnel junction 130 to improve the driving ability of the storage unit. Moreover, the channel material of the vertical transistor 110 is single-crystal semiconductor, which can further improve the driving ability of the storage unit.

[0081] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0082] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A plurality of memory cells arranged in a staggered manner on a substrate, the memory cells including an odd number of vertical transistors, a connection pad connected to one end of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad; Wherein, the channel material of the vertical transistor includes single-crystal semiconductor; The vertical transistors of the plurality of memory cells are arranged in a staggered array structure on the substrate; The cross-section of the vertical transistor in the direction of the substrate surface is circular, and the cross-section of the connection pad in the direction of the substrate surface is triangular, and the vertices of the triangle are respectively located at the midpoint of the circular cross-section.

2. The semiconductor structure according to claim 1, characterized in that, The single-crystal semiconductor includes single-crystalline silicon or single-crystalline germanium.

3. The semiconductor structure according to claim 1, characterized in that, A single connection pad is connected to one end of three of the vertical transistors.

4. The semiconductor structure according to claim 1, characterized in that, The projection of the magnetic tunnel junction on the substrate is located inside the projection of the connection pad on the substrate.

5. The semiconductor structure according to claim 3, characterized in that, The vertical transistors in adjacent two rows of the memory cells are located in three consecutive rows of the array structure.

6. The semiconductor structure according to claim 1, characterized in that, Further comprising: A plurality of word lines arranged at intervals, the extending direction of the word lines being the same as one of the side lengths of the triangle.

7. The semiconductor structure according to claim 6, characterized in that, The word line includes a gate electrode portion and a wire portion; The gate electrode portion is connected to the channel of the vertical transistor in a single memory cell, and the wire portion is connected to a plurality of the gate electrode portions.

8. The semiconductor structure according to claim 7, characterized in that, The projection of the gate electrode portion and the connection pad on the substrate surface coincide.

9. The semiconductor structure according to claim 8, characterized in that, The gate electrode portion and the wire portion are formed in the same etching step.

10. The semiconductor structure according to claim 7, characterized in that, The width of the word line portion is smaller than the pitch between the vertical transistors.

11. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate, and forming a plurality of vertical transistors on the substrate; wherein, the channel material of the vertical transistor includes single-crystal semiconductor; Forming a plurality of connection pads above the plurality of vertical transistors away from the substrate, so that the projection of one connection pad on the substrate overlaps with the projections of an odd number of vertical transistors; Forming a magnetic tunnel junction above each connection pad away from the vertical transistor; Forming a plurality of vertical transistors on the substrate, specifically including: Forming a common source electrode plate on the substrate; Forming a plurality of vertical channels arranged in an array on the common source electrode plate; Forming a gate electrode portion connecting an odd number of vertical channels and a wire portion connecting the gate electrode portions on the common source electrode plate; A drain electrode plate is formed on the surface of each of the vertical channels away from the common source electrode plate; A gate electrode portion connecting an odd number of vertical channels and a wire portion connecting the gate electrode portion are formed on the common source electrode plate. Specifically, it includes: Depositing a metal material on the surface of the common source electrode plate away from the substrate to form a gate electrode plate; Forming a plurality of triangular mask patterns on the gate electrode plate, and making the projections of three vertical channels on the mask pattern located inside the triangular mask pattern; Forming a plurality of strip-shaped mask patterns on the gate electrode plate, and making the strip-shaped mask patterns overlap with the triangular mask patterns; Etching the gate electrode plate to form a gate electrode portion and a wire portion connecting the gate electrode portion.

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