Improved superconducting Q-life and coherence through backside etching

Abstract

A method for improving the lifetime and coherence time of a qubit in a quantum mechanical device includes: providing a substrate having at least one qubit formed on a front side, the at least one qubit having a capacitor pad; and removing substrate material from a back side at a region opposite the qubit and / or depositing a superconducting metal layer at a back side region opposite the qubit to reduce radio frequency current loss due to at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface.

Description

Technical Field

[0001] The presently claimed embodiments of the present invention relate to superconducting quantum mechanical devices, and more specifically to a method for improving the lifetime and coherence time of qubits in a quantum mechanical device, and a quantum mechanical device having one or more qubits with improved lifetime and coherence time. Background Technology

[0002] In superconducting quantum computing systems, the lifetime (T1) and coherence time (T2) of qubits are fundamental metrics of system performance, with the overall goal of creating a system in which T1 and T2 are as long as possible while maintaining adequately correlated qubit quantum interactions. Longer T1 and T2 times enable the use of quantum computers to solve more complex problems because the longer time metrics allow for more complex computations. T1 and T2 times are improved by using front-side etching to mitigate surface states present at interfaces between various materials. Surface states cause radio frequency (RF) losses, which degrade T1 and T2. Currently, front-side etching of qubits is used to reduce existing surface states near the qubit shunt capacitors, which interact with RF energy and generate losses. These lossy surface states can exist in silicon-air (SA), silicon-metal (SM), and metal-air (MA) interfaces. RF loss mechanisms can include contributions from SA, SM, and MA surface states, as well as contributions from the bulk Si loss tangent.

[0003] Conventionally, qubit performance specifications have been modified through front-side etching. However, front-side etching is undesirable because (i) it significantly interferes with the qubit in situations where electromagnetic (e.g., microwave or radio frequency) fields are very strong, (ii) it cannot be performed once the chip has been flip-chip bump-bonded without debonding the chip for further processing, and (iii) the bump-bonding process itself may affect the final qubit performance metrics. Summary of the Invention

[0004] An aspect of the present invention is to provide a method for improving the lifetime and coherence time of a qubit in a quantum mechanical device. The method includes: providing a substrate having a front side and a back side, the front side having at least one qubit formed thereon, the at least one qubit having a capacitor pad; and removing a quantity of substrate material from the back side of the substrate in a region opposite to the at least one qubit, or depositing at least one superconducting metal layer on the back side of the substrate in the region opposite to the at least one qubit, in order to reduce radio frequency current loss due to at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, thereby enhancing the lifetime (T1) and coherence time (T2) in the at least one qubit.

[0005] In implementation, reducing radio frequency current loss includes reducing current loss by increasing radio frequency overlap with lower loss geometry features in quantum mechanical devices and reducing radio frequency overlap with higher loss geometry features in quantum mechanical devices.

[0006] In one embodiment, removing substrate material from the back side of the substrate in a region opposite the at least one qubit comprises selectively chemically etching the back side of the substrate using a chemical etchant selected according to the substrate material. In one embodiment, prior to chemically etching the back side of the substrate, an initial cavity is formed in the vicinity of the at least one qubit in the back side of the substrate by mechanically removing material from the back side of the substrate, and then the back side of the substrate is chemically etched at the formed initial cavity. In one embodiment, forming the initial cavity in the back side of the substrate comprises defining a surface of the initial cavity having one or more first crystal planes and one or more second crystal planes, such that the chemical etchant preferentially etches the substrate material from the one or more first crystal planes, while substantially not etching the substrate material from the one or more second crystal planes, to form a final etched cavity in the vicinity of the at least one qubit.

[0007] In one embodiment, removing the amount of substrate material from the back side of the substrate includes removing the amount of substrate material from a region on the back side of the substrate to form a trench near the gap between the capacitor pads of the at least one qubit. In another embodiment, removing the amount of substrate material from a region on the back side of the substrate to form the trench near the gap between the capacitor pads of the at least one qubit includes removing the amount of substrate material such that the trench is substantially centered on the gap between the capacitor pads of the at least one qubit.

[0008] In one embodiment, removing a portion of the substrate such that the trench is formed substantially centered on the gap between the capacitor pads of the at least one qubit includes forming the trench to reduce the participation rate of surface states and RF energy density at the silicon-metal (SM) interface and increase the participation rate of surface states and RF energy density at the silicon-air (SA) interface. In this embodiment, as the trench depth increases, the overlap of RF energy density with surface states at the silicon-metal (SM) interface decreases, and the overlap of RF energy density with surface states at the silicon-air (SA) interface increases.

[0009] In one embodiment, removing the amount of substrate material from the back side of the substrate includes removing the amount of substrate material from a region on the back side of the substrate to form a trench near the gap between the capacitor pads of the at least one qubit, and depositing the superconducting metal layer within the trench to reduce RF current loss due to the metal-air (MA) interface. In one embodiment, forming the trench near the gap between the capacitor pads of the at least one qubit includes forming the trench below and centered on one of the capacitor pads of the at least one qubit. In this embodiment, the RF current loss due to the metal-air (MA) interface is reduced based on the back side width of the trench.

[0010] In one embodiment, removing substrate material from the back side of a substrate in a region opposite to at least one qubit includes: applying an etch mask to the back side of the substrate; and etching a selected region on the back side of the substrate opposite to at least one qubit. In another embodiment, the method further includes forming one or more openings in the etch mask in the selected region after applying the etch mask to the back side of the substrate and before etching the selected region on the back side of the substrate. In one embodiment, etching the selected region on the back side of the substrate opposite to the at least one qubit includes chemically etching the substrate to a desired thickness in the selected region to form a trench in the selected region. In yet another embodiment, the method further includes depositing the superconducting metal layer within the trench.

[0011] In one embodiment, removing substrate material from the back side of the substrate in a region opposite to the at least one qubit includes applying a mask film to the back side of the substrate and depositing a metal superconductor on the masked region of the back side of the substrate.

[0012] Another aspect of the present invention is to provide a quantum mechanical device. The quantum mechanical device includes a substrate having a front side and a back side; and a plurality of qubits formed on the front side of the substrate, the plurality of qubits having a plurality of capacitor pads, the substrate including at least one trench formed on the back side of the substrate opposite to at least one of the plurality of qubits, and at least one of the dimensions, shape, or location of the at least one trench or the superconducting material deposited therein being selected to reduce radio frequency current loss due to at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, or any combination thereof, in order to enhance the lifetime (T1) and coherence time (T2) in the at least one qubit.

[0013] In one embodiment, the substrate is selected from the group consisting of silicon, high-resistivity silicon, and sapphire. In another embodiment, the plurality of capacitor pads are made of a superconducting material. In one embodiment, the superconducting material may be one of aluminum (Al) and niobium (Nb).

[0014] In one embodiment, a trench is disposed near the gap between two capacitor pads in a plurality of capacitor pads. In another embodiment, the trench is substantially centered on the gap to reduce the surface state energy density at the silicon-metal (SM) interface and increase the surface state energy density at the silicon-air (SA) interface.

[0015] In one embodiment, the superconducting metal layer is disposed within the trench to reduce radio frequency current loss due to the metal-air (MA) interface. In another embodiment, the trench is formed beneath one or more of the plurality of capacitor pads and centered on one or more of the plurality of capacitor pads. Attached Figure Description

[0016] This patent or application document contains at least one color drawing. A copy of this patent or application disclosure with color drawings will be provided by the Patent Office upon request and payment of the necessary fees.

[0017] The operation and function of the relevant elements of this disclosure, as well as the economy of combination and manufacture of the components, will become more apparent when the following description and appended claims are considered in conjunction with the accompanying drawings, all of which form part of this specification, wherein similar reference numerals denote corresponding components in the various drawings. However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and are not intended to be limiting of the invention.

[0018] Figure 1A This is a schematic cross-sectional view of a qubit device according to an embodiment of the present invention;

[0019] Figure 1B This is an electron microscope (EM) image of the Josephson junction of the qubit device according to an embodiment of the present invention;

[0020] Figure 1C This is an electronic diagram of a quantum bit device coupled to an electromagnetic signal line via a capacitor, according to an embodiment of the present invention;

[0021] Figure 2 This is a contour plot of a simulated two-dimensional electric field generated by the capacitor pad connected to the Josephson junction according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic top view of a qubit device showing the relative positions of the capacitor pad and the Josephson junction (JJ) according to an embodiment of the present invention;

[0023] Figures 4A-4C This is a contour plot of the potential distribution around the capacitor pad according to an embodiment of the present invention;

[0024] Figure 5A The figure shows a graph of surface state energy density versus etching depth (in μm) according to an embodiment of the present invention, the etching depth corresponding to the amount of substrate material removed on the back side of the substrate;

[0025] Figure 5B The relationship between bulk energy density and etching depth (in μm) according to an embodiment of the present invention is shown, the etching depth corresponding to the amount of substrate material removed on the back side of the substrate;

[0026] Figure 6 A graph showing the relationship between the percentage of metal-air (MA) overlap and the back-side etching width according to one embodiment of the present invention is provided.

[0027] Figure 7A and Figure 7B This is a contour plot of the potential distribution around a capacitor pad when a trench is formed under one of the capacitor pads according to an embodiment of the present invention.

[0028] Figure 8 A schematic diagram of a plurality of qubits having corresponding geometrically etched trenches is shown according to an embodiment of the present invention;

[0029] Figures 9A-9D The illustration shows process steps for removing substrate material from the back side of a substrate in a region opposite to at least one qubit (qubit 1, qubit 2, qubit 3) according to an embodiment of the present invention; and

[0030] Figure 10 This is a flowchart of a method for improving the lifetime and coherence time of qubits in a quantum mechanical device according to an embodiment of the present invention. Detailed Implementation

[0031] In embodiments of the invention, back-side etching and / or grounded back-side metallization can be used to modify the RF overlap with bulk silicon, air, and interfaces of different materials. Different loss mechanisms (i.e., bulk silicon loss tangent, SA, MA, and SM surface states) have different amplitudes, and the total RF loss of a qubit is essentially a weighted average of the RF overlaps of different loss mechanisms associated with the specific geometry of that qubit.

[0032] There is an opportunity to enhance (e.g., maximize) lifetime (T1) and coherence time (T2) by reducing (e.g., minimizing) total loss through increasing RF overlap with low-loss geometry and reducing overlap with high-loss geometry.

[0033] Different processing flows can be implemented to achieve similar physical structures. Furthermore, different manufacturing lines can use different processing protocols. Both of these issues can potentially alter which material interface contributes most to RF loss. Therefore, the material interface of greatest concern can vary depending on the specific processing choices made during manufacturing.

[0034] Therefore, it can be beneficial to have flexible strategies for RF loss reduction (e.g., minimization), in which the amount of RF overlap with various geometries within the qubit can be manipulated to accommodate different potential loss mechanisms that may arise from different process flows, with the goal of minimizing the overall loss.

[0035] As also described in the following paragraphs, T1 and T2 in a superconducting qubit system can be enhanced or increased (e.g., maximized) using two device modification methods. The first method involves etching a substrate from the back side of the qubit or qubit chip. The second method involves metallizing and grounding the back side of the qubit or qubit chip. These two methods can be implemented separately or independently, or together as needed, depending on the specific circumstances.

[0036] As will be shown in the following paragraphs, simulations demonstrate that fully back-side etched qubits enable a reduction in RF overlap (or RF participation factor) with silicon-air (SA) and silicon-metal (SM) surface states and bulk silicon. However, metal-air (MA) overlap increases with the device geometry of a fully back-side etched qubit. MA overlap can be reduced (e.g., minimized) by appropriately etching the back side of the chip close to the qubit, metallizing the back side of the chip, and optionally grounding the back side of the chip. Thus, for example, if the contribution of RF damage from the MA interface to the loss is smaller than that of bulk Si, and the contributions of SA and SM, an overall improvement in T1 and T2 can be achieved when the qubit is fully back-side etched. If the RF loss generated from the MA interface is a more significant contributor to the RF loss compared to the contributions of bulk Si, and SA and SM, the back side of the chip can be appropriately etched, metallized with a superconductor, and optionally grounded to minimize the total RF loss. In the preceding paragraphs, we often refer to silicon (Si) or bulk Si as an example of a substrate. However, as is recognized and described in the following paragraphs, other materials, such as high-resistivity silicon and sapphire, may also be used.

[0037] Figure 1A This is a schematic cross-sectional view of a qubit device 100 according to an embodiment of the present invention. Figure 1AAs shown, the qubit device 100 includes a Josephson junction 102 and capacitor pads 104A and 104B. The Josephson junction 102 is connected to capacitor pads 104A and 104B. Capacitor pads 104A and 104B can then be capacitively coupled to electromagnetic (e.g., microwave or radio frequency) signal lines 106A, 106B, and 106C via, for example, capacitors 108A, 108B, and 108C.

[0038] Figure 1B This is an electron microscope (EM) image of a Josephson junction according to an embodiment of the present invention. In this embodiment, the Josephson junction may have a diameter of approximately 100 x 100 nm. 2 Size.

[0039] Figure 1C This is an electronic diagram of a qubit device 100 coupled to an electromagnetic signal line via capacitors 108A, 108B, and 108C according to an embodiment of the present invention. The Josephson junction 102 has an internal capacitance C. j and internal inductance L j (For example, L) j It is approximately 20 nH and C j It is approximately 1 fF). However, as must be recognized, the internal inductance L of the Josephson junction... j and internal capacitor C j It can have other values ​​depending on the construction of the Josephson junction 102. Besides the internal capacitance C of the Josephson junction... j In addition, due to capacitor pads 104A and 104B, the qubit 100 also has a coupling capacitance or signal capacitance C. s In this embodiment, the capacitance C (from capacitor pads 104A and 104B) s It can be approximately 60 fF. However, depending on the size, geometry, or shape of the capacitor pads 104A and 104B, the capacitance C... s It can also have other values.

[0040] In the embodiment, the resonant frequency is determined by the Josephson junction (including the internal capacitance C). j and inductor L j ) and associated capacitor C from capacitor pads 104A and 104B. s The capacitance and resistance contributions of both are determined. Therefore, for example, the first resonant frequency f of the qubit... 01 It depends on the device capacitance and can be expressed mathematically by the following equation (1). For example, “0” in the exponent indicates the ground state of Josephson junction 102 and “1” in the exponent indicates the first excited state of Josephson junction 102.

[0041] (1)

[0042] Energy E j and E c It can be represented by the following two equations (2) and (3).

[0043] (2)

[0044] (3)

[0045] Where e is the electron charge, h is Planck's constant, and C ∑ It is the sum of all capacitances, and I c It is the critical current (Ambegaokar-Baratoff), given by the following equation (4).

[0046] (4)

[0047] Where R n Δ is the resistance of the Josephson junction (JJ), and Δ is the superconducting band gap, a material property independent of the material geometry, where the size of the superconducting band gap indicates the energy gain of two electrons when they form a Cooper pair. The band gap depends on temperature and increases as temperature decreases.

[0048] Therefore, by changing the capacitance C ∑ Associated RF field distribution (including capacitance C) s The contribution of the qubit may alter or change its resonant frequency (e.g., the first resonant frequency f). 01 Furthermore, it alters the overlap (or participation rate) of the RF current with loss sources associated with at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, which in turn reduces the amount of total RF loss in order to enhance the lifetime (T1) and coherence time (T2) in the at least one qubit.

[0049] Figure 2 This is a contour plot of a simulated two-dimensional electric field generated by capacitor pads 104A and 104B connected to the Josephson junction 102 according to an embodiment of the present invention. The two capacitor pads 104A and 104B of the qubit 100 are in... Figure 2 The bars are represented as bars. A Josephson junction 102 (not shown) is located between these two bars 104A and 104B. For example, the left bar corresponding to capacitor pad 104A can be connected to zero potential, while the right bar corresponding to capacitor pad 104B can be connected to a higher potential of 1V (e.g., this could result in approximately 7 × 10⁻⁶ V). 3 (Field strength in V / m). Figure 2In the diagram, electron contour plots are superimposed on a representation of capacitor pads 104A and 104B, which are part of a quantum mechanical device 200. A qubit 100 is also part of the quantum mechanical device 200, which also includes a substrate 202. The substrate 202 has a front side 202A and a back side 202B. Figure 2 The capacitor pads 104A and 104B, represented as bars, and the Josephson junction 102 located between the two capacitor pads 104A and 104B at qubit 100 are located on the front side 200A of the substrate 202 of the quantum mechanical device 200.

[0050] Changes in the electric field distribution indicate changes in the effective dielectric constant of substrate 202. The capacitance of quantum mechanical device 200 is related to the effective dielectric constant of substrate 202. Changes in the electric field distribution can be achieved by altering the thickness of substrate 200 at a specific location within substrate 202. For example, this can be performed by etching substrate 202 from the back side 202B (i.e., removing substrate material from the back side 202B). Changes in the electric field distribution attributable to the etching of substrate 202 at the back side 202B indicate changes in the capacitance of the quantum mechanical device.

[0051] Figure 3 This is a schematic top view of a qubit device 100 according to an embodiment of the present invention, showing the relative positions of capacitor pads 104A and 104B to the Josephson junction (JJ) 102. The qubit device 100 is surrounded by a ground plane 300, which is part of the quantum mechanical device 200.

[0052] Figures 4A-4C This is a contour plot of the potential distribution around capacitor pads 104A and 104B according to an embodiment of the present invention. Figure 4A The capacitor pads 104A and 104B connected to the Josephson junction 102 are along... Figure 3 The contour plot of the simulated two-dimensional electric field generated by section line 4-4 shown is illustrated. Electrostatic calculations can be used to estimate the RF energy density overlay with various surface states. This is a reasonable approach because the RF wavelength is much larger than the device geometry. Potential contour lines 400 are drawn around the ends of capacitor pads 104A and 104B. Figure 4A The potential distribution around Josephson junction 102 is shown, with the back side 202B of the substrate 202 of quantum mechanical device 200 unetched. The ends of capacitor pads 104A and 104B are identifiable by the presence of a higher concentration of potential 400. Josephson junction 102 is located between the ends of capacitor pads 104A and 104B. Figure 4B The potential distribution around Josephson junction 102 is shown. Josephson junction 102 is also located between the ends of capacitor pad 104A and capacitor pad 104B. However, as Figure 4B As shown, the back side 202B of substrate 202 is etched near Josephson junction 102. The outline of the etched material on substrate 202 is shown as a trapezoidal shape 402, where more material is removed near Josephson junction 102 than further away. The removal of material at the back side 202B of substrate 202 alters the shape of potential line 400, and thus changes the potential distribution around or near Josephson junction 102. Therefore, this indicates that the capacitance of qubits 100 around Josephson junction 102 and capacitor pads 104A and 104B is altered. Figure 4C The potential distribution around Josephson junction 102 is shown. Josephson junction 102 is also located between the ends of capacitor pad 104A and capacitor pad 104B. Figure 4C As shown, with Figure 4B Compared to the etch profile shown, the back side 202B of substrate 202 is etched more near Josephson junction 102. The outline of the etched material of substrate 202 is shown as a trapezoidal shape 404, wherein... Figure 4B Compared to the trapezoidal profile 402 shown, even more material is removed near the Josephson junction 102. The removal of material at the back side 202B of the substrate 202 alters the shape of the potential line 400, and thus changes the potential distribution around or near the Josephson junction 102. Therefore, this indicates the capacitance of the qubits around the Josephson junction 102 and the capacitor pads 104A and 104B. Figure 4B Compared to the changes, it is more fundamental.

[0053] Figure 5A A graph showing the relationship between surface state energy density and etching depth (in μm) according to an embodiment of the present invention is shown, the etching depth corresponding to the amount of substrate material removed at the back side 202B of substrate 202. Figure 5A Curve 502 in the figure shows the change in surface state energy density at the silicon-air (SA) interface with etch depth. Figure 5A Curve 504 in the figure shows the change in surface state energy density at the silicon-metal (SM) interface with etch depth. Figure 5A Curve 506 in the figure shows the change in surface state energy density at the metal-air (MA) interface with etching depth.

[0054] like Figure 5A As shown, more material is removed from the back side of qubit 100 to form trenches 402 and 404 of increased depth, as... Figures 4A-4C The diagram depicts an increased participation rate of surface states with RF energy density at the silicon-air (SA) interface (curve 502). Figure 5A As shown, more material is removed from the back side of the qubit to form a trench with increased depth, such as Figures 4A-4CThe depiction shows that at the silicon-metal (SM) interface, the participation rate of surface states in RF energy density decreases (curve 504). For example... Figure 5A As shown, more material is removed from the back side of the qubit to form a trench with increased depth, such as Figures 4A-4C As depicted, for the metal-air (MA) interface, the participation rate of surface states with RF energy density remains substantially flat or constant (curve 506). Figure 5A Point "PA" in the middle and Figure 4A The configuration shown corresponds to a situation where no material is removed from the back side 202B of the substrate 202. Figure 5A The point "PB" in the middle corresponds to Figure 4B The configuration shown in the diagram involves removing relatively little material from the back side 202B of the substrate 202. Figure 5A The point "PC" in the middle and Figure 4C The configuration shown corresponds to the removal of a relatively large amount of material from the back side 202B of the substrate 202. The point "PC" corresponds to... Figure 4C The configuration shown in the figure has virtually no material remaining in the area directly beneath the Josephson junction. At point "PC", curve 502 drops sharply.

[0055] like Figure 5A As shown, the RF overlap with the SA surface state is reduced by more than about 90%, the RF overlap with the SM surface state is reduced by more than about 90%, and the RF overlap with the MA surface state is increased by more than about 2 times.

[0056] Figure 5B The volume energy density relative to the etching depth (in μm) according to an embodiment of the present invention is shown, which corresponds to the removal of a certain amount of substrate material at the back side 202B of the substrate 202. Figure 5B Curve 508 in the figure shows the change in bulk energy density of silicon with etch depth. Figure 5B Curve 509 in the figure shows the variation of air volume energy density with etching depth. For example... Figure 5B As shown, more material is removed from the back side of qubit 100 to form trenches 402 and 404 of increased depth, as... Figure 4A As depicted in Figure C of Figure 4, the participation rate of silicon in bulk energy density decreases (curve 508). Figure 5B As shown, more material is removed from the back side of qubits 100 and 200 to form trenches 402 and 404 of increased depth, as... Figures 4A-4C The depiction shows an increase in the participation rate of volumetric energy density with air (curve 509). For example... Figure 5B As shown, at point “PC”, the RF overlap with silicon is reduced by about 85% to about 15%, and the RF overlap with air is increased by more than about 8 times to about 85%.

[0057] Figure 6 A graph showing the percentage fraction of MA relative to the back-side etch width according to an embodiment of the invention is shown. The term "back-side etch width" refers here to the width of the trapezoidal trench at the apex of the trapezoidal trench (i.e., at the thinnest point in the substrate). Figure 6 The various curves in the graph correspond to increasing etch depths from the top curve to the bottom curve, as shown. For example, the top curve corresponds to a substrate thickness (e.g., Si) of 25 μm at the apex of the trapezoidal trench, while the bottom curve corresponds to a substrate thickness (e.g., Si) of 2 μm at the apex of the trapezoidal trench. For the deepest trenches (i.e., the thinnest portion of the substrate near the qubits), the fraction of MA changes more significantly as a function of the back-side etch width, as shown... Figure 6 The bottom curve is shown in the figure.

[0058] Figure 7A and Figure 7B This is a contour plot of the potential distribution around capacitor pads 104A and 104B when a trench is formed beneath one of the capacitor pads according to an embodiment of the present invention. In one embodiment, as Figure 7A and Figure 7B As shown, one capacitor pad is biased, while the other is grounded. In one embodiment, a trench is located directly beneath the biased capacitor pad to alter the potential and electric field generated around a particular capacitor pad. In another embodiment, a metal layer may be deposited within the trench. The metal layer may be grounded. Note that when the substrate is etched in this manner, there is an increase in capacitance, which results in a corresponding change in the qubit operating frequency. To maintain an appropriate operating frequency, the geometry of the shunt capacitors can be modified to reduce their total capacitance to be closer to that of an unetched device instance, which will then have an additional effect on the RF energy density overlap factor with different surface state regions.

[0059] Figure 7A It shows that the corresponding Figure 6 The device profile represents the fraction of the MA at point "PL". Compared to an unetched design without backside metal, this device profile reduces the RF energy density overlapping with the MA by approximately 40%, and serves as an example of the concept that energy density overlapping with different surface state types can be minimized by appropriately modifying the device profile geometry. RF overlap with silicon increases to approximately 95%. RF overlap with air decreases to approximately 5%. RF overlap with SA surface states decreases by approximately 40%. RF overlap with SM surface states increases by approximately 40%. RF overlap with MA surface states decreases by approximately 40%.

[0060] Figure 7B It shows that the corresponding Figure 6The device profile is a portion of the MA (Main Body) marked with the point "PM". Compared to an unetched design without backside metal, this device profile reduces the RF energy density overlap with the MA by approximately 85%, and this device profile represents an example of the concept that energy density overlap with different surface state species can be minimized by appropriately modifying the device profile geometry. RF overlap with silicon increases to approximately 99%. RF overlap with air decreases to approximately 1%. RF overlap with SA surface states decreases by approximately 85%. RF overlap with SM surface states increases by approximately 14 times. RF overlap with MA surface states decreases by approximately 85%.

[0061] Figure 8 A schematic diagram of a plurality of qubits having corresponding geometrically etched trenches is shown according to an embodiment of the present invention. For example... Figure 8 As shown, the geometry of the back-side etching can be altered, for example, by using a chemical etchant such as KOH or TMAH in combination with dry etching, to change the process flow used to achieve the back-side etching of the substrate. Furthermore, anisotropic etching and the resulting self-limiting etching characteristics allow for various geometric profiles to be achieved using back-side etching. For example, substrate material can be removed from the back side of the substrate in a region opposite the at least one qubit by using selective chemical etching. The chemical etchant can be selected depending on the substrate material. In one embodiment, before chemical etching of the back side, one or more initial cavities can be formed in the back side of the substrate near the at least one qubit by, for example, mechanically removing material from the back side of the substrate. After mechanical removal, chemical etching of the back side of the substrate at the formed initial cavities can be performed, for example. By forming initial cavities in the back side of the substrate, a surface of the initial cavity having one or more first crystal planes and one or more second crystal planes can be defined such that the chemical etchant preferentially etches the substrate material from the one or more first crystal planes, while substantially not etching the substrate material from the one or more second crystal planes, to form a final etched cavity or trench near the at least one qubit.

[0062] Figure 8 Also shown is the back side 202B of a substrate 202 having a plurality of trenches 800 according to an embodiment of the invention. For example, the size and / or shape of the trenches can be controlled by selecting an appropriate shape for the initial cavity. In this way, etching of the substrate material stops when one or more first crystal planes (e.g., (111) planes) are substantially eliminated to form the final trenches 800 of size-limited etching. In an embodiment, controlling the amount of material etched includes controlling the etching depth of the final etched trenches from the back side to the front side of the substrate 202.

[0063] Figures 9A-9DThe illustration shows process steps for removing substrate material from the back side 202B of substrate 202 in a region opposite to at least one qubit 100 (qubit 1, qubit 2, qubit 3) according to an embodiment of the present invention. An etching mask 900 (in...) Figure 9B (As shown in the diagram) can be applied to the back side 202B of substrate 202 (in Figure 9A (as shown in the image) and etched with at least one quantum bit 100 (in the image) Figure 9C (Not shown) The selected region 902 at the back side 202B of the substrate 202 (in) Figure 9C (as shown in the figure). In one embodiment, applying the etching mask 900 to the back side 202B of the substrate 202 includes depositing niobium (Nb) on the back side 202B of the substrate 202. In another embodiment, applying the etching mask 900 to the back side 202B of the substrate 202 includes depositing oxide or silicon nitride (SiN) on the back side 202B of the substrate 202. Figure 9D A patterned back-side mask film on an etched qubit wafer is shown, depicting multiple trenches 904 formed therein.

[0064] In one embodiment, after an etch mask 900 is applied to or created on substrate 202, substrate 202 is treated by performing aluminum evaporation on the front side of substrate 202 to create capacitor pads, Josephson junctions, etc. The back-side coated treated substrate is then sliced ​​to produce multiple chips with one or more qubits.

[0065] Figure 10 This is a flowchart of a method for improving the lifetime and coherence time of a qubit in a quantum mechanical device according to an embodiment of the present invention. The method includes providing a substrate having a front side and a back side at 1002, the front side having at least one qubit formed thereon, the at least one qubit including a capacitor pad. The method further includes removing a portion of substrate material from the back side of the substrate at a region opposite to the at least one qubit, or depositing a superconducting metal layer on the back side of the substrate at the region opposite to the at least one qubit, at 1004, to reduce radio frequency current losses due to at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, thereby enhancing the lifetime (T1) and coherence time (T2) in the at least one qubit. In an embodiment, the superconducting metal layer may be grounded.

[0066] In implementation, reducing radio frequency current loss includes reducing current loss by increasing radio frequency overlap with lower loss geometry features in quantum mechanical devices and reducing radio frequency overlap with higher loss geometry features in quantum mechanical devices.

[0067] In one embodiment, removing substrate material from the back side of the substrate in a region opposite the at least one qubit comprises selectively chemically etching the back side of the substrate using a chemical etchant selected according to the substrate material. In one embodiment, prior to chemically etching the back side of the substrate, an initial cavity is formed in the vicinity of the at least one qubit in the back side of the substrate by mechanically removing material from the back side of the substrate, and then the back side of the substrate is chemically etched at the formed initial cavity. In one embodiment, forming the initial cavity in the back side of the substrate comprises defining a surface of the initial cavity having one or more first crystal planes and one or more second crystal planes, such that the chemical etchant preferentially etches the substrate material from the one or more first crystal planes, while substantially not etching the substrate material from the one or more second crystal planes, to form a final etched cavity in the vicinity of the at least one qubit.

[0068] In one embodiment, removing the amount of substrate material from the back side of the substrate includes removing the amount of substrate material from a region on the back side of the substrate to form a trench near the gap between the capacitor pads of the at least one qubit. In one embodiment, removing the amount of substrate material from a region on the back side of the substrate to form the trench near the gap between the capacitor pads of the at least one qubit includes removing the amount of substrate material such that the trench is substantially centered on the gap between the capacitor pads of the at least one qubit. In one embodiment, removing the amount of substrate such that the trench is substantially centered on the gap between the capacitor pads of the at least one qubit includes forming the trench to reduce the participation rate of surface states and RF energy density at the silicon-metal (SM) interface and increase the participation rate of surface states and RF energy density at the silicon-air (SA) interface. In embodiments, as the trench depth increases, the RF energy density overlap with surface states at the silicon-metal (SM) interface decreases, and the RF energy density overlap with surface states at the silicon-air (SA) interface increases.

[0069] In one embodiment, removing the amount of substrate material from the back side of the substrate includes removing the amount of substrate material from a region on the back side of the substrate to form a trench near the gap between the capacitor pads of the at least one qubit, and depositing the superconducting metal layer within the trench to reduce RF current loss due to the metal-air (MA) interface. In one embodiment, forming the trench near the gap between the capacitor pads of the at least one qubit includes forming the trench below and centered on one of the capacitor pads of the at least one qubit. In this embodiment, RF current loss due to the metal-air (MA) interface is reduced based on the back side width of the trench.

[0070] In one embodiment, removing substrate material from the back side of a substrate in a region opposite to at least one qubit includes: applying an etch mask to the back side of the substrate; and etching a selected region on the back side of the substrate opposite to the at least one qubit. In one embodiment, after applying the etch mask to the back side of the substrate and before etching the selected region on the back side of the substrate, one or more openings are formed in the etch mask in the selected region. In one embodiment, etching the selected region on the back side of the substrate opposite to the at least one qubit includes chemically etching the substrate to a desired thickness in the selected region to form a trench in the selected region. In one embodiment, the method further includes depositing the superconducting metal layer within the trench.

[0071] In one embodiment, removing substrate material from the back side of the substrate in a region opposite to the at least one qubit includes applying a mask to the back side of the substrate and depositing a metal superconductor on the masked region of the back side of the substrate.

[0072] As can be understood from the foregoing paragraphs, a quantum mechanical device is also provided. This quantum mechanical device includes 1) a substrate having a front side and a back side; and 2) a plurality of qubits formed on the front side of the substrate, the plurality of qubits including a plurality of capacitor pads. The substrate includes at least one trench formed on the back side of the substrate opposite to at least one of the plurality of qubits. At least one of the size, shape, or location of the at least one trench or the superconducting material deposited therein is selected to reduce radio frequency current loss due to at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, or any combination thereof, in order to enhance the lifetime (T1) and coherence time (T2) in the at least one qubit.

[0073] In one embodiment, the substrate can be any of silicon, high-resistivity silicon, and sapphire. In another embodiment, the plurality of capacitor pads are made of a superconducting material. In one embodiment, the superconducting material can be any of aluminum (Al) and niobium (Nb).

[0074] In one embodiment, a trench is disposed near the gap between two capacitor pads in a plurality of capacitor pads. In another embodiment, the trench is substantially centered on the gap to reduce the surface state energy density at the silicon-metal (SM) interface and increase the surface state energy density at the silicon-air (SA) interface.

[0075] In one embodiment, the superconducting metal layer is disposed within the trench to reduce radio frequency current loss due to the metal-air (MA) interface. In another embodiment, the trench is formed beneath one or more of the plurality of capacitor pads and centered on one or more of the plurality of capacitor pads.

[0076] The aforementioned back-side etching method offers several advantages: different loss mechanisms (i.e., bulk silicon loss tangent, SA, MA, and SM surface states) have different amplitudes, and the total RF loss of a qubit is essentially a weighted linear sum of all loss contributors, such that this weighting is determined by the overlap of RF field strengths with various loss mechanisms. These loss mechanisms happen to be associated with specific geometric features within the qubit. The RF overlap with the interfaces of bulk silicon, air, and SA, MA, and SM surface states is modified by using wafer back-side etching. We note that reducing the energy density overlap with a given device geometry surface generally increases the energy density overlap with other surfaces in the device geometry, provided the overall dimensions of the device electrodes are not significantly altered. Therefore, the aforementioned method can be used when a surface has a higher probability of increasing RF loss than other surface types. Variations in the amount of RF overlap with various interfaces and the bulk substrate (whether silicon or another substrate material) are used to minimize the total RF loss through wafer back-side etching and / or back-side metallization. Therefore, reducing (e.g., minimizing) total loss by increasing RF overlap with low-loss geometries and decreasing RF overlap with higher-loss geometries can increase (e.g., maximize) T1 and T2. We also note that different manufacturing facilities and processes can influence which material interface contributes most to RF loss, thus the interface of greatest concern depends on the process flow and / or manufacturing line. Therefore, flexible strategies for RF loss minimization are beneficial, as different manufacturing lines may require different balances of RF overlap strength with different qubit geometries to minimize how various RF loss mechanisms contribute to total loss.

[0077] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for improving the lifetime and coherence time of a qubit in a quantum mechanical device, comprising: providing a substrate having a front side and a back side, the front side having at least one qubit formed thereon, the at least one qubit including a capacitor pad; and removing an amount of substrate material from the back side of the substrate at a region opposite the at least one qubit to reduce radio frequency current loss due to at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface in order to enhance the lifetime (Tl) and coherence time (T2) in the at least one qubit; wherein removing the amount of substrate material from the back side of the substrate includes removing the amount of substrate material in a region of the back side of the substrate to form a trench proximate a gap between capacitor pads of the at least one qubit.

2. The method of claim 1, wherein reducing radio frequency current loss includes reducing current loss by increasing radio frequency overlap with lower loss geometrical features in the quantum mechanical device and reducing radio frequency overlap with higher loss geometrical features in the quantum mechanical device.

3. The method of claim 1 or 2, wherein removing the substrate material from the back side of the substrate at the region opposite the at least one qubit includes selectively chemically etching the back side of the substrate using a chemical etchant selected according to the substrate material.

4. The method of claim 3, further comprising: forming an initial cavity in the back side of the substrate proximate the at least one qubit by mechanically removing material from the back side of the substrate prior to chemically etching the back side of the substrate and then chemically etching the back side of the substrate at the formed initial cavity.

5. The method of claim 4, wherein forming the initial cavity in the backside of the substrate comprises: defining a facet of the initial cavity having one or more first crystal planes and one or more second crystal planes such that the chemical etchant preferentially etches the substrate material from the one or more first crystal planes while substantially not etching substrate material from the one or more second crystal planes to form a final etched cavity proximate the at least one qubit.

6. The method of claim 1, wherein removing the amount of substrate material in a region of the back side of the substrate to form a trench proximate a gap between capacitor pads of the at least one qubit includes removing an amount of the substrate material such that the trench is substantially concentrated around the gap between capacitor pads of the at least one qubit.

7. The method of claim 6, wherein removing an amount of the substrate such that the trench is substantially centered on the gap between the capacitor pads of the at least one qubit comprises: forming the trench to reduce the participation rate of surface states with silicon-metal (SM) interface RF energy density and increase the participation rate of surface states with silicon-air (SA) interface RF energy density.

8. The method of claim 1, wherein as the depth of the trench increases, the RF energy density overlap with surface states in a silicon-metal (SM) interface decreases and the silicon-air (SA) interface surface state RF energy density overlap increases.

9. The method of claim 1 or 2, wherein removing the amount of substrate material from the backside of the substrate comprises: removing the amount of substrate material in the region of the backside of the substrate to form a trench in the vicinity of a gap between the capacitor pads of the at least one qubit, and depositing a layer of superconducting metal within the trench to reduce radio frequency current loss due to metal-air (MA) interfaces.

10. The method of claim 9, wherein forming the trench in the vicinity of a gap between the capacitor pads of the at least one qubit comprises forming the trench below and centered on one of the capacitor pads of the at least one qubit.

11. The method of claim 1 or 2, wherein radio frequency current loss due to metal-air (MA) interfaces is reduced based on a backside width of the trench.

12. The method of claim 1 or 2, wherein removing the substrate material from the backside of the substrate at the region opposite the at least one qubit comprises: applying an etch mask film to the backside of the substrate, and etching a selected region at the backside of the substrate opposite the at least one qubit.

13. The method of claim 12, further comprising: forming one or more openings in the etch mask film at the selected region after applying the etch mask film to the backside of the substrate and before etching the selected region at the backside of the substrate.

14. The method of claim 13, wherein etching a selected region at a backside of the substrate opposite the at least one qubit comprises: chemically etching a desired thickness of the substrate at the selected region to form a trench at the selected region.

15. The method of claim 14, further comprising depositing a layer of superconducting metal within the trench.

16. The method of claim 1 or 2, wherein removing the substrate material from a backside of the substrate at the region opposite the at least one qubit comprises: applying a mask film to the backside of the substrate, and depositing a metallic superconductor on masked regions of the backside of the substrate.

17. A quantum mechanical device, comprising: a substrate having a frontside and a backside; and a plurality of qubits formed on the frontside of the substrate, the plurality of qubits comprising a plurality of capacitor pads, wherein the substrate comprises at least one trench formed on the backside of the substrate opposite at least one qubit of the plurality of qubits, and wherein the trench is disposed in the vicinity of a gap between two capacitor pads of the plurality of capacitor pads, and wherein at least one of a size, shape, or position of the at least one trench or superconducting material deposited therein is selected to reduce radio frequency current loss due to at least one of a silicon-air (SA) interface, a metal-air (MA) interface, or a silicon-metal (SM) interface, or any combination thereof, to enhance a lifetime (Tl) and a coherence time (T2) in the at least one qubit.

18. The quantum mechanical device of claim 17, wherein the substrate is selected from the group consisting of silicon, high resistivity silicon, and sapphire.

19. The quantum mechanical device of claim 18, wherein the plurality of capacitor pads are made of a superconducting material.

20. The quantum mechanical device of claim 19, wherein the superconducting material is selected from the group consisting of aluminum (Al) and niobium (Nb).

21. The quantum mechanical device of claim 17, wherein the trench is substantially centered on the gap so as to reduce surface state energy density of a silicon-metal (SM) interface and increase surface state energy density of a silicon-air (SA) interface.

22. The quantum mechanical device of claim 17, further comprising a layer of superconducting metal disposed within the trench to reduce radio frequency current loss due to a metal-air (MA) interface.

23. The quantum mechanical device of claim 22, wherein the trench is formed below and centered on one or more of the plurality of capacitor pads.

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