Method and device for determining design yield of integrated circuit layout

Abstract

The present application provides a method and device for determining the design yield of an integrated circuit layout. The method includes: performing optical proximity effect correction on each key layer of the integrated circuit layout, using various lithography simulation models to perform lithography simulation on the corrected data and determine the location of the lithography hotspot, obtaining the key dimensions corresponding to the lithography hotspot locations on each simulation contour, fitting all key dimensions with a Weibull distribution, obtaining the failure probability of the minimum preset key dimension from the cumulative probability distribution function, and then determining the design yield of the corrected data in combination with the failure probabilities corresponding to all lithography hotspot locations, and determining the design yield of the integrated circuit layout based on the design yield of each corrected data. The entire method analyzes the design yield changes caused by lithography process fluctuations through lithography models, and analyzes the failure probability of integrated circuit devices through lithography hotspot statistical information, so that design problems can be discovered in advance, thereby improving the manufacturing yield in wafer production and enhancing process stability.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method and device for determining the design yield of an integrated circuit layout. Background Art

[0002] With the advent of the transistor in the late 1940s, electronic devices have been evolving towards ever-smaller sizes. These small devices can be combined to form complex circuit structures, known as integrated circuits. The development of integrated circuits generally follows Moore's Law, requiring continuous shrinking of feature sizes and the integration of more transistor structures on chips to achieve higher computing power and lower power consumption. Because a company's economic profitability is often directly tied to the yield of integrated circuit devices, yield improvement engineers are required to continuously improve the yield of integrated circuit devices. The yield of an integrated circuit device typically includes both manufacturing yield and design yield. Manufacturing yield is the product of the manufacturing yield of each production process, while design yield is the yield of the integrated circuit layout, reflecting the yield of the design itself.

[0003] Among the various production processes for integrated circuit devices, the photolithography process is key to influencing the yield of integrated circuit devices. During the photolithography process, the pattern on the mask is projected onto the photoresist through an exposure system. When the parameters of the photolithography machine fluctuate, the light intensity on the imaging plane will also change, which may cause photolithography hotspots (such as bridging and necking), thereby affecting the image quality and causing the function of the integrated circuit device to fail. However, traditional design yield determination methods mainly focus on the entire production process of integrated circuit devices, and do not provide design yield analysis specifically for the photolithography process. Because the photolithography process plays an extremely critical role in the production of integrated circuit devices, how to quickly and accurately determine the design yield of the integrated circuit layout for the photolithography process so that yield improvement engineers can better formulate photolithography process parameters, guide photolithography process production, and thus improve the manufacturing yield of the photolithography process has become an urgent problem to be solved. Summary of the Invention

[0004] The present application provides a method and device for determining the design yield of an integrated circuit layout, which can be used to solve the technical problem that traditional design yield determination methods lack design yield analysis specifically for the photolithography process, and thus cannot effectively guide photolithography process production and improve the photolithography process manufacturing yield.

[0005] In a first aspect, an embodiment of the present application provides a method for determining a design yield of an integrated circuit layout, comprising:

[0006] Obtaining an integrated circuit layout file and a computational lithography model of a lithography process at a corresponding process node; the integrated circuit layout file includes at least one key layer, and the computational lithography model includes at least one key layer model, wherein the key layer model is used to model and simulate the lithography process for the matching key layer;

[0007] For any key layer, performing optical proximity effect correction on the key layer to obtain corrected data;

[0008] Performing lithography simulation on the corrected data using respective computational lithography simulation models matched to the key layers to obtain respective simulation profiles formed on a simulation imaging plane, wherein the respective computational lithography simulation models are generated based on a process fluctuation simulation of the key layer model matched to the key layers;

[0009] Detecting a photolithography hotspot position from each simulation profile, the photolithography hotspot position being a position corresponding to a critical dimension smaller than a minimum preset critical dimension, the critical dimension being a minimum profile spacing of the simulation profile;

[0010] For any photolithography hotspot position, obtaining the critical dimension corresponding to the photolithography hotspot position in each simulation profile;

[0011] Performing Weibull distribution fitting on all critical dimensions corresponding to the photolithography hotspot position to obtain a Weibull probability distribution function and a cumulative probability distribution function of the photolithography hotspot position, wherein the cumulative probability distribution function is used to represent the failure probability of each critical dimension;

[0012] Obtaining a failure probability of a minimum preset critical dimension based on a cumulative probability distribution function of the photolithography hotspot position;

[0013] Based on the failure probability of the minimum preset critical dimension corresponding to each lithography hotspot position, the design yield of the critical layer after optical proximity effect correction is obtained;

[0014] Based on the design yield of each key layer after correction of the optical proximity effect, the design yield of the integrated circuit layout file for the photolithography process is obtained.

[0015] In conjunction with the first aspect, in one implementation of the first aspect, detecting the photolithography hotspot position from each simulation profile includes:

[0016] For any simulated contour, using a preset tool to detect the contour spacing of each position on the simulated contour;

[0017] Determine a minimum profile spacing from the profile spacings at various locations, and determine the minimum profile spacing as a critical dimension;

[0018] If the critical dimension is smaller than the minimum preset critical dimension, the position corresponding to the critical dimension is determined as a photolithography hotspot position.

[0019] In conjunction with the first aspect, in an implementation manner of the first aspect, performing Weibull distribution fitting on all critical dimensions corresponding to the lithography hotspot position to obtain the Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position includes:

[0020] According to all the critical dimensions corresponding to the photolithography hotspot positions, fitting is performed using the three sigma criterion to obtain the scale parameter and shape parameter of the Weibull distribution;

[0021] According to the scale parameter and shape parameter of the Weibull distribution, the Weibull probability distribution function and the cumulative probability distribution function of the lithography hotspot position are obtained.

[0022] In combination with the first aspect, in an implementation manner of the first aspect, obtaining the Weibull probability distribution function and the cumulative probability distribution function of the lithography hotspot position according to the scale parameter and shape parameter of the Weibull distribution includes:

[0023] The Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position are obtained by the following formula:

[0024]

[0025]

[0026] Wherein, f(CD;λ,k) is the Weibull probability distribution function of the photolithography hotspot position, f(CD;λ,k) is the cumulative probability distribution function of the photolithography hotspot position, CD is the critical dimension, λ is the scale parameter, and k is the shape parameter.

[0027] In conjunction with the first aspect, in one possible implementation of the first aspect, obtaining the design yield of the key layer after optical proximity effect correction based on the failure probability of the minimum preset critical dimension corresponding to each lithography hotspot position includes:

[0028] The design yield of the key layer after optical proximity effect correction is determined by the following formula:

[0029]

[0030] Wherein, Y(layer) is the design yield of the key layer after correction of optical proximity effect, i is the index of the lithography hotspot position, is the failure probability of the minimum preset critical dimension corresponding to the i-th lithography hotspot position.

[0031] In conjunction with the first aspect, in one implementation of the first aspect, obtaining the design yield of the integrated circuit layout file for the photolithography process based on the design yield of each key layer after correction for the optical proximity effect includes:

[0032] The design yield of the integrated circuit layout file for the photolithography process is determined by the following formula:

[0033]

[0034] Wherein, Y(chip) is the design yield of the integrated circuit layout file for the photolithography process, j is the layer number of the key layer, and Y(layer j ) is the design yield of the jth key layer after optical proximity effect correction.

[0035] In combination with the first aspect, in an implementation manner of the first aspect, the at least one key layer includes at least one of an ion implantation layer, a polysilicon layer, a metal layer, and a metal and transistor interconnection layer.

[0036] In conjunction with the first aspect, in one implementation of the first aspect, each computational lithography simulation model is generated by:

[0037] The pupil lens defocus parameters in the key layer model are adjusted according to preset rules to obtain multiple computational lithography simulation models.

[0038] In a second aspect, an embodiment of the present application provides a device for determining a design yield of an integrated circuit layout, comprising:

[0039] an acquisition unit, configured to acquire an integrated circuit layout file and a computational lithography model of a lithography process at a corresponding process node; the integrated circuit layout file includes at least one key layer, the computational lithography model includes at least one key layer model, and the key layer model is used to model and simulate the lithography process for a matching key layer;

[0040] a correction unit, configured to perform optical proximity effect correction on any key layer to obtain correction data;

[0041] a simulation unit configured to perform lithography simulation on the corrected data using respective computational lithography simulation models matched to the key layer, to obtain respective simulation profiles formed on a simulation imaging plane, wherein the respective computational lithography simulation models are generated based on a process fluctuation simulation of the key layer model matched to the key layer;

[0042] A lithography hotspot detection unit is used to detect a lithography hotspot position from each simulation profile, wherein the lithography hotspot position is a position corresponding to a critical dimension smaller than a minimum preset critical dimension, and the critical dimension is a minimum profile spacing of the simulation profile;

[0043] A critical dimension acquisition unit, configured to acquire, for any photolithography hotspot position, a critical dimension corresponding to the photolithography hotspot position in each simulation profile;

[0044] a fitting unit, configured to perform Weibull distribution fitting on all critical dimensions corresponding to the lithography hotspot position, and obtain a Weibull probability distribution function and a cumulative probability distribution function of the lithography hotspot position, wherein the cumulative probability distribution function is used to represent the failure probability of each critical dimension;

[0045] A failure probability determination unit, configured to obtain a failure probability of a minimum preset critical dimension based on a cumulative probability distribution function of the photolithography hotspot position;

[0046] a key layer design yield determination unit, configured to obtain a design yield of the key layer after optical proximity effect correction based on a failure probability of a minimum preset critical dimension corresponding to each lithography hotspot position;

[0047] The integrated circuit layout design yield determination unit is used to obtain the design yield of the integrated circuit layout file for the photolithography process based on the design yield of each key layer after optical proximity effect correction.

[0048] In conjunction with the second aspect, in one implementation of the second aspect, the photolithography hotspot detection unit is specifically configured to:

[0049] For any simulated contour, using a preset tool to detect the contour spacing of each position on the simulated contour;

[0050] Determine a minimum profile spacing from the profile spacings at various locations, and determine the minimum profile spacing as a critical dimension;

[0051] If the critical dimension is smaller than the minimum preset critical dimension, the position corresponding to the critical dimension is determined as a photolithography hotspot position.

[0052] In conjunction with the second aspect, in one possible implementation of the second aspect, the fitting unit includes:

[0053] a parameter determination module, configured to obtain a scale parameter and a shape parameter of a Weibull distribution by fitting all critical dimensions corresponding to the photolithography hotspot positions using a three-sigma criterion;

[0054] The function determination module is used to obtain the Weibull probability distribution function and the cumulative probability distribution function of the lithography hotspot position according to the scale parameter and shape parameter of the Weibull distribution.

[0055] In conjunction with the second aspect, in one implementation of the second aspect, the function determination module is specifically configured to:

[0056] The Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position are obtained by the following formula:

[0057]

[0058]

[0059] Wherein, f(CD;λ,k) is the Weibull probability distribution function of the photolithography hotspot position, f(CD;λ,k) is the cumulative probability distribution function of the photolithography hotspot position, CD is the critical dimension, λ is the scale parameter, and k is the shape parameter.

[0060] In conjunction with the second aspect, in one implementation of the second aspect, the key layer design yield determination unit is specifically configured to:

[0061] The design yield of the key layer after optical proximity effect correction is determined by the following formula:

[0062]

[0063] Wherein, Y(layer) is the design yield of the key layer after correction of optical proximity effect, i is the index of the lithography hotspot position, is the failure probability of the minimum preset critical dimension corresponding to the i-th lithography hotspot position.

[0064] In conjunction with the second aspect, in one implementation of the second aspect, the integrated circuit layout design yield determination unit is specifically configured to:

[0065] The design yield of the integrated circuit layout file for the photolithography process is determined by the following formula:

[0066]

[0067] Wherein, Y(chip) is the design yield of the integrated circuit layout file for the photolithography process, j is the layer number of the key layer, and Y(layer j ) is the design yield of the jth key layer after optical proximity effect correction.

[0068] In combination with the second aspect, in an implementation manner of the second aspect, the at least one key layer includes at least one of an ion implantation layer, a polysilicon layer, a metal layer, and a metal and transistor interconnection layer.

[0069] In conjunction with the second aspect, in one implementation of the second aspect, each computational lithography simulation model is generated by:

[0070] The pupil lens defocus parameters in the key layer model are adjusted according to preset rules to obtain multiple computational lithography simulation models.

[0071] The present application discloses a method and apparatus for determining the design yield of an integrated circuit layout. In the method, for each key layer of the integrated circuit layout, after correction for optical proximity effect, lithography simulation is performed on the corrected data using multiple computational lithography simulation models obtained by adjusting the corresponding computational lithography model. After determining the lithography hotspot position from the simulation contour, the critical dimensions corresponding to the lithography hotspot position on each simulation contour are obtained for the same lithography hotspot position. A Weibull distribution is fitted for all critical dimensions corresponding to the same lithography hotspot position, and the failure probability of the minimum preset critical dimension is obtained from the cumulative probability distribution function. The design yield of the corrected data is then obtained in combination with the failure probabilities of the minimum preset critical dimensions corresponding to other lithography hotspot positions. Finally, the design yield of the integrated circuit layout for the lithography process is determined based on the design yield of the corrected data of each key layer. The entire method uses a computational lithography model to analyze changes in design yield caused by fluctuations in the lithography process. By using statistical information on lithography hotspots, it analyzes the failure probability of integrated circuit devices caused by lithography hotspots. This allows for early detection of design problems, helping yield engineers effectively analyze the impact of the lithography process on yield and design process parameters tailored to the lithography process, thereby improving manufacturing yield in wafer production and enhancing the stability of process capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 A schematic diagram of the overall flow corresponding to a method for determining the design yield of an integrated circuit layout provided in an embodiment of the present application;

[0073] Figure 2 Schematic diagram of each simulation profile provided in the embodiment of the present application;

[0074] Figure 3 A schematic diagram of the photolithography hotspot types provided in an embodiment of the present application;

[0075] Figure 4 A schematic diagram of the Weibull probability distribution provided in an embodiment of the present application;

[0076] Figure 5A Weibull probability distribution curve corresponding to a photolithography hotspot position in the example provided in the embodiment of the present application;

[0077] Figure 6 A Weibull probability distribution curve corresponding to another lithography hotspot position in the example provided in the embodiment of the present application;

[0078] Figure 7 A schematic diagram of the structure of a device for determining the design yield of an integrated circuit layout provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0080] In order to address the technical problem that traditional design yield determination methods lack design yield analysis specifically for photolithography processes, and thus cannot effectively guide photolithography production and improve photolithography manufacturing yield, this application discloses a method for determining the design yield of an integrated circuit layout through the following embodiments. The design yield determination method provided in the embodiments of this application is applied to determine the design yield of an integrated circuit layout for a photolithography process. In addition, it can also be extended and applied to design yield analysis of other production processes based on the overall concept. Figure 1 The overall flow diagram corresponding to a method for determining the design yield of an integrated circuit layout provided in an embodiment of the present application specifically includes the following steps:

[0081] 101: Obtain an integrated circuit layout file and a computational lithography model of a lithography process at a corresponding process node.

[0082] The integrated circuit layout file may typically be a GDSII file or an OASIS file. The integrated circuit layout file includes at least one key layer. A key layer represents the corresponding key layer layout file. For example, the integrated circuit layout file may be in the .gds file format, such as a file named design.gds. In some embodiments, the at least one key layer may include at least one of an ion implantation layer AA, a polysilicon layer Poly, metal layers M1 and M2, and a metal and transistor interconnect layer CT.

[0083] The process node generally refers to the "feature size" in the integrated circuit processing process. The smaller the size, the higher the process level. It can usually be expressed in nanometers (nm), for example: 55nm.

[0084] The computational lithography model includes at least one key layer model. The key layer model is used to model and simulate the lithography process for the matching key layer. The key layer model matches the key layer layout file.

[0085] The key layer model for each key layer can be in .so file format. For example, the key layer model for the ion implantation layer AA is named AA.model.so. The key layer model is a binary file that stores basic parameters for lithography process simulation, such as light source wavelength (lambda), mask transmission settings (mask), image depth (image depth), pupil lens defocus parameters (defocus), and photoresist (resist) parameters.

[0086] It should be noted that different key layers match different key layer models. In addition, different process nodes also match different computational lithography models.

[0087] For each key layer, perform steps 102 to 109 as follows:

[0088] 102: Perform optical proximity effect correction on the key layer to obtain corrected data.

[0089] Correcting the key layer for optical proximity effect can make the imaging profile of the lithography simulation closer to the layout design pattern. In some embodiments, the key layer model matched by the key layer can be used to correct the key layer for optical proximity effect.

[0090] 103: Perform process fluctuation simulation on the key layer model of the key layer matching to generate multiple computational lithography simulation models.

[0091] Among them, performing process fluctuation simulation is to perform parameter adjustment. In some embodiments, the pupil lens defocus parameters in the key layer model can be adjusted according to preset rules to generate multiple computational lithography simulation models. Exemplarily, the preset rules can be preset parameter adjustment rules, including increasing or decreasing specific parameters according to equal intervals or unequal intervals. In other embodiments, other parameters in the key layer model can also be adjusted, or multiple parameters can be adjusted simultaneously to generate multiple computational lithography simulation models. The specific parameters can be determined according to needs and actual conditions, and the embodiments of the present application do not specifically limit this.

[0092] In this way, by changing the optical parameter settings of the key layer model file for the corrected key layer layout file, the parameter fluctuation of the simulated lithography can be formed, which can more accurately simulate the actual lithography situation.

[0093] It should be noted that one of the computational lithography simulation models is a key layer model.

[0094] 104: Utilizing the respective computational lithography simulation models matched with the key layers, respectively perform lithography simulation on the corrected data to obtain respective simulation profiles formed on the simulation imaging plane.

[0095] Figure 2 Schematic diagram of each simulation profile provided in the embodiment of this application. Figure 2 As shown, in one example, assuming there are two computational lithography simulation models, each computational lithography simulation model performs lithography simulation on the corrected data to form corresponding simulation profiles A1 and B1 on the simulation imaging plane. Profile C is the actual design profile.

[0096] 105: Detect the lithography hotspot position from each simulation contour.

[0097] The photolithography hotspot position is the position corresponding to the critical dimension that is smaller than the minimum preset critical dimension, and the critical dimension is the minimum contour spacing of the simulation contour. For example, Figure 2 As shown, the photolithography hotspot positions include position 1, position 2 and position 3.

[0098] Figure 3 Schematic diagram of the photolithography hotspot type provided in the embodiment of the present application. In one example, Figure 3 The figure shows the superposition effect of the corresponding simulation contours formed on the simulation imaging plane after multiple computational lithography simulation models perform lithography simulation on the correction data when there are many computational lithography simulation models. Figure 3 As shown, the lithography hotspots provided by the embodiment of the present application mainly include pitch and bridge. These two types of exposure errors are closely related to the electrical parameter yield. The location of the pitch is when the critical dimension of the same contour line is smaller than the minimum preset critical dimension. In the actual lithography conditions, there is a possibility that one pattern will be exposed as two patterns. The location of the pitch is as follows: Figure 3 The bridge position is shown as position 1 in the figure. If the critical dimensions of different contour lines are less than a certain threshold, then the exposure pattern under real lithography conditions may have two patterns exposed into one pattern. The bridge position is shown as Figure 3 As shown in positions 2 and 3 in FIG.

[0099] In some embodiments, the lithography hotspot positions can be detected from each simulation profile by the following steps:

[0100] Step 1: For any simulated contour, use a preset tool to detect the contour spacing of each position on the simulated contour.

[0101] Detecting the contour spacing at each position on the simulation contour includes detecting the horizontal and vertical contour spacing of the same contour line in the simulation contour, and detecting the horizontal and vertical contour spacing of different contour lines in the simulation contour.

[0102] Step 2: determine the minimum contour spacing from the contour spacings at various positions, and determine the minimum contour spacing as the critical dimension.

[0103] Step 3: If the critical dimension is smaller than the minimum preset critical dimension, the position corresponding to the critical dimension is determined as the photolithography hotspot position. If the critical dimension is greater than or equal to the minimum preset critical dimension, the position corresponding to the critical dimension is not the photolithography hotspot position.

[0104] Exemplarily, the minimum preset critical dimension may be 70 nm.

[0105] If the critical dimension is smaller than the minimum preset critical dimension, the position corresponding to the critical dimension is considered to be a lithography hotspot, and necking and bridging will occur at this position. Figure 2 and Figure 3 As shown, after detecting one of the simulation contours, three critical dimensions are determined, and the corresponding positions are position 1, position 2 and position 3. These three critical dimensions are all smaller than the minimum preset critical dimension, so position 1, position 2 and position 3 are all lithography hotspot positions.

[0106] In the embodiment of the present application, the location where the lithography hotspot occurs is not detected, and the failure occurs with an extremely low probability event, so the location can be considered reliable.

[0107] 106: For any photolithography hotspot position, obtain the critical dimension corresponding to the photolithography hotspot position in each simulation profile.

[0108] 107: Perform Weibull distribution fitting on all critical dimensions corresponding to the photolithography hotspot position to obtain the Weibull probability distribution function and cumulative probability distribution function of the photolithography hotspot position.

[0109] Among them, the cumulative probability distribution function is used to represent the failure probability of each critical dimension.

[0110] Specifically, the Weibull probability distribution function of the lithography hotspot position can be obtained by the following steps:

[0111] Step 1: According to all the critical dimensions corresponding to the photolithography hotspot positions, the three-sigma criterion is used to perform fitting to obtain the scale parameter and shape parameter of the Weibull distribution.

[0112] The three-sigma criterion states that the sample follows an approximately normal distribution, with sample values ​​concentrated within the interval (μ-3σ, μ+3σ), with a probability of less than 0.3% exceeding this range, where μ is the expectation of the random variable and σ is the standard deviation. Considering the influence of lithography fluctuations, the critical dimension of the lithography hotspot follows a certain probability distribution, and the value lies within a certain interval, with a probability of only 0.3% exceeding this interval. Therefore, in the embodiments of the present application, the critical dimension CD of the lithography hotspot follows a Weibull probability distribution f(CD; λ, k), where λ is the scale parameter and k is the shape parameter.

[0113] Specifically, the expected μ and standard deviation σ of the critical dimension CD can be determined based on all the critical dimensions corresponding to the lithography hotspot position, and then the negatively changing critical dimension CD can be determined. - =μ-3σ, positively changing critical dimension CD + =μ-3σ, the critical dimension is in the interval (CD - , CD + ) is 99.7%. The Weibull probability distribution function and cumulative probability distribution function can be expressed by the following formulas (1) and (2):

[0114]

[0115]

[0116] In formula (1) and formula (2), f(CD; λ, k) is the Weibull probability distribution function of the lithography hotspot position, F(CD; λ, k) is the cumulative probability distribution function of the lithography hotspot position, CD is the critical dimension, λ is the scale parameter, and k is the shape parameter.

[0117] Based on formulas (1) and (2), the scale parameter λ and shape parameter k can be obtained by the following formula (3):

[0118]

[0119] In formula (3), F(CD - ;λ,k) is the critical dimension CD - The corresponding cumulative probability, F(CD + ;λ,k) is the critical dimension CD + The cumulative probability corresponding to the time, E is the expected function of the Weibull probability distribution.

[0120] Step 2: Obtain the Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position based on the scale parameter and shape parameter of the Weibull distribution.

[0121] Specifically, by substituting the fitted scale parameters and shape parameters into formula (1) and formula (2), the Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position can be obtained.

[0122] 108: Obtaining a failure probability of a minimum preset critical dimension based on a cumulative probability distribution function of the lithography hotspot position.

[0123] Specifically, the failure probability of the minimum preset critical size can be expressed by the following formula (4):

[0124] p fault =F(CD min ;λ,k) Formula (4)

[0125] In formula (4), p fault is the probability of failure of the minimum preset critical dimension, CD min is the minimum preset critical dimension, λ is the scale parameter, k is the shape parameter, and F is the cumulative probability distribution function of the lithography hotspot position.

[0126] 109: Based on the failure probability of the minimum preset critical dimension corresponding to each lithography hotspot position, obtain the design yield of the key layer after the optical proximity effect correction.

[0127] Specifically, the design yield of the key layer after optical proximity effect correction can be determined by the following formula (5):

[0128]

[0129] In formula (5), Y(layer) is the design yield of the key layer after optical proximity effect correction, i is the index of the lithography hotspot position, is the failure probability of the minimum preset critical dimension corresponding to the i-th lithography hotspot position.

[0130] 110: Based on the design yield of each key layer after correction of the optical proximity effect, the design yield of the integrated circuit layout file for the photolithography process is obtained.

[0131] Specifically, the design yield of the integrated circuit layout file for the photolithography process can be determined by the following formula (6):

[0132]

[0133] In formula (6), Y(chip) is the design yield of the integrated circuit layout file for the photolithography process, j is the layer number of the key layer, and Y(layer j ) is the design yield of the jth key layer after optical proximity effect correction.

[0134] The following describes a method for determining the design yield of an integrated circuit layout provided in an embodiment of the present application through a specific example.

[0135] For the DUV (Deep Ultra-Violet) dry lithography process under the 55nm process node, the integrated circuit design layout file SRAM.gds and the corresponding computational lithography model model.so are obtained. Among them, the integrated circuit design layout SRAM.gds is a type of 16M storage unit device. Taking the four key layers (ion implantation layer AA, polysilicon Poly, metal and transistor interconnection layer CT, metal layer M1) in the integrated circuit design layout as an example, optical proximity effect correction is performed for each key layer to obtain the corresponding correction data. The pupil lens defocus parameter (defocus) in the key layer model matching each key layer is adjusted according to ±90nm to obtain multiple computational lithography simulation models. Use the computational lithography simulation model to simulate any key layer, count all lithography hotspot positions, and record the key size CD under different computational lithography simulation models (defocus difference) - 、CD ’ and CD + , as shown in Table 1 below.

[0136] Table 1: Critical dimension sizes under different computational lithography simulation models

[0137] index hotPoints Type <![CDATA[CD - ]]> CD′ <![CDATA[CD + ]]> ... ... ... ... ... 137 bridge 67 73 80 ... ... ... ... ... 201 pitching 68 74 78 ... ... ... ... ...

[0138] Under the fluctuation of lithography process, the key dimension of each lithography hotspot position is recorded, and the key dimension size CD is used. - , CD' and CD + Fit the scale parameter and shape parameter of the two-parameter Weibull distribution, and express the two-parameter Weibull distribution under the fluctuation condition through formula (1) and formula (2). Figure 4 The schematic diagram of Weibull probability distribution is shown in Figure 2. Figure 4 The horizontal axis (CD nm) represents the size of the critical dimension (CD), the vertical axis (p(CD)) represents the probability of occurrence of a CD dimension at that location after exposure under the current calculated lithography process conditions, and CD-hot represents the critical dimension at the lithography hotspot. The fitted cumulative probability distribution function is used to obtain the failure probability corresponding to the minimum preset critical dimension (assuming it is 70 nm) that causes design failure.

[0139] Figure 5 This is the Weibull probability distribution curve corresponding to a photolithography hotspot position in the example provided in the embodiment of this application. Figure 5 As shown, the scale parameter k of the fitted Weibull probability distribution curve is 47.2199, the shape parameter λ is 76.8902, the expected value is 75.9838, and the failure criterion is 70. In Table 1, a bridge will occur at the lithography hotspot position with index position 137. According to CD -=67, CD'=73 and CD + =80, the failure probability of this position can be obtained by formula (4)

[0140] Figure 6 This is the Weibull probability distribution curve corresponding to another lithography hotspot position in the example provided in the embodiment of this application. Figure 6 As shown, the scale parameter k of the fitted Weibull probability distribution curve is 61.0334, the shape parameter λ is 75.6436, the expected value is 74.9480, and the failure criterion is 70. Pinching occurs at the lithography hotspot position with index position 201 in Table 1. According to CD - =68, CD'=74 and CD + =78, the failure probability of this position can be obtained by formula (4)

[0141] After obtaining the failure probability at each lithography hotspot, the design yield of the layout file for this layer after optical proximity effect correction can be calculated using formula (5): 0.91. After calculating the design yields of the ion implantation layer AA, polysilicon Poly, metal and transistor interconnect layer CT, and metal layer M1, the design yield of the integrated circuit design layout for the lithography process can be determined using formula (6): Y(chip) = Y(AA)·Y(Poly)·Y(CT)·Y(M1) = 81%.

[0142] Thus, in a method for determining the design yield of an integrated circuit layout disclosed in an embodiment of the present application, for each key layer of the integrated circuit layout, after correction for the optical proximity effect, multiple computational lithography simulation models obtained by adjusting the corresponding computational lithography model are used to perform lithography simulation on the corrected data respectively. After the lithography hotspot position is determined from the simulation contour, the critical dimensions corresponding to the lithography hotspot position on each simulation contour are obtained for the same lithography hotspot position, Weibull distribution fitting is performed on all critical dimensions corresponding to the same lithography hotspot position, and the failure probability of the minimum preset critical dimension is obtained from the cumulative probability distribution function. Combined with the failure probability of the minimum preset critical dimension corresponding to other lithography hotspot positions, the design yield of the corrected data is obtained. Finally, the design yield of the integrated circuit layout for the lithography process is determined based on the design yield of the corrected data of each key layer. The entire method uses a computational lithography model to analyze changes in design yield caused by fluctuations in the lithography process. By using statistical information on lithography hotspots, it analyzes the failure probability of integrated circuit devices caused by lithography hotspots. This allows for early detection of design problems, helping yield engineers effectively analyze the impact of the lithography process on yield and design process parameters tailored to the lithography process, thereby improving manufacturing yield in wafer production and enhancing the stability of process capabilities.

[0143] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0144] Figure 7 The following is a schematic diagram showing the structure of a device for determining the design yield of an integrated circuit layout provided by an embodiment of the present application. Figure 7 As shown, the device has the function of implementing the above-mentioned design yield determination method, and the function can be implemented by hardware or by hardware executing corresponding software. The device may include: an acquisition unit 701, a correction unit 702, a simulation unit 703, a lithography hotspot detection unit 704, a critical dimension acquisition unit 705, a fitting unit 706, a failure probability determination unit 707, a key layer design yield determination unit 708, and an integrated circuit layout design yield determination unit 709. Among them:

[0145] Acquisition unit 701 is configured to acquire an integrated circuit layout file and a computational lithography model for a lithography process at a corresponding process node. The integrated circuit layout file includes at least one key layer, and the computational lithography model includes at least one key layer model. The key layer model is used to model and simulate the lithography process for the matching key layer.

[0146] The correction unit 702 is configured to perform optical proximity effect correction on any key layer to obtain correction data.

[0147] The simulation unit 703 is used to use various computational lithography simulation models of key layer matching to perform lithography simulation on the corrected data respectively, and obtain various simulation contours formed on the simulation imaging plane. Each computational lithography simulation model is generated based on the process fluctuation simulation of the key layer model of the key layer matching.

[0148] The lithography hotspot detection unit 704 is used to detect the lithography hotspot position from each simulation contour. The lithography hotspot position is the position corresponding to the critical dimension smaller than the minimum preset critical dimension. The critical dimension is the minimum contour spacing of the simulation contour.

[0149] The critical dimension acquisition unit 705 is used to acquire the critical dimension corresponding to any photolithography hotspot position in each simulation profile.

[0150] The fitting unit 706 is used to perform Weibull distribution fitting on all critical dimensions corresponding to the lithography hotspot position to obtain the Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position. The cumulative probability distribution function is used to represent the failure probability of each critical dimension.

[0151] The failure probability determination unit 707 is configured to obtain the failure probability of a minimum preset critical dimension based on the cumulative probability distribution function of the lithography hotspot position.

[0152] The key layer design yield determination unit 708 is configured to obtain the design yield of the key layer after optical proximity effect correction based on the failure probability of the minimum preset critical size corresponding to each lithography hotspot position.

[0153] The integrated circuit layout design yield determination unit 709 is configured to obtain the design yield of the integrated circuit layout file for the photolithography process based on the design yield of each key layer after correction for the optical proximity effect.

[0154] In one implementation, the photolithography hotspot detection unit 704 is specifically configured to:

[0155] For any simulated contour, use the preset tool to detect the contour spacing at each position on the simulated contour.

[0156] A minimum profile spacing is determined from the profile spacings at the respective positions, and the minimum profile spacing is determined as a critical dimension.

[0157] If the critical dimension is smaller than the minimum preset critical dimension, the position corresponding to the critical dimension is determined as the photolithography hotspot position.

[0158] In one implementation, the fitting unit 706 includes:

[0159] The parameter determination module is used to obtain the scale parameter and shape parameter of the Weibull distribution by fitting all the critical dimensions corresponding to the photolithography hotspot positions using the three sigma criterion.

[0160] The function determination module is used to obtain the Weibull probability distribution function and the cumulative probability distribution function of the lithography hotspot position according to the scale parameter and shape parameter of the Weibull distribution.

[0161] In one implementable manner, the function determination module is specifically configured to:

[0162] The Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position are obtained by the following formula:

[0163]

[0164]

[0165] Where f(CD;λ,k) is the Weibull probability distribution function of the lithography hotspot location, f(CD;λ,k) is the cumulative probability distribution function of the lithography hotspot location, CD is the critical dimension, λ is the scale parameter, and k is the shape parameter.

[0166] In one implementation, the key layer design yield determination unit 708 is specifically configured to:

[0167] The design yield of the key layer after optical proximity effect correction is determined by the following formula:

[0168]

[0169] Where Y(layer) is the design yield of the key layer after optical proximity effect correction, i is the index of the lithography hotspot position, is the failure probability of the minimum preset critical dimension corresponding to the i-th lithography hotspot position.

[0170] In one implementation, the integrated circuit layout design yield determination unit 709 is specifically configured to:

[0171] The design yield of the integrated circuit layout file for the photolithography process is determined by the following formula:

[0172]

[0173] Among them, Y(chip) is the design yield of the integrated circuit layout file for the photolithography process, j is the layer number of the key layer, and Y(layer j ) is the design yield of the jth key layer after optical proximity effect correction.

[0174] In one implementation, the at least one key layer includes at least one of an ion implantation layer, a polysilicon layer, a metal layer, and a metal and transistor interconnection layer.

[0175] In one implementation, each computational lithography simulation model is generated by:

[0176] The pupil lens defocus parameters in the key layer model are adjusted according to preset rules to obtain multiple computational lithography simulation models.

[0177] The embodiment of the present application discloses a device for determining the design yield of an integrated circuit layout. The device analyzes the design yield changes caused by fluctuations in the lithography process by calculating a lithography model, and analyzes the failure probability of integrated circuit devices caused by lithography hotspots through lithography hotspot statistical information. This can detect design problems in advance, help yield engineers effectively analyze the impact of the lithography process on the yield, design process parameters for the lithography process, and thus improve the manufacturing yield in wafer production and enhance the stability of process capabilities.

[0178] The present application has been described in detail above with reference to specific embodiments and exemplary examples. However, these descriptions should not be construed as limiting the present application. Those skilled in the art will appreciate that, without departing from the spirit and scope of the present application, various equivalent substitutions, modifications, or improvements may be made to the technical solutions and implementations of the present application, all of which fall within the scope of the present application. The scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for determining the design yield of an integrated circuit layout, characterized in that: include: Obtaining an integrated circuit layout file and a computational lithography model of a lithography process at a corresponding process node; the integrated circuit layout file includes at least one key layer, and the computational lithography model includes at least one key layer model, wherein the key layer model is used to model and simulate the lithography process for the matching key layer; For any key layer, performing optical proximity effect correction on the key layer to obtain corrected data; Performing lithography simulation on the corrected data using respective computational lithography simulation models matched to the key layers to obtain respective simulation profiles formed on a simulation imaging plane, wherein the respective computational lithography simulation models are generated based on a process fluctuation simulation of the key layer model matched to the key layers; Detecting a photolithography hotspot position from each simulation profile, the photolithography hotspot position being a position corresponding to a critical dimension smaller than a minimum preset critical dimension, the critical dimension being a minimum profile spacing of the simulation profile; For any photolithography hotspot position, obtaining the critical dimension corresponding to the photolithography hotspot position in each simulation profile; Performing Weibull distribution fitting on all critical dimensions corresponding to the photolithography hotspot position to obtain a Weibull probability distribution function and a cumulative probability distribution function of the photolithography hotspot position, wherein the cumulative probability distribution function is used to represent the failure probability of each critical dimension; Obtaining a failure probability of a minimum preset critical dimension based on a cumulative probability distribution function of the photolithography hotspot position; Based on the failure probability of the minimum preset critical dimension corresponding to each lithography hotspot position, the design yield of the critical layer after optical proximity effect correction is obtained; Based on the design yield of each key layer after correction of the optical proximity effect, the design yield of the integrated circuit layout file for the photolithography process is obtained.

2. The method according to claim 1, characterized in that The detecting of the photolithography hotspot position from each simulation profile includes: For any simulated contour, using a preset tool to detect the contour spacing of each position on the simulated contour; Determine a minimum profile spacing from the profile spacings at various locations, and determine the minimum profile spacing as a critical dimension; If the critical dimension is smaller than the minimum preset critical dimension, the position corresponding to the critical dimension is determined as a photolithography hotspot position.

3. The method according to claim 1, characterized in that The step of performing Weibull distribution fitting on all critical dimensions corresponding to the photolithography hotspot position to obtain the Weibull probability distribution function and the cumulative probability distribution function of the photolithography hotspot position includes: According to all the critical dimensions corresponding to the photolithography hotspot positions, fitting is performed using the three sigma criterion to obtain the scale parameter and shape parameter of the Weibull distribution; According to the scale parameter and shape parameter of the Weibull distribution, the Weibull probability distribution function and the cumulative probability distribution function of the lithography hotspot position are obtained.

4. The method according to claim 3, characterized in that The step of obtaining the Weibull probability distribution function and the cumulative probability distribution function of the lithography hotspot position according to the scale parameter and the shape parameter of the Weibull distribution includes: The Weibull probability distribution function and cumulative probability distribution function of the lithography hotspot position are obtained by the following formula: Wherein, f(CD;λ,k) is the Weibull probability distribution function of the photolithography hotspot position, f(CD;λ,k) is the cumulative probability distribution function of the photolithography hotspot position, CD is the critical dimension, λ is the scale parameter, and k is the shape parameter.

5. The method according to claim 1, wherein The method of obtaining the design yield of the key layer after optical proximity effect correction based on the failure probability of the minimum preset critical dimension corresponding to each lithography hotspot position includes: The design yield of the key layer after optical proximity effect correction is determined by the following formula: Wherein, Y(layer) is the design yield of the key layer after correction of optical proximity effect, i is the index of the lithography hotspot position, is the failure probability of the minimum preset critical dimension corresponding to the i-th lithography hotspot position.

6. The method according to claim 5, characterized in that The step of obtaining the design yield of the integrated circuit layout file for the photolithography process based on the design yield of each key layer after correction for the optical proximity effect comprises: The design yield of the integrated circuit layout file for the photolithography process is determined by the following formula: Wherein, Y(chip) is the design yield of the integrated circuit layout file for the photolithography process, j is the layer number of the key layer, and Y(layer j ) is the design yield of the jth key layer after optical proximity effect correction.

7. The method according to claim 1, characterized in that The at least one key layer includes at least one of an ion implantation layer, a polysilicon layer, a metal layer, and a metal and transistor interconnection layer.

8. The method according to claim 1, characterized in that Each computational lithography simulation model is generated by: The pupil lens defocus parameters in the key layer model are adjusted according to preset rules to obtain multiple computational lithography simulation models.

9. A device for determining the design yield of an integrated circuit layout, characterized in that: include: an acquisition unit, configured to acquire an integrated circuit layout file and a computational lithography model of a lithography process at a corresponding process node; the integrated circuit layout file includes at least one key layer, the computational lithography model includes at least one key layer model, and the key layer model is used to model and simulate the lithography process for a matching key layer; a correction unit, configured to perform optical proximity effect correction on any key layer to obtain correction data; a simulation unit configured to perform lithography simulation on the corrected data using respective computational lithography simulation models matched to the key layer, to obtain respective simulation profiles formed on a simulation imaging plane, wherein the respective computational lithography simulation models are generated based on a process fluctuation simulation of the key layer model matched to the key layer; A lithography hotspot detection unit is used to detect a lithography hotspot position from each simulation profile, wherein the lithography hotspot position is a position corresponding to a critical dimension smaller than a minimum preset critical dimension, and the critical dimension is a minimum profile spacing of the simulation profile; A critical dimension acquisition unit, configured to acquire, for any photolithography hotspot position, a critical dimension corresponding to the photolithography hotspot position in each simulation profile; a fitting unit, configured to perform Weibull distribution fitting on all critical dimensions corresponding to the lithography hotspot position, and obtain a Weibull probability distribution function and a cumulative probability distribution function of the lithography hotspot position, wherein the cumulative probability distribution function is used to represent the failure probability of each critical dimension; A failure probability determination unit, configured to obtain a failure probability of a minimum preset critical dimension based on a cumulative probability distribution function of the photolithography hotspot position; a key layer design yield determination unit, configured to obtain a design yield of the key layer after optical proximity effect correction based on a failure probability of a minimum preset critical dimension corresponding to each lithography hotspot position; The integrated circuit layout design yield determination unit is used to obtain the design yield of the integrated circuit layout file for the photolithography process based on the design yield of each key layer after optical proximity effect correction.

10. The device according to claim 9, characterized in that The photolithography hotspot detection unit is specifically used for: For any simulated contour, using a preset tool to detect the contour spacing of each position on the simulated contour; Determine a minimum profile spacing from the profile spacings at various locations, and determine the minimum profile spacing as a critical dimension; If the critical dimension is smaller than the minimum preset critical dimension, the position corresponding to the critical dimension is determined as a photolithography hotspot position.

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