Electronic device, nonvolatile memory, storage unit and control method

Abstract

The present invention discloses an electronic device, a non-volatile memory, a storage unit and a control method, wherein the storage unit includes a non-volatile memory, a first inverter, a second inverter, a first switching element and a second switching element; the first inverter includes a first storage node, and the second inverter includes a second storage node; the first switching element is connected between the first storage node and a bit line, and a control end is connected to a first word line; the second switching element is connected between a first electrode of the non-volatile memory and an inverted bit line, and a control end is connected to the second word line; the input end of the first inverter is connected to a first electrode of the non-volatile memory, and a power supply end of the first inverter is connected to a first power supply; the input end of the second inverter is connected to the first storage node, and the second storage node is connected to a second electrode of the non-volatile memory, and a power supply end of the second inverter is connected to a second power supply; the storage unit can reduce the size of the memory and improve the storage density.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuits, and in particular to an electronic device, a non-volatile memory, a storage unit, and a control method. Background Art

[0002] Static Random-Access Memory (SRAM) technology is currently the mainstream volatile memory and has broad application prospects. However, it faces issues such as volatility and high leakage current power consumption. Therefore, non-volatile SRAM has become a research hotspot. Currently, the storage cells of common non-volatile SRAMs are 7T1R or 8T2R structures, where T represents transistors and R represents non-volatile memory such as resistive random access memory (RRAM). However, the 7T1R or 8T2R structures use a large number of transistors or non-volatile memory, resulting in a larger memory size and affecting storage density. Summary of the Invention

[0003] The present invention provides an electronic device, a non-volatile memory, a storage unit and a control method, which can further reduce the size of the non-volatile random access static memory and improve the storage density.

[0004] In a first aspect, a nonvolatile memory cell is provided according to an embodiment of the present invention. The nonvolatile memory cell includes a nonvolatile memory, a first inverter, a second inverter, a first switching element, and a second switching element. The first inverter includes a first storage node, and the second inverter includes a second storage node.

[0005] The first switch element is connected between the first storage node and the bit line, and the control terminal is connected to the first word line;

[0006] The second switch element is connected between the first electrode of the non-volatile memory and the inverting bit line, and the control terminal is connected to the second word line;

[0007] An input terminal of the first inverter is connected to a first electrode of the non-volatile memory, and a power supply terminal of the first inverter is connected to a first power supply;

[0008] An input terminal of the second inverter is connected to the first storage node, the second storage node is connected to a second electrode of the nonvolatile memory, and a power supply terminal of the second inverter is connected to a second power supply.

[0009] Optionally, the non-volatile memory is a resistive random access memory.

[0010] Optionally, the first switching element is a first gate transistor, a drain of the first gate transistor is connected to the bit line, a source is connected to the output end of the first inverter, and a gate is connected to the first word line.

[0011] Optionally, the second switching element is a second gate transistor, a drain of the second gate transistor is connected to the inverting bit line, a source is connected to the first electrode of the resistive memory, and a gate is connected to the second word line.

[0012] Optionally, the input end of the first inverter is connected between the first electrode of the resistive memory and the source of the second gate transistor.

[0013] Optionally, the first inverter includes a first pull-up transistor and a first pull-down transistor;

[0014] The source of the first pull-up transistor is connected to the first power supply;

[0015] The drain of the first pull-down transistor is grounded, and the gate is connected to the gate of the first pull-up transistor;

[0016] A drain of the first pull-up transistor and a source of the first pull-down transistor are coupled to the first storage node.

[0017] Optionally, the second inverter includes a second pull-up transistor and a second pull-down transistor;

[0018] The source of the second pull-up transistor is connected to the second power supply;

[0019] The drain of the second pull-down transistor is grounded, and the gate is connected to the gate of the second pull-up transistor;

[0020] A drain of the second pull-up transistor and a source of the second pull-down transistor are coupled to the second storage node.

[0021] In a second aspect, an embodiment of the present invention provides a control method for controlling any storage unit described in the first aspect, the method comprising:

[0022] During a read operation or a write operation, if the first storage node is at a high potential, the first word line and the bit line are controlled to be at a high potential, the second word line and the inverted bit line are controlled to be at a low potential, and the first power supply and the second power supply are at a high potential;

[0023] During a write operation, if the first storage node is at a low potential, the first word line is controlled to be at a high potential, the bit line, the inverted bit line and the second word line are at a low potential, and the first power supply and the second power supply are at a high potential;

[0024] During a read operation, if the first storage node is at a low potential, the first word line and the bit line are controlled to be at a high potential, the inverted bit line and the second word line are at a low potential, and the first power supply and the second power supply are at a high potential.

[0025] In a third aspect, a non-volatile memory is provided according to an embodiment of the present invention, comprising any storage unit provided in the first aspect.

[0026] In a fourth aspect, an electronic device is provided according to an embodiment of the present invention, comprising the non-volatile memory provided in the third aspect.

[0027] Through one or more technical solutions of the present invention, the present invention has the following beneficial effects or advantages:

[0028] The present invention provides a nonvolatile memory cell, comprising a nonvolatile memory, a first inverter, a second inverter, a first switching element, and a second switching element. Since two transistors are used in the inverter, the first switching element and the second switching element are combined to form a nonvolatile memory cell with a 6T1R structure. Compared with existing 7T1R memory cells or 8T2R memory cells, this cell can reduce the number of transistors and / or nonvolatile memory used, thereby reducing the size of the nonvolatile SRAM memory and improving the storage density. Furthermore, the control terminals of the first switching element and the second switching element are connected to a first word line and a second word line, respectively. The first inverter and the second inverter are connected to a first power supply and a second power supply, respectively. The input terminal of the first inverter is connected to a first electrode of the nonvolatile memory, the input terminal of the second inverter is connected to a first storage node, and the second storage node is connected to a second electrode of the nonvolatile memory. In this way, by controlling the potential of the first power supply or the second power supply and the first word line or the second word line, data can still be successfully recovered even when the ratio (R-Ratio) of the high-resistance resistance to the low-resistance resistance of the nonvolatile memory is small, thereby improving data access quality.

[0029] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be construed as limiting the present invention. The same reference numerals are used throughout the accompanying drawings to denote the same components.

[0031] In the attached figure:

[0032] Figure 1 A schematic structural diagram of a 7T1R storage unit is shown;

[0033] Figure 2 shows the waveforms of the 7T1R memory cell in store and restore modes;

[0034] Figure 3 A schematic diagram showing the data recovery success rate of a 7T1R storage unit at different R-Ratios;

[0035] Figure 4 shows a structural schematic diagram of an 8T2R memory cell;

[0036] Figure 5 shows the waveforms of the 8T2R memory cell in store and restore modes;

[0037] Figure 6 FIG. 4 shows a schematic structural diagram of a nonvolatile memory unit according to an embodiment of the present invention.

[0038] Figure 7 shows a waveform diagram of a 6T1R memory in read and write modes according to an embodiment of the present invention;

[0039] Figure 8 shows a waveform diagram of a 6T1R memory in a store-set mode according to an embodiment of the present invention;

[0040] Figure 9 shows a waveform diagram of a 6T1R memory in a store-reset mode according to an embodiment of the present invention;

[0041] Figure 10 shows a waveform diagram of a 6T1R memory in a restore mode according to an embodiment of the present invention;

[0042] Figure 11 A schematic diagram of a 6T1R storage array according to an embodiment of the present invention is shown;

[0043] Figure 12 A schematic diagram of an electronic device according to an embodiment of the present invention is shown;

[0044] Description of some reference numerals:

[0045] 1. First inverter; 11. First pull-up transistor; 12. First pull-down transistor; 2. Second inverter; 21. Second pull-up transistor; 22. Second pull-down transistor; 3. Nonvolatile memory; 4. First switching element; 5. Second switching element; 100. Nonvolatile memory cell;

[0046] Q, first storage node; QB, second storage node; BL, bit line; BLB, bit bar; WL1, first word line; WL2, second word line; VDD1: first power supply; VDD2: second power supply. DETAILED DESCRIPTION

[0047] In order to make those skilled in the art to which this application belongs understand this application more clearly, the technical scheme of this application is described in detail below in conjunction with the accompanying drawings by way of specific embodiments. Throughout this specification, unless otherwise specified, the terms used herein should be understood to have the same meaning as commonly used in the art. Therefore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which this invention belongs. In the event of a conflict, this specification takes precedence. Unless otherwise specified, the various devices used in the present invention, etc., can be purchased commercially or can be prepared by existing methods.

[0048] The storage cells of current non-volatile random access static memories often adopt a 7T1R structure or an 8T2R structure.

[0049] An optional 7T1R non-volatile random access static memory storage unit structure is as follows Figure 1 As shown, it is a three-dimensional stack of 1R1T at the data node of SRAM, and the state of R is controlled by transistor T. Figure 2 The waveform diagrams of 7T1R during storage (store) and recovery (restore) are provided: during SET, RSL (reference source line) is connected to a high potential, RSWL (reference word line) is connected to a high potential, CVDDQ is connected to V_SET, and CVDDQB is connected to V_SET; during RESET, RSL is connected to a low potential, RSWL is connected to a high potential, CVDDQ is connected to V_RESET, and CVDDQB is connected to V_RESET; during RESTORE, RSL is connected to a low potential, CVDDQ is connected to a high potential first, CVDDQB is connected to a high potential with a delay, and then RSWL is turned on and off after nanoseconds.

[0050] 7T1R is a single-sided storage device that only requires one resistive random access memory (RRAM) to store one bit. However, it has a low data recovery success rate, which affects the quality of the finished product. Figure 3 It can be seen that when the R-Ratio of the current 7T1R storage array is small (such as 1.5), the data recovery (Restore) success rate is only about 60%, which cannot meet the demand.

[0051] An optional 8T2R non-volatile random access static memory storage unit structure is as follows Figure 4 As shown, it is a three-dimensional stack of 1R1T at the data node of SRAM, and the state of R (RRAM) is controlled by transistor T. Figure 5The waveform diagrams of 8T2R during storage (store) and recovery (restore) are provided: during SET, CVDD is connected to V_SET, RSWL is connected to a high potential, and BL / BLB are both connected to V_SET; during RESET, CVDD is connected to V_RESET, RSWL is connected to a high potential, and BL / BLB are both connected to a low potential; during RESTORE, RSWL is first connected to a high potential, then CVDD is connected to a high potential, and RSWL is set to a low potential after CVDD stabilizes for a period of time, and BL / BLB are both connected to a low potential.

[0052] 8T2R adopts a differential structure for storage, using two resistive random access memories (RRAM) but only storing one bit. This increases the number of RRAMs without adding any extra storage bits.

[0053] In general, both 8T2R and 7T1R add 1T1R to SRAM to create an SRAM-based non-volatile memory structure. Both require additional transistors to control the resistive memory. Therefore, how to further reduce the size of non-volatile random access memory without compromising data access quality has become a pressing issue.

[0054] First, in order to further reduce the size of non-volatile random access static memory, please refer to Figure 6 , provides a non-volatile memory cell, including a non-volatile memory 3, a first inverter 1, a second inverter 2, a first switching element 4 and a second switching element 5; the first inverter 1 includes a first storage node Q, and the second inverter 2 includes a second storage node QB; the first switching element 4 is connected between the first storage node Q and the bit line BL, and the control end is connected to the first word line WL1; the second switching element 5 is connected between the first electrode of the non-volatile memory 3 and the inverted bit line BLB, and the control end is connected to the second word line WL2; the input end of the first inverter 1 is connected to the first electrode of the non-volatile memory 3, and the power supply end of the first inverter 1 is connected to the first power supply VDD1; the input end of the second inverter 2 is connected to the first storage node Q, the second storage node QB is connected to the second electrode of the non-volatile memory 3, and the power supply end of the second inverter 2 is connected to the second power supply VDD2.

[0055] The nonvolatile memory cell provided in this embodiment has a 6T1R structure. Compared to existing 7T1R or 8T2R memory cells, this structure can reduce the number of transistors and / or nonvolatile memory 3 used, thereby reducing the size of the nonvolatile SRAM memory and improving storage density. Furthermore, the control terminals of the first switching element 4 and the second switching element 5 are connected to the first word line WL1 and the second word line WL2, respectively. The first inverter 1 and the second inverter 2 are connected to the first power supply VDD1 and the second power supply VDD2, respectively. The input terminal of the first inverter 1 is connected to the first electrode of the nonvolatile memory 3, the input terminal of the second inverter 2 is connected to the first storage node Q, and the second storage node QB is connected to the second electrode of the nonvolatile memory 3. In this way, by controlling the potential of the first power supply VDD1 or the second power supply VDD2 and the potential of the first word line WL1 or the second word line WL2, data can still be successfully recovered even when the ratio R-Ratio of the high-resistance resistance to the low-resistance resistance of the nonvolatile memory 3 is small, thereby improving data access quality.

[0056] Alternatively, the non-volatile memory 3 may utilize ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), phase change memory (PCM), and resistive random access memory (RRAM). This embodiment utilizes resistive random access memory (RRAM) to form a 6T1R memory cell. The RRAM comprises an upper electrode TE and a lower electrode BE, wherein the first electrode is one of the upper electrode TE and the lower electrode BE, and the second electrode is the other of the upper electrode TE and the lower electrode BE. Unless otherwise specified, the non-volatile memory 3 in this embodiment is an RRAM, in which case the first electrode is the lower electrode BE and the second electrode is the upper electrode TE.

[0057] The first switching element 4 and the second switching element 5 function as switches for controlling the path of memory read / write or access signals, and transistors can be used to implement the corresponding functions. In this embodiment, a gate transistor is selected. The advantage of the gate transistor is that when integrated with the memory cell, it does not affect the original memory cell performance, and its switching speed is much lower than the erase / write time of the memory cell.

[0058] The first switch element 4 is a first gate transistor, the second switch element 5 is a second gate transistor, and the non-volatile memory 3 is a resistive switching memory. Figure 6 The drain of the first selection tube is connected to the bit line BL, the source is connected to the output end of the first inverter 1, and the gate is connected to the first word line WL1; the drain of the second selection tube is connected to the inverted bit line BLB, the source is connected to the first electrode of the resistive memory, and the gate is connected to the second word line WL2; the input end of the first inverter 1 is connected between the first electrode of the resistive memory and the source of the second selection tube.

[0059] The inverter can reverse the phase of the input signal by 180 degrees and can be composed of two field effect transistors. Figure 6 As shown, the first inverter 1 includes a first pull-up transistor 11 and a first pull-down transistor 12; wherein: the source of the first pull-up transistor 11 is connected to the first power supply VDD1; the drain of the first pull-down transistor 12 is grounded, and the gate is connected to the gate of the first pull-up transistor 11; the drain of the first pull-up transistor 11 and the source of the first pull-down transistor 12 are coupled to the first storage node Q. The second inverter 2 includes a second pull-up transistor 21 and a second pull-down transistor 22; wherein the source of the second pull-up transistor 21 is connected to the second power supply VDD2; the drain of the second pull-down transistor 22 is grounded, and the gate is connected to the gate of the second pull-up transistor 21; the drain of the second pull-up transistor 21 and the source of the second pull-down transistor 22 are coupled to the second storage node QB.

[0060] Optionally, the first pull-up transistor 11 and the second pull-up transistor 21 in the inverter can use p-MOSFET (P-type field effect transistor) as load transistors, and the first pull-down transistor 12 and the second pull-down transistor 22 can use n-MOSFET (N-type field effect transistor) as drive transistors, and the n-MOSFET and p-MOSFET form a complementary push-pull structure.

[0061] The aforementioned nonvolatile memory cell is based on a two-inverter structure. The power supply terminals of the two inverters are independently connected to a first power supply VDD1 and a second power supply VDD2. The gates of the first and second gate transistors are independently connected to a first and second word lines WL1 and WL2, respectively. The output terminal of the second inverter 2 (i.e., the second storage node QB) is connected to the upper electrode (or lower electrode) of the RRAM, and the lower electrode (or upper electrode) of the RRAM is connected to the source of the second gate transistor and the input terminal of the first inverter 1. This allows the RRAM value to be restored even when the ratio (R-Ratio) between the high-resistance and low-resistance resistances of the RRAM is small, by adjusting the potential of the second power supply VDD2 and the second word line WL2, thereby improving the success rate of data recovery.

[0062] The 6T1R storage unit provided in this embodiment has the following advantages:

[0063] 1) Compared with the existing 7T1R non-volatile static random access memory (SRAM), it does not require the use of redundant transistors, while reducing the size of the memory cell and improving the data recovery success rate at low R-Ratio;

[0064] 2) Compared with the existing 8T2R non-volatile random access static memory, it does not require the use of redundant transistors and resistive memory, thus reducing the size of the memory cell and increasing the storage density of the memory.

[0065] In a second aspect, another optional embodiment provides a control method for the 6T1R storage unit in the embodiment of the first aspect, which is specifically as follows:

[0066] During a read or write operation, if the first storage node Q is at a high potential, the first word line WL1 and the bit line BL are controlled to be at a high potential, the second word line WL2 and the bar bit line BLB are at a low potential, and the first power supply VDD1 and the second power supply VDD2 are at a high potential;

[0067] During a write operation, if the first storage node Q is at a low potential, the first word line WL1 is controlled to be at a high potential, the bit line BL, the bar bit line BLB and the second word line WL2 are at a low potential, and the first power supply VDD1 and the second power supply VDD2 are at a high potential;

[0068] During a read operation, if the first storage node Q is at a low potential, the first word line WL1 and the bit line BL are controlled to be at a high potential, the bar bit line BLB and the second word line WL2 are at a low potential, and the first power supply VDD1 and the second power supply VDD2 are at a high potential.

[0069] In order to intuitively illustrate the above solution, the following is described with reference to the accompanying drawings:

[0070] See also Figure 7 During a write operation, the first storage node Q = 0 and the second storage node QB = 1 at the initial moment. Assuming that the first storage node Q = 1 and the second storage node QB = 0 are written at this time, the first word line WL1 is set to 1 and the second word line WL2 is set to 0. The first power supply VDD1 and the second power supply VDD2 are both set to 1, but the potential of the first power supply VDD1 is slightly higher than the second potential of the second power supply VDD2. The bit line BL is set to 1 and the bit bar BLB is set to 0. When the first storage node Q = 0 and the second storage node QB = 1 are written, the bit line BL is set to 0, and the other bits remain unchanged.

[0071] See also Figure 7 During a read operation, the first storage node Q = 1 and the second storage node QB = 0 at the initial moment. When reading the value of the first storage node Q, the first word line WL1 is set to 1, the second word line WL2 is set to 0, the first power supply VDD1 and the second power supply VDD2 are both set to 1, the bit line BL is set to 1, and the bit line bar BLB is set to 0. During the read process, the voltage at the bit line BL does not change relative to the reference voltage Vref. If the first storage node Q = 0 and the second storage node QB = 1 at the initial moment, the voltage at the bit line BL does change relative to the reference voltage Vref during the read process.

[0072] When performing a Store operation, there are two states: SET and RESET. In the SET state, please refer to Figure 8If the first storage node Q=0 and the second storage node QB=1, the second word line WL2 is set to 1, and the bit line BL and the bar bit line BLB are both set to 0, so that the resistive random access memory RRAM changes from a high resistance value to a low resistance value;

[0073] In the RESET state, please refer to Figure 9 If Q=1, QB=0, the first word line WL1 is set to 1 in advance, the bit line BL is set to 1, so that the first storage node Q is always 1, and then the second word line WL2 is set to 1, and the inverted bit line BLB is set to a higher potential, so that the RRAM changes from a low resistance value to a high resistance value;

[0074] In the Power-Off state, all voltages are set to 0.

[0075] When performing a restore operation, see Figure 10 , the bit line BL and the inverted bit line BLB are both set to 0, the first word line WL1 is set to 0, and the second word line WL2 is set to the set value V_RWL2 before the Restore operation. The second power supply VDD2 is first set to the set value V_RUP2. At this time, the potential of the second storage node QB rises; secondly, the first power supply VDD1 is set to the set value V_RUP1. If the resistive random access memory RRAM is in the low resistance state (LRS), the potential of the second storage node QB reaches V_RUP1; if the resistive random access memory RRAM is in the high resistance state (HRS), the potential of the second storage node QB drops to 0, and the potential of the first storage node Q rises to V_RUP1. Then the first power supply VDD1 and the second power supply VDD2 are both raised to 1, the second word line WL2 is set to 0, and the potentials of the first storage node Q and the second storage node QB reach a stable state, and finally the read / write operation is performed.

[0076] The above method adjusts the potential of the second power source VDD2 and the second word line WL2 to restore the value of the resistive random access memory RRAM even when the R-Ratio is small.

[0077] In a third aspect, based on the same inventive concept, a non-volatile memory is provided, comprising the storage unit provided in the first aspect. For a storage array of a non-volatile memory, please refer to Figure 11 Each storage unit in the storage array uses Figure 6 A non-volatile memory cell 100 is shown.

[0078] In a fourth aspect, based on the same inventive concept, an electronic device is provided, which may be a mobile phone, a computer, a digital broadcast terminal, a message sending and receiving device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0079] like Figure 12As shown, the electronic device 1200 may include one or more of the following components: a processing component 1202, a memory 1204, a power supply component 1206, a multimedia component 1208, an audio component 1210, an input / display (I / O) interface 1212, a sensor component 1214, and a communication component 1216. The memory 1204 may be the non-volatile memory provided in the third aspect.

[0080] The processing component 1202 generally controls the overall operation of the electronic device 1200, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 1202 may include one or more processors 1220 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 1202 may include one or more modules to facilitate interaction between the processing component 1202 and other components. For example, the processing component 1202 may include a multimedia module to facilitate interaction between the multimedia component 1208 and the processing component 1202.

[0081] The memory 1204 is configured to store various types of data to support operations on the device 1200. Examples of such data include instructions for any application or method operating on the electronic device 1200, contact data, phone book data, messages, pictures, videos, etc. The memory 1204 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0082] The power supply component 1206 provides power to the various components of the electronic device 1200. The power supply component 1206 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1200.

[0083] The multimedia component 1208 includes a screen that provides a presentation interface between the electronic device 1200 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1208 includes a front camera and / or a rear camera. When the device 1200 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0084] The audio component 1210 is configured to present and / or input audio signals. For example, the audio component 1210 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 1200 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 1204 or transmitted via the communication component 1216. In some embodiments, the audio component 1210 further includes a speaker for presenting audio signals.

[0085] I / O interface 1212 provides an interface between processing component 1202 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0086] The sensor assembly 1214 includes one or more sensors for providing various aspects of the status assessment of the electronic device 1200. For example, the sensor assembly 1214 can detect the open / closed state of the device 1200, the relative positioning of components, such as the display and keypad of the electronic device 1200. The sensor assembly 1214 can also detect changes in the position of the electronic device 1200 or a component of the electronic device 1200, the presence or absence of user contact with the electronic device 1200, the orientation or acceleration / deceleration of the electronic device 1200, and changes in the temperature of the electronic device 1200. The sensor assembly 1214 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 1214 can also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1214 can also include an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0087] The communication component 1216 is configured to facilitate wired or wireless communication between the electronic device 1200 and other devices. The electronic device 1200 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 1216 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1216 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0088] Through one or more embodiments of the present invention, the present invention has the following beneficial effects or advantages:

[0089] The present invention provides an electronic device, a non-volatile memory, a storage unit and a control method, wherein the non-volatile memory unit includes a non-volatile memory, a first inverter, a second inverter, a first switching element and a second switching element. Since two transistors are used in the inverter, the first switching element and the second switching element are combined to form a 6T1R structure non-volatile memory unit. Compared with the current 7T1R storage unit or 8T2R storage unit, the number of transistors and / or non-volatile memory used can be reduced, which is conducive to reducing the size of the non-volatile SRAM memory and improving the storage density. At the same time, through the first switch The control ends of the element and the second switching element are connected to the first word line and the second word line respectively, the first inverter and the second inverter are connected to the first power supply and the second power supply respectively, the input end of the first inverter is connected to the first electrode of the non-volatile memory, the input end of the second inverter is connected to the first storage node, and the second storage node is connected to the second electrode of the non-volatile memory. In this way, by controlling the potential of the first power supply or the second power supply and the first word line or the second word line, data can still be successfully recovered when the ratio R-Ratio of the high-resistance resistance to the low-resistance resistance of the non-volatile memory is small, thereby improving data access quality.

[0090] The term "and / or" that appears in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship; the word "comprising" does not exclude the existence of elements or steps that are not listed in the claims. The word "one" or "an" placed before an element does not exclude the existence of multiple such elements. The present invention can be implemented with the aid of hardware comprising several different elements and with the aid of appropriately programmed computers. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

[0091] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0092] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A non-volatile memory cell, characterized in that: The storage unit includes a nonvolatile memory, a first inverter, a second inverter, a first switching element, and a second switching element; the first inverter includes a first storage node, and the second inverter includes a second storage node; The first switch element is connected between the first storage node and the bit line, and the control terminal is connected to the first word line; The second switch element is connected between the first electrode of the non-volatile memory and the inverting bit line, and the control terminal is connected to the second word line; An input terminal of the first inverter is connected to a first electrode of the non-volatile memory, and a power supply terminal of the first inverter is connected to a first power supply; An input terminal of the second inverter is connected to the first storage node, the second storage node is connected to a second electrode of the nonvolatile memory, and a power supply terminal of the second inverter is connected to a second power supply.

2. The storage unit according to claim 1, wherein The non-volatile memory is a resistive random access memory.

3. The storage unit according to claim 2, wherein The first switch element is a first gate transistor, a drain of the first gate transistor is connected to the bit line, a source of the first gate transistor is connected to the output end of the first inverter, and a gate of the first gate transistor is connected to the first word line.

4. The storage unit according to claim 2, wherein The second switch element is a second gate transistor, a drain of the second gate transistor is connected to the inverting bit line, a source of the second gate transistor is connected to the first electrode of the resistive memory, and a gate of the second gate transistor is connected to the second word line.

5. The storage unit according to claim 4, wherein The input end of the first inverter is connected between the first electrode of the resistive memory and the source of the second gate transistor.

6. The storage unit according to claim 2, wherein: The first inverter includes a first pull-up transistor and a first pull-down transistor; The source of the first pull-up transistor is connected to the first power supply; The drain of the first pull-down transistor is grounded, and the gate is connected to the gate of the first pull-up transistor; A drain of the first pull-up transistor and a source of the first pull-down transistor are coupled to the first storage node.

7. The storage unit according to claim 2, wherein: The second inverter includes a second pull-up transistor and a second pull-down transistor; The source of the second pull-up transistor is connected to the second power supply; The drain of the second pull-down transistor is grounded, and the gate is connected to the gate of the second pull-up transistor; A drain of the second pull-up transistor and a source of the second pull-down transistor are coupled to the second storage node.

8. A control method, characterized in that: The method is used to control the storage unit according to any one of claims 1 to 7, and the method includes: During a read operation or a write operation, if the first storage node is at a high potential, the first word line and the bit line are controlled to be at a high potential, the second word line and the inverted bit line are controlled to be at a low potential, and the first power supply and the second power supply are at a high potential; During a write operation, if the first storage node is at a low potential, the first word line is controlled to be at a high potential, the bit line, the inverted bit line and the second word line are at a low potential, and the first power supply and the second power supply are at a high potential; During a read operation, if the first storage node is at a low potential, the first word line and the bit line are controlled to be at a high potential, the inverted bit line and the second word line are at a low potential, and the first power supply and the second power supply are at a high potential.

9. A non-volatile memory, characterized in that: The invention comprises the storage unit described in any one of claims 1 to 7.

10. An electronic device, characterized in that: Comprising the non-volatile memory as claimed in claim 9.

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