Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: forming a protection layer on top of a substrate in an isolation region, on sidewalls of a protrusion closest to the isolation region, and on top of an etching stop layer; forming a sacrificial layer in the isolation region on sidewalls of the protection layer; removing the protection layer and the sacrificial layer above the top of the etching stop layer; forming a first isolation layer on top of the protection layer in the isolation region and in a first recess in a device cell region, the top of the first isolation layer being flush with the top of the etching stop layer; removing the sacrificial layer to form an opening in the isolation region surrounded by sidewalls of the first isolation layer, the top of the protection layer on the substrate, and sidewalls of the protection layer; forming a conductive layer in the opening, the top of the conductive layer being lower than the top of the bottom fin. The pattern density in the device cell region is increased, the formation area of the semiconductor structure is reduced, and the probability of the fin in the device cell region being damaged during the formation of the conductive layer is also reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance towards smaller process nodes driven by Moore's Law, resulting in integrated circuits that are smaller in size, higher in circuit precision, and higher in circuit complexity.

[0003] Modern integrated circuits include transistors, capacitors, and other devices formed on a semiconductor substrate. On the substrate, these devices are initially isolated from one another and then interconnected by interconnect structures to form functional circuits. Typical interconnect structures include lateral interconnect structures (e.g., metal interconnect lines) and vertical interconnect structures (e.g., via interconnect structures and contacts).

[0004] A buried power rail (BPR) structure is an interconnect structure disposed in a substrate, which is formed in a front end of line (FEOL) process and used to supply power to an integrated circuit. The BPR can be used as a Vdd power line or a Vss power line. SUMMARY

[0005] Embodiments of the present application solve the problem of providing a semiconductor structure and a forming method thereof, which is beneficial to improve the performance of the semiconductor structure.

[0006] To solve the above problem, an embodiment of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising an isolation region and a device unit region, the device unit region being located between adjacent isolation regions; a bottom fin located in the device unit region and protruding from a top of the substrate; a channel structure located above a top of the bottom fin; a protective layer located on a top of the substrate in the isolation region and a sidewall of the bottom fin closest to the isolation region, the protective layer comprising a first sub-protective layer located on the top of the substrate and a second sub-protective layer located on the sidewall of the bottom fin; a conductive layer protruding from a top of the first sub-protective layer and covering a sidewall of the second sub-protective layer away from the bottom fin, a top of the conductive layer being lower than a top of the second sub-protective layer; a first isolation layer located on the substrate between adjacent bottom fins and on a top of the first sub-protective layer exposed by the conductive layer, a top of the first isolation layer being flush with the top of the second sub-protective layer; and a second isolation layer located on the top of the conductive layer and covering a sidewall of the second sub-protective layer and the first isolation layer exposed by the conductive layer.

[0007] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising an isolation region and a device unit region, the device unit region being located between adjacent isolation regions, and a protruding portion protruding from the substrate being formed in the device unit region, the protruding portion comprising a bottom fin portion protruding from the substrate and a channel protruding portion located on top of the bottom fin portion, the adjacent protruding portion and the top surface of the substrate surrounding a first groove, the top of the protruding portion being formed with a channel stack of a partial height close to the substrate as the bottom fin portion, and a channel structure of a remaining height, the adjacent channel stack and the top surface of the substrate surrounding the first groove, and the top of the channel stack being formed with an etching stop layer; forming a protective layer on the top of the substrate in the isolation region, the sidewall of the protruding portion closest to the isolation region, and the top of the etching stop layer, the protective layer also sealing the top of the first groove; forming a sacrificial layer on the sidewall of the protective layer in the isolation region; after the formation of the sacrificial layer, removing the protective layer and the sacrificial layer higher than the top of the etching stop layer; after the removal of the protective layer and the sacrificial layer higher than the top of the etching stop layer, forming a first isolation layer on the top of the protective layer in the isolation region and in the first groove of the device unit region, the top of the first isolation layer being flush with the top of the etching stop layer; removing the sacrificial layer to form an opening surrounded by the sidewall of the first isolation layer, the top of the protective layer on the substrate, and the sidewall of the protective layer in the isolation region; forming a conductive layer in the opening, the top of the conductive layer being lower than the top of the bottom fin portion; after the formation of the conductive layer, filling a second isolation layer in the remaining space of the opening; removing the first isolation layer, the second isolation layer, and the protective layer higher than the top of the bottom fin portion to expose the channel protruding portion.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] The embodiment of the present application provides a forming method of a semiconductor structure, a protective layer is formed on the top of the substrate in the isolation region, the sidewall of the protruding portion closest to the isolation region, and the top of the etching stop layer, the protective layer also sealing the top of the first groove, so that the protective layer completes the sealing of the substrate exposed by the device unit region, then a sacrificial layer is formed on the sidewall of the protective layer in the isolation region, the formation position of the conductive layer is defined through the sacrificial layer, and after the removal of the sacrificial layer, the conductive layer is formed in the opening, compared with the prior art in which the conductive layer is formed between the adjacent protruding portions, the embodiment of the present application only needs to form the conductive layer on both sides of the plurality of protruding portions, so that the pattern density in the device unit region is increased, the formation area of the semiconductor structure is reduced, and the probability of damage of the protruding portion in the device unit region in the process of forming the conductive layer is also reduced, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures 1 to 5 It is a structure schematic diagram corresponding to each step in a forming method of a semiconductor structure.

[0011] Figure 6 is a structural schematic diagram of an embodiment of a semiconductor structure of the present application;

[0012] Figures 7 to 22 is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present application. DETAILED DESCRIPTION

[0013] The performance of a semiconductor structure needs to be improved. The reasons why the performance of a semiconductor structure needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0014] Figures 1 to 5 is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] REFERENCE Figure 1 A substrate 10 is provided, which includes an isolation region 10A and a device unit region 10B, the device unit region 10B including a sub-device region 11B and a partition region 11A, and a fin 11 is formed in the device unit region 10B and protrudes from the substrate 10, and a top portion of the fin 11 is formed with a fin mask layer 12.

[0016] REFERENCE Figure 2 A dielectric layer 13 is formed on the substrate 10 exposed by the fin 11, and a top portion of the dielectric layer 13 is flush with a top portion of the fin mask layer 12.

[0017] REFERENCE Figure 3 The dielectric layer 13 in the isolation region 10A and the partition region 11A is removed, and a first recess 20 is formed in the isolation region 10A and the partition region 11A to expose a top portion of the substrate 10.

[0018] REFERENCE Figure 4 A protective layer 16 is formed on sidewalls of the first recess 20.

[0019] With continued reference to Figure 4 After the protective layer 16 is formed, a portion of the substrate 10 is removed in the isolation region 10A and the partition region 11A to form a second recess 30 surrounded by sidewalls and a bottom of the remaining substrate 10.

[0020] REFERENCE Figure 5 After the second recess 30 is formed, the protective layer 16 is removed; after the protective layer 16 is removed, an insulating layer 60 is formed on sidewalls and a bottom of the second recess 30 and on sidewalls of the first recess 20; and after the insulating layer 60 is formed, a conductive layer 17 is formed in a remaining space of the second recess 30 and in a portion of a space of the first recess 20.

[0021] It is found that in the process of forming the conductive layer 17, the material of the isolation region 10A and the partition region 11A in which the conductive layer 17 is formed is etched back, the etching process used increases the probability of damage to the fin 11 in the device unit region 10B, and in the lateral direction perpendicular to the extension direction of the fin 11, the pattern density in the device unit region 10B decreases due to the excessive area occupied by the conductive layer 17 under the condition that the lateral dimension of the substrate 10 is constant, and the above two aspects result in the performance of the semiconductor structure being reduced.

[0022] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps: providing a substrate, the substrate comprising an isolation region and a device unit region, the device unit region being located between adjacent isolation regions, and a protruding part being formed in the device unit region and protruding from the substrate, the protruding part comprising a bottom fin protruding from the substrate and a channel protruding part located on the top of the bottom fin, the adjacent protruding parts and the top surface of the substrate surrounding a first groove, the top of the protruding part being formed with a channel stack with a partial height close to the substrate as a bottom fin and a channel structure with a remaining height, the adjacent channel stacks and the top surface of the substrate surrounding the first groove, and the top of the channel stack being formed with an etching stop layer; forming a protective layer on the top of the substrate in the isolation region, the sidewall of the protruding part closest to the isolation region, and the top of the etching stop layer, the protective layer also sealing the top of the first groove; forming a sacrificial layer on the sidewall of the protective layer in the isolation region; after the sacrificial layer is formed, removing the protective layer and the sacrificial layer higher than the top of the etching stop layer; after the protective layer and the sacrificial layer higher than the top of the etching stop layer are removed, forming a first isolation layer on the top of the protective layer in the isolation region and in the first groove of the device unit region, the top of the first isolation layer being flush with the top of the etching stop layer; removing the sacrificial layer to form an opening in the isolation region, the opening being surrounded by the sidewall of the first isolation layer, the top of the protective layer on the substrate, and the sidewall of the protective layer; forming a conductive layer in the opening, the top of the conductive layer being lower than the top of the bottom fin; after the conductive layer is formed, filling a second isolation layer in the remaining space of the opening; removing the first isolation layer, the second isolation layer, and the protective layer higher than the top of the bottom fin to expose the channel protruding part.

[0023] The forming method provided by the embodiment of the present application comprises the following steps: forming a protection layer on the top of the substrate in the isolation region, the sidewall of the protruding part closest to the isolation region, and the top of the etching stop layer, the protection layer also seals the top of the first groove, so that the protection layer seals the substrate exposed by the device unit region, then forming a sacrificial layer on the sidewall of the protection layer in the isolation region, the forming position of the conductive layer is defined by the sacrificial layer, and the conductive layer is formed in the opening after the sacrificial layer is removed, compared with the prior art in which the conductive layer is formed between adjacent fin parts, the embodiment of the present application only needs to form the conductive layer on both sides of the plurality of fin parts, so that the pattern density in the device unit region is increased, the forming area of the semiconductor structure is reduced, and meanwhile, the probability that the fin part in the device unit region is damaged in the process of forming the conductive layer is also reduced, thereby improving the performance of the semiconductor structure.

[0024] In order to make the above-mentioned purpose, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0025] Figure 6 FIG. 1 is a structural schematic diagram of an embodiment of a semiconductor structure.

[0026] The semiconductor structure comprises: a substrate 200, the substrate 200 comprising an isolation region 200A and a device unit region 200B, the device unit region 200B being located between adjacent isolation regions 200A; a bottom fin 201 located in the device unit region 200B and standing on the top of the substrate 200; a channel structure 290 located above the top of the bottom fin 201; a protection layer 251 located on the top of the substrate 200 in the isolation region 200A and the sidewall of the bottom fin 201 closest to the isolation region 200A, the protection layer 251 comprising a first sub-protection layer 209 located on the top of the substrate 200 and a second sub-protection layer 250 located on the sidewall of the bottom fin 201; a conductive layer 217 standing on the top of the first sub-protection layer 209 and covering the sidewall of the second sub-protection layer 250 away from the bottom fin 201, the top of the conductive layer 217 being lower than the top of the second sub-protection layer 250; a first isolation layer 213 located on the substrate 200 between adjacent bottom fins 201 and the top of the first sub-protection layer 209 exposed by the conductive layer 217, the top of the first isolation layer 213 being flush with the top of the second sub-protection layer 250; and a second isolation layer 222 located on the top of the conductive layer 217 and covering the sidewall of the second sub-protection layer 250 and the first isolation layer 213 exposed by the conductive layer 217.

[0027] In the embodiment, the conductive layer 217 protrudes on top of the first sub-protection layer 209 and covers the sidewall of the second sub-protection layer 250 facing away from the bottom fin 201, and the conductive layer 217 is located on both sides of the plurality of bottom fins 201, so that the pattern density in the device unit area 200B is increased, the formation area of the semiconductor structure is reduced, and the probability of damage to the bottom fin 201 in the device unit area 200B in the process of forming the conductive layer 217 is also reduced, thereby improving the performance of the semiconductor structure.

[0028] In the embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials such as indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0029] In the embodiment, the bottom fin 201 protrudes on the substrate 200, and the material of the bottom fin 201 is the same as that of the substrate 200, both of which are silicon.

[0030] The channel structure 290 is used to provide a channel of a transistor.

[0031] In the embodiment, the substrate 200 is used to form a fin field effect transistor (FinFET). The channel structure 290 includes a channel fin protruding on top of the bottom fin 201. The channel fin is used as a conductive channel in a transistor.

[0032] In the embodiment, the channel structure 290 and the bottom fin 201 are integrated structures, and for this purpose, the material of the channel structure 290 is the same as that of the bottom fin 201.

[0033] In other embodiments, the substrate 200 can also be used to form a gate-all-around transistor (GAA) or a complementary field effect transistor (CFET), and the channel structure 290 includes a channel stack suspended above the top of the bottom fin, and along the normal direction of the surface of the substrate, the channel stack includes one or more channel layers arranged at intervals. The channel layer is used as a conductive channel in the transistor.

[0034] In the embodiment, the substrate 200 includes an isolation area 200A and a device unit area 200B, the device unit area 200B is used to form a transistor, and the isolation area 200A is used to isolate adjacent device unit areas 200B.

[0035] In the embodiment, the device unit area 200B includes a sub-device area 210A and a partition area 210B located between adjacent sub-device areas 210A.

[0036] Specifically, the adjacent sub-device regions 210A are used to form a first type of transistor and a second type of transistor, respectively, the first type and the second type being different. In this embodiment, the first type is N type and the second type is P type, and in other embodiments, the first type is P type and the second type is N type.

[0037] It should be noted that the partition region 210B between the adjacent sub-device regions 210A is used to isolate the first type of transistor and the second type of transistor, so as to reduce the probability of mutual diffusion of ions doped in the well regions of the substrates of the first type of transistor and the second type of transistor, and to facilitate guaranteeing the respective performances of the first type of transistor and the second type of transistor, thereby improving the performance of the semiconductor structure.

[0038] In this embodiment, the top of the substrate 200 in the partition region 210B is lower than the top of the substrate 200 in the sub-device region 210A, and the top of the substrate 200 in the partition region 210B and the sidewall of the substrate 200 in the sub-device region 210A enclose a groove (not shown in the figure).

[0039] Specifically, the top of the substrate 200 in the partition region 210B is lower than the top of the substrate 200 in the sub-device region 210A, and the second isolation layer 222 is filled in the groove, which facilitates further reducing the probability of mutual diffusion of ions doped in the substrates of the adjacent sub-device regions 210A, and plays a good isolation role.

[0040] The protective layer 251 is located on the top of the substrate 200 of the isolation region 200A and the sidewall of the bottom fin 201 closest to the bottom of the isolation region 200A, and the protective layer 251 exposes the channel structure 290, so as to ensure that the channel structure 290 can realize normal functions.

[0041] The second sub-protective layer 250 covers the sidewall of the bottom fin 201 closest to the isolation region 200B, and the second sub-protective layer 250 is used to electrically isolate the bottom fin 201 and the conductive layer 217, thereby reducing the risk of short circuit between the conductive layer 217 and the bottom fin 201 and protecting the sidewall of the bottom fin 201, thereby improving the performance of the semiconductor structure.

[0042] The first sub-protective layer 209 is located on the top of the substrate 200 of the isolation region 200A, and the first sub-protective layer 209 is used to electrically isolate the conductive layer 217 and the substrate 200, thereby reducing the risk of short circuit between the conductive layer 217 and the substrate 200 and protecting the top of the substrate 200 in the process of forming the conductive layer 217.

[0043] The protective layer 251 can electrically isolate the conductive layer 217 from the bottom fin 201 and the substrate 200.

[0044] In the embodiment, the protective layer 251 is formed on the sidewall of the bottom fin 201 and extends to cover the top of the substrate 200, that is, the first sub-protective layer 209 is located on the top of the substrate 200 in the isolation region 200A, and the conductive layer 217 is formed on the conductive layer 217, so that the conductive layer 217 is located on the top of the first sub-protective layer 209, that is, the conductive layer 217 is located above the top of the substrate 200.

[0045] It should be noted that the thickness of the protective layer 251 should not be too large or too small. If the thickness of the protective layer 251 is too large, it will occupy too much space of the conductive layer 217 in the isolation region 200A, so that the size of the conductive layer 217 does not meet the process requirement, and accordingly, the electrical performance of the conductive layer 217 is poor, thereby affecting the performance of the semiconductor structure. If the thickness of the protective layer 251 is too small, the isolation effect of the protective layer 251 on the bottom fin 201 and the conductive layer 217 is reduced, and the probability of short circuit between the conductive layer 217 and the bottom fin 201 is increased, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, the thickness of the protective layer 251 is 7 nanometers to 50 nanometers.

[0046] The protective layer 251 is used to electrically isolate the protruding portion 291 and the conductive layer 217. The protective layer 251 is an insulating material. Therefore, the material of the protective layer 251 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. As an example, the material of the protective layer 251 is silicon oxide.

[0047] The conductive layer 217 is used to electrically connect with an interconnection structure to be formed in the isolation region 200A subsequently. Specifically, the conductive layer 217 is a buried power rail (BPR) structure.

[0048] In the embodiment, the material of the conductive layer 217 is tungsten. The resistivity of tungsten is low, which is beneficial to improve the signal delay of the back-end RC and improve the processing speed of the chip, and is also beneficial to reduce the resistance of the conductive layer 217 and accordingly reduce the power consumption. In other embodiments, the material of the conductive layer can also be a conductive material such as cobalt, ruthenium, or nickel.

[0049] It should be noted that the lateral dimension of the conductive layer 217 should not be too large or too small in the direction perpendicular to the extension direction of the bottom fin 201. If the lateral dimension of the conductive layer 217 is too large, the size of the sub-device region 210A will be too small under the condition that the lateral dimension of the substrate 200 is constant, which will accordingly cause the pattern density in the sub-device region 210A to decrease, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the conductive layer 217 is too small, the aspect ratio of the conductive layer 217 will be too small, which will increase the difficulty of forming the conductive layer 217 in the forming process of the conductive layer 217. Meanwhile, the lateral dimension of the conductive layer 217 is too small, which will cause the conductive layer in the isolation region 100A to fail to meet the electrical requirement, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the conductive layer 217 is 15-30 nm in the direction perpendicular to the extension direction of the bottom fin 201.

[0050] It should be noted that the top of the conductive layer 217 is lower than the top of the bottom fin 201, which provides a spatial position for forming the second isolation layer 222 on the top of the conductive layer 217, reduces the probability of damage to the top of the conductive layer 217 in the subsequent process, and thereby improves the performance of the semiconductor structure.

[0051] Moreover, the conductive layer 217 is buried in the second isolation layer 222 and the first isolation layer 213 to ensure the normal operation of the device.

[0052] It should also be noted that the distance from the top of the conductive layer 217 to the top of the second sub-protective layer 250 should not be too large or too small. If the distance from the top of the conductive layer 217 to the top of the second sub-protective layer 250 is too large, the filling difficulty of forming the second isolation layer 222 on the top of the conductive layer 217 will be increased. If the distance from the top of the conductive layer 217 to the top of the second sub-protective layer 250 is too small, the protection effect of the second isolation layer 222 on the top of the conductive layer 217 will be poor, which will increase the probability of damage to the top of the conductive layer 217 and the probability of exposure of the conductive layer 217. Therefore, in this embodiment, the distance from the top of the conductive layer 217 to the top of the second sub-protective layer 250 is 10-50 nm.

[0053] The first isolation layer 213 plays an electrical isolation role for adjacent transistors.

[0054] The first isolation layer 213 is located on the top of the substrate 200 in the sub-device region 210A.

[0055] Specifically, the first isolation layer 213 on the top of the substrate 200 in the sub-device region 210A plays an isolation role to the bottom fin 201 standing in the sub-device region 210A.

[0056] The top of the first isolation layer 213 is flush with the top of the second sub-protective layer 250, thereby providing a spatial position for forming the second isolation layer 222 on the top of the conductive layer.

[0057] The first isolation layer 213 is an insulating material, and for this purpose, the material of the first isolation layer 213 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the first isolation layer 213 is silicon oxide.

[0058] The first isolation layer 213 is on the top of the substrate 200 in the sub-device region 210A.

[0059] Specifically, the first isolation layer 213 on the top of the substrate 200 in the sub-device region 210A plays an isolation role to the bottom fin 201 standing in the sub-device region 210A.

[0060] Specifically, the second isolation layer 222 covers the top of the conductive layer 217, and plays a protective role to the top of the conductive layer 217 in the process of forming a gate structure, thereby reducing the probability of damage to the conductive layer 217.

[0061] In this embodiment, the second isolation layer 222 is also on the top of the substrate 200 in the partition region 210B.

[0062] Specifically, the second isolation layer 222 also fills in the groove, so that the second isolation layer 222 in the partition region 210B can play a better isolation role, thereby better reducing the probability of mutual diffusion of doped ions in the first type transistor and the second type transistor substrates.

[0063] The second isolation layer 222 is an insulating material, and plays an isolation role to adjacent device regions, and for this purpose, the material of the second isolation layer 222 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the second isolation layer 222 is silicon oxide.

[0064] Figures 7 to 22 is a structure diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure.

[0065] Reference Figures 7 to 9A substrate 100 is provided, which includes isolation regions 100A and device cell regions 100B located between adjacent isolation regions 100A, and the device cell regions 100B have a raised portion 191 formed thereon, the raised portion 191 includes a bottom fin 101 raised from the substrate 100, and a channel raised portion 190 located on top of the bottom fin 101, and a first recess 106 is formed between the raised portion 191 and the top surface of the substrate 100, and the top of the raised portion 191 has an etching stop layer 102 formed thereon.

[0066] The substrate 100 is used to provide a process platform for subsequent process.

[0067] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate can also be made of germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0068] In this embodiment, the raised portion 191 is raised from the substrate 100, and a portion of the height of the raised portion 191 is used as the bottom fin 101, and the remaining height of the bottom fin 101 is used as the channel raised portion 190, and the bottom fin 101 is closer to the substrate 100.

[0069] In this embodiment, the substrate 100 is used to form a fin field effect transistor (FinFET). The channel raised portion 190 includes a channel fin raised from the top of the bottom fin 101.

[0070] The channel raised portion 190 is used as a conductive channel in a transistor in subsequent process.

[0071] In this embodiment, the material of the raised portion 191 is the same as the material of the substrate 100, and both are silicon.

[0072] In this embodiment, the step of forming the raised portion 191 in the device cell region 100B includes: as shown in Figure 7 providing a substrate; forming an etching stop material layer on the top of the substrate; forming a patterned fin mask layer 103 on the top of the etching stop material layer in the device cell region 100B and the isolation region 100A; patterning the substrate using the fin mask layer 103 as a mask to form the substrate 100 and the raised portion 191 raised from the substrate 100; and as shown in Figure 8As shown, a first mask layer 108 covering the top and sidewall of the protruding portion 191 is formed in the device unit region 100B, and the first mask layer 108 exposes the protruding portion 191 in the isolation region 100A; the protruding portion 191 in the isolation region 100A is removed with the first mask layer 108 as a mask, and the protruding portion 191 standing on the substrate 100 is formed in the device unit region 100B, and the remaining etching stop material layer serves as the etching stop layer 102.

[0073] In the process of forming the fin mask layer 103, the etching stop material layer plays a role of etching stop, and reduces the probability of damage to the material corresponding to the protruding portion 191.

[0074] It should be noted that in the embodiment, after the protruding portion 191 in the isolation region 100A is removed, the first mask layer 108 is also removed.

[0075] Specifically, the process of removing the first mask layer 108 includes a gray ash process.

[0076] In the embodiment, the substrate 100 includes an isolation region 100A and a device unit region 100B, the device unit region 100B is used to form a transistor, and the isolation region 100A is used to isolate adjacent device unit regions 100B.

[0077] In the embodiment, the device unit region 100B includes a sub-device region 110A and a partition region 110B located between adjacent sub-device regions 110A.

[0078] Specifically, adjacent sub-device regions 110A are used to form a first type transistor and a second type transistor, respectively, and the first type and the second type are different. In the embodiment, the first type is N type, and the second type is P type. In other embodiments, the first type is P type, and the second type is N type.

[0079] It should be noted that the partition region 110B located between adjacent sub-device regions 110A is used to isolate the first type transistor and the second type transistor, and reduce the probability of mutual diffusion of ions in the well region doped in the substrate of the first type transistor and the second type transistor, which is conducive to guaranteeing the performance of the first type transistor and the second type transistor, thereby improving the performance of the semiconductor structure.

[0080] In other embodiments, the substrate 100 can also be used to form a fully-enclosed gate-all-around transistor (GAA) or a nanosheet field effect transistor (CFET), the channel protrusion includes a stack structure standing on top of the bottom fin, the stack structure includes one or more stacked channel stacks, the channel stack includes a sacrificial layer and a channel layer on the sacrificial layer.

[0081] Meanwhile, in the subsequent process of removing the protective layer and the sacrificial layer above the top of the etching stop layer 102, the etching stop layer 102 plays a role of etching stop, improving the flatness of the top surface of the protective layer and the sacrificial layer.

[0082] It should be noted that the first groove 106 surrounded by the adjacent protrusion 191 and the top surface of the substrate 100 provides a spatial position for the subsequent formation of the first isolation layer.

[0083] Reference Figure 10 The protective layer 109 is formed on the top of the substrate 100 of the isolation region 100A, the sidewall of the protrusion 191 closest to the isolation region 100B, and the top of the etching stop layer 102, and the protective layer 109 also seals the top of the first groove 106.

[0084] Specifically, the protective layer 109 seals the top of the first groove 106, achieving the purpose of the protective layer 109 sealing the entire substrate 100 exposed by the device unit region 100B, and reducing the probability of the subsequent formation of the sacrificial layer in the device unit region 100B.

[0085] The protective layer 109 covers the sidewall of the protrusion 191 closest to the isolation region 100B, and the protective layer 109 is used for electrically isolating the protrusion 191 and the subsequently formed conductive layer, reducing the risk of short circuit between the conductive layer and the protrusion 191, and the protective layer 109 is also used for protecting the sidewall of the bottom fin 101 during the subsequent formation of the conductive layer, thereby improving the performance of the semiconductor structure.

[0086] Moreover, the protective layer 109 is located on the top of the substrate 100 of the isolation region 100A, and the protective layer 109 is used for electrically isolating the conductive layer 117 and the substrate 100, reducing the risk of short circuit between the conductive layer 117 and the substrate 100, and the protective layer 109 protects the top of the substrate 100 during the process of forming the conductive layer 117.

[0087] It should be noted that the thickness of the protective layer 109 should not be too large or too small. If the thickness of the protective layer 109 is too large, it will occupy too much space of the conductive layer formed subsequently in the isolation region 100A, so that the size of the conductive layer does not meet the process requirement, and accordingly, the electrical performance of the conductive layer is poor, thereby affecting the performance of the semiconductor structure. If the thickness of the protective layer 109 is too small, the effect of electrically isolating the protruding part 191 and the conductive layer by the protective layer 109 is reduced, and the probability of short circuit between the conductive layer and the protruding part 191 is increased, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, the thickness of the protective layer 109 is 7 nanometers to 50 nanometers.

[0088] The protective layer 109 is used to electrically isolate the protruding part 191 and the conductive layer formed subsequently, and the protective layer 109 is an insulating material. Therefore, the material of the protective layer 109 is one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the protective layer 109 is silicon oxide.

[0089] In the embodiment, the process of forming the protective layer 109 on the top of the substrate 100 in the isolation region 100A, the sidewall of the protruding part 191 closest to the isolation region 100A, and the top of the etching stop layer 102 includes a plasma enhanced chemical vapor deposition process.

[0090] As an example, the process of forming the protective layer 109 includes a plasma enhanced chemical vapor deposition process. The plasma enhanced chemical vapor deposition process has the characteristics of low deposition temperature, high film deposition thickness uniformity, and strong film adhesion. Since the spacing between adjacent protruding parts 191 is small, and the deposition rate of the material forming the protective layer 109 on the protruding part 191 is higher than that on the sidewall of the protruding part 191, the protective layer 109 on the top of the protruding part 191 can be contacted first. Therefore, by using the plasma enhanced chemical vapor deposition process, the protective layer 109 can seal the top of the first groove 106, thereby sealing the exposed substrate 100 in the device unit region 100B. As an example, the process of forming the protective layer 109 includes a plasma enhanced chemical vapor deposition process.

[0091] Reference Figures 11 to 12 In the isolation region 100A, a sacrificial layer 111 is formed on the sidewall of the protective layer 109.

[0092] Specifically, the forming position of the conductive layer formed later is defined by the sacrificial layer 111, that is, the thickness of the sacrificial layer 111 can be controlled to control the size of the conductive layer. Compared with the scheme of forming a dielectric layer in the isolation region 100A, forming an opening in the dielectric layer, and forming a conductive layer in the opening, the sacrificial layer 111 is a film layer structure, and the thickness of the sacrificial layer 111 is easy to control accurately, thereby facilitating the accurate control of the size of the conductive layer. Moreover, the sacrificial layer 111 is a film layer structure covering the sidewall of the protective layer 109, thereby forming the conductive layer on both sides of the device unit region and achieving self-alignment, improving the controllability of the forming area of the conductive layer, and reducing the process difficulty of forming the conductive layer.

[0093] In addition, compared with the scheme of forming a dielectric layer in the isolation region 100A, forming an opening in the dielectric layer, and forming a conductive layer in the opening, the embodiment can avoid the photolithography process, thereby reducing the process difficulty of forming the conductive layer, and correspondingly, reducing the probability of damaging the protruding part 191 in the device unit region 100B.

[0094] It should be noted that in the direction perpendicular to the extension direction of the protruding part 191, the thickness of the sacrificial layer 111 should not be too large or too small. If the thickness of the sacrificial layer 111 is too large, under the condition that the lateral size of the substrate 100 is constant, the size of the device unit region 100B is likely to be too small, and correspondingly, the pattern density in the device unit region 100B is reduced, thereby affecting the performance of the semiconductor structure. If the thickness of the sacrificial layer 111 is too small, the aspect ratio of the sacrificial layer 111 is increased, and in the subsequent process of removing the sacrificial layer 111, the process difficulty of removing the sacrificial layer 111 is increased, and correspondingly, the process effect of forming the conductive layer later is affected, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, in the direction perpendicular to the extension direction of the protruding part 191, the thickness of the sacrificial layer 111 is 15 nanometers to 30 nanometers.

[0095] In order to reduce the process difficulty of removing the sacrificial layer 111 later, a material easy to remove needs to be selected as the material of the sacrificial layer 111. Therefore, in the embodiment, the material of the sacrificial layer 111 includes one or more of Si, SiN, and SiC.

[0096] In the embodiment, the step of forming the sacrificial layer 111 on the sidewall of the protective layer 109 in the isolation region 100A includes: Figure 11 as shown, forming a sacrificial material layer 110 on the top and sidewall of the protective layer 109; Figure 12As shown, the sacrificial material layer 110 on the top of the protective layer 109 is removed, and the remaining sacrificial material layer 110 covering the sidewall of the protective layer 109 is used as the sacrificial layer 111.

[0097] In this embodiment, the process of forming the sacrificial material layer 110 on the top and sidewall of the protective layer 109 includes an atomic layer deposition process.

[0098] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which has good step coverage and is beneficial to improve the thickness uniformity of the sacrificial material layer 110 and enable the sacrificial material layer 110 to cover the top and sidewall of the protective layer 109. In other embodiments, a chemical vapor deposition (CVD) process can also be used to form the sacrificial material layer.

[0099] In this embodiment, an etching process is used to remove the sacrificial material layer 110 on the top of the protective layer 109.

[0100] Specifically, the etching process can remove the sacrificial material layer 110 on the top of the protective layer 109 completely, and only the sacrificial material layer 110 on the sidewall of the protective layer 109 is retained.

[0101] Specifically, the etching process is an inductively coupled plasma dry etching process.

[0102] Reference Figure 13 After the formation of the sacrificial layer 111, the protective layer 109 and the sacrificial layer 111 higher than the top of the etching stop layer 102 are removed.

[0103] The removal of the protective layer 109 and the sacrificial layer 111 higher than the top of the etching stop layer 102 provides a good process basis for the subsequent formation of the first isolation layer.

[0104] In this embodiment, the step of removing the protective layer 109 and the sacrificial layer 111 higher than the top of the etching stop layer 102 includes: taking the top of the etching stop layer 102 as a stop position, and performing a planarization process on the sacrificial layer 111 and the protective layer 109 higher than the top of the etching stop layer 102.

[0105] Compared with using an etching process to remove the protective layer 109 and the sacrificial layer 111 higher than the top of the etching stop layer 102, the etching process increases the difficulty of selecting the etching rate, making the process steps complicated. Therefore, using the planarization process can improve the flatness of the top of the protruding portion 191, which is beneficial to reduce the process complexity, and also reduces the probability of the flatness of the top of the protruding portion 191.

[0106] In this embodiment, the planarization process includes a chemical mechanical polishing process.

[0107] Referring to Figures 14 to 15 After the protective layer 109 and the sacrificial layer 111 above the etching stop layer 102 are removed, a first isolation layer 113 is formed on the top of the protective layer 109 in the isolation region 100A and in the first recess 106 in the device unit region 100B, and the top of the first isolation layer 113 is flush with the top of the etching stop layer 102.

[0108] Specifically, in the subsequent removal of the sacrificial layer 111, the first isolation layer 113 protects the top of the substrate 100 and the sidewall of the protrusion 191 exposed in the device unit region 100B, and by forming the first isolation layer 113 on the top of the protective layer 109 in the isolation region 100A, an opening surrounded by the sidewall of the first isolation layer 113, the top of the protective layer 109 on the substrate 100, and the sidewall of the protective layer 109 can be formed after the sacrificial layer 111 is removed, which defines the position of the subsequently formed conductive layer and improves the position accuracy of the conductive layer, thereby improving the performance of the semiconductor structure.

[0109] The first isolation layer 113 is an insulating material and electrically isolates adjacent device regions. In order to make the etching rate of the first isolation layer 113 less than that of the sacrificial layer 111 during the subsequent removal of the sacrificial layer 111, a high etching selectivity is required between the first isolation layer 113 and the sacrificial layer 111. Therefore, the material of the first isolation layer 113 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the first isolation layer 113 is silicon oxide.

[0110] In this embodiment, the step of forming the first isolation layer 113 on the top of the protective layer 109 in the isolation region 100A and in the first recess 106 in the device unit region 100B includes: as shown in Figure 14 forming a first isolation material layer 112 on the top of the substrate 100, which covers the top of the sacrificial layer 111, the protective layer 109, and the etching stop layer 102 and fills the first recess 106; and Figure 15 as shown in

[0111] In this embodiment, the semiconductor structure density is increased, and the distance between adjacent protruding portions 191 and the distance between the protruding portions 191 and other semiconductor structures are correspondingly reduced. Therefore, in order to enable the first isolation material layer 112 to be filled sufficiently, the first isolation material layer 112 can be formed by using a flowable chemical vapor deposition (FCVD) process. In other embodiments, the process of forming the first isolation material layer 112 can further include an atomic layer deposition process or a combination of an atomic layer deposition process and a flowable chemical vapor deposition process.

[0112] Referring to Figure 16 The sacrificial layer 111 is removed, and an opening 116 surrounded by the sidewall of the first isolation layer 113, the top of the protective layer 109 on the substrate 100, and the sidewall of the protective layer 109 is formed in the isolation region 100A.

[0113] The opening 116 provides a spatial position for subsequent formation of the conductive layer, and the conductive layer is formed only on both sides of the plurality of protruding portions 191, so that the pattern density in the device unit region 100B is increased, and the formation area of the semiconductor structure is reduced.

[0114] Moreover, the opening 116 is formed by removing the sacrificial layer 111, which is self-aligned, and the protective layer 109 protects the protruding portions 191, thereby reducing the probability of damage to the protruding portions 191 in the device unit region 100B during the formation of the opening 116 and the conductive layer, and improving the performance of the semiconductor structure.

[0115] In this embodiment, the process of removing the sacrificial layer 111 includes a wet etching process.

[0116] The wet etching process has the characteristics of an isotropic etching process, has strong etching target, high etching efficiency, and strong lateral etching capability, and can reduce damage to the protective layer 109 at the bottom of the opening 116 and the first isolation layer 113 on the sidewall of the opening 116 during lateral removal of the sacrificial layer 111.

[0117] In other embodiments, the sacrificial layer can also be removed by using an ashing process.

[0118] Referring to Figure 17 A conductive layer 117 is formed in the opening 116, and the top of the conductive layer 117 is lower than the top of the bottom fin 101.

[0119] The conductive layer 117 is used to electrically connect with an interconnection structure subsequently formed in the isolation region 100A.

[0120] Specifically, the conductive layer 117 is a buried power rail (BPR) structure.

[0121] In this embodiment, the material of the conductive layer 117 is tungsten. The resistivity of tungsten is low, which is conducive to improving the signal delay of the back-end RC, improving the processing speed of the chip, and reducing the resistance of the conductive layer 117, thereby reducing the power consumption. In other embodiments, the material of the conductive layer can also be a conductive material such as cobalt, ruthenium, or nickel.

[0122] In this embodiment, the step of forming the conductive layer 117 in the opening 116 includes: filling a conductive material layer (not shown in the figure) in the opening 116; and etching back a partial thickness of the conductive material layer, and the conductive material layer remaining in the opening 116 as the conductive layer 117.

[0123] In this embodiment, the process of etching back a partial thickness of the conductive material layer includes an anisotropic dry etching process.

[0124] Specifically, the anisotropic dry etching process has the characteristics of anisotropic etching, and the longitudinal etching rate is much greater than the lateral etching rate, which can obtain a relatively accurate pattern transfer and improve the morphology quality of the sidewall of the opening 116. At the same time, the dry etching process has high process controllability, which reduces the probability of damage to the protective layer 109 and the first isolation layer 113 on the sidewall of the opening 116 during the process of etching back a partial thickness of the conductive material layer.

[0125] It should be noted that the top of the conductive layer 117 is lower than the top of the bottom fin 101, which provides a spatial position for forming a second isolation layer on the top of the conductive layer 117, and reduces the probability of damage to the top of the conductive layer 117 in subsequent process technology, thereby improving the performance of the semiconductor structure.

[0126] At the same time, the conductive layer 117 is buried in the first isolation layer 113 and the second isolation layer formed subsequently.

[0127] Reference Figures 18 to 19 After forming the conductive layer 117, before filling a second isolation layer in the remaining space of the opening 116, the method further includes: removing the protruding portion 191 of the partition area 110B and the first isolation layer 113.

[0128] Specifically, as known from the foregoing, since the adjacent sub-device regions 110A are used to form first-type transistors and second-type transistors respectively, the first-type and the second-type are different. In order to reduce the probability of mutual diffusion of ions doped in the substrates of the first-type transistors and the second-type transistors, and thus to help guarantee the respective performances of the first-type transistors and the second-type transistors, the protruding portion 191 and the first isolation layer 113 of the partition region 110B are removed to provide a space position for forming a second isolation layer in the partition region 110B subsequently.

[0129] In this embodiment, the step of removing the protruding portion 191 and the first isolation layer 113 of the partition region 110B includes: as shown in Figure 18 , forming a second mask layer 118 on the top of the first isolation layer 113, the etching stop layer 102, the protective layer 109 and the conductive layer 117 in the sub-device regions 110A and the isolation region 100A, the second mask layer 118 exposing the first isolation layer 113 and the protruding portion 191 in the partition region 110B; as shown in Figure 19 , removing the protruding portion 191 and the first isolation layer 113 in the partition region 110B with the second mask layer 118 as a mask.

[0130] In this embodiment, the step of removing the protruding portion 191 and the first isolation layer 113 of the partition region 110B includes a dry etching process.

[0131] It should be noted that in the step of removing the protruding portion 191 and the first isolation layer 113 of the partition region 110B, a part of the thickness of the substrate 100 of the partition region 110B is also removed, and a second recess 120 is formed in the substrate 100.

[0132] In order to better reduce the probability of mutual diffusion of ions doped in the well regions of the substrates of the first-type transistors and the second-type transistors, a part of the thickness of the substrate 100 of the partition region 110B is also removed, so that the second isolation layer formed in the second recess 120 in the partition region 110B subsequently can play a better isolation role.

[0133] It should also be noted that after the protruding portion 191 and the first isolation layer 113 of the partition region 110B are removed, the method for forming the semiconductor structure further includes: removing the second mask layer 118.

[0134] In this embodiment, the process of removing the second mask layer 118 includes an ashing process.

[0135] Referring to Figures 20 to 21 , after the conductive layer 117 is formed, a second isolation layer 122 is filled in the remaining space of the opening 116.

[0136] Specifically, the second isolation layer 122 covers the top of the conductive layer 117, and protects the top of the conductive layer 117 in a subsequent process of forming a gate structure, thereby reducing the probability of damage to the conductive layer 117.

[0137] In the embodiment, the step of filling the second isolation layer 122 in the remaining space of the opening 116 includes: forming a second isolation material layer 121 in the opening 116, as shown in FIG. 1C, the second isolation material layer 121 also covers the top of the first isolation layer 113, the etching stop layer 102 and the protection layer 109; and Figure 20 Figure 21 As shown in FIG. 1D, the top of the etching stop layer 102 is used as an etching stop position, and the second isolation material layer 121 higher than the top of the etching stop layer 102 is planarized, and the remaining second isolation material layer 121 in the opening 116 is used as the second isolation layer 122.

[0138] In the embodiment, in the step of filling the second isolation layer 122 in the remaining space of the opening 116, the second isolation layer 122 is also formed on the substrate 100 of the partition region 110B, and the top of the second isolation layer 122 of the partition region 110B is flush with the top of the second isolation layer 122 in the opening 116.

[0139] The second isolation layer 122 of the partition region 110B isolates the transistors in the adjacent sub-device region 110A, and the top of the second isolation layer 122 in the partition region 110B is flush with the top of the second isolation layer 122 in the opening 116, so that the flatness of the top surface of the second isolation layer 122 is high, thereby providing a good process basis for subsequent process.

[0140] In the embodiment, in the step of forming the second isolation layer 122, the second isolation layer 122 also fills the second groove 120.

[0141] Specifically, the second isolation layer 122 filling the second groove 120 reduces the probability of mutual diffusion of ions of doped well regions in the substrate of the adjacent sub-device region 110A, and has a good isolation effect.

[0142] The second isolation layer 122 is an insulating material, and isolates adjacent device regions, and therefore the material of the second isolation layer 122 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the second isolation layer 122 is silicon oxide.

[0143] Reference is made to FIG. 1A, which is a schematic diagram of a semiconductor device according to an embodiment of the present application. Figure 22 ​, the first isolation layer 113, the second isolation layer 122 and the protective layer 109 above the top surface of the bottom fin 101 are removed to expose the channel protrusion 190.

[0144] Specifically, the channel protrusion 190 is exposed to provide a process basis for a subsequent process of forming a gate structure.

[0145] It should be noted that the first isolation layer 113, the second isolation layer 122 and the protective layer 109 are made of the same material, and therefore, the first isolation layer 113, the second isolation layer 122 and the protective layer 109 above the top surface of the bottom fin 101 can be removed simultaneously in the same step under the same etching selectivity.

[0146] In the embodiment, the process of removing the first isolation layer 113, the second isolation layer 122 and the protective layer 109 above the top surface of the bottom fin 101 includes a dry etching process.

[0147] Continuing to refer to Figure 22 After the first isolation layer 113, the second isolation layer 122 and the protective layer 109 above the top surface of the bottom fin 101 are removed, the process further includes removing the etching stop layer 102 on the top of the channel protrusion 190.

[0148] In the embodiment, the process of removing the etching stop layer 102 includes a dry etching process.

[0149] In other embodiments, the process of removing the etching stop layer 102 can also be a wet etching process.

[0150] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including an isolation region and a device cell region, the device cell region being located between adjacent isolation regions; The bottom fin is located in the device unit area and protrudes from the top of the substrate; A channel structure is located above the top of the bottom fin; A protective layer is located on the top of the substrate of the isolation region and on the sidewall of the bottom fin closest to the isolation region. The protective layer includes a first sub-protective layer located on the top of the substrate and a second sub-protective layer located on the sidewall of the bottom fin. A conductive layer protrudes from the top of the first sub-protective layer and covers the sidewall of the second sub-protective layer facing away from the bottom fin, with the top of the conductive layer being lower than the top of the second sub-protective layer; A first isolation layer is located on the substrate between adjacent bottom fins and on top of the first sub-protective layer exposed by the conductive layer, with the top of the first isolation layer flush with the top of the second sub-protective layer; The second isolation layer is located on top of the conductive layer and covers the exposed sidewalls of the second sub-protective layer and the first isolation layer of the conductive layer.

2. The semiconductor structure as described in claim 1, characterized in that, The device unit region includes a sub-device region and a partition region located between adjacent sub-device regions, and the bottom fin protrudes from the substrate of the sub-device region; The first isolation layer is located on top of the substrate of the sub-device region; The second isolation layer is also located on top of the substrate of the isolation area.

3. The semiconductor structure as described in claim 2, characterized in that, The top of the substrate of the partition region is lower than the top of the substrate of the sub-device region, and the top of the substrate of the partition region and the sidewall of the substrate of the sub-device region form a groove; The second insulating layer also fills the groove.

4. The semiconductor structure as described in claim 1, characterized in that, With the direction perpendicular to the extension direction of the bottom fin as the lateral direction, the lateral dimension of the conductive layer is 15 nanometers to 30 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The conductive layer includes a buried power rail structure.

6. The semiconductor structure as described in claim 1, characterized in that, The conductive layer is made of one or more of tungsten, cobalt, copper, and aluminum.

7. The semiconductor structure as described in claim 1, characterized in that, The distance from the top of the conductive layer to the top of the second sub-protective layer is 10 nanometers to 50 nanometers.

8. The semiconductor structure as described in claim 1, characterized in that, The thickness of the protective layer is 7 nanometers to 50 nanometers.

9. The semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first isolation layer includes one or more of silicon oxide, silicon nitride, and silicon carbide.

11. The semiconductor structure as claimed in claim 1, characterized in that, The material of the second isolation layer includes one or more of silicon oxide and silicon oxynitride.

12. The semiconductor structure as claimed in claim 1, characterized in that, The channel structure includes a channel fin protruding from the top of the bottom fin, or a channel stack suspended above the top of the bottom fin, along the normal direction of the substrate surface, the channel stack including one or more spaced channel layers.

13. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an isolation region and a device cell region, the device cell region being located between adjacent isolation regions, a protrusion protruding from the substrate is formed in the device cell region, the protrusion including a bottom fin protruding from the substrate and a channel protrusion located at the top of the bottom fin, adjacent protrusions and the top surface of the substrate forming a first groove, and an etching stop layer is formed at the top of the protrusion; A protective layer is formed on the top of the substrate in the isolation region, the sidewall of the protrusion closest to the isolation region, and the top of the etch stop layer, and the protective layer also seals the top of the first groove; In the isolation zone, a sacrificial layer is formed on the sidewall of the protective layer; After the sacrificial layer is formed, the protective layer and sacrificial layer above the top of the etch stop layer are removed; After removing the protective layer and sacrificial layer above the top of the etch stop layer, a first isolation layer is formed on top of the protective layer in the isolation region and in the first groove of the device cell region, with the top of the first isolation layer flush with the top of the etch stop layer; Remove the sacrificial layer to form an opening in the isolation region formed by the sidewall of the first isolation layer, the top of the protective layer located on the substrate, and the sidewall of the protective layer; A conductive layer is formed in the opening, the top of which is lower than the top of the bottom fin. After the conductive layer is formed, a second insulating layer is filled into the remaining space of the opening; Remove the first isolation layer, the second isolation layer, and the protective layer above the top surface of the bottom fin to expose the channel protrusion.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming a conductive layer in the opening includes: filling the opening with a conductive material layer; etching back a portion of the conductive material layer, with the remaining conductive material layer in the opening serving as the conductive layer.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the isolation zone, the step of forming a sacrificial layer on the sidewall of the protective layer includes: forming a sacrificial material layer on the top and sidewall of the protective layer; removing the sacrificial material layer on the top of the protective layer, leaving the remaining sacrificial material layer covering the sidewall of the protective layer as the sacrificial layer.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of removing the protective layer and sacrificial layer above the top of the etch stop layer includes: using the top of the etch stop layer as the stop position, performing planarization on the sacrificial layer and protective layer above the top of the etch stop layer.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming a first isolation layer on top of the protective layer in the isolation region and in the first groove of the device cell region includes: forming a first isolation material layer on top of the substrate, the first isolation material layer covering the top of the sacrificial layer, the protective layer and the etch stop layer, and filling the first groove; taking the top of the etch stop layer as the stop position, performing planarization on the first isolation material layer above the top of the etch stop layer, and the remaining first isolation material layer located on top of the protective layer and in the first groove as the first isolation layer.

18. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of filling the remaining space of the opening with a second isolation layer includes: forming a second isolation material layer in the opening, the second isolation material layer also covering the top of the first isolation layer, the etch stop layer and the protective layer; using the top of the etch stop layer as the etch stop position, planarizing the second isolation material layer above the top of the etch stop layer, and the remaining second isolation material layer in the opening serving as the second isolation layer.

19. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process of forming a protective layer on top of the substrate in the isolation region, on the sidewall of the protrusion closest to the isolation region, and on top of the etch stop layer includes a plasma-enhanced chemical vapor deposition process.

20. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process of forming a sacrificial material layer on the top and sidewalls of the protective layer includes atomic layer deposition.

21. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process for forming the first isolation material layer includes atomic layer deposition, fluid chemical vapor deposition, or a combination of atomic layer deposition and fluid chemical vapor deposition.

22. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for removing the sacrificial layer includes a wet etching process.

23. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the sacrificial layer, the material of the sacrificial layer includes one or more of Si, SiN, and SiC.

24. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing a substrate, the channel protrusion includes a channel fin protruding from the top of the bottom fin, or a stacked structure protruding from the top of the bottom fin, the stacked structure including one or more stacked channel layers, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer.

25. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing a substrate, the device cell region includes a sub-device region and a partition region located between adjacent sub-device regions; After the conductive layer is formed, before the second insulating layer is filled into the remaining space of the opening, the method further includes: removing the protrusion and the first insulating layer of the partition area; In the step of filling the remaining space of the opening with a second isolation layer, the second isolation layer is also formed on the substrate of the partition region, with the top of the second isolation layer in the partition region being flush with the top of the second isolation layer in the opening.

26. The method for forming a semiconductor structure as described in claim 25, characterized in that, In the step of removing the protrusion and the first isolation layer of the partition area, a portion of the substrate of the partition area is also removed, and a second groove is formed in the substrate; In the step of forming the second isolation layer, the second isolation layer is also filled in the second groove.

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