Low-RF-loss silicon-based gallium nitride high-electron-mobility transistor and its fabrication method

Abstract

This invention discloses a low-RF-loss silicon-based gallium nitride (GaN) high-electron-mobility transistor, primarily addressing the problems of leakage current at the interface between GaN material and silicon substrate and high RF loss in existing devices. From bottom to top, it comprises a silicon substrate, an RF-loss suppression layer, a channel layer, an AlN insertion layer, and a barrier layer. An insulating gate dielectric layer and a gate electrode are sequentially disposed on the barrier layer, with source and drain electrodes on either side. The RF-loss suppression layer is a composite stacked structure of AlN and transition metal nitride (ScYAlN), with the transition metal nitride layer composition gradually changing from AlN along the growth direction to a composition matching the lattice constant within the channel layer. This invention avoids the remelting etching of aluminum atoms against the silicon substrate during high-temperature MOCVD growth of the AlN nucleation layer on the silicon substrate, suppresses leakage current at the heteroepitaxial interface and RF power loss in the device, and improves the breakdown voltage and reliability of silicon-based GaN devices. It can be used in microwave and millimeter-wave RF integrated circuits and high-efficiency power switches.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a silicon-based gallium nitride high electron mobility transistor, which can be used in microwave and millimeter-wave radio frequency integrated circuits and high-efficiency power switches. Background Technology

[0002] Gallium nitride-based high electron mobility transistors (HEMTs), as a typical representative of third-generation wide-bandgap semiconductor electronic devices, have been widely used in broadband communications, information sensing, consumer electronics, data centers, and energy-saving motors after nearly 30 years of development. They have promoted the construction of an information-based and low-carbon environmentally friendly society and will further play an important role in emerging industries and technologies such as wireless power transmission and electric vehicles. The development of GaN HEMT devices relies on innovation and advancements in material epitaxy technology, device structure design, and manufacturing processes.

[0003] Large-size, low-cost silicon-based GaN HEMT devices are one development direction, enabling heterogeneous integration with silicon-based CMOS circuits and driving Moore's Law towards multifunctionality. Silicon-based GaN HEMT devices are also strong competitors to SiC power devices in the 900V voltage range, reducing the size and weight of power switches and their power supply systems, facilitating the development of compact module components. A typical silicon-based GaN HEMT device structure is as follows: Figure 1 As shown, from bottom to top, it includes a substrate, a nucleation layer, a GaN channel layer, an AlN insertion layer, a barrier layer, and a barrier protection layer. A gate electrode is provided on the barrier protection layer, and a source electrode and a drain electrode are provided on the ohmic contacts of the source and drain regions.

[0004] The high-density dislocations in the channel layer of this device, caused by lattice mismatch and significant differences in thermal expansion coefficients, greatly affect the transport of two-dimensional electron gas in the channel and the reliability of the device. At the same time, because the two-dimensional electron gas in the channel layer can easily overflow from the quantum well at the heterojunction interface and become three-dimensional electrons, it leads to the degradation of material carrier mobility and device output performance. In addition, during the high-temperature growth of AlN nucleation layer in MOCVD, aluminum atoms are prone to back-melting etching problems with the silicon substrate surface, forming leakage channels at the heteroepitaxial interface between gallium nitride epitaxial material and silicon substrate, thereby causing power loss of RF device and reducing device breakdown voltage. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the existing technologies mentioned above by proposing a low-RF loss silicon-based gallium nitride high electron mobility transistor and its fabrication method. This invention aims to avoid the remelting etching of Al atoms on the silicon substrate surface and leakage current at the heteroepitaxial interface during high-temperature heteroepitaxialization of gallium nitride-based materials on silicon substrates, thereby reducing RF loss and dislocation density in the channel layer, improving device breakdown voltage and carrier transport characteristics, and enhancing device output performance.

[0006] The technical solution of the present invention is realized as follows:

[0007] 1. A silicon-based gallium nitride high electron mobility transistor with low radio frequency loss, which includes a substrate, a channel layer, an AlN insertion layer, and a barrier layer from bottom to top, and is characterized in that:

[0008] The substrate is made of silicon material, and a radio frequency loss suppression layer is provided between the substrate and the channel layer;

[0009] The radio frequency loss suppression layer is composed of a composite laminated structure of AlN and transition metal nitride Sc w Y x Al y N. The thickness of the AlN layer in a single laminate is 0.5 nm - 5 nm, and the thickness of the Sc w Y x Al y N layer is 0.5 nm - 10 nm, and the total thickness is 50 nm - 900 nm; the components in each layer of the transition metal nitride Sc w Y x Al y N layer remain unchanged, and the components between different layers gradually change from AlN to the components matching the lattice constant in the plane of the channel layer along the growth direction. The components of each layer are 0 ≤ w ≤ 0.35, 0 ≤ x ≤ 0.25, 0 < y < 1, and w + x + y = 1;

[0010] An insulating gate dielectric layer and a gate electrode are sequentially provided on the upper part of the barrier layer, and source electrodes and drain electrodes are provided on both sides.

[0011] Furthermore, the channel layer is made of GaN, or InGaN, or AlGaN, and its thickness is 10 nm - 2000 nm; the AlN insertion layer has a thickness of 1 nm - 2 nm.

[0012] Furthermore, the barrier layer is made of any one of AlGaN, InAlN, AlN, InAlGaN, ScAlN, YAlN, BAlN, AlPN, BPN, and its thickness is 3 nm - 30 nm;

[0013] Furthermore, the insulating gate dielectric layer is made of an Al2O3, or HfO2, or HfAlO dielectric layer, and its thickness is 5 nm - 20 nm.

[0014] 2. A manufacturing method of a silicon-based gallium nitride high electron mobility transistor with low radio frequency loss, which is characterized by including the following steps:

[0015] 1) On the substrate wafer, a radio frequency loss suppression layer with a thickness of 50 nm - 900 nm is grown by molecular beam epitaxy;

[0016] 2) A channel layer with a thickness of 10nm-2000nm was grown on the radio frequency loss suppression layer using metal-organic chemical vapor deposition.

[0017] 3) An AlN insertion layer with a thickness of 1 nm-2 nm was grown on the channel layer using metal-organic chemical vapor deposition.

[0018] 4) A barrier layer with a thickness of 3 nm to 30 nm was grown on the AlN insertion layer using metal-organic chemical vapor deposition.

[0019] 5) Using photoresist as a mask, dry etching is used to etch the barrier layer down to the surface of the channel layer to form grooves in the source and drain electrode regions.

[0020] 6) Using electron beam evaporation, Ti / Al / Ni / Au metal composites are deposited in the grooves of the source and drain electrode regions, and then annealed at 830℃ in a nitrogen atmosphere to form the source and drain electrodes.

[0021] 7) An insulating gate dielectric layer of 5nm-20nm is grown in the region between the source and drain electrodes above the barrier layer using atomic layer deposition technology.

[0022] 8) The gate electrode pattern is defined on the surface of the insulating gate dielectric layer using photolithography, and then Ni / Au metal combination is deposited on the insulating gate dielectric layer using electron beam evaporation to form the gate electrode, thus completing the device fabrication.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] 1. This invention provides a radio frequency loss suppression layer between the silicon substrate and the channel layer, which also serves as a nucleation layer for heteroepitaxial growth of gallium nitride (GaN) on silicon. This avoids the remelting and etching of Al atoms on the silicon substrate surface caused by the high-temperature growth of AlN nucleation layer on the silicon substrate via MOCVD, thus suppressing the formation of leakage channels at the heteroepitaxial interface and reducing device radio frequency power loss. Furthermore, this layer structure is an ultra-wide bandgap material, which can act as a back barrier, improving the confinement and transport characteristics of the two-dimensional electron gas in the active region channel layer of the GaN device. It can also suppress vertical leakage and improve the device's withstand voltage capability.

[0025] 2. This invention uses an AlN and transition metal nitride Sc layer to suppress radio frequency loss. w Y x Al yThe composite laminated structure of N with a graded composition can not only achieve near lattice matching with the in-plane lattice constant of the channel layer material, reduce the dislocation density in the epitaxial material without setting a buffer layer with a complex structure, thereby improving the material quality and device reliability of the active region of the gallium nitride on silicon device and simplifying the material epitaxy process; but also effectively filter the dislocations generated in the heteroepitaxy of the gallium nitride on silicon material and release the accumulated strain, and can realize a large-size low-warpage thick-film gallium nitride on silicon epitaxial material. Brief Description of the Drawings

[0026] Figure 1 is a structural diagram of a traditional gallium nitride on silicon high electron mobility transistor;

[0027] Figure 2 is a structural diagram of the low radio frequency loss gallium nitride on silicon high electron mobility transistor of the present invention;

[0028] Figure 3 is a schematic flow chart of manufacturing the low radio frequency loss gallium nitride on silicon high electron mobility transistor of the present invention. Detailed Description of the Invention

[0029] Referring to Figure 2 The low radio frequency loss gallium nitride on silicon high electron mobility transistor of the present invention includes a substrate 1, a radio frequency loss suppression layer 2, a channel layer 3, an AlN insertion layer 4, and a barrier layer 5, wherein:

[0030] The substrate 1 is made of silicon material, and a radio frequency loss suppression layer 2 is provided between the substrate 1 and the channel layer 3 to solve the problems of back-melting etching of Al atoms on the surface of the silicon substrate and leakage current at the heteroepitaxial interface when the AlN nucleation layer is heteroepitaxially grown on the gallium nitride material on the silicon substrate at high temperature by MOCVD;

[0031] The radio frequency loss suppression layer 2 is located above the substrate 1 and is composed of a composite laminated structure of AlN and transition metal nitrides Sc w Y x Al y N, with a total thickness of 50 nm - 900 nm; the thickness of the AlN layer in a single laminate is 0.5 nm - 5 nm, and the thickness of the Sc w Y x Al y N layer is 0.5 nm - 10 nm, and the composition within each layer remains unchanged. The composition between different layers gradually changes from AlN to a composition matching the in-plane lattice constant of the channel layer along the growth direction, and the composition should satisfy 0 ≤ w ≤ 0.35, 0 ≤ x ≤ 0.25, 0 < y < 1, and w + x + y = 1;

[0032] The channel layer 3 is located above the radio frequency loss suppression layer 2 and is made of GaN, InGaN or AlGaN, with a thickness of 10 nm - 2000 nm;

[0033] The AlN insertion layer 4 is located above the channel layer 3 and has a thickness of 1nm-2nm;

[0034] The barrier layer 5 is located above the AlN insertion layer 4, and it is made of any one of AlGaN, InAlN, AlN, InAlGaN, ScAlN, YAlN, BAlN, AlPN, and BPN, with a thickness of 3nm-30nm; the two sides of the barrier layer are the source electrode and the drain electrode.

[0035] The insulating gate dielectric layer 6 is located above the barrier layer 5. It is made of Al2O3, HfO2 or HfAlO dielectric layer and has a thickness of 5nm-20nm. A gate electrode is provided on the upper part of the insulating gate dielectric layer.

[0036] Reference Figure 3 This invention fabricates low-RF-loss silicon-based gallium nitride high-electron-mobility transistors, and provides the following three embodiments.

[0037] Example 1: The RF loss suppression layer is fabricated using an AlN and ScAlN composite stacked structure, the channel layer is GaN, and the barrier layer is Al. 0.25 Ga 0.75 Low-RF-loss GaN-based high-electron-mobility silicon transistors.

[0038] Step 1: Deposit an AlN / ScAlN composite stacked structure RF loss suppression layer, such as... Figure 3 (a).

[0039] A radio frequency loss suppression layer of AlN and ScAlN composite stack structure with a total thickness of 50 nm and a period of 50 was epitaxially plotted on a silicon substrate using molecular beam epitaxy. The AlN layer thickness and ScAlN layer thickness were both 0.5 nm in each period. The epitaxial process conditions were: temperature 550 °C, nitrogen flow rate 0.6 sccm, and aluminum beam equilibrium vapor pressure 0.6 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the scandium beam is 0.9 × 10⁻⁶. -8 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0040] Step 2, deposit the GaN channel layer, such as Figure 3 (b)

[0041] A 2000 nm thick GaN channel layer was deposited on the RF loss suppression layer using metal-organic chemical vapor deposition (MOCVD). The deposition process conditions were: temperature 1200 °C, pressure 40 Torr, ammonia flow rate 3500 sccm, hydrogen flow rate 3000 sccm, and gallium source flow rate 200 sccm.

[0042] Step 3: Deposit the AlN insertion layer, such as... Figure 3 (c)

[0043] A 1 nm thick AlN insertion layer was deposited on the GaN channel layer using metal-organic chemical vapor deposition (MOCVD). The deposition process conditions were: temperature 1200 °C, pressure 40 Torr, ammonia flow rate 3500 sccm, hydrogen flow rate 3000 sccm, and aluminum source flow rate 4 sccm.

[0044] Step 4, Al deposition 0.25 Ga 0.75 N-barrier layer, such as Figure 3 (d)

[0045] A 30 nm thick Al layer was deposited on the AlN insertion layer using metal-organic chemical vapor deposition (MOCVD). 0.25 Ga 0.75 N-barrier layer; deposition process conditions are: temperature 1200℃, pressure 40 Torr, ammonia flow rate 3500 sccm, hydrogen flow rate 3000 sccm, gallium source flow rate 200 sccm, and aluminum source flow rate 4 sccm.

[0046] Step 5: Dry etching to form grooves in the source and drain electrode regions, such as... Figure 3 (e).

[0047] In Al 0.25 Ga 0.75 A mask is fabricated on the N-barrier layer, and Al in the source and drain electrode regions is removed using dry etching. 0.25 Ga 0.75 An N-type barrier layer, an AlN insertion layer, and a partial GaN channel layer are used to form the source and drain electrode region grooves. The etching process conditions are: Cl2 flow rate of 15 sccm, reaction chamber pressure of 11 mTorr, and electrode power of 180 W.

[0048] Step six: Fabricate the source and drain electrodes, such as... Figure 3 (f).

[0049] Electron beam evaporation was used to deposit Ti / Al / Ni / Au metal composites with thicknesses of 0.02 μm / 0.05 μm / 0.04 μm / 0.04 μm on the grooves in the source and drain electrode regions to form the source and drain electrodes. The process conditions for electron beam evaporation were: vacuum degree less than 1.2 × 10⁻⁶. -3 Pa, power is 400W, evaporation rate is

[0050] Step 7: Deposit an Al2O3 insulating gate dielectric layer, such as... Figure 3 (g)

[0051] Atomic layer deposition process is used in Al 0.25 Ga 0.75 An Al2O3 insulating gate dielectric layer with a thickness of 20 nm is deposited in the region between the source and drain electrodes above the N-barrier layer. The process conditions for atomic layer deposition are: pressure of 2000 mTorr, temperature of 300℃, Al(CH3)3 flow rate of 850 sccm, H2O flow rate of 350 sccm, and N2 flow rate of 1000 sccm.

[0052] Step 8: Fabricate the gate electrode, such as... Figure 3 (h).

[0053] The gate electrode pattern was defined on the Al2O3 insulating gate dielectric layer using photolithography. Then, a Ni / Au metal composite with a thickness of 0.02 μm / 0.3 μm was deposited on the Al2O3 insulating gate dielectric layer using electron beam evaporation to form the gate electrode, thus completing the device fabrication. The electron beam evaporation process conditions were: vacuum degree less than 1.2 × 10⁻⁶. -3 Pa, power is 400W, evaporation rate is

[0054] Example 2: The RF loss suppression layer is fabricated using an AlN / YAlN composite stacked structure, and the channel layer is made of In. 0.1 Ga 0.9 N, the barrier layer uses In 0.17 Al 0.83 Low-RF-loss GaN-based high-electron-mobility silicon transistors.

[0055] Step 1: Epitaxially grow an AlN / YAlN composite stacked structure RF loss suppression layer using molecular beam epitaxy, such as... Figure 3 (a).

[0056] The set temperature is 750℃, the nitrogen flow rate is 3.0 sccm, and the aluminum beam equilibrium vapor pressure is 3.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the yttrium beam is 1.8 × 10⁻⁶. -8 Torr, with a nitrogen RF source power of 380W, is used to epitaxially construct an AlN and YAlN composite stacked structure RF loss suppression layer on a silicon substrate with an epitaxial period of 60 and a total thickness of 900nm. In each period, the AlN layer is 5nm thick and the YAlN layer is 10nm thick.

[0057] Step 2: Deposit In using organometallic chemical vapor deposition (MOCVD). 0.1 Ga 0.9 N-channel layer, such as Figure 3 (b)

[0058] Under the following process conditions: temperature 700℃, pressure 200 Torr, ammonia flow rate 3500 sccm, nitrogen flow rate 3000 sccm, gallium source flow rate 60 sccm, and indium source flow rate 120 sccm, a 10 nm thick In layer is deposited on the RF loss suppression layer. 0.1 Ga 0.9 N-channel layer.

[0059] Step 3: Deposit the AlN insertion layer using metal-organic chemical vapor deposition (MOCVD), such as... Figure 3 (c)

[0060] The process conditions are set as follows: temperature 700℃, pressure 200 Torr, ammonia flow rate 3500 sccm, nitrogen flow rate 3000 sccm, and aluminum source flow rate 10 sccm. (In...) 0.1 Ga 0.9 An AlN insertion layer with a thickness of 1.5 nm is deposited on the N-channel layer.

[0061] Step 4: Deposit In using organometallic chemical vapor deposition (MOCVD). 0.17 Al 0.83 N-barrier layer, such as Figure 3 (d)

[0062] Under the following process conditions: temperature 700℃, pressure 200 Torr, ammonia flow rate 3500 sccm, nitrogen flow rate 3000 sccm, aluminum source flow rate 10 sccm, and indium source flow rate 120 sccm, a 12 nm In layer was deposited on the AlN insertion layer. 0.17 Al 0.83 N-barrier layer.

[0063] Step 5: Use dry etching technology to form grooves in the source and drain electrode regions, such as... Figure 3 (e).

[0064] In 0.17 Al 0.83 A mask was fabricated on the N-barrier layer, and process conditions were set as follows: Cl2 flow rate of 20 sccm, reaction chamber pressure of 15 mTorr, and electrode power of 220 W. In was removed from the source and drain electrode regions respectively. 0.17 Al 0.83 N-barrier layer, AlN insertion layer and part of In 0.1 Ga 0.9 The N-channel layer forms grooves in the source and drain electrode regions.

[0065] Step 6: Fabricate the source and drain electrodes using electron beam evaporation technology, such as... Figure 3 (f).

[0066] Set the vacuum level to less than 1.2 × 10⁻⁶.-3 Pa, power is 600W, evaporation rate is Under the specified process conditions, a Ti / Al / Ni / Au metal combination with a thickness of 0.05μm / 0.12μm / 0.08μm / 0.08μm is deposited on the grooves in the source and drain electrode regions to form the source and drain electrodes.

[0067] Step 7: Deposit the HfO2 insulating gate dielectric layer using atomic layer deposition (ALD) technology, such as... Figure 3 (g)

[0068] The process conditions are set as follows: temperature 280℃, ethyl methylamino hafnium flow rate 1200 sccm, H2O flow rate 110 sccm, and N2 flow rate 1000 sccm. In In 0.17 Al 0.83 A 5 nm thick HfO2 insulating gate dielectric layer is deposited in the region between the source and drain electrodes above the N-barrier layer.

[0069] Step 8: Fabricate the gate electrode using electron beam evaporation technology, such as... Figure 3 (h).

[0070] A mask is fabricated on the HfO2 insulating gate dielectric layer, with a vacuum level of less than 1.2 × 10⁻⁶. -3 Pa, power is 600W, evaporation rate is Under the specified process conditions, a Ni / Au metal combination with a thickness of 0.04μm / 0.5μm was deposited on the HfO2 insulating gate dielectric layer to form the gate, thus completing the device fabrication.

[0071] Example 3: The RF loss suppression layer is fabricated using an AlN and ScYAlN composite stacked structure, and the channel layer uses Al... 0.1 Ga 0.9 N, the barrier layer uses Sc 0.18 Al 0.82 Low-RF-loss GaN-based high-electron-mobility silicon transistors.

[0072] Step A: Deposit an RF loss suppression layer of an AlN / ScYAlN composite stack, such as... Figure 3 (a).

[0073] Using molecular beam epitaxy (MBE), at a temperature of 650℃, a nitrogen flow rate of 1.8 sccm, and an aluminum beam equilibrium vapor pressure of 2.1 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the yttrium beam is 0.6 × 10⁻⁶. -8 Torr, the equilibrium vapor pressure of the scandium beam is 2.5 × 10⁻⁶. -8Torr, under the process conditions of nitrogen RF source power of 380W, an AlN and ScYAlN composite stacked structure RF loss suppression layer with an epitaxial period of 80 and a total thickness of 720nm is formed on a silicon substrate, wherein the AlN layer thickness is 2.5nm and the ScYAlN layer thickness is 6.5nm in each period.

[0074] Step B, Al deposition 0.1 Ga 0.9 N-channel layer, such as Figure 3 (b)

[0075] Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 1100℃, pressure 60 Torr, ammonia flow rate 3500 sccm, hydrogen flow rate 3000 sccm, gallium source flow rate 100 sccm, and aluminum source flow rate 20 sccm, a 100 nm thick Al2O3 layer was deposited on the AlN / ScYAlN composite stacked RF loss suppression layer. 0.1 Ga 0.9 N-channel layer.

[0076] Step C, deposit the AlN insertion layer, as follows: Figure 3 (c)

[0077] Using metal-organic chemical vapor deposition (MOCVD), under process conditions of 1100℃, 60 Torr, ammonia flow rate of 3500 sccm, hydrogen flow rate of 3000 sccm, and aluminum source flow rate of 20 sccm, Al... 0.1 Ga 0.9 A 2 nm AlN insertion layer is deposited on the N-channel layer.

[0078] Step D, Deposition of Sc 0.18 Al 0.82 N-barrier layer, such as Figure 3 (d)

[0079] Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 1100℃, pressure 100 Torr, ammonia flow rate 3500 sccm, hydrogen flow rate 3000 sccm, aluminum source flow rate 20 sccm, and scandium source flow rate 2000 sccm, a 3 nm Scandium layer was deposited on the AlN insertion layer. 0.18 Al 0.82 N-barrier layer.

[0080] Step E: Dry etching to form grooves in the source and drain electrode regions, such as... Figure 3 (e).

[0081] In Sc 0.18 Al 0.82A mask was fabricated on the N-barrier layer, and dry etching was used to remove Sc from the source and drain electrode regions under the following process conditions: Cl2 flow rate of 18 sccm, reaction chamber pressure of 12 mTorr, and electrode power of 160 W. 0.18 Al 0.82 N-barrier layer, AlN insertion layer and part of Al 0.1 Ga 0.9 The N-channel layer forms grooves in the source and drain electrode regions.

[0082] Step F: Fabricate the source and drain electrodes, as follows Figure 3 (f).

[0083] Electron beam evaporation was used at a vacuum level of less than 1.2 × 10⁻⁶. -3 Pa, power 500W, evaporation rate 2 Under the specified process conditions, a Ti / Al / Ni / Au metal combination with a thickness of 0.02μm / 0.2μm / 0.05μm / 0.05μm is deposited on the grooves in the source and drain electrode regions to form the source and drain electrodes.

[0084] Step G: Deposit the HfAlO insulating gate dielectric layer, such as... Figure 3 (g)

[0085] Using atomic layer deposition (ALD), under the following process conditions: temperature 300℃, ethyl methylamino hafnium flow rate 700 sccm, Al(CH3)3 flow rate 650 sccm, H2O flow rate 250 sccm, and N2 flow rate 1000 sccm, at Sc 0.18 Al 0.82 A 10 nm thick HfAlO insulating gate dielectric layer is deposited on the N barrier layer.

[0086] Step H, fabricate the gate electrode, as follows: Figure 3 (h).

[0087] A mask was fabricated on an HfAlO insulating gate dielectric layer, and electron beam evaporation was used at a vacuum level of less than 1.2 × 10⁻⁶. - 3 Pa, power is 500W, evaporation rate is Under the specified process conditions, a Ni / Au metal combination with a thickness of 0.03μm / 0.4μm was deposited on the HfAlO insulating gate dielectric layer to fabricate the gate and complete the device fabrication.

[0088] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. For example, in addition to using the materials mentioned in the above embodiments, the barrier layer may use any one of AlN, InAlGaN, YAlN, BAlN, AlPN, and BPN. However, these modifications and changes based on the concept of the present invention are still within the scope of the claims of the present invention.

Claims

1. A low radio frequency loss silicon-based gallium nitride high electron mobility transistor, from bottom to top, comprising a substrate (1), a channel layer (3), an AlN insertion layer (4), and a barrier layer (5), characterized in that: the substrate (1) is made of silicon material, and a radio frequency loss suppression layer (2) is provided between the substrate (1) and the channel layer (3); the channel layer (3) is made of GaN, or InGaN, or AlGaN; the upper part of the barrier layer (5) is provided with an insulating gate dielectric layer (6) and a gate electrode in sequence, and the two sides are source and drain electrodes; a radio frequency loss suppression layer is provided between the silicon substrate and the channel layer, which also serves as a nucleation layer for heteroepitaxy of silicon-based gallium nitride material, thereby avoiding the remelting etching of Al atoms on the surface of the silicon substrate caused by high-temperature growth of the AlN nucleation layer by MOCVD, inhibiting the formation of a leakage channel at the heteroepitaxy interface and the radio frequency power loss of the device, and playing a role of back barrier to improve the confinement and transport properties of the two-dimensional electron gas in the channel layer of the active region of the gallium nitride device, while inhibiting vertical leakage and improving the voltage withstand capability of the device. The thickness of the channel layer (3) is 10 nm-2000 nm. The radio frequency loss suppression layer (2) is composed of a composite laminated structure of AlN and transition metal nitride Sc w Y x Al y N, the thickness of the AlN layer in a single layer is 0.5 nm-5 nm, the thickness of the Sc w Y x Al y N layer is 0.5 nm-10 nm, and the total thickness is 50 nm-900 nm; the component in each layer of the transition metal nitride Sc w Y x Al y N layer remains unchanged, the component between different layers gradually changes from AlN to a component matching the lattice constant in the channel layer along the growth direction, the component in each layer is 0≤w≤0.35, 0≤x≤0.25, 0<y<1, and w+x+y=1; The thickness of the AlN insertion layer (4) is 1 nm-2 nm. The barrier layer (5) is made of any one of AlGaN, InAlN, AlN, InAlGaN, ScAlN, YAlN, BAlN, AlPN, and BPN, and the thickness is 3 nm-30 nm. The insulating gate dielectric layer (6) is made of Al2O3, or HfO2, or HfAlO dielectric layer, and the thickness is 5 nm-20 nm.

2. The transistor of claim 1, wherein: The method comprises the following steps:

3. The transistor of claim 1, wherein: 1) A radio frequency loss suppression layer (2) with a thickness of 50 nm-900 nm is grown on the substrate wafer (1) by molecular beam epitaxy; 4. The transistor of claim 1, wherein: 2) A channel layer (3) with a thickness of 10 nm-2000 nm is grown on the radio frequency loss suppression layer (2) by metal organic chemical vapor deposition; 5. The transistor of claim 1, wherein: 3) An AlN insertion layer (4) with a thickness of 1 nm-2 nm is grown on the channel layer (3) by metal organic chemical vapor deposition; 6. The method of fabricating a low radio frequency loss silicon-based gallium nitride high electron mobility transistor as defined in claim 1, wherein, 4) A barrier layer (5) with a thickness of 3 nm-30 nm is grown on the AlN insertion layer (4) by metal organic chemical vapor deposition; 5) The barrier layer is etched to the surface of the channel layer to form source and drain electrode recesses by dry etching with photoresist as a mask; 6) Ti / Al / Ni / Au metal combination is deposited in the source and drain electrode recesses by electron beam evaporation process, and source and drain electrodes are formed by annealing at 830 ℃ in a nitrogen atmosphere; 7) An insulating gate dielectric layer (6) with a thickness of 5 nm-20 nm is grown between the source and drain electrodes on the barrier layer (5) by atomic layer deposition; 8) The gate electrode pattern is defined on the surface of the insulating gate dielectric layer (6) by photolithography, and the gate electrode is formed by depositing Ni / Au metal combination on the insulating gate dielectric layer (6) by electron beam evaporation process, thereby completing the device fabrication. ​ ​ ​ ​ 7. The method of claim 6, wherein: The molecular beam epitaxy method in the step 1) has the following process conditions: temperature is 550 o C-750 o C; The nitrogen flow rate is 0.6 sccm-3.0 sccm; The aluminum beam was balanced at a vapor pressure of 0.6 x 10 -7 Torr-3.2 x 10 -7 Torr; The scandium beam current is balanced at a vapor pressure of 0.9 x 10 -8 Torr-2.5 x 10 -8 Torr; The yttrium beam current is balanced at a vapor pressure of 0.6 x 10 -8 Torr-1.8 x 10 -8 Torr; The nitrogen radio frequency source power is 380 W.

8. The method of claim 6, wherein: The metal organic chemical vapor deposition method in the step 2) has the following process conditions: The temperature is 700 ℃-1200 ℃; The pressure is 40 Torr-200 Torr; The ammonia flow rate is 3500 sccm; The hydrogen flow rate is 3000 sccm; The nitrogen flow rate is 3000 sccm; The aluminum source flow rate is 4 sccm-20 sccm; The gallium source flow rate is 60 sccm-200 sccm; The indium source flow rate is 50 sccm-120 sccm.

9. The method of claim 6, wherein: The metal organic chemical vapor deposition method in the step 3) has the following process conditions: The temperature is 700 ℃-1200 ℃; The pressure is 40 Torr-200 Torr; The ammonia flow rate is 3500 sccm; The hydrogen flow rate is 3000 sccm; The nitrogen flow rate is 3000 sccm; The aluminum source flow rate is 4 sccm-20 sccm.

10. The method of claim 6, wherein: The metal organic chemical vapor deposition method in the step 4) has the following process conditions: The temperature is 700 ℃-1200 ℃; The pressure is 40 Torr-200 Torr; The ammonia flow rate is 3500 sccm; The hydrogen flow rate is 3000 sccm; The nitrogen flow rate is 3000 sccm; The aluminum source flow rate is 4 sccm-20 sccm; The gallium source flow rate is 60 sccm-200 sccm; The indium source flow rate is 50 sccm-120 sccm; The scandium source flow rate is 2000 sccm-5000 sccm; The yttrium source flow rate is 1000 sccm-3000 sccm; The boron source flow rate is 10 mol / min-30 μmol / min; The phosphorus source flow rate is 20 μmol / min-50 μmol / min.

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