Light emitting diode and method of manufacturing the same

Abstract

The application discloses a light emitting diode and a preparation method thereof. A substrate is provided, and a buffer layer, a U-GaN layer and a first N-GaN layer are sequentially grown on the substrate; a silicon dioxide protective layer or a silicon nitride protective layer is grown on the first N-GaN layer; a second N-GaN layer, a multi-quantum well layer, a P-type Al y Ga 1‑y N electron blocking layer, a P-type gallium nitride layer and a P-type contact layer are sequentially grown on the silicon dioxide protective layer or the silicon nitride protective layer to form an epitaxial structure; a "concave" electrode is formed on the epitaxial structure to obtain the light emitting diode; the light emitting diode electrode is arranged on one side of the "concave" epitaxial structure with a concave-convex surface; the "concave" epitaxial structure comprises the substrate and the silicon dioxide protective layer or the silicon nitride protective layer, and the silicon dioxide protective layer or the silicon nitride protective layer is arranged on one side of the substrate, so that the charge distribution can be balanced, the concentration of charges at local positions of a chip structure can be reduced, the effective driving of holes can be provided, the hole injection can be improved, and the quantum efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a light emitting diode and a preparation method thereof. BACKGROUND

[0002] At present, gallium nitride-based LED (light emitting diode) is paid more and more attention and researched, and the epitaxial structure thereof is mainly composed of a sapphire substrate, a gallium nitride or aluminum-doped gallium nitride buffer layer, an undoped GaN (gallium nitride) layer, an N-type doped layer, a current spreading layer, an MQW (multi-quantum well) active region, a P-type AlGaN (aluminum gallium nitride) layer and a P-type layer. When current passes through, the electrons in the N-type region and the holes in the P-type region enter the MQW active region and recombine to emit visible light of a required waveband.

[0003] The P-type gallium nitride usually adopts Mg (magnesium) as a dopant, but Mg is easily bonded with H (hydrogen) and needs a higher activation energy, and only about 1% of the doped Mg is effectively activated. With the increase of the used current, especially in high-power density applications, the injection of holes is insufficient, and the effective mass of the holes is large and difficult to move, so that the limitation of the holes becomes a major influencing factor for the improvement of quantum efficiency. SUMMARY

[0004] The present application aims at providing a light emitting diode and a preparation method thereof, which can improve the injection of holes and improve the quantum efficiency.

[0005] To solve the above technical problems, one technical solution adopted by the present application is as follows:

[0006] A light emitting diode preparation method, comprising the steps of:

[0007] providing a substrate, growing a buffer layer, a U-GaN layer and a first N-GaN layer on the substrate in sequence;

[0008] growing a silicon dioxide protective layer or a silicon nitride protective layer on the first N-GaN layer;

[0009] growing a second N-GaN layer, a multi-quantum well layer, a P-type Al y Ga 1-y N electron blocking layer, a P-type gallium nitride layer and a P-type contact layer on the silicon dioxide protective layer or the silicon nitride protective layer in sequence to form an epitaxial structure;

[0010] forming a "concave" electrode on the epitaxial structure to obtain a light emitting diode.

[0011] To solve the above technical problems, another technical solution adopted by the present application is as follows:

[0012] A light emitting diode, comprising a "concave" epitaxial structure and an electrode.

[0013] The electrode is arranged on the side of the "concave" type epitaxial structure with concave and convex surfaces.

[0014] The "concave" type epitaxial structure comprises a substrate and a silicon dioxide protective layer or a silicon nitride protective layer arranged on one side of the substrate.

[0015] The present application has the beneficial effect that a silicon dioxide protective layer or a silicon nitride protective layer is grown on the N-GaN layer, and a "concave" type electrode is formed on the epitaxial structure to obtain a light emitting diode. The silicon dioxide protective layer or the silicon nitride protective layer can balance the charge distribution and reduce the concentration of charges at local positions of the chip structure. The "concave" type electrode layout can provide effective driving of holes, thereby improving hole injection and enhancing quantum efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A step flow chart of a light emitting diode preparation method according to an embodiment of the present application;

[0017] Figure 2 A schematic diagram of an epitaxial structure in a light emitting diode preparation method according to an embodiment of the present application;

[0018] Figure 3 A schematic diagram of the overall structure of a light emitting diode according to an embodiment of the present application;

[0019] REFERENCE NUMERALS:

[0020] 1, "concave" type epitaxial structure; 11, substrate; 12, silicon dioxide protective layer or silicon nitride protective layer; 13, buffer layer; 14, U-GaN layer; 15, first N-GaN layer; 16, second N-GaN layer; 17, multi-quantum well layer; 18, P-type AlyGa1-yN electron blocking layer; 19, P-type gallium nitride layer; 110, P-type contact layer; 2, electrode; 21, anode; 22, cathode; 3, fluorescent powder. DETAILED DESCRIPTION

[0021] To explain the technical content, purposes and effects of the present application in detail, the following embodiments are described with reference to the accompanying drawings.

[0022] Please refer to Figure 1 The present application provides a light emitting diode preparation method, comprising the steps of:

[0023] A substrate is provided, and a buffer layer, a U-GaN layer and a first N-GaN layer are sequentially grown on the substrate;

[0024] A silicon dioxide protective layer or a silicon nitride protective layer is grown on the first N-GaN layer.

[0025] A second N-GaN layer, a multi-quantum well layer, a P-type Al y Ga 1-y N electron barrier layer, a P-type gallium nitride layer and a P-type contact layer are sequentially grown on the silicon dioxide protective layer or the silicon nitride protective layer, so as to form an epitaxial structure.

[0026] A "concave" electrode is formed on the epitaxial structure, so as to obtain a light emitting diode.

[0027] As can be seen from the above description, the present application has the advantages that: the silicon dioxide protective layer or the silicon nitride protective layer is grown on the N-GaN layer, and the "concave" electrode is formed on the epitaxial structure, so as to obtain a light emitting diode, the silicon dioxide protective layer or the silicon nitride protective layer can balance the charge distribution and reduce the concentration of the charge at the local position of the chip structure, the "concave" electrode layout can provide effective driving of the holes, so as to improve the hole injection and enhance the quantum efficiency.

[0028] Further, the growing of the silicon dioxide protective layer or the silicon nitride protective layer on the first N-GaN layer comprises:

[0029] The 20-150 nm silicon dioxide protective layer or the silicon nitride protective layer is grown on the first N-GaN layer under the pressure of 100-500 Torr and the growth temperature of 800-1100 ℃.

[0030] As can be seen from the above description, the silicon dioxide protective layer or the silicon nitride protective layer formed in this way can regulate the current distribution and prevent the concentration of the charge at the local sharp corner position, so as to improve the hole injection and enhance the quantum efficiency.

[0031] Further, the providing of a substrate and the sequentially growing of a buffer layer, a U-GaN layer and a first N-GaN layer on the substrate comprises:

[0032] The substrate is provided, and the substrate is annealed in a hydrogen atmosphere under the temperature of 1000-1200 ℃ for 8 minutes, so as to obtain an annealed substrate.

[0033] The annealed substrate is subjected to nitriding treatment, so as to obtain a treated substrate.

[0034] The buffer layer, the U-GaN layer and the first N-GaN layer are sequentially grown on the treated substrate.

[0035] As can be seen from the above description, the annealing and the nitriding treatment of the substrate can clean the surface of the substrate and increase the hardness of the surface of the substrate, so as to ensure the reliability and stability of the subsequent growth of each layer.

[0036] Further, the growing the buffer layer, the U-GaN layer and the first N-GaN layer on the processed substrate in sequence comprises:

[0037] growing a 15-35 nm gallium nitride nucleation layer on the processed substrate at a temperature of 400-600 °C and a pressure of 400-600 Torr;

[0038] annealing the gallium nitride nucleation layer in situ at a temperature of 1000-1200 °C, a pressure of 400-600 Torr and a time of 5-10 min to form a buffer layer;

[0039] growing a 1-5 μm U-GaN layer on the buffer layer at a temperature of 1000-1100 °C and a pressure of 100-500 Torr;

[0040] growing a 1-5 μm first N-GaN layer on the U-GaN layer at a temperature of 1000-1200 °C, a pressure of 100-500 Torr and a time of 10 18 -10 19 cm -3 silicon doping concentration.

[0041] It can be seen from the above description that the buffer layer, the U-GaN layer and the first N-GaN layer are grown in sequence to ensure the basic working performance of the light emitting diode.

[0042] Further, the growing the second N-GaN layer, the multi-quantum well layer, the P-type Al y Ga 1-y N electron barrier layer, the P-type gallium nitride layer and the P-type contact layer on the silicon dioxide protective layer or the silicon nitride protective layer in sequence to form an epitaxial structure comprises:

[0043] growing a 500-1500 nm second N-GaN layer on the silicon dioxide protective layer or the silicon nitride protective layer at a temperature of 1000-1200 °C, a pressure of 100-500 Torr and a time of 10 18 -10 19 cm -3 silicon doping concentration;

[0044] growing a well region of the multi-quantum well layer on the second N-GaN layer at a temperature of 720-829 °C and a pressure of 100-500 Torr, and growing a barrier region of the multi-quantum well layer at a temperature of 850-959 °C and a pressure of 100-500 Torr to form the multi-quantum well layer;

[0045] growing a 50-150 nm P-type Al yGa 1-y N electron barrier layer;

[0046] A P-type Al y Ga 1-y N electron barrier layer is grown at a temperature of 850-1080℃ and a pressure of 100-300Torr;

[0047] A P-type contact layer of 5-300nm is grown on the P-type gallium nitride layer at a temperature of 850-1050℃ and a pressure of 100-300Torr, forming an initial epitaxial structure;

[0048] The initial epitaxial structure is annealed at an annealing temperature of 650-850℃ for 5-15min in a nitrogen atmosphere, and after the annealing, the temperature is lowered to room temperature, forming an epitaxial structure.

[0049] As can be seen from the above description, the epitaxial structure formed is more stable, which can ensure the working performance of the light emitting diode.

[0050] Further, the "concave" electrode formed on the epitaxial structure to obtain a light emitting diode comprises:

[0051] The epitaxial structure is etched to form a "concave" epitaxial structure;

[0052] A positive electrode is formed on the convex part of the "concave" epitaxial structure, and a negative electrode is formed on the concave part of the "concave" epitaxial structure;

[0053] The negative electrode is filled with fluorescent powder to obtain a light emitting diode.

[0054] As can be seen from the above description, the double positive electrode structure provides effective driving of holes, improves hole injection, and improves quantum efficiency. At the same time, filling the fluorescent powder on the negative electrode reduces the distance between the conventional photons and the fluorescent powder, which adversely affects the excitation efficiency, facilitates the design of the subsequent packaging geometry, and improves the light emitting effect of the light emitting diode.

[0055] Please refer to Figure 3 A light emitting diode comprises a "concave" epitaxial structure and an electrode;

[0056] The electrode is arranged on one side of the "concave" epitaxial structure having a concave-convex surface;

[0057] The "concave" epitaxial structure comprises a substrate and a silicon dioxide protective layer or a silicon nitride protective layer, and the silicon dioxide protective layer or the silicon nitride protective layer is arranged on one side of the substrate.

[0058] From the above description, the beneficial effects of the present application are that the silicon dioxide protective layer or silicon nitride protective layer can balance the charge distribution, reduce the concentration of the local position charge of the chip structure, the electrode is arranged on one side of the "concave" type epitaxial structure, the "concave" type electrode layout is realized, the effective driving of holes can be provided, the hole injection is improved, and the quantum efficiency is improved.

[0059] Further, the electrode comprises an anode and a cathode.

[0060] The anode is arranged on the protruding part of the one side of the "concave" type epitaxial structure, and the cathode is arranged on the recessed part of the one side of the "concave" type epitaxial structure.

[0061] From the above description, the double-anode structure provides effective driving of holes, improves hole injection, and improves quantum efficiency.

[0062] Further, the "concave" type epitaxial structure further comprises a buffer layer, a U-GaN layer, a first N-GaN layer, a second N-GaN layer, a multi-quantum well layer, a P-type AlyGa1-yN electron blocking layer, a P-type gallium nitride layer and a P-type contact layer.

[0063] The one side of the substrate is sequentially provided with the buffer layer, the U-GaN layer and the first N-GaN layer arranged in layers, and the silicon dioxide protective layer or the silicon nitride protective layer is arranged on the side of the first N-GaN layer away from the U-GaN layer.

[0064] The side of the silicon dioxide protective layer or the silicon nitride protective layer away from the first N-GaN layer is sequentially provided with the second N-GaN layer, the multi-quantum well layer, the P-type AlyGa1-yN electron blocking layer, the P-type gallium nitride layer and the P-type contact layer arranged in layers.

[0065] From the above description, the epitaxial structure is more stable, and the working performance of the light emitting diode can be ensured.

[0066] Further, it further comprises fluorescent powder.

[0067] The side of the cathode away from the "concave" type epitaxial structure is provided with the fluorescent powder.

[0068] From the above description, the distance between the conventional photons and the fluorescent powder is reduced, the adverse effects on the excitation efficiency are reduced, the subsequent packaging geometry design is facilitated, and the light emitting effect of the light emitting diode is improved.

[0069] The above-mentioned light emitting diode and the preparation method thereof can be applied to the preparation of light emitting diodes with high current density requirements, and the following specific embodiments are described:

[0070] Embodiment One

[0071] Please refer to Figure 1 and Figure 2 The embodiment of the application provides a light emitting diode preparation method, which comprises the following steps:

[0072] S1, providing a substrate, growing a buffer layer, a U-GaN layer and a first N-GaN layer on the substrate in sequence, specifically comprising the following steps:

[0073] S11, providing a substrate, annealing the substrate in a hydrogen atmosphere at a temperature of 1000-1200 DEG C for 8 minutes to obtain an annealed substrate;

[0074] The substrate is a sapphire substrate, a single crystal substrate or a multifunctional composite engineering substrate, and the single crystal substrate comprises SiC (silicon carbide), GaN (gallium nitride), AlN (diamond nitride), GaAs (gallium arsenide) or InP (indium phosphide) and diamond.

[0075] In an alternative embodiment, a substrate is provided, and the substrate is annealed in a hydrogen atmosphere at a temperature of 1000 DEG C for 8 minutes to obtain an annealed substrate.

[0076] In another alternative embodiment, a substrate is provided, and the substrate is annealed in a hydrogen atmosphere at a temperature of 1100 DEG C for 8 minutes to obtain an annealed substrate.

[0077] In another alternative embodiment, a substrate is provided, and the substrate is annealed in a hydrogen atmosphere at a temperature of 1200 DEG C for 8 minutes to obtain an annealed substrate.

[0078] S12, performing nitriding treatment on the annealed substrate to obtain a treated substrate;

[0079] S13, growing a buffer layer, a U-GaN layer and a first N-GaN layer on the treated substrate in sequence, specifically comprising the following steps:

[0080] S131, growing a gallium nitride nucleation layer with a thickness of 15-35 nm on the treated substrate at a temperature of 400-600 DEG C and a pressure of 400-600 Torr;

[0081] In an alternative embodiment, a gallium nitride nucleation layer with a thickness of 15 nm is grown on the treated substrate at a temperature of 400 DEG C and a pressure of 400 Torr.

[0082] In another alternative embodiment, a gallium nitride nucleation layer with a thickness of 20 nm is grown on the treated substrate at a temperature of 500 DEG C and a pressure of 500 Torr.

[0083] In another alternative embodiment, a 35 nm gallium nitride nucleation layer is grown on the processed substrate at a temperature of 600 °C and a pressure of 600 Torr.

[0084] S132, in-situ annealing the gallium nitride nucleation layer at a temperature of 1000-1200 °C, a pressure of 400-600 Torr, and a time of 5-10 min to form a buffer layer;

[0085] In one alternative embodiment, the gallium nitride nucleation layer is in-situ annealed at a temperature of 1000 °C, a pressure of 400 Torr, and a time of 5 min to form a buffer layer.

[0086] In another alternative embodiment, the gallium nitride nucleation layer is in-situ annealed at a temperature of 1100 °C, a pressure of 500 Torr, and a time of 7 min to form a buffer layer.

[0087] In another alternative embodiment, the gallium nitride nucleation layer is in-situ annealed at a temperature of 1200 °C, a pressure of 600 Torr, and a time of 10 min to form a buffer layer.

[0088] S133, growing a 1-5 μm U-GaN (U-shaped gallium nitride) layer on the buffer layer at a temperature of 1000-1100 °C and a pressure of 100-500 Torr;

[0089] In one alternative embodiment, a 1 μm U-GaN layer is grown on the buffer layer at a temperature of 1000 °C and a pressure of 100 Torr.

[0090] In another alternative embodiment, a 2.5 μm U-GaN layer is grown on the buffer layer at a temperature of 1050 °C and a pressure of 300 Torr.

[0091] In another alternative embodiment, a 5 μm U-GaN layer is grown on the buffer layer at a temperature of 1100 °C and a pressure of 500 Torr.

[0092] S134, growing a 1-5 μm first N-GaN (N-shaped gallium nitride) layer on the U-GaN layer at a temperature of 1000-1200 °C, a pressure of 100-500 Torr, and a time of 10 18 ~10 19 cm -3

[0093] In one alternative embodiment, a 1 μm first N-GaN layer is grown on the U-GaN layer at a temperature of 1000 °C, a pressure of 100 Torr, and a time of 10 18 ​cm -3 a first N-GaN layer with a silicon doping concentration of 10

[0094] In another alternative embodiment, a first N-GaN layer with a silicon doping concentration of 10 18 cm -3 a first N-GaN layer with a silicon doping concentration of 10

[0095] In another alternative embodiment, a first N-GaN layer with a silicon doping concentration of 10 19 cm -3 a first N-GaN layer with a silicon doping concentration of 10

[0096] The first N-GaN layer is a silicon-doped N-GaN layer.

[0097] S2, growing a silicon dioxide protective layer or a silicon nitride protective layer on the first N-GaN layer;

[0098] Specifically, a silicon dioxide protective layer or a silicon nitride protective layer with a thickness of 20-150 nm is grown on the first N-GaN layer at a pressure of 100-500 Torr and a growth temperature of 800-1100 °C.

[0099] In one alternative embodiment, a silicon dioxide protective layer or a silicon nitride protective layer with a thickness of 20 nm is grown on the first N-GaN layer at a pressure of 100 Torr and a growth temperature of 800 °C.

[0100] In another alternative embodiment, a silicon dioxide protective layer or a silicon nitride protective layer with a thickness of 50 nm is grown on the first N-GaN layer at a pressure of 200 Torr and a growth temperature of 900 °C.

[0101] In another alternative embodiment, a silicon dioxide protective layer or a silicon nitride protective layer with a thickness of 150 nm is grown on the first N-GaN layer at a pressure of 500 Torr and a growth temperature of 1100 °C.

[0102] S3, sequentially growing a second N-GaN layer, a multi-quantum well layer, a P-type Al y Ga 1-y N electron blocking layer, a P-type gallium nitride layer and a P-type contact layer on the silicon dioxide protective layer or the silicon nitride protective layer to form an epitaxial structure, specifically including:

[0103] S31, growing the second N-GaN layer at a temperature of 1000-1200 °C, a pressure of 100-500 Torr and a growth rate of 10 18 -1019 cm -3 of silicon doping concentration, a second N-GaN layer of 500-1500 nm is grown on the silicon dioxide protective layer or silicon nitride protective layer;

[0104] In an alternative embodiment, a temperature of 1000°C, a pressure of 100 Torr and a silicon doping concentration of 10 18 cm -3 of 500 nm is grown on the silicon dioxide protective layer or silicon nitride protective layer.

[0105] In another alternative embodiment, a temperature of 1100°C, a pressure of 300 Torr and a silicon doping concentration of 10 18 cm -3 of 1000 nm is grown on the silicon dioxide protective layer or silicon nitride protective layer.

[0106] In another alternative embodiment, a temperature of 1200°C, a pressure of 500 Torr and a silicon doping concentration of 10 19 cm -3 of 1500 nm is grown on the silicon dioxide protective layer or silicon nitride protective layer.

[0107] S32, a well region of a multi-quantum well layer is grown on the second N-GaN layer at a temperature of 720-829°C and a pressure of 100-500 Torr, and a barrier region of the multi-quantum well layer is grown at a temperature of 850-959°C and a pressure of 100-500 Torr, to form the multi-quantum well layer.

[0108] Specifically, a well region of a multi-quantum well layer with a well thickness of 3 nm is grown on the second N-GaN layer at a temperature of 720-829°C and a pressure of 100-500 Torr, and a barrier region of the multi-quantum well layer with a barrier thickness of 9-20 nm is grown at a temperature of 850-959°C and a pressure of 100-500 Torr, to form the multi-quantum well layer, the multi-quantum well layer being composed of 5 to 15 periods of In x Ga 1-x N and GaN, where 0 < x < 1.

[0109] In an alternative embodiment, a well region of a multi-quantum well layer with a well thickness of 3 nm is grown on the second N-GaN layer at a temperature of 720°C and a pressure of 100 Torr, and a barrier region of the multi-quantum well layer with a barrier thickness of 9 nm is grown at a temperature of 850°C and a pressure of 100 Torr, to form the multi-quantum well layer.

[0110] In another alternative embodiment, a well region of a multiple quantum well layer having a well thickness of 3 nm is grown on the second N-GaN layer at a temperature of 800 °C and a pressure of 300 Torr, and a barrier region of a multiple quantum well layer having a barrier thickness of 15 nm is grown at a temperature of 900 °C and a pressure of 350 Torr, thereby forming the multiple quantum well layer.

[0111] In another alternative embodiment, a well region of a multiple quantum well layer having a well thickness of 3 nm is grown on the second N-GaN layer at a temperature of 829 °C and a pressure of 500 Torr, and a barrier region of a multiple quantum well layer having a barrier thickness of 20 nm is grown at a temperature of 959 °C and a pressure of 500 Torr, thereby forming the multiple quantum well layer.

[0112] S33, growing a P-type Al y Ga 1-y N electron barrier layer having a thickness of 50-150 nm on the multiple quantum well layer at a temperature of 850-1080 °C and a pressure of 200-500 Torr;

[0113] In another alternative embodiment, a P-type Al y Ga 1-y N electron barrier layer having a thickness of 100 nm is grown on the multiple quantum well layer at a temperature of 900 °C and a pressure of 300 Torr.

[0114] In another alternative embodiment, a P-type Al y Ga 1-y N electron barrier layer having a thickness of 150 nm is grown on the multiple quantum well layer at a temperature of 1080 °C and a pressure of 500 Torr.

[0115] In another alternative embodiment, a P-type Al y Ga 1-y N electron barrier layer having a thickness of 150 nm is grown on the multiple quantum well layer at a temperature of 1080 °C and a pressure of 500 Torr.

[0116] S34, growing a P-type gallium nitride layer having a thickness of 100-800 nm on the P-type Al y Ga 1-y N electron barrier layer at a temperature of 850-1080 °C and a pressure of 100-300 Torr;

[0117] In another alternative embodiment, a P-type gallium nitride layer having a thickness of 100 nm is grown on the P-type Al y Ga 1-y N electron barrier layer at a temperature of 850 °C and a pressure of 100 Torr.

[0118] In another alternative embodiment, a 500 nm P-type gallium nitride layer is grown on the P-type Al y Ga 1-y N electron barrier layer at a temperature of 900 °C and a pressure of 200 Torr.

[0119] In another alternative embodiment, a 800 nm P-type gallium nitride layer is grown on the P-type Al y Ga 1-y N electron barrier layer at a temperature of 1080 °C and a pressure of 300 Torr.

[0120] S35, growing a 5-300 nm P-type contact layer on the P-type gallium nitride layer at a temperature of 850-1050 °C and a pressure of 100-300 Torr to form an initial epitaxial structure;

[0121] In an alternative embodiment, a 5 nm P-type contact layer is grown on the P-type gallium nitride layer at a temperature of 850 °C and a pressure of 100 Torr to form an initial epitaxial structure.

[0122] In another alternative embodiment, a 150 nm P-type contact layer is grown on the P-type gallium nitride layer at a temperature of 900 °C and a pressure of 200 Torr to form an initial epitaxial structure.

[0123] In another alternative embodiment, a 300 nm P-type contact layer is grown on the P-type gallium nitride layer at a temperature of 1050 °C and a pressure of 300 Torr to form an initial epitaxial structure.

[0124] S36, annealing the initial epitaxial structure in a nitrogen atmosphere at an annealing temperature of 650-850 °C for 5-15 min, and after the annealing, reducing the temperature to room temperature to form an epitaxial structure.

[0125] In an alternative embodiment, the initial epitaxial structure is annealed in a nitrogen atmosphere at an annealing temperature of 650 °C for 5 min, and after the annealing, reducing the temperature to room temperature to form an epitaxial structure.

[0126] In another alternative embodiment, the initial epitaxial structure is annealed in a nitrogen atmosphere at an annealing temperature of 700 °C for 10 min, and after the annealing, reducing the temperature to room temperature to form an epitaxial structure.

[0127] In another alternative embodiment, the initial epitaxial structure is annealed in a nitrogen atmosphere at an annealing temperature of 850 °C for 15 min, and after the annealing, reducing the temperature to room temperature to form an epitaxial structure.

[0128] S4, forming a "concave" electrode on the epitaxial structure to obtain a light emitting diode, specifically comprising:

[0129] S41, etching the epitaxial structure to form a "concave" epitaxial structure;

[0130] In an alternative embodiment, the epitaxial structure is etched to form a "concave" epitaxial structure with a single size of 50*50 mil or more.

[0131] S42, forming an anode electrode on the convex part of the "concave" epitaxial structure and forming a cathode electrode on the concave part of the "concave" epitaxial structure;

[0132] S43, filling the fluorescent powder on the cathode electrode to obtain a light emitting diode.

[0133] Example two

[0134] Please refer to Figure 3 The light emitting diode of the embodiment comprises a "concave" epitaxial structure 1 and an electrode 2.

[0135] The electrode 2 is arranged on one side of the "concave" epitaxial structure 1 with concave and convex surfaces.

[0136] The "concave" epitaxial structure 1 comprises a substrate 11 and a silicon dioxide protective layer or a silicon nitride protective layer 12, and the silicon dioxide protective layer or the silicon nitride protective layer 12 is arranged on one side of the substrate 11.

[0137] Specifically, the electrode 2 comprises an anode electrode 21 and a cathode electrode 22.

[0138] The anode electrode 21 is arranged on the convex part of the one side of the "concave" epitaxial structure 1, and the cathode electrode 22 is arranged on the concave part of the one side of the "concave" epitaxial structure 1.

[0139] Specifically, the "concave" epitaxial structure 1 further comprises a buffer layer 13, a U-GaN layer 14, a first N-GaN layer 15, a second N-GaN layer 16, a multi-quantum well layer 17, a P-type AlyGa1-yN electron blocking layer 18, a P-type gallium nitride layer 19 and a P-type contact layer 110.

[0140] The one side of the substrate 11 is sequentially provided with the buffer layer 13, the U-GaN layer 14 and the first N-GaN layer 15 arranged in layers, and the silicon dioxide protective layer or the silicon nitride protective layer 12 is arranged on the side of the first N-GaN layer 15 away from the U-GaN layer 14.

[0141] The second N-GaN layer 16, the multi-quantum well layer 17, the P-type AlyGa1-yN electron blocking layer 18, the P-type gallium nitride layer 19 and the P-type contact layer 110 are sequentially arranged on the side of the silicon dioxide protective layer or the silicon nitride protective layer 12 away from the first N-GaN layer 15.

[0142] Specifically, the fluorescent powder 3 is further included.

[0143] The fluorescent powder 3 is arranged on the side of the cathode 22 away from the "concave" epitaxial structure 1.

[0144] In summary, the application provides a light emitting diode and a preparation method thereof. A substrate is provided, and a buffer layer, a U-GaN layer and a first N-GaN layer are sequentially grown on the substrate. A silicon dioxide protective layer or a silicon nitride protective layer is grown on the first N-GaN layer. A second N-GaN layer, a multi-quantum well layer, a P-type AlyGa1-yN electron blocking layer, a P-type gallium nitride layer and a P-type contact layer are sequentially grown on the silicon dioxide protective layer or the silicon nitride protective layer to form an epitaxial structure. A "concave" electrode is formed on the epitaxial structure to obtain a light emitting diode. Specifically, the epitaxial structure is etched to form a "concave" epitaxial structure. An anode is formed on the convex part of the "concave" epitaxial structure, and a cathode is formed on the concave part of the "concave" epitaxial structure. The fluorescent powder is filled on the cathode to obtain a light emitting diode. The double-anode structure provides effective driving of holes, improves hole injection and enhances quantum efficiency. The fluorescent powder filled on the cathode reduces the distance between the conventional photons and the fluorescent powder, which adversely affects the excitation efficiency. The subsequent packaging geometry design is facilitated, the light emitting effect of the light emitting diode is improved, the silicon dioxide protective layer or the silicon nitride protective layer can balance the charge distribution and reduce the concentration of charges in the local position of the chip structure, and the "concave" electrode layout can provide effective driving of holes, thereby improving hole injection and enhancing quantum efficiency. y Ga 1-y N electron blocking layer, a P-type gallium nitride layer and a P-type contact layer are sequentially grown on the silicon dioxide protective layer or the silicon nitride protective layer to form an epitaxial structure. A "concave" electrode is formed on the epitaxial structure to obtain a light emitting diode. Specifically, the epitaxial structure is etched to form a "concave" epitaxial structure. An anode is formed on the convex part of the "concave" epitaxial structure, and a cathode is formed on the concave part of the "concave" epitaxial structure. The fluorescent powder is filled on the cathode to obtain a light emitting diode. The double-anode structure provides effective driving of holes, improves hole injection and enhances quantum efficiency. The fluorescent powder filled on the cathode reduces the distance between the conventional photons and the fluorescent powder, which adversely affects the excitation efficiency. The subsequent packaging geometry design is facilitated, the light emitting effect of the light emitting diode is improved, the silicon dioxide protective layer or the silicon nitride protective layer can balance the charge distribution and reduce the concentration of charges in the local position of the chip structure, and the "concave" electrode layout can provide effective driving of holes, thereby improving hole injection and enhancing quantum efficiency.

[0145] The above description is only an embodiment of the application, and does not limit the patent scope of the application. Any equivalent transformation or direct or indirect application in the related technical field based on the content of the specification and the drawings is also included in the patent protection scope of the application.

Claims

1. A method for fabricating a light-emitting diode, characterized in that, The method comprises the steps of: providing a substrate, and sequentially growing a buffer layer, a U-GaN layer and a first N-GaN layer on the substrate; growing a silicon dioxide protective layer or a silicon nitride protective layer on the first N-GaN layer; A second N-GaN layer, a multi-quantum well layer, a P-type Al y Ga 1-y N electron barrier layer, a P-type gallium nitride layer and a P-type contact layer are sequentially grown on the silicon dioxide protective layer or the silicon nitride protective layer, forming an epitaxial structure; forming a "concave" electrode on the epitaxial structure to obtain a light emitting diode; the step of growing a silicon dioxide protective layer or a silicon nitride protective layer on the first N-GaN layer comprises: growing a 20-150 nm silicon dioxide protective layer or a silicon nitride protective layer on the first N-GaN layer at a pressure of 100-500 Torr and a growth temperature of 800-1100 ℃.

2. The method of claim 1, wherein the substrate is a sapphire substrate. the step of providing a substrate, and sequentially growing a buffer layer, a U-GaN layer and a first N-GaN layer on the substrate comprises: providing a substrate, and annealing the substrate in a hydrogen atmosphere at a temperature of 1000-1200 ℃ for 8 min to obtain an annealed substrate; nitriding the annealed substrate to obtain a treated substrate; sequentially growing a buffer layer, a U-GaN layer and a first N-GaN layer on the treated substrate.

3. The method of claim 2, wherein the substrate is a sapphire substrate. the step of sequentially growing a buffer layer, a U-GaN layer and a first N-GaN layer on the treated substrate comprises: growing a 15-35 nm gallium nitride nucleation layer on the treated substrate at a temperature of 400-600 ℃ and a pressure of 400-600 Torr; in-situ annealing the gallium nitride nucleation layer at a temperature of 1000-1200 ℃, a pressure of 400-600 Torr and a time of 5-10 min to form a buffer layer; growing a 1-5 μm U-GaN layer on the buffer layer at a temperature of 1000-1100 ℃ and a pressure of 100-500 Torr; A first N-GaN layer of 1-5 μm is grown on the U-GaN layer at a temperature of 1000-1200 °C, a pressure of 100-500 Torr, and a silicon doping concentration of 10 18 ~10 19 cm -3 -2.0 x 1018 cm-3.

4. The method of claim 1, wherein the substrate is a sapphire substrate. The second N-GaN layer, the multi-quantum well layer, the P-type Al y Ga 1-y N electron blocking layer, the P-type gallium nitride layer and the P-type contact layer are sequentially grown on the silicon dioxide protective layer or the silicon nitride protective layer, and an epitaxial structure is formed. growing a second N-GaN layer of 500-1500 nm on the silicon-doped silicon dioxide protective layer or silicon nitride protective layer at a temperature of 1000-1200 °C, a pressure of 100-500 Torr, and a silicon doping concentration of 10 18 ~10 19 cm -3 ​ growing a well region of a multi-quantum well layer on the second N-GaN layer at a temperature of 720-829 ℃ and a pressure of 100-500 Torr, and growing a barrier region of the multi-quantum well layer at a temperature of 850-959 ℃ and a pressure of 100-500 Torr to form the multi-quantum well layer; P-type Al₂O₃ with a thickness of 50-150 nm is grown on the multi-quantum-well layer at a temperature of 850-1080 °C and a pressure of 200-500 Torr. y Ga 1-y N electron blocking layer; A P-type Al y Ga 1-y N electron barrier layer, a P-type gallium nitride layer of 100-800 nm is grown at a temperature of 850-1080 °C and a pressure of 100-300 Torr; growing a 5-300 nm P-type contact layer on the P-type gallium nitride layer at a temperature of 850-1050 ℃ and a pressure of 100-300 Torr to form an initial epitaxial structure; annealing the initial epitaxial structure in a nitrogen atmosphere at an annealing temperature of 650-850 ℃ for 5-15 min, and reducing the temperature to room temperature after the annealing to form an epitaxial structure.

5. The method of claim 1, wherein the substrate is a sapphire substrate. the step of forming a "concave" electrode on the epitaxial structure to obtain a light emitting diode comprises: etching the epitaxial structure to form a "concave" epitaxial structure; forming an anode electrode on a convex part of the "concave" epitaxial structure, and forming a cathode electrode on a concave part of the "concave" epitaxial structure; filling a fluorescent powder on the cathode electrode to obtain a light emitting diode.

6. A light emitting diode prepared according to the method of any one of claims 1-5, wherein, The light emitting diode comprises a "concave" epitaxial structure and an electrode. the electrode is arranged on one side of the "concave" epitaxial structure having a concave-convex surface. The concave-shaped epitaxial structure comprises a substrate and a silicon dioxide protective layer or a silicon nitride protective layer arranged on one side of the substrate.

7. The light emitting diode of claim 6, wherein, The electrode comprises an anode and a cathode; The anode is arranged on a convex part of the one side of the concave-shaped epitaxial structure, and the cathode is arranged on a concave part of the one side of the concave-shaped epitaxial structure.

8. The light emitting diode of claim 6, wherein, The concave-shaped epitaxial structure further comprises a buffer layer, a U-GaN layer, a first N-GaN layer, a second N-GaN layer, a multi-quantum well layer, a P-type AlyGa1-yN electron blocking layer, a P-type gallium nitride layer and a P-type contact layer. The one side of the substrate is sequentially provided with the buffer layer, the U-GaN layer and the first N-GaN layer arranged in a stack, and the silicon dioxide protective layer or the silicon nitride protective layer is arranged on a side of the first N-GaN layer away from the U-GaN layer; The side of the silicon dioxide protective layer or the silicon nitride protective layer away from the first N-GaN layer is sequentially provided with the second N-GaN layer, the multi-quantum well layer, the P-type AlyGa1-yN electron blocking layer, the P-type gallium nitride layer and the P-type contact layer arranged in a stack.

9. The light emitting diode of claim 7, wherein, Further comprising a fluorescent powder; The cathode is provided with the fluorescent powder on a side away from the concave-shaped epitaxial structure.

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