High-precision, low-noise, low-power programmable gain amplifier for audio systems

Abstract

The present invention discloses a high-precision, low-noise, low-power programmable gain amplifier for use in audio systems. The amplifier comprises two high-precision, low-noise, controllable-power single-ended output operational amplifiers, an adjustable resistor array, a low-frequency anti-aliasing filter, and a digital control module. After an externally preset operating mode, the digital control module generates a system-internal control logic signal that is input into the operational amplifier to adjust the output current of the operational amplifier. After an externally preset amplification factor, the digital control module generates a system-internal control logic signal that is input into the adjustable resistor array to adjust the resistance ratio between different nodes. The amplifier, in conjunction with the high-precision, low-noise, low-power single-ended output operational amplifier, amplifies the signal to the target gain, and then filters it through the low-frequency anti-aliasing filter before outputting it. The present invention has the advantages of high precision, low noise, low power consumption, and the ability to change the amplification factor in real time.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-precision, low-noise, low-power programmable gain amplifier applied to an audio system. Background Art

[0002] Analog front-end circuits are crucial building blocks for integrated circuit systems, enabling interaction between the real world and smart devices. In the real world, there are various continuous analog signals, such as sound, temperature, light, voltage, and various pressures. While humans can directly perceive these analog signals, they are difficult for smart devices to directly process. Therefore, it is necessary to convert these continuous analog signals into discrete digital signals that smart devices can recognize and process.

[0003] In actual use, it is necessary to select accelerometers with different structures for design according to different application scenarios. Therefore, in order to increase a certain degree of versatility and enable the same sampling chip to be applied to more sensor structures, it is necessary to add an adjustable gain function to the analog front end to meet the needs of accelerometers with different sensitivities and bandwidths.

[0004] The programmable gain amplifier is one of the core components of the analog front-end module. It can artificially amplify the signal to different multiples according to the size of the input signal, thereby improving the dynamic range of the system.

[0005] As technology develops and matures, integration and miniaturization are key trends in integrated circuits. As a crucial module in signal systems, the performance of programmable gain amplifiers (PGA) significantly impacts the system, and integrating them into system chips is a mainstream trend. Audio systems require relatively low-frequency input signals and demand high signal processing performance, making high-precision, low-noise, and low-power PGAs indispensable.

[0006] Chinese patent publication number CN112968684A proposes a wideband programmable gain amplifier based on transconductance switching technology. This technology achieves different amplification gains by varying the transconductance of the MOS transistors in the op amp input stage. However, this technology is limited by manufacturing process variations and mismatches between the MOS transistors themselves, preventing precise amplification and resulting in a relatively crude programmable gain amplifier. Chinese patent publication number CN113328711A proposes a programmable gain amplifier with a constant transconductance and full-swing input. This amplifier achieves high-precision performance by adjusting the proportional relationship of the load resistors. However, it fails to address system noise, resulting in a significant noise impact on the output signal.

[0007] It can be seen that the existing technologies mainly focus on high-precision processing, with only a few mentioning the realization of low noise. There is a lack of programmable gain amplifiers that can achieve ultra-high precision and low noise at the same time. For high-precision processing, usually only the input stage is redesigned separately or the gain stage is redesigned separately. There is no design solution to achieve ultra-high precision dB linear characteristics by coordinating the input and gain stages. Summary of the Invention

[0008] In view of the foregoing, the present invention provides a high-precision, low-noise, and low-power programmable gain amplifier for use in audio systems. By utilizing a novel high-transconductance input stage and a gain stage with an auxiliary operational amplifier, the amplifier provides high and low-frequency gain, achieving high precision in the signal amplification process. Simultaneously, the amplifier utilizes multiplexing of CHOP switching to shift and filter the low-frequency noise portion of the circuit, thereby achieving the purpose of low-noise amplification.

[0009] A high-precision, low-noise, low-power programmable gain amplifier for use in audio systems includes two single-ended output operational amplifiers A1 and A2, an adjustable resistor array, a digital control module, and a low-frequency anti-aliasing filter. The non-inverting inputs of A1 and A2 are connected to differential input signals INPUT_A and INPUT_B, respectively; the inverting inputs of A1 and A2 are connected to the adjustable resistor array; the outputs of A1 and A2 are connected to the adjustable resistor array and the low-frequency anti-aliasing filter; and the amplified INPUT_A and INPUT_B are filtered by the low-frequency anti-aliasing filter to obtain differential output signals OUTPUT_A and OUTPUT_B.

[0010] The digital control module receives an external clock signal, thereby generating a pair of mutually inverted clock signals to be provided to A1 and A2. At the same time, the digital control module receives an external enable signal for controlling the output current of the op amp, thereby generating two pairs of mutually inverted enable signals to be provided to A1 and A2. In addition, the digital control module also receives an external digital logic signal for controlling the amplification factor, thereby generating six pairs of mutually inverted digital logic signals to be transmitted to the adjustable resistor array.

[0011] The adjustable resistor array enables the gain amplifier to have multiple amplification factors by changing the proportional relationship of the operational amplifier load resistance.

[0012] Furthermore, the adjustable resistor array includes six high-linearity double-throw switches SW1 to SW6 and six pairs of resistors R1a and R1b, R2a and R2b, R3a and R3b, R4a and R4b, R5a and R5b, and R6a and R6b, wherein the two resistors in each pair have the same resistance value, wherein one end of R6a is connected to the VOUTa terminal of SW6 and serves as the PORT_A port of the adjustable resistor array, the other end of R6a is connected to one end of R5a and the VOUTa terminal of SW5, the other end of R5a is connected to one end of R4a and the VOUTa terminal of SW4, the other end of R4a is connected to one end of R3a and the VOUTa terminal of SW3, the other end of R3a is connected to one end of R2a and the VOUTa terminal of SW2, the other end of R2a is connected to one end of R1a and the VOUTa terminal of SW1, and the other end of R1a is connected to R One end of R1b is connected to another end of R2b, the other end of R2b is connected to another end of R3b and the VOUTb end of SW2, the other end of R3b is connected to another end of R4b and the VOUTb end of SW3, the other end of R4b is connected to another end of R5b and the VOUTb end of SW4, the other end of R5b is connected to another end of R6b and the VOUTb end of SW5, the other end of R6b is connected to the VOUTb end of SW6 and serves as the PORT_B port of the adjustable resistor array, the VINa ends of SW1 to SW6 are connected in common and serve as the PORT_C port of the adjustable resistor array, the VINb ends of SW1 to SW6 are connected in common and serve as the PORT_D port of the adjustable resistor array, and the opening and closing of SW1 to SW6 are controlled by six pairs of digital logic signals provided by the digital control module;

[0013] The PORT_A port of the adjustable resistor array is connected to the output end of A1, the PORT_B port is connected to the output end of A2, the PORT_C port is connected to the inverting input end of A1, and the PORT_D port is connected to the inverting input end of A2.

[0014] Furthermore, the high linearity double throw switches SW1 to SW6 have the same structure, including 8 PMOS transistors P1a, P2a, P3a, P4a, P1b, P2b, P3b, P4b and 8 NMOS transistors P5a, P6a, P7a, P8a, P5b, P6b, P7b, P8b, wherein the source of P1a is connected to the source of P1b and connected to the power supply voltage VDD, and the gate of P1a is connected to the gate of P8a and the gate of P7a. , the gate of P6a, the gate of P1b are connected to the gate of P8b, the gate of P7b and the gate of P6b and connected to RS-, the gate of P2a is connected to the gate of P2b, the gate of P3a, the gate of P3b, the gate of P4a, the gate of P4b, the gate of P5a and the gate of P5b and connected to RS+, the drain of P1a is connected to the drain of P8a, the source of P2a and the substrate of P3a, the drain of P1b is connected to the drain of P8b, P The source of P2b is connected to the substrate of P3b, the source of P8a is connected to the drain of P2a, the drain of P7a and the source of P3a and serves as the VINa terminal of the double-throw switch, the source of P8b is connected to the drain of P2b, the drain of P7b and the source of P3b and serves as the VINb terminal of the double-throw switch, the source of P7a is connected to the drain of P3a, the drain of P6a and the source of P4a and serves as the VOUTa terminal of the double-throw switch, the source of P7b is connected to the drain of P3a, the drain of P6a and the source of P4a and serves as the VOUTa terminal of the double-throw switch The electrode is connected to the drain of P3b, the drain of P6b and the source of P4b and serves as the VOUTb end of the double-throw switch. The source of P6a is connected to the drain of P4a, the drain of P5a and the substrate of P7a. The source of P6b is connected to the drain of P4b, the drain of P5b and the substrate of P7b. The source of P5a is connected to the source of P5b and to the power ground VSS. RS+ and RS- are a pair of mutually inverted digital logic signals provided by the digital control module.

[0015] Furthermore, the operational amplifiers A1 and A2 have the same structure, which is composed of a high transconductance input stage, a gain amplifier stage, and a Class-AB adjustable current output stage connected in sequence, wherein:

[0016] The high transconductance input stage improves the transconductance of the op amp input stage by proportionally splitting and cross-coupling the input pair transistors and the NMOS tail current transistors in the folded cascode structure, thereby improving the overall low-frequency gain of the op amp and extending the overall unity gain bandwidth of the op amp, thereby achieving high precision of the gain amplifier and meeting the frequency range of the processable input signal;

[0017] The gain amplifier stage provides gain amplification to the input signal through a folded cascode structure with an auxiliary operational amplifier, wherein the CHOP switch serves as a secondary spectrum shift switch of the operational amplifier and also as a primary spectrum shift switch of the auxiliary operational amplifier, thereby realizing a multiplexing function;

[0018] The Class-AB adjustable current output stage controls the current of the operational amplifier output stage through floating gate voltage feedforward control and a switch structure, thereby achieving controllable power consumption of the operational amplifier.

[0019] Furthermore, the high transconductance input stage includes a CHOP switch CHOPPER_B, five PMOS transistors M0, M1a, M1b, M2a, M2b, and four NMOS transistors M3a, M3b, M4a, and M4b, wherein the input ports IN_A and IN_B of CHOPPER_B correspond to the non-inverting input and inverting input of the operational amplifier, the output port OUT_A of CHOPPER_B is connected to the gate of M1a and the gate of M1b, the output port OUT_B of CHOPPER_B is connected to the gate of M2a and the gate of M2b, and the source of M0 is connected to the power supply voltage VDD. The gate of M0 is connected to a fixed bias voltage VBP3, the drain of M0 is connected to the source of M1a, the source of M1b, the source of M2a, and the source of M2b, the drain of M1a is connected to the drain of M3a and serves as the non-inverting output terminal of the high transconductance input stage, the drain of M2a is connected to the drain of M4a and serves as the inverting output terminal of the high transconductance input stage, the drain of M1b is connected to the drain of M4b, the gate of M4b, and the gate of M4a, the drain of M2b is connected to the drain of M3b, the gate of M3b, and the gate of M3a, and the source of M3a is connected to the source of M3b, the source of M4a, and the source of M4b and to the power supply ground VSS.

[0020] Furthermore, the gain amplifier stage includes two auxiliary operational amplifiers GBP and GBN, two CHOP switches CHOPPER_P and CHOPPER_N, four PMOS transistors M7 to M10, and two NMOS transistors M5 and M6, wherein the source of M9 is connected to the source of M10 and connected to the power supply voltage VDD, the gate of M9 is connected to the gate of M10, the drain of M7 and the drain of M5, the drain of M9 is connected to the non-inverting input terminal of GBN and the input port IN_A of CHOPPER_P, the drain of M10 is connected to the inverting input terminal of GBN and the input port IN_B of CHOPPER_P, the output port OUT_A of CHOPPER_P is connected to the source of M7, and the gate of CHOPPER_N ... The output port OUT_B of P is connected to the source of M8, the non-inverting output terminal of GBN is connected to the gate of M7, the inverting output terminal of GBN is connected to the gate of M8, the drain of M8 is connected to the drain of M6, the source of M5 is connected to the input port IN_A of CHOPPER_N, the source of M6 is connected to the input port IN_B of CHOPPER_N, the non-inverting input terminal of GBP is connected to the output port OUT_A of CHOPPER_N and the non-inverting output terminal of the high transconductance input stage, the inverting input terminal of GBP is connected to the output port OUT_B of CHOPPER_N and the inverting output terminal of the high transconductance input stage, the non-inverting output terminal of GBP is connected to the gate of M5, and the inverting output terminal of GBP is connected to the gate of M6.

[0021] Furthermore, the auxiliary operational amplifier GBP includes eight PMOS transistors PM0, PM1, PM2, PM3, PM8, PM9, PM10 and PM11, four NMOS transistors PM4, PM5, PM6, PM7 and two CHOP switches CHOPPER_P1 and CHOPPER_N1, wherein the source of PM0 is connected to the source of PM10, the source of PM11 and the source of PM1 and is connected to the power supply voltage VDD, and the gate of PM0 is connected to the gate of PM1 and is connected to a fixed bias voltage. The voltage VBP3 is applied, the drain of PM0 is connected to the source of PM2, the drain of PM1 is connected to the source of PM3, the gate of PM2 and the gate of PM3 serve as the non-inverting input and the inverting input of the auxiliary operational amplifier GBP respectively, the gate of PM10 is connected to the gate of PM11 and connected to the fixed bias voltage VBP1, the drain of PM10 is connected to the input port IN_A of CHOPPER_P1, the drain of PM11 is connected to the input port IN_B of CHOPPER_P1, the source of PM8 is connected to the CHOPP The output port OUT_A of ER_P1 is connected, the source of PM9 is connected to the output port OUT_B of CHOPPER_P1, the gate of PM8 is connected to the gate of PM9 and connected to the fixed bias voltage VBP2, the drain of PM8 is connected to the drain of PM6 and serves as the inverting output terminal of the auxiliary operational amplifier GBP, the drain of PM9 is connected to the drain of PM7 and serves as the inverting output terminal of the auxiliary operational amplifier GBP, the gate of PM6 is connected to the gate of PM7 and connected to the fixed bias voltage VBN2, the source of PM6 is connected to CH The input port IN_A of OPPER_N1 is connected, the source of PM7 is connected to the input port IN_B of CHOPPER_N1, the drain of PM2 is connected to the drain of PM4 and the output port OUT_A of CHOPPER_N1, the drain of PM3 is connected to the drain of PM5 and the output port OUT_B of CHOPPER_N1, the gate of PM4 is connected to the gate of PM5 and connected to the fixed bias voltage VBN1, and the source of PM4 is connected to the source of PM5 and connected to the power ground VSS.

[0022] Furthermore, the auxiliary operational amplifier GBN includes eight NMOS transistors NM0, NM1, NM2, NM3, NM4, NM5, NM6 and NM7, four PMOS transistors NM8, NM9, NM10, NM11 and two CHOP switches CHOPPER_P2 and CHOPPER_N2, wherein the source of NM0 is connected to the source of NM1, the source of NM4 and the source of NM5 and is connected to the power ground VSS, and the gate of NM0 is connected to the gate of NM1 and is connected to the fixed bias voltage VB The drains of N3 and NM0 are connected to the source of NM2, the drain of NM1 is connected to the source of NM3, the gates of NM2 and NM3 serve as the non-inverting input and inverting input of the auxiliary op amp GBN respectively, the gate of NM4 is connected to the gate of NM5 and connected to the fixed bias voltage VBN1, the drain of NM5 is connected to the output port OUT_A of CHOPPER_N2, the drain of NM4 is connected to the output port OUT_B of CHOPPER_N2, and the source of NM7 is connected to CHOPPER_N2. The input port IN_A of NM6 is connected to the input port IN_B of CHOPPER_N2, the gate of NM6 is connected to the gate of NM7 and connected to the fixed bias voltage VBN2, the drain of NM7 is connected to the drain of NM9 and serves as the non-inverting output terminal of the auxiliary operational amplifier GBN, the drain of NM6 is connected to the drain of NM8 and serves as the inverting output terminal of the auxiliary operational amplifier GBN, the gate of NM8 is connected to the gate of NM9 and connected to the fixed bias voltage VBP2, and the source of NM9 is connected to CHOPPER_P The output port OUT_A of CHOPPER_P2 is connected to the source of NM8, the output port OUT_B of CHOPPER_P2 is connected to the drain of NM11, the drain of NM11 is connected to the drain of NM2 and the input port IN_A of CHOPPER_P2, the drain of NM10 is connected to the drain of NM3 and the input port IN_B of CHOPPER_P2, the gate of NM10 is connected to the gate of NM11 and connected to the fixed bias voltage VBP1, and the source of NM10 is connected to the source of NM11 and connected to the power supply voltage VDD.

[0023] Furthermore, the CHOP switches CHOPPER_B, CHOPPER_P, CHOPPER_N, CHOPPER_P1, CHOPPER_P2, CHOPPER_N1, and CHOPPER_N2 have the same structure and include four switch modules K1 to K4, wherein the input end of K1 is connected to the input end of K2 and serves as the input port IN_A of the CHOP switch, the output end of K1 is connected to the output end of K3 and serves as the output port OUT_A of the CHOP switch, the input end of K3 is connected to the input end of K4 and serves as the input port IN_B of the CHOP switch, and the output end of K2 is connected to the output end of K4 and serves as the output port OUT_B of the CHOP switch; the switch modules K1 to K4 in the CHOP switches CHOPPER_P, CHOPPER_P1, and CHOPPER_P2 use PMOS transistors, the switch modules K1 to K4 in CHOPPER_N, CHOPPER_N1, and CHOPPER_N2 use NMOS transistors, and the switch modules K1 to K4 in CHOPPER_B use bootstrap switches.

[0024] Furthermore, the Bootstrap switch includes a capacitor C1, four PMOS transistors SM1, SM2, SM3, SM6 and seven NMOS transistors SM4, SM5, SM7, SM8, SM9, SM10 and SM11, wherein the drain of SM1 is connected to the source of SM6, the gate of SM4 and the source of SM2 and is connected to the power supply voltage VDD, the gate of SM1 is connected to the drain of SM3, the drain of SM4, the gate of SM8, the gate of SM9 and the gate of SM10, the source of SM1 is connected to one end of C1 and the source of SM3, and the other end of C1 is connected to the drain of SM11, the source of SM7 and the source of SM8. The gate of SM11 is connected to CLK1, the gate of SM6 is connected to the gate of SM7 and to CLK2, the drain of SM6 is connected to the drain of SM7, the gate of SM3 and the drain of SM8, the drain of SM2 is connected to the source of SM4 and the drain of SM5, the gate of SM2 is connected to the gate of SM5 and to CLK1, the source of SM5 is connected to the power ground VSS, the source of SM9 is connected to the drain of SM10 and serves as the input end of the switch module, the source of SM10 serves as the output end of the switch module, and CLK1 and CLK2 are a pair of mutually inverse clock signals provided by the digital control module.

[0025] Based on the above technical solution, the present invention has the following beneficial technical effects:

[0026] 1. The present invention adopts differential input and differential output, which can achieve larger input and output swings.

[0027] 2. The present invention can provide extremely high low-frequency gain, so that the system has high precision when amplifying signals.

[0028] 3. The present invention can filter low-frequency noise, making the system noise extremely low and providing a high signal-to-noise ratio output signal.

[0029] 4. The present invention can provide a controllable output current, thereby providing an optional driving capability, can directly provide the output signal to the back-end circuit module, and can effectively control the overall power consumption of the system.

[0030] 5. The present invention can be applied to the amplification of audio signals, providing low harmonic distortion and maintaining signal performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of the structure of a high-precision, low-noise, low-power programmable gain amplifier according to the present invention.

[0032] Figure 2 Schematic diagram of the structure of the adjustable resistor array.

[0033] Figure 3 It is a structural diagram of a double-throw switch.

[0034] Figure 4 This is a structural diagram of the digital control module.

[0035] Figure 5 Schematic diagram of the structure of the operational amplifier of the present invention.

[0036] Figure 6 It is a structural diagram of the novel high transconductance input stage and gain amplifier stage of the present invention.

[0037] Figure 7 This is a structural diagram of the auxiliary operational amplifier GBP.

[0038] Figure 8 This is a structural diagram of the auxiliary operational amplifier GBN.

[0039] Figure 9 Schematic diagram of the CHOP switch structure.

[0040] Figure 10 This is a structural diagram of the new gate voltage bootstrap switch Bootstrap.

[0041] FIG11( a ) is a schematic diagram of simulation waveforms of the operational amplifier of the present invention using a novel high transconductance input gain stage.

[0042] Figure 11(b) is a schematic diagram showing the noise comparison before and after using the multiplexed CHOP switch chopping technology. DETAILED DESCRIPTION

[0043] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] like Figure 1 As shown, the present invention is applied to a high-precision, low-noise, low-power programmable gain amplifier with differential input and differential output in an audio processing system, comprising an adjustable resistor array consisting of 6 pairs of resistors R1 to R6 with different resistance values ​​and a plurality of switches, two single-ended output operational amplifiers A1 and A2, a digital control module, and a low-frequency anti-aliasing filter, wherein the non-inverting input terminals of A1 and A2 are connected to the differential input signals INPUT_A and INPUT_B; the output terminal of A1 is connected to one end of PORT_A in the adjustable resistor array, the inverting input terminal of A1 is connected to one end of PORT_C in the adjustable resistor array, the output terminal of A2 is connected to one end of PORT_B in the adjustable resistor array, and the inverting input terminal of A2 is connected to one end of PORT_D in the adjustable resistor array; the digital control module receives a clock signal input from the outside The CLOCK signal generates a pair of mutually inverted CLK (CLK1, CLK2) signals and transmits them to the op amp. The two enable signals ENABLE_A and ENABLE_B that control the output current of the op amp are input from the outside to generate two pairs of mutually inverted enable signals ENA and ENB that are transmitted to the op amp. The three digital logic signals that control the amplification factor are input from the outside to generate a group of six pairs of mutually inverted digital logic signals GAIN_CTRL that are transmitted to the adjustable resistor array. The amplified differential signals output by A1 and A2 are transmitted to the VIN1 and VIN2 input terminals of the anti-aliasing filter. After filtering, the differential output signals OUTPUT_A and OUTPUT_B of the system are output through the VOUT1 and VOUT2 output terminals. VDD and VSS provide power and ground for the entire system.

[0045] like Figure 2 As shown, the adjustable resistor array consists of six circuit units consisting of switches and resistors connected in series. Each circuit unit consists of a high-linearity double-throw switch (SW) and a pair of resistors of equal value. The switch's VOUT terminal is connected to one end of the resistor, the switch's VIN terminal is connected to the VIN terminal of the switch of another circuit unit, and the other end of the resistor is connected to the resistor of the other circuit unit and the switch's VOUT terminal. The double-throw switches are configured to have two states: one on and one off. The six resistor pairs (R1-R6) have a ratio of 1:1:2:4:8:16, resulting in amplification factors of 1, 2, 4, 8, 16, and 32.

[0046] like Figure 3As shown, the high-linearity double-throw switch SW includes two groups of symmetrically structured MOS transistor switches, each group of switches includes eight MOS transistors M1 to M8, wherein the substrate voltages of the MOS transistors except M3 and M7 are treated as follows: a PMOS transistor is connected to VDD, and an NMOS transistor is grounded; the source of M1 is connected to the power supply voltage VDD, the drain of M1 is connected to the source of M2, the drain of M8, and the substrate of M3, the gate of M1 is connected to the gate of M8, the gate of M7, the gate of M6, and the gate of M6, and is connected to a switching signal RS-, the gate of M2 is connected to the gate of M3, the gate of M4, and the gate of M5, and is connected to a switching signal RS+, the drain of M2 is connected to the source of M8, the source of M3, the drain of M7, and the input signal VIN, the drain of M3 is connected to the source of M7, the drain of M6, the source of M4, and the output signal VOUT, the drain of M5 is connected to the source of M6, the drain of M4, and the substrate of M7, and the source of M5 is grounded. M1~M4 are PMOS tubes, and M5~M8 are NMOS tubes.

[0047] like Figure 4 As shown, the digital control module consists of eighteen NOT gates, six three-input AND gates, and a delay module. The external input CLOCK signal passes through a NOT gate and a delay module to obtain the CLK2 signal, and then passes through two NOT gates to obtain the CLK1 signal. The external input ENABLE_A signal passes through a NOT gate to obtain the ENAN signal, and then passes through two NOT gates to obtain the ENAP signal. The external input ENABLE_B signal passes through a NOT gate to obtain the ENBN signal, and then passes through two NOT gates to obtain the ENBP signal. The external input GAIN_CTRL_A, GAIN_CTRL_B, and GAIN_CTRL_C signals pass through a three-line to six-line decoder consisting of six NOT gates and six three-input AND gates to obtain the six signals RS6+, RS5+, RS4+, RS3+, RS2+, and RS1+. These six signals are then passed through six NOT gates to generate the six signals RS6-, RS5-, RS4-, RS3-, RS2-, and RS1-. These six pairs of mutually inverted GAIN_CTRL signals are respectively connected to the corresponding control terminals of the six switches in the adjustable resistor array.

[0048] like Figure 5 As shown, op amps A1 and A2 include:

[0049] The new high transconductance input stage improves the transconductance of the op amp input stage by proportionally splitting and cross-coupling the input pair tubes and the NMOS tail current tubes in the folded cascode structure, thereby improving the overall low-frequency gain of the op amp and extending the overall unity-gain bandwidth of the op amp, achieving high precision of the amplifier and meeting the frequency range of the processable input signal.

[0050] The gain amplifier stage provides gain amplification for the input signal through a folded cascode structure with an auxiliary op amp. The CHOP switch serves as the secondary spectrum shift switch of the op amp and also the primary spectrum shift switch of the auxiliary op amp, realizing the multiplexing function, saving circuit area and improving the transient performance of the circuit.

[0051] The Class-AB adjustable current output stage controls the quiescent current of the circuit output stage through floating gate voltage feedforward control and switch structure, thereby achieving controllable power consumption of the op amp.

[0052] like Figure 6 As shown in FIG, the new high transconductance input stage and gain amplifier stage includes 15 MOS tubes M0 to M10, 2 auxiliary operational amplifiers and 3 CHOP switches, wherein the source of M0 is connected to the power supply voltage VDD, the gate of M0 is connected to a fixed bias VBP3 as a fixed current source, the drain of M0 is connected to the sources of M1a, M1b, M2a and M2b, the input signals VIN_A and VIN_B are connected to the gates of M1a, M1b and the gates of M2a and M2b respectively through a CHOP switch, the sources of M9 and M10 are connected to the power supply voltage VDD, the gates of M9 and M10 are connected to the drain of M7 and the drain of M5, the drain of M9 and the drain of M10 are connected to the source of M7 and the source of M8 respectively through a CHOP switch, and the input terminals of the auxiliary operational amplifier GBN are connected to Connect to the drain of M9 and the drain of M10, the output of the auxiliary op amp GBN is connected to the gate of M7 and the gate of M8 respectively, the drain of M8 is connected to the drain of M6, the source of M5 and the source of M6 are connected to the drain of M3a and the drain of M4a respectively through a CHOP switch, the source of M3a, M3b, M4a, and M4b are connected to the ground VSS, the drain of M1a is connected to the drain of M3a, the drain of M1b is connected to the drain of M4b, the drain of M2a is connected to the drain of M4a, the drain of M2b is connected to the drain of M3b, the gate of M3a and the gate of M3b are connected to the drain of M3b, the gate of M4a and the gate of M4b are connected to the drain of M4b, the input of the auxiliary op amp GBP is connected to the drain of M3a and the drain of M4a respectively, and the output of the auxiliary op amp GBP is connected to the gate of M5 and the gate of M6 respectively.

[0053] like Figure 7As shown, the auxiliary operational amplifier GBP includes 12 MOS tubes PM0~PM11 and two CHOP switches, wherein the sources of PM0 and PM1 are connected to the power supply voltage VDD, the gates of PM0 and PM1 are connected to a fixed bias VBP3, the drain of PM0 is connected to the source of PM2, the drain of PM1 is connected to the source of PM3, the gates of PM2 and PM3 serve as the input terminals of GBP respectively, the sources of PM10 and PM11 are connected to the power supply voltage VDD, the gates of PM10 and PM11 are connected to a fixed bias VBP1, and the drains of PM10 and PM11 are connected through a CHOP. The OP switch is connected to the source of PM8 and the source of PM9 respectively, the gates of PM8 and PM9 are connected to a fixed bias VBP2, the drain of PM8 and the drain of PM6 are connected and serve as the output of GBP, the drain of PM9 and the drain of PM7 are connected and serve as another output of GBP, the gates of PM6 and PM7 are connected to a fixed bias VBN2, the source of PM6 and the source of PM7 are connected to the drain of PM4 and the drain of PM5 respectively through a CHOP switch, the sources of PM4 and PM5 are connected to ground, the drain of PM2 is connected to the drain of PM4, and the drain of PM3 is connected to the drain of PM5.

[0054] like Figure 8 As shown, the auxiliary operational amplifier GBN includes 12 MOS tubes NM0~NM11 and two CHOP switches, wherein the sources of NM0 and NM1 are connected to the ground VSS, the gates of NM0 and NM1 are connected to a fixed bias VBN3, the drain of NM0 is connected to the source of NM2, the drain of NM1 is connected to the source of NM3, the gates of NM2 and NM3 serve as the input terminals of GBN respectively, the sources of NM10 and NM11 are connected to the power supply voltage VDD, the gates of NM10 and NM11 are connected to a fixed bias VBP1, and the drains of NM10 and NM11 are connected through a CHO The P switch is connected to the source of NM8 and the source of NPM9 respectively, the gates of NM8 and NM9 are connected to a fixed bias VBP2, the drain of NM8 and the drain of NM6 are connected and serve as the output of GBN, the drain of NM9 and the drain of NM7 are connected and serve as another output of GBN, the gates of NM6 and NM7 are connected to a fixed bias VBN2, the source of NM6 and the source of NM7 are connected to the drain of NM4 and the drain of NM5 respectively through a CHOP switch, the sources of NM4 and NM5 are connected to ground, the drain of NM2 is connected to the drain of NM4, and the drain of NM3 is connected to the drain of NM5.

[0055] like Figure 9As shown, the CHOP switch consists of four switch modules, K1 through K4. The left end of K1 is connected to the left end of K2 and to IN_A, the left end of K3 is connected to the left end of K4 and to IN_B, the right end of K1 is connected to the right end of K3 and to OUT_A, and the right end of K2 is connected to the right end of K4 and to OUT_B. There are three types of CHOP switches: CHOPPER_P, CHOPPER_N, and CHOPPER_Bootstrap. CHOPPER_P replaces the switch modules with simple PMOS transistors, CHOPPER_N replaces the switch modules with simple NMOS transistors, and CHOPPER_Bootstrap uses bootstrap switches as the switch modules.

[0056] like Figure 10 As shown, the bootstrap switch includes 11 MOS transistors SM1 to SM11 and a capacitor C1, wherein the drain of SM1, the source of SM2, the gate of SM4 and the source of SM6 are connected to the power supply voltage, the gate of SM1, the drain of SM3, the drain of SM4, the gate of SM8, the gate of SM9 and the gate of SM10 are connected, the drain of SM2, the source of SM4 and the drain of SM5 are connected, the gate of SM2 and the gate of SM5 are connected to CLK1, the source of SM5 is connected to ground, the source of SM1, the source of SM3 and the upper plate of C1 are connected, the gate of SM6 and the gate of SM7 are connected to CLK2, the drain of SM6, the drain of SM7, the gate of SM3 and the drain of SM8 are connected, the source of SM7, the source of SM8, the drain of SM9, the lower plate of C1 and the drain of SM11 are connected, the gate of SM11 is connected to CLK1, the source of SM11 is connected to ground, the source of SM9 and the drain of SM10 are connected to the switch input terminal IN, and the source of SM10 serves as the switch output OUT. SM1, SM2, SM3, and SM6 are PMOS tubes, and SM4, SM5, SM7, SM8, SM9, SM10, and SM11 are NMOS tubes.

[0057] like Figure 5As shown, the Class-AB adjustable current output stage includes 16 MOS tubes M11 to M26, two capacitors C1 and C2 and two resistors R1 and R2, wherein the gates of M11 and M12 are connected to a fixed bias VBP_AB, the gates of M13 and M14 are connected to a fixed bias VBN_AB, the source of M11 is connected to the drain of M13, the drain of M11 is connected to the source of M13, the small circuit unit composed of M11 and M13 is inserted as a whole between the input gain stages M7 and M5, the source of M12 is connected to the drain of M14, the drain of M12 is connected to the source of M14, the small circuit unit composed of M12 and M14 is inserted as a whole between the input gain stages M8 and M6, the source of M12 is connected to the upper plate of C1, the gate of M15 and the gate of M16, the source of M14 is connected to the upper plate of C2, the gate of M17 and the gate of M18, and the lower plate of C1 The plate is connected to one end of R1, the lower plate of C2 is connected to one end of R2, the source of M15 and the source of M16 are connected to the power supply voltage VDD, the drain of M15 is connected to the source of M19 and the drain of M20, the drain of M16 is connected to the source of M21 and the drain of M22, the source of M17 and the source of M18 are connected to ground, the drain of M17 is connected to the drain of M23 and the source of M24, the drain of M18 is connected to the drain of M25 and the source of M26, the drain of M19, the source of M20, the drain of M21, the source of M22, the source of M23, the drain of M24, the source of M25, the drain of M26, the other end of R1, and the other end of R2 are connected to the output terminal OUTPUT of the op amp, the gates of M19 and M23 are connected to ENAP, the gates of M20 and M24 are connected to ENAN, the gates of M21 and M25 are connected to ENBP, and the gates of M22 and M26 are connected to ENBN.

[0058] The high-precision, low-noise, and low-power programmable gain amplifier with differential input and differential output applied to an audio processing system adopts a dual-op-amp instrumentation amplifier structure, and changes in amplification are achieved through an adjustable resistor array. The op-amp adopts a novel high-transconductance input stage structure, and simultaneously uses gain boosting technology and multiplexing CHOP switch chopping technology to add auxiliary op-amps and CHOP switches to the circuit, so that the system meets the requirements of high precision and low noise. The op-amp output stage adopts floating gate voltage control Class-AB technology and output current selection technology, which can achieve a large output voltage swing and control system power consumption.

[0059] The system's amplification factor is determined by changing the resistance ratio between different nodes in the adjustable resistor array. There are four nodes in the adjustable resistor array: PORT_A, PORT_B, PORT_C, and PORT_D. Only one of the six double-throw switches will be turned on at each amplification factor. The resistance between PORT_A and PORT_B is fixed and constant, which is the sum of all the resistance values, denoted as R. totWhen a double-throw switch is turned on, there is a path between PORT_C and PORT_D. The resistance value of the path can change with the conduction of different switches. The sum of the resistance values ​​of this part is recorded as R gain , the system magnification determined from this is:

[0060]

[0061] Because PORT_C and PORT_D are connected to the inverting input of the op amps respectively to extract from the adjustable resistor array, the switch itself does not exist in the output connection branch of the two op amps A1 and A2. Therefore, the change of the on-resistance of the switch with voltage will not affect the system's amplification factor and amplification accuracy.

[0062] Three external input logic signals, GAIN_CTRL_A, GAIN_CTRL_B, and GAIN_CTRL_C, that control the gain are encoded by the digital control module to form the GAIN_CTRL signal that controls the on / off switching of the adjustable resistor module. This control switch exhibits high linearity. When all transmission gates are off, the upper and lower current sources are on, connecting the PMOS transistor substrate of the transmission gate located in the middle of the input and output to the power supply voltage VDD and the NMOS transistor substrate to ground. When all transmission gates are on, the upper and lower current sources are off, connecting the PMOS transistor substrate of the transmission gate located in the middle of the input and output to its source, and the NMOS transistor substrate to its source as well. This reduces the impact of the MOS transistor body effect on the switch's on-resistance and nonlinearity.

[0063] The op amp's input gain stage features a novel high-transconductance input gain stage structure with an auxiliary op amp for gain boost and a CHOP switch for filtering. The four MOS transistors (M1a, M1b, M2a, and M2b) are of identical size, dividing the current I passing through M0 into four parts, with the current flowing from M9 and M10 being I / 2. The two MOS transistors (M3a and M3b, and M4a and M4b) have a size ratio of 2:3, forming a current mirror structure. The current flowing through M3b and M4b is I / 4, while the current flowing through M3a is 3I / 4, which is exactly the sum of the current flowing through M1a and the current flowing through the M9 branch. The same applies to M4a. This design improves the gain stage's low-frequency gain and unity-gain bandwidth, at the expense of slightly reduced phase margin. Adding the auxiliary op amp increases the output impedance seen by the input gain stage's output node, further increasing gain. Properly setting the unity-gain bandwidth of the auxiliary op amp can improve low-frequency gain without changing the unity-gain bandwidth of the original structure. CHOPPER_P and CHOPPER_N in the input gain stage serve as both CHOP switches within the folded cascode structure and before the input transistors in the auxiliary op amps GBP and GBN. The CHOP switches shift the circuit's low-frequency noise spectrum, which is then filtered by a low-frequency anti-aliasing filter to achieve low noise. The auxiliary op amps utilize a fully symmetrical circuit structure to ensure overall circuit matching. A new high-transconductance input stage uses currents from four branches to clamp the drain and gate voltages of M3 and M4, enabling the auxiliary op amps to achieve adaptive bias without requiring additional bias voltages.

[0064] The op amp output stage utilizes Class-AB floating gate voltage control technology. When current in branch M10 fluctuates slightly under small signals, the gate voltages of output MOSFETs M15-M18 change in unison. Four switches, formed by M19-M26, control the output stage current, thereby controlling system power consumption. The output stage current is primarily determined by the load's required drive capability. The switches are activated and deactivated by externally supplied enable signals, ENABLE_A and ENABLE_B, encoded by the digital control module.

[0065] Figure 11(a) shows the AC simulation results of the programmable operational amplifier (OPA) module. The low-frequency gain of the op amp can reach 175dB, the unity-gain bandwidth can reach 47MHz, and the corresponding phase margin is 64deg, ensuring that the op amp can achieve the required high-precision performance, handle the maximum allowable input signal frequency, and guarantee loop stability. Figure 11(b) shows a noise simulation comparison of the programmable operational amplifier with and without the use of switch-multiplexed chopping technology. The horizontal axis is frequency, and the corresponding vertical axis is the noise power at that frequency. The results clearly show that the use of switch-multiplexed chopping technology greatly suppresses the low-frequency noise of the programmable gain amplifier.

[0066] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It is apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements or modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A high-precision, low-noise, low-power programmable gain amplifier for use in audio systems, characterized by: It includes two single-ended output operational amplifiers A1 and A2, an adjustable resistor array, a digital control module, and a low-frequency anti-aliasing filter. The non-inverting input terminals of A1 and A2 are respectively connected to the differential input signals INPUT_A and INPUT_B, the inverting input terminals of A1 and A2 are connected to the adjustable resistor array, and the output terminals of A1 and A2 are connected to the adjustable resistor array and the low-frequency anti-aliasing filter. The amplified INPUT_A and INPUT_B are finally filtered by the low-frequency anti-aliasing filter to obtain differential output signals OUTPUT_A and OUTPUT_B. The digital control module receives an external clock signal, thereby generating a pair of mutually inverted clock signals to be provided to A1 and A2. At the same time, the digital control module receives an external enable signal for controlling the output current of the op amp, thereby generating two pairs of mutually inverted enable signals to be provided to A1 and A2. In addition, the digital control module also receives an external digital logic signal for controlling the amplification factor, thereby generating six pairs of mutually inverted digital logic signals to be transmitted to the adjustable resistor array. The adjustable resistor array enables the gain amplifier to have multiple amplification factors by changing the proportional relationship between the operational amplifier load resistance; The operational amplifiers A1 and A2 have the same structure, which consists of a high transconductance input stage, a gain amplifier stage, and a Class-AB adjustable current output stage connected in sequence, wherein: The high transconductance input stage improves the transconductance of the op amp input stage by proportionally splitting and cross-coupling the input pair transistors and the NMOS tail current transistors in the folded cascode structure, thereby improving the overall low-frequency gain of the op amp and extending the overall unity gain bandwidth of the op amp, thereby achieving high precision of the gain amplifier and meeting the frequency range of the processable input signal; The gain amplifier stage provides gain amplification to the input signal through a folded cascode structure with an auxiliary operational amplifier, wherein the CHOP switch serves as a secondary spectrum shift switch of the operational amplifier and also as a primary spectrum shift switch of the auxiliary operational amplifier, thereby realizing a multiplexing function; The Class-AB adjustable current output stage controls the current of the operational amplifier output stage through floating gate voltage feedforward control and a switch structure, thereby achieving controllable power consumption of the operational amplifier; The high transconductance input stage includes a CHOP switch CHOPPER_B, five PMOS transistors M0, M1a, M1b, M2a, M2b and four NMOS transistors M3a, M3b, M4a, M4b, wherein the input ports IN_A and IN_B of CHOPPER_B correspond to the non-inverting input and inverting input of the operational amplifier, the output port OUT_A of CHOPPER_B is connected to the gate of M1a and the gate of M1b, the output port OUTB of CHOPPER_B is connected to the gate of M2a and the gate of M2b, the source of M0 is connected to the power supply voltage VDD, and the output of M0 is connected to the gate of M1a and the gate of M1b. The gate is connected to a fixed bias voltage VBP3, the drain of M0 is connected to the source of M1a, the source of M1b, the source of M2a, and the source of M2b, the drain of M1a is connected to the drain of M3a and serves as the non-inverting output terminal of the high transconductance input stage, the drain of M2a is connected to the drain of M4a and serves as the inverting output terminal of the high transconductance input stage, the drain of M1b is connected to the drain of M4b, the gate of M4b, and the gate of M4a, the drain of M2b is connected to the drain of M3b, the gate of M3b, and the gate of M3a, the source of M3a is connected to the source of M3b, the source of M4a, and the source of M4b and connected to the power supply ground VSS; The gain amplifier stage includes two auxiliary operational amplifiers GBP and GBN, two CHOP switches CHOPPER_P and CHOPPER_N, four PMOS transistors M7 to M10, and two NMOS transistors M5 and M6, wherein the source of M9 is connected to the source of M10 and connected to the power supply voltage VDD, the gate of M9 is connected to the gate of M10, the drain of M7, and the drain of M5, the drain of M9 is connected to the non-inverting input terminal of GBN and the input port IN_A of CHOPPER_P, the drain of M10 is connected to the inverting input terminal of GBN and the input port INB of CHOPPER_P, the output port OUT_A of CHOPPER_P is connected to the source of M7, and the drain of CHOPPER_P is connected to the inverting input terminal of GBN and the input port INB of CHOPPER_P. The output port OUTB is connected to the source of M8, the non-inverting output terminal of GBN is connected to the gate of M7, the inverting output terminal of GBN is connected to the gate of M8, the drain of M8 is connected to the drain of M6, the source of M5 is connected to the input port IN_A of CHOPPER_N, the source of M6 is connected to the input port IN_B of CHOPPER_N, the non-inverting input terminal of GBP is connected to the output port OUT_A of CHOPPER_N and the non-inverting output terminal of the high transconductance input stage, the inverting input terminal of GBP is connected to the output port OUTB of CHOPPER_N and the inverting output terminal of the high transconductance input stage, the non-inverting output terminal of GBP is connected to the gate of M5, and the inverting output terminal of GBP is connected to the gate of M6.

2. The high-precision, low-noise, low-power programmable gain amplifier according to claim 1, wherein: The adjustable resistor array includes six high-linearity double-throw switches SW1 to SW6 and six pairs of resistors R1a and R1b, R2a and R2b, R3a and R3b, R4a and R4b, R5a and R5b, and R6a and R6b. The two resistors in each pair have the same resistance value, wherein one end of R6a is connected to the VOUTa terminal of SW6 and serves as the PORT_A port of the adjustable resistor array, the other end of R6a is connected to one end of R5a and the VOUTa terminal of SW5, the other end of R5a is connected to one end of R4a and the VOUTa terminal of SW4, the other end of R4a is connected to one end of R3a and the VOUTa terminal of SW3, the other end of R3a is connected to one end of R2a and the VOUTa terminal of SW2, the other end of R2a is connected to one end of R1a and the VOUTa terminal of SW1, and the other end of R1a is connected to the VOUTa terminal of R1b. One end of R1b is connected to another end of R2b, the other end of R2b is connected to another end of R3b and the VOUTb end of SW2, the other end of R3b is connected to another end of R4b and the VOUTb end of SW3, the other end of R4b is connected to another end of R5b and the VOUTb end of SW4, the other end of R5b is connected to another end of R6b and the VOUTb end of SW5, the other end of R6b is connected to the VOUTb end of SW6 and serves as the PORT_B port of the adjustable resistor array, the VINa ends of SW1 to SW6 are connected in common and serve as the PORT_C port of the adjustable resistor array, the VINb ends of SW1 to SW6 are connected in common and serve as the PORT_D port of the adjustable resistor array, and the opening and closing of SW1 to SW6 are controlled by six pairs of digital logic signals provided by the digital control module; The PORT_A port of the adjustable resistor array is connected to the output end of A1, the PORT_B port is connected to the output end of A2, the PORT_C port is connected to the inverting input end of A1, and the PORT_D port is connected to the inverting input end of A2.

3. The high-precision, low-noise, low-power programmable gain amplifier according to claim 2, wherein: The high linearity double throw switches SW1 to SW6 have the same structure, including 8 PMOS transistors P1a, P2a, P3a, P4a, P1b, P2b, P3b, P4b and 8 NMOS transistors P5a, P6a, P7a, P8a, P5b, P6b, P7b, P8b, wherein the source of P1a is connected to the source of P1b and connected to the power supply voltage VDD, and the gate of P1a is connected to the gate of P8a, the gate of P7a, the gate of P6a The gate of P1a is connected to the gate of P8a, the gate of P2a, the gate of P7b and the gate of P6b and connected to RS-, the gate of P2a is connected to the gate of P2b, the gate of P3a, the gate of P3b, the gate of P4a, the gate of P4b, the gate of P5a and the gate of P5b and connected to RS+, the drain of P1a is connected to the drain of P8a, the source of P2a and the substrate of P3a, the drain of P1b is connected to the drain of P8b, the drain of P2b The source of P8a is connected to the drain of P2a, the drain of P7a and the source of P3a and serves as the VINa terminal of the double-throw switch. The source of P8b is connected to the drain of P2b, the drain of P7b and the source of P3b and serves as the VINb terminal of the double-throw switch. The source of P7a is connected to the drain of P3a, the drain of P6a and the source of P4a and serves as the VOUTa terminal of the double-throw switch. The source of P7b is connected to the drain of P3a, the drain of P6a and the source of P4a and serves as the VOUTa terminal of the double-throw switch. The drain of P3b, the drain of P6b and the source of P4b are connected and serve as the VOUTb terminal of the double-throw switch. The source of P6a is connected to the drain of P4a, the drain of P5a and the substrate of P7a. The source of P6b is connected to the drain of P4b, the drain of P5b and the substrate of P7b. The source of P5a is connected to the source of P5b and connected to the power ground VSS. RS+ and RS- are a pair of mutually inverted digital logic signals provided by the digital control module.

4. The high-precision, low-noise, low-power programmable gain amplifier according to claim 1, wherein: The auxiliary operational amplifier GBP includes eight PMOS transistors PM0, PM1, PM2, PM3, PM8, PM9, PM10 and PM11, four NMOS transistors PM4, PM5, PM6, PM7 and two CHOP switches CHOPPER_P1 and CHOPPER_N1, wherein the source of PM0 is connected to the source of PM10, the source of PM11 and the source of PM1 and is connected to the power supply voltage VDD, and the gate of PM0 is connected to the gate of PM1 and is connected to the fixed bias voltage V BP3, the drain of PM0 is connected to the source of PM2, the drain of PM1 is connected to the source of PM3, the gate of PM2 and the gate of PM3 are used as the non-inverting input and inverting input of the auxiliary operational amplifier GBP respectively, the gate of PM10 is connected to the gate of PM11 and connected to the fixed bias voltage VBP1, the drain of PM10 is connected to the input port IN_A of CHOPPER_P1, the drain of PM11 is connected to the input port INB of CHOPPER_P1, the source of PM8 is connected to CHOPPE The output port OUT_A of R_P1 is connected, the source of PM9 is connected to the output port OUTB of CHOPPER_P1, the gate of PM8 is connected to the gate of PM9 and connected to the fixed bias voltage VBP2, the drain of PM8 is connected to the drain of PM6 and serves as the inverting output terminal of the auxiliary operational amplifier GBP, the drain of PM9 is connected to the drain of PM7 and serves as the inverting output terminal of the auxiliary operational amplifier GBP, the gate of PM6 is connected to the gate of PM7 and connected to the fixed bias voltage VBN2, the source of PM6 is connected to CH The input port IN_A of OPPER_N1 is connected, the source of PM7 is connected to the input port INB of CHOPPER_N1, the drain of PM2 is connected to the drain of PM4 and the output port OUT_A of CHOPPER_N1, the drain of PM3 is connected to the drain of PM5 and the output port OUTB of CHOPPER_N1, the gate of PM4 is connected to the gate of PM5 and connected to the fixed bias voltage VBN1, and the source of PM4 is connected to the source of PM5 and connected to the power ground VSS.

5. The high-precision, low-noise, low-power programmable gain amplifier according to claim 1, wherein: The auxiliary operational amplifier GBN includes eight NMOS transistors NM0, NM1, NM2, NM3, NM4, NM5, NM6 and NM7, four PMOS transistors NM8, NM9, NM10 and NM11, and two CHOP switches CHOPPER_P2 and CHOPPER_N2, wherein the source of NM0 is connected to the source of NM1, the source of NM4 and the source of NM5 and to the power ground VSS, the gate of NM0 is connected to the gate of NM1 and to the fixed bias voltage VBN3, The drain of NM0 is connected to the source of NM2, the drain of NM1 is connected to the source of NM3, the gate of NM2 and the gate of NM3 serve as the non-inverting input and inverting input of the auxiliary operational amplifier GBN respectively, the gate of NM4 is connected to the gate of NM5 and connected to the fixed bias voltage VBN1, the drain of NM5 is connected to the output port OUT_A of CHOPPER_N2, the drain of NM4 is connected to the output port OUT_B of CHOPPER_N2, the source of NM7 is connected to the output port OUT_B of CHOPPER_N2 The input port IN_A is connected, the source of NM6 is connected to the input port INB of CHOPPER_N2, the gate of NM6 is connected to the gate of NM7 and connected to the fixed bias voltage VBN2, the drain of NM7 is connected to the drain of NM9 and serves as the non-inverting output terminal of the auxiliary op amp GBN, the drain of NM6 is connected to the drain of NM8 and serves as the inverting output terminal of the auxiliary op amp GBN, the gate of NM8 is connected to the gate of NM9 and connected to the fixed bias voltage VBP2, the source of NM9 is connected to CHOPPER_P The output port OUT_A of CHOPPER_P2 is connected to the source of NM8, the output port OUTB of CHOPPER_P2 is connected to the drain of NM11, the drain of NM11 is connected to the drain of NM2 and the input port IN_A of CHOPPER_P2, the drain of NM10 is connected to the drain of NM3 and the input port INB of CHOPPER_P2, the gate of NM10 is connected to the gate of NM11 and connected to the fixed bias voltage VBP1, and the source of NM10 is connected to the source of NM11 and connected to the power supply voltage VDD.

6. The high-precision, low-noise, low-power programmable gain amplifier according to claim 4 or 5, characterized in that: The CHOP switches CHOPPER_B, CHOPPER_P, CHOPPER_N, CHOPPER_P1, CHOPPER_P2, CHOPPER_N1, and CHOPPER_N2 have the same structure and include four switch modules K1 to K4, wherein the input end of K1 is connected to the input end of K2 and serves as the input port IN_A of the CHOP switch, the output end of K1 is connected to the output end of K3 and serves as the output port OUT_A of the CHOP switch, the input end of K3 is connected to the input end of K4 and serves as the input port INB of the CHOP switch, and the output end of K2 is connected to the output end of K4 and serves as the output port OUT_B of the CHOP switch; the switch modules K1 to K4 in the CHOP switches CHOPPER_P, CHOPPER_P1, and CHOPPER_P2 use PMOS transistors, the switch modules K1 to K4 in CHOPPER_N, CHOPPER_N1, and CHOPPER_N2 use NMOS transistors, and the switch modules K1 to K4 in CHOPPER_B use bootstrap switches.

7. The high-precision, low-noise, low-power programmable gain amplifier according to claim 6, characterized in that: The bootstrap switch includes a capacitor C1, four PMOS transistors SM1, SM2, SM3, SM6 and seven NMOS transistors SM4, SM5, SM7, SM8, SM9, SM10 and SM11, wherein the drain of SM1 is connected to the source of SM6, the gate of SM4 and the source of SM2 and is connected to the power supply voltage VDD, the gate of SM1 is connected to the drain of SM3, the drain of SM4, the gate of SM8, the gate of SM9 and the gate of SM10, the source of SM1 is connected to one end of C1 and the source of SM3, and the other end of C1 is connected to the drain of SM11, the source of SM7, the source of SM8 and the gate of SM10. The drain of SM9 is connected, the source of SM11 is connected to the power ground VSS, the gate of SM11 is connected to CLK1, the gate of SM6 is connected to the gate of SM7 and to CLK2, the drain of SM6 is connected to the drain of SM7, the gate of SM3 and the drain of SM8, the drain of SM2 is connected to the source of SM4 and the drain of SM5, the gate of SM2 is connected to the gate of SM5 and to CLK1, the source of SM5 is connected to the power ground VSS, the source of SM9 is connected to the drain of SM10 and serves as the input end of the switch module, the source of SM10 serves as the output end of the switch module, and CLK1 and CLK2 are a pair of mutually inverse clock signals provided by the digital control module.

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