Drive circuit and signal conversion circuit

Abstract

A driving circuit includes a first push-pull circuit and a second push-pull circuit, each including a first output terminal and a second output terminal and first to fourth transistors. The first to fourth transistors are coupled in series. At least one of control terminals of the first and second transistors of the first push-pull circuit and at least one of control terminals of the third and fourth transistors of the second push-pull circuit receive a positive input signal, and at least one of control terminals of the third and fourth transistors of the first push-pull circuit and at least one of control terminals of the first and second transistors of the second push-pull circuit receive a negative input signal; the first output terminals of the first and second push-pull circuits output a first positive signal and a first negative signal, respectively; and the second output terminals of the first and second push-pull circuits output a second negative signal and a second positive signal, respectively.

Description

Technical Field

[0001] This invention relates to a driving circuit and a signal conversion circuit, and more particularly to a driving circuit and a signal conversion circuit that includes a splitting circuit. Background Technology

[0002] When the amplitude of a differential signal is amplified or reduced, one of the positive and negative signals draws energy from the power supply, while the other releases energy to ground. Because the released energy cannot be reused, the circuit's energy utilization efficiency is poor. Therefore, how to effectively utilize the energy in a circuit has become a pressing problem in this field. Summary of the Invention

[0003] This invention discloses a driving circuit comprising a first push-pull circuit and a second push-pull circuit. Each of the first and second push-pull circuits includes a first output terminal, a second output terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled between a first reference voltage and the first output terminal; the second transistor is coupled between the first output terminal and a circuit node; the third transistor is coupled between the circuit node and the second output terminal; and the fourth transistor is coupled between the second output terminal and the second reference voltage. At least one of the control terminals of the first transistor and the second transistor in the first push-pull circuit, and at least one of the control terminals of the third transistor and the fourth transistor in the second push-pull circuit, are used to receive the positive input signal of a pair of differential input signals. At least one of the control terminals of the third transistor and the fourth transistor in the first push-pull circuit, and at least one of the control terminals of the first transistor and the second transistor in the second push-pull circuit, are used to receive the negative input signal of the differential input signal. The first output terminals of the first push-pull circuit and the second push-pull circuit are used to output the first positive signal and the first negative signal of the first pair of differential output signals, respectively. The second output terminals of the first push-pull circuit and the second push-pull circuit are used to output the second negative signal and the second positive signal of the second pair of differential output signals, respectively.

[0004] This invention discloses a signal conversion circuit, comprising a sampling circuit and a driving circuit. The sampling circuit samples a first pair of differential output signals and a second pair of differential output signals to generate a pair of differential conversion signals. The driving circuit is coupled to the sampling circuit and generates the first pair of differential output signals and the second pair of differential output signals based on a pair of differential input signals. The driving circuit includes a first push-pull circuit and a second push-pull circuit. The first push-pull circuit has a first output terminal and a second output terminal, and generates a first positive terminal signal of the first pair of differential output signals and a second negative terminal signal of the second pair of differential output signals at the first output terminal based on the positive and negative input signals of the differential input signals. The second push-pull circuit has a third output terminal and a fourth output terminal, and generates a first negative terminal signal of the first pair of differential output signals at the third output terminal and a second positive terminal signal of the second pair of differential output signals at the fourth output terminal based on the positive and negative input signals. When the positive input signal increases and the negative input signal decreases, some of the charge on the third output terminal is transferred to the fourth output terminal, causing the first negative signal to decrease and the second positive signal to increase.

[0005] The driving circuit and signal conversion circuit of the present invention effectively utilize the energy that would otherwise be released to the ground terminal, thereby improving the efficiency of energy utilization. Attached Figure Description

[0006] The various forms of the invention can be best understood by reading the following embodiments and accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0007] Figure 1 This is a schematic diagram of a signal conversion circuit in some embodiments of the present invention.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 This is a schematic diagram of the driving circuit in some embodiments of the present invention.

[0009] Figure 7 and Figure 8 This is a schematic diagram of the sampling circuit in some embodiments of the present invention. Detailed Implementation

[0010] Figure 1This is a schematic diagram of a signal conversion circuit 10 according to some embodiments of the present invention. The signal conversion circuit 10 includes a driving circuit 100 and a sampling circuit 200. The driving circuit 100 is used to receive a pair of differential input signals V0 and output a pair of differential output signals V1 and a pair of differential output signals V2. The sampling circuit 200 is used to sample the differential output signals V1 and V2 to generate a pair of differential conversion signals V3. In some embodiments, the driving circuit 100 is a split differential signal buffer.

[0011] Specifically, the drive circuit 100 includes a push-pull circuit 110 and a push-pull circuit 120. Push-pull circuit 110 receives the positive signal Vip and the negative signal Vin from the differential input signal V0 to generate the positive signal Vop1 in the differential output signal V1 and the negative signal Von2 in the differential output signal V2. Push-pull circuit 120 receives the positive signal Vip and the negative signal Vin to generate the negative signal Von1 in the differential output signal V1 and the positive signal Vop2 in the differential output signal V2. Sampling circuit 200 samples the positive signals Vop1 and Vop2, and samples the negative signals Von1 and Von2. Then, sampling circuit 200 converts the sampled signals into the positive signal Vops and the negative signal Vons in the differential conversion signal V3.

[0012] The relationship between the differential input signal V0, the differential output signals V1 and V2, and the differential conversion signal V3 can be represented by the following equations.

[0013] Vop1 = Vcm1 + a * Vip.

[0014] Von1 = Vcm1 + a*Vin.

[0015] Vop2 = Vcm2 + b * Vip.

[0016] Von2 = Vcm2 + b*Vin.

[0017] Vops-Vons=(a*c+b*d)*(Vip-Vin).

[0018] Wherein, Vcm1 is the common-mode voltage of the differential output signal V1 (including the positive terminal signal Vop1 and the negative terminal signal Von1), Vcm2 is the common-mode voltage of the differential output signal V2 (including the positive terminal signal Vop2 and the negative terminal signal Von2), a and b are the gain values ​​provided by the driving circuit 100, and c and d are the gain values ​​provided by the sampling circuit 200. In some embodiments, the common-mode voltage Vcm1 and the common-mode voltage Vcm2 are the same. In other embodiments, the common-mode voltage Vcm1 and the common-mode voltage Vcm2 are different.

[0019] refer to Figure 2 . Figure 2 This is a schematic diagram of a drive circuit 100 according to some embodiments of the present invention.

[0020] The push-pull circuit 110 includes output terminals N1 and N2, transistors M1, M2, M3, and M4, capacitors C1, C2, C3, and C4, and resistors R1, R2, R3, and R4. The first terminal (which may be source / drain depending on the transistor type) 11 of transistor M1 receives a reference voltage VDD1; the second terminal 12 of transistor M1 is coupled to the first terminal 21 of transistor M2, wherein the second terminal 12 of transistor M1 and the first terminal 21 of transistor M2 are used to generate a positive signal Vop1 at output terminal N1; the second terminal 22 of transistor M2 is coupled to the first terminal 31 of transistor M3; the second terminal 32 of transistor M3 is coupled to the first terminal 41 of transistor M4, wherein the second terminal 32 of transistor M3 and the first terminal 41 of transistor M4 are used to generate a negative signal Von2 at output terminal N2; the second terminal 42 of transistor M4 receives a reference voltage VDD2, wherein the reference voltage VDD1 is higher than the reference voltage VDD2. In some embodiments, the reference voltage VDD2 is ground voltage. The control terminals G1 to G4 of transistors M1 to M4 are respectively coupled to the first terminals of resistors R1 to R4. The second terminals of resistors R1 to R4 are used to receive bias voltages Vbn1, Vbp1, Vbn2, and Vbp2, respectively. The first terminal of capacitor C1 is coupled to the first terminal of capacitor C2 and is used to receive the positive terminal signal Vip; the second terminal of capacitor C1 is coupled to the control terminal G1; the second terminal of capacitor C2 is coupled to the control terminal G2. The first terminal of capacitor C3 is coupled to the first terminal of capacitor C4 and is used to receive the negative terminal signal Vin; the second terminal of capacitor C3 is coupled to the control terminal G3; the second terminal of capacitor C4 is coupled to the control terminal G4.

[0021] Push-pull circuits 110 and 120 are symmetrically arranged. Push-pull circuit 120 includes output terminals N3 and N4, transistors M5, M6, M7, and M8, capacitors C5, C6, C7, and C8, and resistors R5, R6, R7, and R8. The first terminal 51 of transistor M5 receives a reference voltage VDD1; the second terminal 52 of transistor M5 is coupled to the first terminal 61 of transistor M6, wherein the second terminal 52 of transistor M5 and the first terminal 61 of transistor M6 are used to generate a negative signal Von1 at output terminal N3; the second terminal 62 of transistor M6 is coupled to the first terminal 71 of transistor M7; the second terminal 72 of transistor M7 is coupled to the first terminal 81 of transistor M8, wherein the second terminal 72 of transistor M7 and the first terminal 81 of transistor M8 are used to generate a positive signal Vop2 at output terminal N4; the second terminal 82 of transistor M8 receives the reference voltage VDD2. The control terminals G5 to G8 of transistors M5 to M8 are respectively coupled to the first terminals of resistors R5 to R8. The second terminals of resistors R5 to R8 are used to receive bias voltages Vbn1, Vbp1, Vbn2, and Vbp2, respectively. The first terminal of capacitor C5 is coupled to the first terminal of capacitor C6 and is used to receive the negative terminal signal Vin; the second terminal of capacitor C5 is coupled to the control terminal G5; the second terminal of capacitor C6 is coupled to the control terminal G6. The first terminal of capacitor C7 is coupled to the first terminal of capacitor C8 and is used to receive the positive terminal signal Vip; the second terminal of capacitor C7 is coupled to the control terminal G7; the second terminal of capacitor C8 is coupled to the control terminal G8.

[0022] In some embodiments, the push-pull circuit 110 further includes capacitors Cn1 and Cn2. Capacitor Cn1 is coupled between the output terminal N1 and the ground terminal, and capacitor Cn2 is coupled between the output terminal N2 and the ground terminal. Similarly, in some embodiments, the push-pull circuit 120 further includes capacitors Cn3 and Cn4. Capacitor Cn3 is coupled between the output terminal N3 and the ground terminal, and capacitor Cn4 is coupled between the output terminal N4 and the ground terminal.

[0023] exist Figure 2 In the embodiments, transistors M1, M3, M5, and M7 are N-type transistors, and transistors M2, M4, M6, and M8 are P-type transistors.

[0024] In some embodiments, transistors M1, M3, M5, and M7 are pull-up transistors, and transistors M2, M4, M6, and M8 are pull-down transistors.

[0025] When the positive terminal signal Vip increases and the negative terminal signal Vin decreases, in the push-pull circuit 110, the increase in the positive terminal signal Vip makes transistor M1 easier to turn on and transistor M2 more difficult to turn on. The increased current (i.e., more energy) drawn by transistor M1 from the reference voltage VDD1 causes more charge to accumulate at the output terminal N1, thus increasing the positive terminal signal Vop1. Conversely, the decrease in the negative terminal signal Vin makes transistor M3 more difficult to turn on and transistor M4 easier to turn on. The charge accumulated at the output terminal N2 is released to the reference voltage VDD2 through transistor M4, causing the negative terminal signal Von2 to decrease.

[0026] Simultaneously, when the positive terminal signal Vip increases and the negative terminal signal Vin decreases, in the push-pull circuit 120, the decrease in the negative terminal signal Vin makes transistor M5 more difficult to turn on and transistor M6 more easy to turn on. The charge accumulated at the output terminal N3 is released to transistor M7 through transistor M6, causing the negative terminal signal Von1 to decrease. The increase in the positive terminal signal Vip makes transistor M7 more easy to turn on and transistor M8 more difficult to turn on. The charge released from the output terminal N3 is further transferred to the output terminal N4 through transistor M7 after passing through transistor M6, causing the positive terminal signal Vop2 to increase. Specifically, when the positive terminal signal Vip increases and the negative terminal signal Vin decreases, the positive terminal signals Vop1 and Vop2 also increase, while the negative terminal signals Von1 and Von2 decrease. However, for the positive terminal signal Vop2, at least part of the energy required for the increase of the positive terminal signal Vop2 is provided by the energy released by the decrease of the negative terminal signal Von1. In other words, under these circumstances, the energy required for the positive terminal signal Vop2 to rise does not necessarily have to be drawn entirely from the reference voltage VDD1, but can be provided by the energy released from other parts of the circuit. Compared to the prior art, the present invention has better energy utilization efficiency.

[0027] When the positive signal Vip decreases and the negative signal Vin increases, in the push-pull circuit 110, the decrease in the positive signal Vip makes transistor M1 more difficult to turn on and transistor M2 more easy to turn on. The charge accumulated at the output terminal N1 is released through transistor M2 to transistor M3, causing the positive signal Vop1 to decrease. The increase in the negative signal Vin makes transistor M3 more easy to turn on and transistor M4 more difficult to turn on. The charge released from the output terminal N1 is further transferred through transistor M2 and then through transistor M3 to the output terminal N2, causing the negative signal Von2 to increase. Specifically, when the positive signal Vip decreases and the negative signal Vin increases, at least part of the energy required for the negative signal Von2 to increase is provided by the energy released by the decrease in the positive signal Vop1. In other words, in this case, the energy required for the negative signal Von2 to increase may not be entirely drawn from the reference voltage VDD1, but may be provided by the energy released from other parts of the circuit.

[0028] Simultaneously, when the positive terminal signal Vip decreases and the negative terminal signal Vin increases, in the push-pull circuit 120, the increased negative terminal signal Vin makes transistor M5 easier to turn on and transistor M6 more difficult to turn on. Transistor M5 draws more current from the reference voltage VDD1, causing more charge to accumulate at the output terminal N3, thus increasing the negative terminal signal Von1. Conversely, the decreased positive terminal signal Vip makes transistor M7 more difficult to turn on and transistor M8 easier to turn on. The charge accumulated at the output terminal N4 is released to the reference voltage VDD2 through transistor M8, causing the positive terminal signal Vop2 to decrease.

[0029] The push-pull circuits 110 and 120 of the present invention are not limited to... Figure 2 The illustrated configuration. Various configurations of push-pull circuits 110 and 120 are all within the scope of this invention. For example, in various embodiments, push-pull circuits 110 and 120 can be as follows: Figures 3-6 The configuration shown in the diagram is implemented.

[0030] refer to Figure 3 Compared to Figure 2 In the embodiments described, push-pull circuit 110 does not include capacitors C2 and C4, and push-pull circuit 120 does not include capacitors C6 and C8. Furthermore, transistors M1 to M8 are all N-type transistors.

[0031] refer to Figure 4 Compared to Figure 2 In the embodiments described, push-pull circuit 110 does not include capacitors C1 and C3, and push-pull circuit 120 does not include capacitors C5 and C7. Furthermore, transistors M1 to M8 are all P-type transistors.

[0032] refer to Figure 5 Compared to Figure 2 In the embodiments described, push-pull circuit 110 does not include capacitors C2 and C3, and push-pull circuit 120 does not include capacitors C6 and C7. Furthermore, transistors M1, M2, M5, and M6 are N-type transistors, and transistors M3, M4, M7, and M8 are P-type transistors.

[0033] refer to Figure 6 Compared to Figure 2 In the embodiments, push-pull circuit 110 does not include capacitors C1 and C4, and push-pull circuit 120 does not include capacitors C5 and C8. Furthermore, transistors M1, M2, M5, and M6 are P-type transistors, and transistors M3, M4, M7, and M8 are N-type transistors.

[0034] For the sake of brevity, Figures 3-6 Some reference numbers in the middle are omitted, and because Figures 3-6 The operation method of the embodiment and Figure 2 The operation method is similar to that of the embodiments, and will not be described again here.

[0035] based on Figures 2-6 In this embodiment, at least one of the control terminals G1 and G2 of transistors M1 and M2 in push-pull circuit 110 and at least one of the control terminals G7 and G8 of transistors M7 and M8 in push-pull circuit 120 are used to receive the positive input signal Vip; at least one of the control terminals G3 and G4 of transistors M3 and M4 in push-pull circuit 110 and at least one of the control terminals G5 and G6 of transistors M5 and M6 in push-pull circuit 120 are used to receive the negative input signal Vin; the output terminals N1 and N3 of push-pull circuits 110 and 120 are used to output the positive signal Vop1 and the negative signal Von1, respectively; the output terminals N2 and N4 of push-pull circuits 110 and 120 are used to output the negative signal Von2 and the positive signal Vop2, respectively.

[0036] refer to Figure 7 . Figure 7This is a schematic diagram illustrating a sampling circuit 200 according to some embodiments of the present invention. The sampling circuit 200 includes a sampling capacitor array A1, a sampling capacitor array A2, and a processing circuit 210. In some embodiments, the sampling circuit 200 operates as a successive approximation register analog-to-digital converter (SAR ADC), and the processing circuit 210 is a comparator. In other embodiments, the sampling circuit 200 operates as a pipeline analog-to-digital converter (pipeline ADC), and the processing circuit 210 is an amplifier. In some embodiments, the switching operation of the sampling capacitor arrays A1 and A2 is the same as that of a typical SAR ADC or pipeline ADC.

[0037] The sampling capacitor array A1 includes capacitors CA1, CA2, and CA3 and switches S1, S2, S3, and S4. The first terminals of capacitors CA1, CA2, and CA3 serve as the first terminal of the sampling capacitor array A1, coupled to the input terminal 211 of the processing circuit 210. Based on switch S4, they selectively receive the positive terminal signal Vop1 and generate the sampling signal SS1. The second terminals of capacitors CA1, CA2, and CA3 are respectively coupled to the first terminals of switches S1, S2, and S3. The second terminals of switches S1, S2, and S3 serve as the second terminals of the sampling capacitor array A1 and are selectively used to receive the negative terminal signal Von2 or the reference voltage VR1. During sampling, switches S1, S2, and S3 couple the second terminals of capacitors CA1, CA2, and CA3 to the negative terminal signal Von2. After sampling, the second terminals of capacitors CA1, CA2, and CA3 are coupled to the reference voltage VR1.

[0038] The sampling capacitor array A2 includes capacitors CA4, CA5, and CA6 and switches S5, S6, S7, and S8. The first terminals of capacitors CA4, CA5, and CA6 serve as the first terminal of the sampling capacitor array A2, coupled to the input terminal 212 of the processing circuit 210. Based on switch S8, they selectively receive the negative terminal signal Von1 and generate the sampling signal SS2. The second terminals of capacitors CA4, CA5, and CA6 are respectively coupled to the first terminals of switches S5, S6, and S7. The second terminals of switches S5, S6, and S7 serve as the second terminals of the sampling capacitor array A2 and are selectively used to receive the positive terminal signal Vop2 or the reference voltage VR1. During sampling, switches S5, S6, and S7 couple the second terminals of capacitors CA4, CA5, and CA6 to the positive terminal signal Vop2. After sampling, switches S5, S6, and S7 couple the second terminals of capacitors CA4, CA5, and CA6 to the reference voltage VR1.

[0039] The processing circuit 210 generates a differential conversion signal V3 based on the sampled signal SS1 and the sampled signal SS2.

[0040] exist Figure 7 In the embodiments, the positive terminal signal Vop1 and the positive terminal signal Vop2 can be interchanged, and the negative terminal signal Von1 and the negative terminal signal Von2 can also be interchanged.

[0041] In some embodiments, the capacitance values ​​of capacitors CA1, CA2, and CA3 are in a ratio of 4:2:1, and the capacitance values ​​of capacitors CA4, CA5, and CA6 are in a ratio of 4:2:1. Specifically, the capacitance values ​​of capacitors CA1, CA2, and CA3 are the same as the capacitance values ​​of capacitors CA4, CA5, and CA6, respectively.

[0042] The sampling circuit 200 is not limited to Figure 7 The illustrated embodiment. In other embodiments, the sampling capacitor arrays A1 and A2 can be as follows: Figure 8 The configuration shown is implemented.

[0043] refer to Figure 8 The sampling capacitor array A1 includes capacitors CA11, CA12, CA21, CA22, CA31, and CA32, and switches S11, S12, S21, S22, S31, S32, and S4. The first terminals of capacitors CA11, CA12, CA21, CA22, CA31, and CA32 serve as the first terminal of the sampling capacitor array A1, coupled to the input terminal 211 of the processing circuit 210. Based on switch S4, they selectively receive the reference signal VR2 and generate the sampling signal SS1. The second terminals of capacitors CA11, CA12, CA21, CA22, CA31, and CA32 are respectively coupled to the first terminals of switches S11, S12, S21, S22, S31, and S32. The second terminals of switches S11, S21, and S31 serve as the second terminals of sampling capacitor array A1 and are selectively used to receive either the positive terminal signal Vop1 or the reference signal VR3. Similarly, the second terminals of switches S12, S22, and S32 also serve as the second terminals of sampling capacitor array A1 and are selectively used to receive either the positive terminal signal Vop2 or the reference signal VR4. During sampling, switches S11, S21, and S31 couple the second terminals of capacitors CA11, CA21, and CA31 to the positive terminal signal Vop1, and switches S12, S22, and S32 couple the second terminals of capacitors CA12, CA22, and CA32 to the positive terminal signal Vop2. After sampling, switches S11, S21, and S31 couple the second terminals of capacitors CA11, CA21, and CA31 to the reference voltage VR3, and switches S12, S22, and S32 couple the second terminals of capacitors CA12, CA22, and CA32 to the reference voltage VR4.

[0044] The sampling capacitor array A2 includes capacitors CA41, CA42, CA51, CA52, CA61, and CA62, and switches S41, S42, S51, S52, S61, S62, and S8. The first terminals of capacitors CA41, CA42, CA51, CA52, CA61, and CA62 are coupled to the input terminal 212 of the processing circuit 210, selectively receiving the reference signal VR2 and generating the sampling signal SS2 according to switch S8. The second terminals of capacitors CA41, CA42, CA51, CA52, CA61, and CA62 are respectively coupled to the first terminals of switches S41, S42, S51, S52, S61, and S62. The second terminals of switches S41, S51, and S61 serve as the second terminals of sampling capacitor array A2 and are selectively used to receive either the negative terminal signal Von1 or the reference signal VR3. Similarly, the second terminals of switches S42, S52, and S62 also serve as the second terminals of sampling capacitor array A2 and are selectively used to receive either the negative terminal signal Von2 or the reference signal VR4. During sampling, switches S41, S51, and S61 couple the second terminals of capacitors CA41, CA51, and CA61 to the negative terminal signal Von1, and switches S42, S52, and S62 couple the second terminals of capacitors CA42, CA52, and CA62 to the negative terminal signal Von2. After sampling, switches S41, S51, and S61 couple the second terminals of capacitors CA41, CA51, and CA61 to the reference voltage VR3, and switches S42, S52, and S62 couple the second terminals of capacitors CA42, CA52, and CA62 to the reference voltage VR4.

[0045] In some embodiments, capacitors CA11, CA12, CA41, and CA42 have the same capacitance value; capacitors CA21, CA22, CA51, and CA52 have the same capacitance value; and capacitors CA31, CA32, CA61, and CA62 have the same capacitance value. The capacitance ratio of capacitors CA11, CA21, and CA31 is 4:2:1, and the capacitance ratio of capacitors CA41, CA51, and CA61 is 4:2:1.

[0046] It should be understood that the number of capacitors in sampling capacitor arrays A1 and A2 is not limited to this. Sampling capacitor arrays A1 and A2 can contain more capacitors, and their capacitance values ​​are not limited to increasing sequentially in multiples of 2.

Claims

1. A driving circuit, comprising: The first push-pull circuit and the second push-pull circuit each include: The first output terminal and the second output terminal; and The first transistor, the second transistor, the third transistor, and the fourth transistor, wherein, The first transistor is coupled between the first reference voltage and the first output terminal; the second transistor is coupled between the first output terminal and the circuit node; the third transistor is coupled between the circuit node and the second output terminal; and the fourth transistor is coupled between the second output terminal and the second reference voltage. In this circuit, at least one of the control terminals of the first and second transistors in the first push-pull circuit, and at least one of the control terminals of the third and fourth transistors in the second push-pull circuit, are used to receive the positive input signal of a pair of differential input signals. Additionally, at least one of the control terminals of the third and fourth transistors in the first push-pull circuit, and at least one of the control terminals of the first and second transistors in the second push-pull circuit, are used to receive the negative input signal of the pair of differential input signals. The first output terminal of the first push-pull circuit and the second push-pull circuit are respectively used to output the first positive terminal signal and the first negative terminal signal of the first pair of differential output signals; the second output terminal of the first push-pull circuit and the second push-pull circuit are respectively used to output the second negative terminal signal and the second positive terminal signal of the second pair of differential output signals.

2. The driving circuit as claimed in claim 1, wherein, The first and third transistors of the first push-pull circuit and the first and third transistors of the second push-pull circuit are N-type transistors, while the second and fourth transistors of the first push-pull circuit and the second push-pull circuit are P-type transistors. The first push-pull circuit and the second push-pull circuit each further include a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. In this circuit, the first and second capacitors of the first push-pull circuit, and the first terminals of the third and fourth capacitors of the second push-pull circuit, are each used to receive the positive input signal. The second terminals of the first and second capacitors of the first push-pull circuit, and the third and fourth capacitors of the second push-pull circuit, are respectively coupled to the control terminals of the first and second transistors of the first push-pull circuit, and the third and fourth transistors of the second push-pull circuit. The first terminals of the third and fourth capacitors of the first push-pull circuit and the first and second capacitors of the second push-pull circuit are each used to receive the negative input signal, and the second terminals of the third and fourth capacitors of the first push-pull circuit and the first and second capacitors of the second push-pull circuit are respectively coupled to the control terminals of the third and fourth transistors of the first push-pull circuit and the first and second transistors of the second push-pull circuit.

3. The driving circuit as claimed in claim 1, wherein, The first, second, third, and fourth transistors in the first and second push-pull circuits are N-type transistors. The first push-pull circuit and the second push-pull circuit each further include a first capacitor and a second capacitor. In this circuit, the first capacitor of the first push-pull circuit is coupled between the positive input signal and the control terminal of the first transistor of the first push-pull circuit; the second capacitor of the first push-pull circuit is coupled between the negative input signal and the control terminal of the third transistor of the first push-pull circuit; the first capacitor of the second push-pull circuit is coupled between the negative input signal and the control terminal of the first transistor of the second push-pull circuit; and the second capacitor of the second push-pull circuit is coupled between the positive input signal and the control terminal of the third transistor of the second push-pull circuit.

4. The driving circuit as claimed in claim 1, wherein, The first, second, third, and fourth transistors in the first and second push-pull circuits are P-type transistors. The first push-pull circuit and the second push-pull circuit each further include a first capacitor and a second capacitor. In this circuit, the first capacitor of the first push-pull circuit is coupled between the positive input signal and the control terminal of the second transistor of the first push-pull circuit, the second capacitor of the first push-pull circuit is coupled between the negative input signal and the control terminal of the fourth transistor of the first push-pull circuit, the first capacitor of the second push-pull circuit is coupled between the negative input signal and the control terminal of the second transistor of the second push-pull circuit, and the second capacitor of the second push-pull circuit is coupled between the positive input signal and the control terminal of the fourth transistor of the second push-pull circuit.

5. The driving circuit as claimed in claim 1, wherein, The first and second transistors in the first and second push-pull circuits are N-type transistors, and the third and fourth transistors in the first and second push-pull circuits are P-type transistors. The first push-pull circuit and the second push-pull circuit each further include a first capacitor and a second capacitor. In this circuit, the first capacitor of the first push-pull circuit is coupled between the positive input signal and the control terminal of the first transistor of the first push-pull circuit; the second capacitor of the first push-pull circuit is coupled between the negative input signal and the control terminal of the fourth transistor of the first push-pull circuit; the first capacitor of the second push-pull circuit is coupled between the negative input signal and the control terminal of the first transistor of the second push-pull circuit; and the second capacitor of the second push-pull circuit is coupled between the positive input signal and the control terminal of the fourth transistor of the second push-pull circuit.

6. The driving circuit as claimed in claim 1, wherein, The first and second transistors in the first and second push-pull circuits are P-type transistors, and the third and fourth transistors in the first and second push-pull circuits are N-type transistors. The first push-pull circuit and the second push-pull circuit each further include a first capacitor and a second capacitor. In this circuit, the first capacitor of the first push-pull circuit is coupled between the positive input signal and the control terminal of the second transistor of the first push-pull circuit; the second capacitor of the first push-pull circuit is coupled between the negative input signal and the control terminal of the third transistor of the first push-pull circuit; the first capacitor of the second push-pull circuit is coupled between the negative input signal and the control terminal of the second transistor of the second push-pull circuit; and the second capacitor of the second push-pull circuit is coupled between the positive input signal and the control terminal of the third transistor of the second push-pull circuit.

7. A signal conversion circuit, comprising: A sampling circuit is used to sample the first pair of differential output signals and the second pair of differential output signals to generate a pair of differential conversion signals; and A driving circuit, coupled to the sampling circuit, is used to generate the first pair of differential output signals and the second pair of differential output signals based on a pair of differential input signals. The driving circuit includes: A first push-pull circuit has a first output terminal and a second output terminal, used to generate a first positive terminal signal of the first pair of differential output signals and a second negative terminal signal of the second pair of differential output signals at the first output terminal, based on the positive and negative terminal input signals of the pair of differential input signals; and The second push-pull circuit has a third output terminal and a fourth output terminal, used to generate a first negative terminal signal of the first pair of differential output signals at the third output terminal and a second positive terminal signal of the second pair of differential output signals at the fourth output terminal based on the positive terminal input signal and the negative terminal input signal. in, When the positive input signal increases and the negative input signal decreases, a portion of the charge on the third output terminal is transferred to the fourth output terminal, causing the first negative signal to decrease and the second positive signal to increase.

8. The signal conversion circuit as claimed in claim 7, wherein, When the positive input signal decreases and the negative input signal increases, a portion of the charge on the first output terminal is transferred to the second output terminal, causing the first positive signal to decrease and the second negative signal to increase.

9. The signal conversion circuit as claimed in claim 7, wherein, The sampling circuit includes: A first sampling capacitor array is coupled to the first pair of differential output signals and the second pair of differential signals to generate a first sampling signal; The second sampling capacitor array is coupled to the first pair of differential output signals and the second pair of differential signals to generate the second sampling signal; as well as The processing circuit has a first input terminal and a second input terminal, for receiving the first sampled signal and the second sampled signal from the first input terminal and the second input terminal respectively, so as to generate the pair of differential conversion signals.

10. The signal conversion circuit of claim 7, wherein, The first push-pull circuit and the second push-pull circuit each include: The first transistor, the second transistor, the third transistor, and the fourth transistor. In the first push-pull circuit, the first transistor is coupled between the first reference voltage and the first output terminal; the second transistor is coupled between the first output terminal and the first circuit node; the third transistor is coupled between the first circuit node and the second output terminal; and the fourth transistor is coupled between the second output terminal and the second reference voltage. In the second push-pull circuit, the first transistor is coupled between the first reference voltage and the third output terminal, and the second transistor is coupled between the third output terminal and the second circuit node; the third transistor is coupled between the second circuit node and the fourth output terminal, and the fourth transistor is coupled between the fourth output terminal and the second reference voltage. In this circuit, at least one of the control terminals of the first and second transistors of the first push-pull circuit and at least one of the control terminals of the third and fourth transistors of the second push-pull circuit are used to receive the positive input signal. At least one of the control terminals of the third and fourth transistors of the first push-pull circuit and at least one of the control terminals of the first and second transistors of the second push-pull circuit are used to receive the negative input signal. The first output terminal of the first push-pull circuit and the third output terminal of the second push-pull circuit are used to output the first positive signal and the first negative signal, respectively. The second output terminal of the first push-pull circuit and the fourth output terminal of the second push-pull circuit are used to output the second negative signal and the second positive signal, respectively.

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