A high-precision pulse synchronization method supporting cascaded delay compensation

Abstract

The application discloses a high-precision pulse synchronization method supporting cascade delay compensation, and communication network comprises FC-AE switch 1, FC-AE switch 2,..., FC-AE switch N, one or more FC-AE communication nodes are respectively connected to each switch, cascade communication is carried out between the switches through optical fiber cables, a source pulse can be input from any node connected to the switch, the FC-AE node samples the source pulse signal, the rising edge and the falling edge of the signal are respectively composed into two kinds of pulse synchronization frames, and the pulse synchronization frames are sent to the connected FC-AE switch, the FC-AE switch generates a time stamp according to local crystal oscillator timing after being powered on, and simultaneously carries out master switch election and link delay measurement through bidirectional frame interaction at a fixed time, a master switch is elected according to comparison of switch equipment ID values, and the pulse signal is delayed for a corresponding delay time according to the delay value, so that high-precision pulse signal synchronization is completed.

Description

Technical Field

[0001] This invention relates to the field of pulse synchronization technology, and in particular to a high-precision pulse synchronization method that supports cascaded delay compensation. Background Technology

[0002] In complex communication systems, each processing unit requires a unified time base for actuator control. A common application scenario involves triggering a pulse signal when hardware detects a certain system state. This pulse signal is then synchronized to other processing units in the system, thus unifying the execution state of all processing units. Traditional pulse synchronization methods connect processing units via hardware cables. While simple in principle, this method suffers from complex wiring, poor interference resistance, and poor performance in harsh electromagnetic environments. Furthermore, with large-scale systems, it is difficult to ensure consistent cable lengths, resulting in poor synchronization accuracy. Utilizing fiber optic communication and fiber optic networking to transmit pulse signals can significantly improve the interference resistance and synchronization accuracy of pulse synchronization systems.

[0003] Chinese patent application publication CN113972959A proposes a method for FC-AE communication. This method involves encoding the rising and falling edges of a source pulse signal using special 8B / 10B encoding techniques. The encoded information is then transmitted to other FC-AE communication nodes via an FC-AE switching network. Finally, the 8B / 10B encoding is decoded, the pulse is recovered, and delay is compensated at the communication nodes. While this patent proposes a method for calculating the relative pulse delay between communication nodes, it does not consider the differences in the length of the FC-AE switch cascading cables. This results in poor pulse synchronization accuracy when the cable lengths vary significantly, making it unsuitable for pulse synchronization applications involving large spatial areas and long communication distances.

[0004] The most commonly used method for accurate delay measurement is peer-to-peer delay measurement based on the IEEE 1588 protocol. However, this method has two problems in practical use: 1) When power-on initialization or when the master clock source fails, a complex and time-consuming master clock election process is required, which is not suitable for applications such as power control systems that need to quickly synchronize pulses after power-on; 2) The delay measurement process cannot compensate for random errors caused by crystal oscillator frequency jitter and environmental factors such as temperature and humidity, thus adversely affecting the accuracy of pulse synchronization. Summary of the Invention

[0005] The technical problem to be solved by this invention is how to achieve high-precision pulse synchronization through the FC-AE network when the lengths of the cascaded cables of FC-AE switches in the network vary greatly.

[0006] This invention provides a high-precision pulse synchronization method supporting cascaded delay compensation. The method is applied to a pulse synchronization system comprising multiple FC-AE switches, which communicate via fiber optic cables. The method includes the following steps:

[0007] Step 1: Measure the delay of the network link where the pulse synchronization signal is located;

[0008] Step 2: Compensate for the delay of the network link where the pulse synchronization signal is located;

[0009] Step S1 also includes the following steps:

[0010] Step 11: The FC-AE switch in the communication network generates a timestamp by accumulating the count using the local crystal oscillator and checks whether a pulse primitive has been received.

[0011] Step 12: The FC-AE switch that detects the pulse primitive periodically broadcasts a master switch election frame to the network. The election frame contains the device ID of this switch and the frame transmission timestamp.

[0012] Step 13: The FC-AE switch in the network parses the received master switch election frame content, obtains the switch device ID field, and compares it with its own device ID. If the ID field value is greater than the switch device ID, the delay compensation calculation enable flag is set to 1 in the switch, and the received master switch election frame is not forwarded from the other cascade port. Instead, a NACK frame is sent back to the switch that sent the election frame through the receiving cascade port. If the ID field value is less than the switch device ID, the delay compensation calculation enable flag is set to 0, and the master switch election frame is forwarded from the other cascade port to the next level FC-AE switch. An election response frame is sent back from the receiving cascade port. The response frame is forwarded sequentially from the cascade ports of each level of the switch and arrives at the switch that sent the election frame. The response frame content includes the switch device ID, the election frame reception timestamp, and the response frame transmission timestamp.

[0013] Step 14: FC-AE switches that do not detect pulse primitives on non-cascaded ports in the network send their own election response frames through the election frame receiving port after receiving the election frame. The response frames contain the switch's device ID, the election frame receiving timestamp, and the response frame sending timestamp.

[0014] Step 15: When the FC-AE switch receives a total of N-1 acknowledgment frames or NACK frames, if the delay compensation calculation enable flag remains at 1, this switch becomes the master switch and begins to perform link delay calculation; during the reception of N-1 acknowledgment frames, if the delay compensation calculation enable flag is 0 once, the delay compensation calculation enable flag remains at 0.

[0015] Step 16: The master switch calculates the link delay between the master switch and other switches based on the timestamp of sending the election frame, the timestamp of receiving the election frame and sending the response frame carried by other switches in the response frame, and the timestamp of receiving the response frame by the master switch.

[0016] Step 17: After the master switch has calculated the link delay, it begins to calculate the delay difference between the pulse source of the master switch and the pulses recovered on each node.

[0017] Step S2 also includes the following steps:

[0018] Step 21: The main switch generates a dataset consisting of the measured delay values;

[0019] Step 22: Perform least-squares fitting on the delay measurements in the dataset;

[0020] Step 23: Use the least squares fitted value as the new delay compensation value to obtain the delay value that each FC-AE node needs to compensate after the Kth fitting.

[0021] Step 24: The main switch performs the (K+1)th delay measurement to obtain the (K+1)th sample dataset.

[0022] Step 25: Update the Kth sample dataset to the (K+1)th sample dataset;

[0023] Step 26: Perform polynomial fitting again on the K+1th sample dataset, and use the obtained delay compensation value as the delay compensation value after iterative update to obtain the delay value that each FC-AE node needs to compensate after iterative update.

[0024] Step 27: The main switch sends the calculated delay compensation value to the FC-AE communication node through FC-AE frame interaction. The FC-AE communication node outputs the recovered pulse after lagging behind the corresponding delay value according to the received delay value, thereby achieving high-precision pulse synchronization.

[0025] Furthermore, in step S16, the clock cycle for the switch timestamp generation logic is:

[0026] pdelay j =(T2) j -T3 j +T4j -T1)×period / 2

[0027] The timestamp for sending the election frame is denoted as T1, and the timestamp for receiving the election frame carried in the response frame by other switches j in the network is denoted as T2. j The timestamp of the response frame sent is T3. j When the master switch receives a response frame, it records the timestamp as T4. j .

[0028] Furthermore, in step S21, the main switch continuously performs N... T The two-way frame interaction is performed several times, and the measured delay values ​​are compiled into a dataset. One two-way frame interaction period is denoted as a fitting period. The index of the two-way frame interaction period within each fitting period is denoted as h, where 0 ≤ j < N and 0 ≤ h < N. T Let M be the dataset composed of N delay values ​​obtained by the master switch after the i-th bidirectional frame interaction within the K-th fitting period. i (K), the dataset can be represented as:

[0029] M i (K)={m i (K)|m i (K)=pdelay j (i)(K)}

[0030] Where, 0≤i <N T pdelay j (i)(K) represents the delay value obtained by the master switch after the i-th bidirectional frame interaction within the K-th fitting period of the j-th switch.

[0031] Furthermore, in step S22, based on M i For the (K) dataset, perform a least-squares fit on the delay measurements, assuming the Kth-th fitting polynomial is:

[0032] pdelay j ′(K)=a0+a1j 2 +…a k j k +…+a m j m

[0033] Where a0~a m The number j indicates the switch number, which starts from 1 and increments. The number of each switch can be set by software during network initialization.

[0034] The polynomial coefficients can then be calculated using formula 4:

[0035]

[0036] Where T represents matrix transpose.

[0037] Furthermore, in step S23, pdelay j The value of ′(K) is used as the new delay compensation value. After the Kth fitting, the delay value that each FC-AE node needs to compensate for is:

[0038] Δdelay j (K)=Max{pdelay j ′(K)}-pdelay j ′(K)

[0039] Δdelay j (K) represents the delay value that needs to be compensated for by each FC-AE node after the Kth fitting.

[0040] Furthermore, in step S24, the master switch performs the (K+1)th delay measurement, and records the h-th bidirectional frame interaction within the fitting period, resulting in a sample dataset M. h (K+1):

[0041]

[0042] Where, 0≤i <N T , 0≤h <N T , K≥0.

[0043] Furthermore, in step S26, the (K+1)th sample dataset is refitted using a polynomial:

[0044] M i (K)=M h (K+1)

[0045]

[0046] pdelay j ′(K)=a0+a1j 2 +…a k j k +…+a m j m

[0047] Using the obtained delay compensation value as the delay compensation value after iterative update, we obtain the delay value that each FC-AE node needs to compensate after iterative update:

[0048] Δdelay j (K)=Max{pdelay j ′(K)}-pdelay j ′(K).

[0049] The beneficial effects achieved by this invention are:

[0050] This invention uses a non-precise time synchronization bidirectional delay measurement mechanism to quickly measure the delay of the FC communication link and applies it as a compensation factor to the pulse synchronization delay calculation, so that the pulse synchronization accuracy does not depend on the difference in the length of the switch cascaded cables.

[0051] In the delay measurement mechanism of this invention, the master switch election and delay measurement are performed simultaneously. Compared with the traditional precise time synchronization method, the processing is greatly simplified and the processing time is significantly reduced, which has obvious advantages in application fields with strict requirements for pulse synchronization start time.

[0052] This invention compensates for delay measurements by using local sample updates and least squares fitting, reducing random errors in delay measurements between switches caused by crystal oscillator frequency jitter and environmental factors such as temperature and humidity, and further improving pulse synchronization accuracy. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of a multi-node communication network as shown in Example 1;

[0054] Figure 2 A schematic diagram of the uncompensated synchronization pulse signal delay in a multi-node communication network shown in Example 1. Detailed Implementation

[0055] The technical solution of the present invention will be described in more detail below with reference to the accompanying drawings. The present invention includes, but is not limited to, the following embodiments.

[0056] As attached Figure 1 As shown, this invention proposes a high-precision pulse synchronization method supporting cascaded delay compensation. The communication network includes FC-AE switch 1, FC-AE switch 2, ..., FC-AE switch N. Each switch is connected to one or more FC-AE communication nodes. The switches communicate with each other via cascaded fiber optic cables with lengths L1, L2, ..., L... N-1The source pulse can be input from any node connected to the switch. The FC-AE node samples the source pulse signal, composing two pulse synchronization frames from the rising and falling edges of the signal, and sends them to the connected FC-AE switch. After powering on, the FC-AE switch generates a timestamp based on its local crystal oscillator and periodically performs master switch election and link delay measurement simultaneously through bidirectional frame interaction. The interaction frame includes both the switch serial number and timestamp information. The master switch is elected based on the comparison of the switch device ID value. The election process and the link delay calculation process are performed simultaneously. The master switch compiles a dataset based on the multiple calculated link delay values ​​and performs data fitting. The value of the fitted polynomial is used as the master delay value. The link delay value between the switch and other switches is updated by updating part of the previous dataset after each new bidirectional frame interaction, and the data is refitted. The fitted polynomial value is taken as the updated link delay value between the master switch and other switches to complete the iterative update of the link delay value. The master switch calculates the link delay value that each switch needs to compensate based on the comparison of the link delay values, and sends the delay value to the FC-AE communication nodes connected to each switch. After receiving the pulse synchronization frame, the communication node recovers the pulse signal according to the frame type, and delays the pulse signal by the corresponding delay time according to the link delay compensation value received from the master switch to complete the high-precision pulse signal synchronization.

[0057] Furthermore, this high-precision pulse synchronization method supporting cascaded delay compensation includes the following steps:

[0058] Step 1: Measure the delay of the network link where the pulse synchronization signal is located;

[0059] Specifically, measuring network link latency includes the following steps:

[0060] Step 11: After powering on, the FC-AE switch in the communication network generates a timestamp by accumulating the count using the local crystal oscillator and detects whether the non-cascaded port receives the pulse primitive.

[0061] Step 12: The FC-AE switch that detects the pulse primitive on the non-cascaded port in the network periodically sends the master switch election frame Master_Req to the network in the form of broadcast through the two cascaded ports. The election frame contains the device ID of this switch and the frame sending timestamp.

[0062] Step 13: In the network, an FC-AE switch that detects a pulse primitive on a non-cascaded port parses the received master switch election frame content, obtains the switch device ID field, and compares it with its own device ID. If the ID field value is greater than the switch's own device ID, the delay compensation calculation enable flag en_delay_com is set to 1 in this switch, and the received master switch election frame is not forwarded from the other cascaded port. A NACK frame is then sent back to the switch that sent the election frame via the receiving cascaded port. The NACK frame is an 8B / 10B encoding set consisting of one K code and three D codes not defined in the known FC-AE protocol. If the ID field... If the value is less than the device ID of this switch, then en_delay_com is set to 0. At the same time, the master switch election frame is forwarded from another cascade port to the next level FC-AE switch. The election response frame Master_Resp is replied from the receiving cascade port. The response frame is forwarded from the cascade ports of each level of the switch and arrives at the switch that sent the election frame. The SID in the response frame header is the SID of this switch, and the DID is the SID parsed from the corresponding Master_Req frame header. The Master_Resp frame content contains the device ID of this switch, the Master_Req frame reception timestamp, and the Master_Resp frame transmission timestamp.

[0063] Step 14: FC-AE switches that do not detect pulse primitives on non-cascaded ports in the network send their own election response frame, Master_Resp, through the Master_Req frame receiving port after receiving the Master_Req frame. The SID in the response frame header is the SID of this switch, and the DID is the SID parsed from the corresponding Master_Req frame header. The Master_Resp frame content contains the device ID of this switch, the Master_Req frame reception timestamp, and the Master_Resp frame transmission timestamp.

[0064] Step 15: When the FC-AE switch receives a total of N-1 acknowledgment frames or NACK frames, if en_delay_com remains at 1, this switch becomes the master switch and starts calculating the link delay. If en_delay_com is 0 once during the reception of N-1 acknowledgment frames, then en_delay_com remains at 0.

[0065] Step 16: The timestamp for the master switch sending the Master_Req frame is recorded as T1, and the timestamp for other switches in the network receiving the Master_Req frame carried in the Master_Resp frame is recorded as T2. j The Master_Resp frame it carries has a transmission timestamp of T3. j The master switch records the timestamp of the received Master_Resp frame as T4.j The link delay between the master switch and other switches is calculated using Formula 1, where period is the clock cycle of the switch timestamp generation logic:

[0066] Formula 1: pdelay j =(T2) j -T3 j +T4 j -T1)×period / 2;

[0067] Step 17: After the master switch has calculated the link delay, it begins to calculate the delay difference between the pulse source of the master switch and the pulses recovered on each node.

[0068] Step 2: Compensate for the delay of the network link where the pulse synchronization signal is located;

[0069] Specifically, network link latency compensation includes the following steps:

[0070] Step 21, the main switch continuously performs N... T The two-way frame interaction is performed several times, and the measured delay values ​​are compiled into a dataset. One two-way frame interaction period is denoted as a fitting period. The index of the two-way frame interaction period within each fitting period is denoted as h, where 0 ≤ j < N and 0 ≤ h < N. T Let M be the dataset composed of N delay values ​​obtained by the master switch after the i-th bidirectional frame interaction within the K-th fitting period. i (K), the dataset can be represented by Equation 2:

[0071] Formula 2: M i (K)={m i (K)|m i (K)=pdelay j (i)(K)}

[0072] Where, 0≤i <N T ;

[0073] Step 22, based on M i (K) dataset, least squares fitting of delay measurements, assuming the Kth fitting polynomial is pdelay j ′(K)=a0+a1j 2 +…a k j k +…+a m j m

[0074] The polynomial coefficients can then be calculated using formula 3:

[0075]

[0076] Step 23, set pdelay j The value of ′(K) is used as the new delay compensation value. Substituting it into Formula 4, we obtain the delay value that each FC-AE node needs to compensate after the Kth fitting:

[0077] Formula 4: Δdelay j (K)=Max{pdelay j ′(K)}-pdelay j ′(K)

[0078] Step 24: The master switch performs the (K+1)th delay measurement, records the h-th bidirectional frame interaction within the fitting period, and the resulting sample dataset is M. h (K+1), this dataset is calculated using Equation 5:

[0079]

[0080] 0≤i <N T , 0≤h <N T K≥0

[0081] Step 25, update the sample set as follows:

[0082] Formula 6: M i (K)=M h (K+1)

[0083] Step 26: Substitute Formula 6 into Formula 3 and perform polynomial fitting again to obtain pdelay. j The value of ′(K) is used as the delay compensation value after iterative update. Substituting it into Formula 4, we obtain the delay value that each FC-AE node needs to compensate after iterative update.

[0084] Step 27: The main switch sends the calculated delay compensation value to the FC-AE communication node through FC-AE frame interaction. The FC-AE communication node outputs the recovered pulse after lagging behind the corresponding delay value according to the received delay value, thereby achieving high-precision pulse synchronization.

[0085] Example 1

[0086] The pulse synchronization method for multi-node communication networks disclosed in this invention will be discussed in detail. Figure 1The network shown includes four FC-AE switches: FC-AE Switch 1, FC-AE Switch 2, FC-AE Switch 3, and FC-AE Switch 4. Each switch has a non-cascaded port connected to an FC-AE communication node. The lengths of the cascaded fiber optic cables between the switches (L1, L2, L3) are 3 meters, 15 meters, 15 meters, and 30 meters, respectively. The lengths of the fiber optic cables between each switch and the FC-AE communication node (L4, L5, L6, L7) are all 3 meters. FC-AE node 3 and FC-AE node 4 both have active pulse inputs. All FC-AE nodes in the network output synchronization pulses after delay compensation. After power-on, FC-AE node 2 and FC-AE node 3 detect the pulse signal, generate pulse primitives, and output them to FC-AE switch 2 and FC-AE switch 3, respectively. Before compensation, the relative relationships between the pulses recovered by the FC-AE nodes connected to the four switches are as follows: Figure 2 As shown, waveforms 1 to 4 represent the pulse waveforms recovered by the nodes under FC-AE switch 1 to FC-AE switch 4, respectively.

[0087] The high-precision pulse synchronization method supporting cascaded delay compensation described in this invention... Figure 1 The network shown includes link delay measurement and link delay compensation, comprising the following steps:

[0088] After powering on, the FC-AE switch in the communication network generates a timestamp by accumulating a count using the local crystal oscillator and detects whether the non-cascaded ports have received pulse primitives.

[0089] FC-AE switches 2 and FC-AE switches 3 in the network detect pulse primitives on their non-cascaded ports. Every 1ms, they broadcast master switch election frames to the network through the two cascaded ports. The election frames sent by the two switches are denoted as Master_Req_2 and Master_Req_3, respectively. Each election frame consists of an FC-AE standard frame header, payload data, and an FC-AE standard frame trailer. The SID in the Master_Req_2 frame header is set to 0x000002, and the SID in the Master_Req_3 frame header is set to 0x000003. The DID in both frames is set to 0xFFFFFF. The field values ​​of FC-AE switches 2 and FC-AE switches 3 in the payload data of Master_Req_2 and Master_Req_3 are shown in Table 1.

[0090] Table 1: Master_Req Frame Format and Corresponding Field Values ​​for Switches

[0091]

[0092] After FC-AE switch 2 and FC-AE switch 3 receive the pulse primitive through the cascade port, the corresponding processing procedures are as follows:

[0093] FC-AE switch 2 parses the Master_Req_3 frame content and obtains the device ID field value as 3. After comparing it with the switch ID value 2, it sets the delay compensation calculation enable flag en_delay_com in the switch to 1, and terminates the forwarding of the Master_Req_2 frame, replying with a NACK frame to FC-AE switch 3.

[0094] FC-AE switch 3 parses the Master_Req_2 frame content and obtains the device ID field value as 2. After comparing it with the switch ID value 3, it sets the delay compensation calculation enable flag en_delay_com in this switch to 0, and forwards the Master_Req_2 frame to FC-AE switch 4 from another cascaded port.

[0095] The processing procedures for FC-AE switch 1 and FC-AE switch 4 in the network after receiving the Master_Req frame are as follows:

[0096] After receiving the Master_Req_2 frame, FC-AE switch 1 sends a master switch election response frame, Master_Resp_2_1, through the Master_Req frame receiving port. The SID in the response frame header is 0x000001, and the DID is 0x000002. The payload content of the Master_Resp_2_1 frame is shown in Table 2.

[0097] Table 2: Payload Content of Master_Resp_2_1 Frame

[0098]

[0099] After receiving the Master_Req_2 frame, FC-AE switch 3 sends a master switch election response frame, Master_Resp_2_3, through the Master_Req frame receiving port. The SID in the response frame header is 0x000003, and the DID is 0x000002. The payload content of the Master_Resp_2_3 frame is shown in Table 3.

[0100] Table 3: Payload Content of Master_Resp_2_3 Frame

[0101]

[0102] After receiving the Master_Req_2 frame, FC-AE switch 4 sends a master switch election response frame, Master_Resp_2_4, through the Master_Req frame receive port. The SID in the response frame header is 0x000004, and the DID is 0x000002. The payload content of the Master_Resp_2_4 frame is shown in Table 4.

[0103] Table 4: Payload Content of Master_Resp_2_4 Frame

[0104]

[0105] The master switch election process for FC-AE switch 2 and FC-AE switch 3 is as follows:

[0106] FC-AE switch 2 received 3 response frames, and en_delay_com was always 1, so it was elected as the master switch;

[0107] FC-AE switch 3 received 2 acknowledgment frames and 1 NACK frame. There were instances where en_delay_com became 0, therefore it was not elected as the master switch.

[0108] Table 5 shows the timestamps of the Master_Resp frames received by FC-AE switch 2, which acts as the master switch.

[0109] Table 5: Timestamps of Master_Resp frames received by FC-AE switch 2 from other switches

[0110]

[0111] The clock period for the switch timestamp generation logic is 8ns. The link delay is calculated using Formula 1. The link delays between the FC-AE switch 2 (the master switch) and other switches are shown in Table 6.

[0112] Table 6: Link Delay Calculation Results Between FC-AE Switch 2 and Other Switches

[0113]

[0114] After the master switch calculates the link delay, it begins to calculate the delay difference between the pulse source of the master switch and the pulses recovered on each node.

[0115] Link delay compensation includes the following steps:

[0116] The main switch performs four consecutive bidirectional frame exchanges and compiles the measured latency values ​​into a dataset. The results of the four link latency measurements within the first fitting period are shown in Table 7 below:

[0117] Table 7: Results of four consecutive measurements of link delay between FC-AE switch 2 and other switches.

[0118]

[0119]

[0120] The dataset consisting of these link delays is M(1)={480,413,10,264,534,342,20,324,514,352,15,344,504,392,0,504};

[0121] Based on the above dataset, a 15th-order least squares fit was performed on the delay measurements, resulting in the following fitting polynomial:

[0122] pdelay j ′(K)=a0+a1j 2 +…a k j k +…+a m j m

[0123] =200*j^6-1400*j^7+10100*j^8-53100*j^9

[0124] +205600*j^10-574400*j^11+1114300*j^12

[0125] -1404600*j^13+1016900*j^14-313400*j^15

[0126] Get pdelay j The data values ​​on the K′ curve were used as new delay compensation values, and the corrected link delay measurement results are shown in Table 8 below:

[0127] Table 8: Corrected link delay between FC-AE switch 2 and other switches

[0128]

[0129] Substituting the results from Table 8 into Formula 4, we obtain the delay values ​​that each FC-AE node needs to compensate for after the first fitting, as shown in Table 9:

[0130] Table 9: Delay values ​​to be compensated for at each FC-AE node after the first fitting

[0131]

[0132] The main switch performs the delay measurement during the second fitting period. After the first bidirectional frame interaction during the fitting period, the four elements with indices 0, 1, 2, and 3 in the M(0) dataset are updated, and the resulting sample dataset is M0(1). After the second bidirectional frame interaction during the fitting period, the four elements with indices 4, 5, 6, and 7 in the M0(1) dataset are updated, and the resulting sample dataset is M1(1). After the third bidirectional frame interaction during the fitting period, the four elements with indices 8, 9, 10, and 11 in the M1(1) dataset are updated, and the resulting sample dataset is M2(1). After the fourth bidirectional frame interaction during the fitting period, the four elements with indices 12, 13, 14, and 15 in the M2(1) dataset are updated, and the resulting sample dataset is M3(1).

[0133] After each update of the sample dataset, polynomial fitting is performed again, and pdelay is taken. j The data values ​​on the K′ curve are used as new delay compensation values. The corrected link delay measurement results are shown in Table 10. According to Formula 4, the delay values ​​that each FC-AE node needs to compensate after iterative updates are shown in Table 11.

[0134] Table 10: Results of four consecutive measurements of link delay between FC-AE switch 2 and other switches.

[0135]

[0136] Table 11: Delay values ​​that need to be compensated for at each FC-AE node during the second fitting period

[0137]

[0138]

[0139] The main switch communicates via FC-AE frames, sending the calculated delay compensation value to the FC-AE communication node. The FC-AE communication node then outputs the recovered pulse after lagging behind the corresponding delay value, achieving high-precision pulse synchronization.

[0140] This invention is not limited to the specific embodiments described above. Those skilled in the art can implement this invention using various other specific embodiments based on the disclosed content of the embodiments and accompanying drawings. Therefore, any design that adopts the design structure and concept of this invention and makes some simple changes or modifications falls within the protection scope of this invention.

Claims

1. A high-precision pulse synchronization method supporting cascaded delay compensation, applied to a pulse synchronization system comprising a plurality of FC-AE switches, cascaded communication between each switch being performed through an optical fiber cable; one or more FC-AE communication nodes being respectively connected to each FC-AE switch through a non-cascaded port; characterized in that, The high-precision pulse synchronization method supporting cascade delay compensation comprises the following steps: Step 1, measuring the delay of the network link where the pulse synchronization signal is located; Step 2, compensating the delay of the network link where the pulse synchronization signal is located; In step S1, the following steps are further included: Step 11, the FC-AE switch in the communication network generates a time stamp by accumulating the local crystal oscillator and detects whether the pulse primitive is received; Step 12, the FC-AE switch detecting the pulse primitive, timing, sends a master switch election frame in a broadcast form to the network, and the election frame contains the switch device ID and the frame sending time stamp; Step 13, the FC-AE switch in the network parses the received master switch election frame content, obtains the switch device ID field and compares it with the switch device ID, if the ID field value is greater than the switch device ID, the delay compensation calculation enable flag is set to 1 in the switch, the received master switch election frame is not forwarded from another cascade port, and an NACK frame is replied to the switch sending the election frame through the receiving cascade port; if the ID field value is less than the switch device ID, the delay compensation calculation enable flag is set to 0, and the master switch election frame is forwarded from another cascade port to the next FC-AE switch, and an election response frame is replied from the receiving cascade port, the response frame is forwarded from the cascade port of each switch in turn and reaches the switch sending the election frame, the response frame content contains the switch device ID, the election frame receiving time stamp and the response frame sending time stamp; Step 14, the FC-AE switch in the network not detecting the pulse primitive on the non-cascade port, after receiving the election frame, sends the switch election response frame through the election frame receiving port, the response frame contains the switch device ID, the election frame receiving time stamp and the response frame sending time stamp; Step 15, when the FC-AE switch receives a total of N-1 response frames or NACK frames, if the delay compensation calculation enable flag remains 1, the switch is the master switch, and starts to calculate the link delay; during the reception of N-1 response frames, if the delay compensation calculation enable flag is 0 once, the delay compensation calculation enable flag remains 0 unchanged; Step 16, the master switch calculates the link delay of the master switch and other switches according to the time stamp of the sending election frame, the election frame receiving time stamp and the response frame sending time stamp carried in the response frame and the time stamp of the master switch receiving the response frame; Step 17, after the master switch calculates the link delay, the master switch starts to calculate the delay difference between the pulse source of the master switch and the restored pulse on each node; In step S2, the following steps are further included: Step 21, the master switch generates a data set composed of the measured delay values; Step 22, performing least square fitting on the delay measurement values in the data set; Step 23, taking the least square fitting value as a new delay compensation value, and obtaining the delay value to be compensated for each FC-AE node after the Kth fitting; Step 24, the master switch performs K+1th delay measurement to obtain a K+1th sample data set; Step 25, updating the Kth sample data set to the K+1th sample data set; Step 26, re-performing polynomial fitting on the K+1th sample data set, taking the obtained delay compensation value as the iteratively updated delay compensation value, and obtaining the iteratively updated delay value to be compensated by each FC-AE node; Step 27, the main switch transmits the calculated delay compensation value to the FC-AE communication node through FC-AE frame interaction, and the FC-AE communication node outputs the recovered pulse lag corresponding to the delay value after compensation, thereby realizing high-precision pulse synchronization.

2. The high precision pulse synchronization method supporting cascaded delay compensation according to claim 1, characterized in that, In step S16, the clock cycle of the switch timestamp generation logic is: pdelay j = (T2 j - T3 j + T4 j - T1) x period / 2 The time stamp of sending the election frame is T1, and the time stamp of receiving the election frame in the reply frame carried by the other switch j in the network is T2 j The time stamp of sending the reply frame is T3 k The time stamp of receiving the reply frame by the master switch is T4 j .

3. The method of claim 1, wherein the method is characterized by: In step S21, the main switch continuously performs N T two-way frame interactions, and forms a data set of the measured delay values, where one two-way frame interaction period is defined as one fitting period, the index of the two-way frame interaction period in each fitting period is defined as h, and 0≤j<N, 0≤h<N T , where the data set M i (K) formed by the N delay values obtained by the main switch after the i-th two-way frame interaction in the K-th fitting period can be expressed as: M i (K) = {m i (K)|m i (K) = pdelay j (i)(K)} where 0≤i T , pdelay j (i)(K) represents the delay value obtained by the master switch after the ith two-way frame interaction in the Kth fitting period of the jth switch.

4. The high precision pulse synchronization method supporting cascaded delay compensation according to claim 3, characterized in that, In step S22, based on M i (K) dataset, a least squares fit is performed on the delay measurements, assuming the Kthfit polynomial to be: pdelay j '(K) = a0+ a1j 2 +…a k j k +…+a m j m wherein a0-a m wherein j represents the switch number, which is incremented from 1, and the number of each switch can be set by software at network initialization. The polynomial coefficients can be calculated by formula 4: Equation 3: Wherein, T represents matrix transposition.

5. The method for high-precision pulse synchronization supporting cascaded delay compensation according to claim 4, characterized in that, In step S23, the value of pdelay j The value of pdelay(K) is taken as the new delay compensation value, and the delay value that each FC-AE node needs to compensate after the Kth fitting is: Δdelay j (K) = Max{p delay j '(K)} - p delay j '(K) Δdelay j (K) indicates the delay value that each FC-AE node needs to compensate after the Kth fitting.

6. The method for high-precision pulse synchronization supporting cascaded delay compensation according to claim 5, characterized in that, In step S24, the master switch performs a K+1th delay measurement, noting the hth two-way frame interaction within the fitting period, resulting in a sample data set M h (K+1): where 0≤i T , 0≤h T < K, and K≥0.

7. The method for high-precision pulse synchronization supporting cascaded delay compensation according to claim 6, characterized in that, In step S26, re-perform polynomial fitting on the K+1th sample data set: M i (K) = M h (K+1) pdelay j '(K) = a0+ a1j 2 +…a k j k +…+a m j m Take the obtained delay compensation value as the iteratively updated delay compensation value, and obtain the iteratively updated delay value to be compensated by each FC-AE node: Δdelay j (K) = Max{p delay j '(K)} - p delay j '(K).

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