RISC-v architecture-based zu chongzhi algorithm implementation method, coprocessor and operation device

Abstract

This invention discloses a method for implementing the Zu Chongzhi algorithm based on the RISC-V architecture, a coprocessor, and a computing device, belonging to the technical field of Zu Chongzhi algorithm implementation. This invention leverages the high speed of hardware logic structure and the high flexibility of software programming by adding the RISC-V extended instruction set to the processor's hardware logic structure. This allows the processor to call the extended instruction set at the instruction set level, thereby increasing the processor's instruction set richness and improving its execution capability for the Zu Chongzhi algorithm. The RISC-V extended instruction set for the Zu Chongzhi algorithm proposed in this invention has good flexibility. Developers can decide whether to add the extended instruction set to the processor's hardware logic structure based on whether there is a need for the Zu Chongzhi algorithm, without changing the hardware logic structure of other parts of the processor.

Description

Technical Field

[0001] This invention belongs to the field of Zu Chongzhi algorithm implementation technology, and more specifically, relates to a Zu Chongzhi algorithm implementation method, coprocessor, and computing device based on RISC-V architecture. Background Technology

[0002] Zu Chongzhi's algorithm is a stream cipher standard adopted in my country. It was released by the State Cryptography Administration in 2012 and became China's national cryptographic standard in 2016. In September 2011, it was adopted by 3GPP as an international encryption standard and became the core algorithm of the third encryption standard of 3GPP LTE. This is also the first cryptographic algorithm in my country to become an international standard.

[0003] Current implementations of Zu Chongzhi's algorithm primarily focus on either hardware logic implementation or software programming implementation. Hardware logic implementation offers relatively high operating efficiency but requires significant hardware resources. Software programming implementation, while offering greater flexibility, suffers from lower execution efficiency. Implementing Zu Chongzhi's algorithm based on instruction set extensions can balance hardware resource consumption and algorithm performance; however, due to the inherent characteristics of the algorithm, research on implementations based on extended instruction sets is relatively limited. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to propose a method for implementing the Zu Chongzhi algorithm based on the RISC-V architecture, a coprocessor, and a computing device, thereby solving the problem of insufficient performance of processors in the existing technology for implementing the Zu Chongzhi algorithm.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for implementing the Zu Chongzhi algorithm based on a RISC-V architecture, including three extended instructions defined for the Zu Chongzhi algorithm based on the RISC-V architecture: the ZUCSET instruction for key loading operations of the Zu Chongzhi algorithm, the ZUCINIT instruction for the initialization phase operations of the Zu Chongzhi algorithm, and the ZUCWORK instruction for working phase 1 and working phase 2 operations of the Zu Chongzhi algorithm; all three extended instructions are based on the RV32 R-type instruction format, and the opcode is selected as the custom-0 instruction type.

[0006] Preferably, the method for defining the ZUCSET instruction for the key loading operation of the Zu Chongzhi algorithm is as follows:

[0007] The encoding format of the ZUCSET instruction is as follows:

[0008] The 0th to 6th bits of the instruction are the opcode field, with a value of 0001011, which is used to indicate that the custom-0 instruction group is used;

[0009] The 7th to 11th bits of the instruction are the rd field, whose value is the index of the destination register rd, used to indicate whether the key loading operation was successful;

[0010] The 12th to 14th bit range of the instruction is the funct3 field, with a value of 000, which is used as the block code for the three extended instructions;

[0011] The 15th to 19th bits of the instruction are the rs1 field, whose value is the index corresponding to the source register rs1, used to store part of the key value required by Zu Chongzhi's algorithm in the current execution phase;

[0012] The 20th to 24th bits of the instruction are the rs2 field, whose value is the index corresponding to the source register rs2, used to store part of the initial vector iv required by Zu Chongzhi's algorithm in the current execution stage;

[0013] The 25th to 31st bit range of the instruction is the funct7 field, encoded in 01pt format. H pt L 111, where the 30th bit is 1, is used to indicate that the value is encoded as the ZUCSET instruction, binary number pt. H pt L The corresponding decimal number pt is used to indicate the current execution stage of the key loading operation;

[0014] The ZUCSET instruction is called as rd = zucset(rs1,rs2,pt), where the instruction is defined to write back the result. The result of the instruction execution is stored in the general-purpose register indexed by rd. The instruction needs to read the value of the source register rs1, the value of the source register rs2, and the flag bit pt.

[0015] Preferably, the method for defining the ZUCINIT instruction used in the initialization phase of Zu Chongzhi's algorithm is as follows:

[0016] The encoding format of the ZUCINIT instruction is as follows:

[0017] The 0th to 6th bits of the instruction are the opcode field, with a value of 0001011, which is used to indicate that the custom-0 instruction group is used;

[0018] The 7th to 11th bits of the instruction are the rd field, whose value is the index of the destination register rd, used to write back the operation result generated during instruction execution;

[0019] The 12th to 14th bit range of the instruction is the funct3 field, with a value of 000, which is used as the block code for the three extended instructions;

[0020] The 15th to 19th bit range of the instruction is the rs1 field, with a value of 00000;

[0021] The 20th to 24th bit range of the instruction is the rs2 field, with a value of 00000;

[0022] The 25th to 31st bit range of the instruction is the funct7 field, with an encoding format of 0001111, which is used to mark the value as the ZUCINIT instruction;

[0023] The ZUCINIT instruction is called as rd = zucinit(), where the instruction is defined to have a write-back result. The instruction execution result is stored in the general-purpose register indexed by rd, and the instruction does not need to read operands rs1 and rs2.

[0024] Preferably, the method for defining the ZUCWORK instructions for the operations of working phase 1 and working phase 2 of Zu Chongzhi's algorithm is as follows:

[0025] The encoding format of the ZUCWORK instruction is as follows:

[0026] The 0th to 6th bits of the instruction are the opcode field, with a value of 0001011, which is used to indicate that the custom-0 instruction group is used;

[0027] The 7th to 11th bits of the instruction are the rd field, whose value is the index of the destination register rd, used to write back the operation result generated during instruction execution;

[0028] The 12th to 14th bit range of the instruction is the funct3 field, with a value of 000, which is used as the block code for the three extended instructions;

[0029] The 15th to 19th bit range of the instruction is the rs1 field, with a value of 00000;

[0030] The 20th to 24th bit range of the instruction is the rs2 field, with a value of 00000;

[0031] The 25th to 31st bit range of the instruction is the funct7 field, with an encoding format of 0000111, used to mark that the value is encoded as a ZUCWORK instruction;

[0032] The ZUCWORK instruction is called as rd = zucwork(), where the instruction is defined to have a write-back result. The instruction execution result is stored in the general-purpose register indexed by rd, and the instruction does not need to read operands rs1 and rs2.

[0033] To achieve the above objectives, in a second aspect, the present invention provides a Zu Chongzhi algorithm coprocessor based on a RISC-V architecture, the coprocessor comprising:

[0034] The controller is configured to receive instructions sent by the main processor, parse the instructions, call the corresponding arithmetic operation process in the arithmetic logic unit according to the parsing result, and perform data read and write to the internal memory according to the data required by the arithmetic logic unit.

[0035] The arithmetic logic unit, connected to the controller and internal memory, is configured to execute functions on data in the internal memory and send the output of the functions to the internal memory to update the data in the internal memory. The functions correspond to the implementation principle of Zu Chongzhi's algorithm.

[0036] The internal memory, connected to the arithmetic logic unit, includes 16 registers with a width of 31 bits and 2 registers with a width of 32 bits, configured to store the data required and generated during the execution of Zu Chongzhi's algorithm.

[0037] Preferably, the controller implements Zu Chongzhi's algorithm in the following manner:

[0038] After obtaining the main processor instruction, the instruction is parsed, the value of the 30th bit is obtained from the 32-bit instruction word, and it is determined whether the value is equal to 1;

[0039] If the value is equal to 1, the 29th and 28th bits of the instruction are read and converted to the corresponding decimal value. The decimal result has four possible values ​​from 0 to 3. This divides the 128-bit key required by Zu Chongzhi's algorithm into four segments: 127-96, 95-64, 63-32, and 31-0. These segments are then passed to the logic unit in four steps through the source register rs1 and further written to the internal memory through the logic unit. Similarly, the 128-bit initial vector iv required by Zu Chongzhi's algorithm is divided into four segments: 127-96, 95-64, 63-32, and 31-0. These segments are then passed to the logic unit in four steps through the source register rs2 and further written to the internal memory through the logic unit.

[0040] Otherwise, continue reading the 28th bit of the instruction and determine whether the value is equal to 1;

[0041] If the value is equal to 1, the initialization process logic operation is performed by calling the arithmetic logic unit. Combining the stored values ​​of the two 32-bit wide registers and the 31-bit wide memories numbered 15, 14, 11, 9, 7, 5, 2, 0, the nonlinear function in the Zu Chongzhi algorithm principle is executed to update the data of the two wide registers and obtain the first execution result. The data in the 31-bit wide registers numbered 15, 13, 10, 4, 0 and the first execution result are further processed by the LFSR operation in the algorithm principle. The result is used to update the 16 31-bit wide registers. There is no return value output in this execution stage.

[0042] Otherwise, by calling the arithmetic logic unit to perform the working stage logic operation, combined with the stored values ​​of the two 32-bit wide registers and the 31-bit wide memories numbered 15, 14, 11, 9, 7, 5, 2, 0, the nonlinear function in the algorithm principle is executed to update the data of the two wide registers and obtain the second execution result. The data in the 31-bit wide registers numbered 15, 13, 10, 4, 0 in the internal memory are further processed by the LFSR operation in the algorithm principle. The result is used to update the 16 31-bit wide registers. The return value of this execution stage is the second execution result.

[0043] To achieve the above objectives, in a third aspect, the present invention provides a computational device for Zu Chongzhi's algorithm, comprising:

[0044] The main processor is configured to define a plurality of RISC-V extended instructions using the method described in the first aspect, and to send the instructions to the coprocessor;

[0045] External memory is configured to store the input data of Zu Chongzhi's algorithm;

[0046] The coprocessor described in the second aspect is configured to receive and parse instructions sent by the main processor, read input data for the Zu Chongzhi algorithm from external memory, and execute the Zu Chongzhi algorithm.

[0047] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:

[0048] This invention discloses a method for implementing the Zu Chongzhi algorithm based on the RISC-V architecture, a coprocessor, and a computing device. Leveraging the high speed of hardware logic structure and the high flexibility of software programming, an extended instruction set is added to the processor's hardware logic structure. This allows the processor to call the extended instruction set at the instruction set level, thereby increasing the processor's instruction set richness and improving its execution capability for the Zu Chongzhi algorithm. The RISC-V extended instruction set for Zu Chongzhi proposed in this invention has good flexibility. Developers can decide whether to add the extended instruction set to the processor's hardware logic structure based on whether there is a need for the Zu Chongzhi algorithm, without changing the hardware logic structure of other parts of the processor. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the logical operation process of the Zu Chongzhi algorithm provided by the present invention.

[0050] Figure 2 This is a schematic diagram of the ZUCSET instruction encoding format provided by the present invention.

[0051] Figure 3This is a schematic diagram of the ZUCINIT instruction encoding format provided by the present invention.

[0052] Figure 4 This is a schematic diagram of the ZUCWORK instruction encoding format provided by the present invention.

[0053] Figure 5 This is a schematic diagram showing the correspondence between logical operations and the main stages of the pipeline provided by the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0055] This invention provides a computing device for the Zu Chongzhi algorithm, comprising: a main processor configured to define a plurality of RISC-V extended instructions and send the instructions to a coprocessor; an external memory configured to store input data of the Zu Chongzhi algorithm; and a coprocessor configured to receive and parse the instructions sent by the main processor, read the input data of the Zu Chongzhi algorithm from the external memory, and execute the Zu Chongzhi algorithm.

[0056] like Figure 1 As shown, the logical operation process of Zu Chongzhi's algorithm includes key loading, initialization, working phase 1, and working phase 2. For the key loading operation, this invention proposes one extended instruction—ZUCSET. For the initialization phase, one extended instruction—ZUCINIT. The operations on the internal memory units in working phase 1 and working phase 2 are consistent, differing only in the processing of the output results. To reduce the number of instruction subsets in the extended instruction set of Zu Chongzhi's algorithm, this invention proposes one extended instruction—ZUCWORK. The resulting extended instruction set of Zu Chongzhi's algorithm is shown in Table 1. Bits 30, 29, and 28 correspond to flags S, B, and I, respectively, used to distinguish different instructions.

[0057] This invention provides a method for implementing the Zu Chongzhi algorithm based on the RISC-V architecture, including three extended instructions defined for the Zu Chongzhi algorithm based on the RISC-V architecture: the ZUCSET instruction for key loading operations of the Zu Chongzhi algorithm, the ZUCINIT instruction for the initialization phase operations of the Zu Chongzhi algorithm, and the ZUCWORK instruction for working phase 1 and working phase 2 operations of the Zu Chongzhi algorithm; all three extended instructions are based on the RV32 R-type instruction format, and the opcode is selected as the custom-0 instruction type.

[0058] Preferably, such as Figure 2As shown, the method for defining the ZUCSET instruction for key loading operations in the Zu Chongzhi algorithm is as follows:

[0059] The encoding format of the ZUCSET instruction is as follows:

[0060] The 0th to 6th bits of the instruction are the opcode field, with a value of 0001011, which is used to indicate that the custom-0 instruction group is used;

[0061] The 7th to 11th bits of the instruction are the rd field, whose value is the index of the destination register rd, used to indicate whether the key loading operation was successful;

[0062] The 12th to 14th bit range of the instruction is the funct3 field, with a value of 000, which is used as the block code for the three extended instructions;

[0063] The 15th to 19th bits of the instruction are the rs1 field, whose value is the index corresponding to the source register rs1, used to store part of the key value required by Zu Chongzhi's algorithm in the current execution phase;

[0064] The 20th to 24th bits of the instruction are the rs2 field, whose value is the index corresponding to the source register rs2, used to store part of the initial vector iv required by Zu Chongzhi's algorithm in the current execution stage;

[0065] The 25th to 31st bit range of the instruction is the funct7 field, encoded in 01pt format. H pt L 111, where the 30th bit is 1, is used to indicate that the value is encoded as the ZUCSET instruction, binary number pt. H pt L The corresponding decimal number pt is used to indicate the current execution stage of the key loading operation;

[0066] The ZUCSET instruction is called as rd = zucset(rs1,rs2,pt), where the instruction is defined to write back the result. The result of the instruction execution is stored in the general-purpose register indexed by rd. The instruction needs to read the value of the source register rs1, the value of the source register rs2, and the flag bit pt.

[0067] Preferably, such as Figure 3 As shown, the method for defining the ZUCINIT instruction used in the initialization phase of Zu Chongzhi's algorithm is as follows:

[0068] The encoding format of the ZUCINIT instruction is as follows:

[0069] The 0th to 6th bits of the instruction are the opcode field, with a value of 0001011, which is used to indicate that the custom-0 instruction group is used;

[0070] The 7th to 11th bits of the instruction are the rd field, whose value is the index of the destination register rd, used to write back the operation result generated during instruction execution;

[0071] The 12th to 14th bit range of the instruction is the funct3 field, with a value of 000, which is used as the block code for the three extended instructions;

[0072] The 15th to 19th bit range of the instruction is the rs1 field, with a value of 00000;

[0073] The 20th to 24th bit range of the instruction is the rs2 field, with a value of 00000;

[0074] The 25th to 31st bit range of the instruction is the funct7 field, with an encoding format of 0001111, which is used to mark the value as the ZUCINIT instruction;

[0075] The ZUCINIT instruction is called as rd = zucinit(), where the instruction is defined to have a write-back result. The instruction execution result is stored in the general-purpose register indexed by rd, and the instruction does not need to read operands rs1 and rs2.

[0076] Preferably, such as Figure 4 As shown, the method for defining the ZUCWORK instructions used for the operations of working phase 1 and working phase 2 of Zu Chongzhi's algorithm is as follows:

[0077] The encoding format of the ZUCWORK instruction is as follows:

[0078] The 0th to 6th bits of the instruction are the opcode field, with a value of 0001011, which is used to indicate that the custom-0 instruction group is used;

[0079] The 7th to 11th bits of the instruction are the rd field, whose value is the index of the destination register rd, used to write back the operation result generated during instruction execution;

[0080] The 12th to 14th bit range of the instruction is the funct3 field, with a value of 000, which is used as the block code for the three extended instructions;

[0081] The 15th to 19th bit range of the instruction is the rs1 field, with a value of 00000;

[0082] The 20th to 24th bit range of the instruction is the rs2 field, with a value of 00000;

[0083] The 25th to 31st bit range of the instruction is the funct7 field, with an encoding format of 0000111, used to mark that the value is encoded as a ZUCWORK instruction;

[0084] The ZUCWORK instruction is called as rd = zucwork(), where the instruction is defined to have a write-back result. The instruction execution result is stored in the general-purpose register indexed by rd, and the instruction does not need to read operands rs1 and rs2.

[0085] This invention provides a Zu Chongzhi algorithm coprocessor based on a RISC-V architecture, the coprocessor comprising:

[0086] The controller is configured to receive instructions sent by the main processor, parse the instructions, call the corresponding arithmetic operation process in the arithmetic logic unit according to the parsing result, and perform data read and write to the internal memory according to the data required by the arithmetic logic unit.

[0087] The arithmetic logic unit, connected to the controller and internal memory, is configured to execute functions on data in the internal memory and send the output of the functions to the internal memory to update the data in the internal memory. The functions correspond to the implementation principle of Zu Chongzhi's algorithm.

[0088] The internal memory, connected to the arithmetic logic unit, includes 16 registers with a width of 31 bits and 2 registers with a width of 32 bits, configured to store the data required and generated during the execution of Zu Chongzhi's algorithm.

[0089] Preferably, the controller implements Zu Chongzhi's algorithm in the following manner:

[0090] After obtaining the main processor instruction, the instruction is parsed, the value of the 30th bit is obtained from the 32-bit instruction word, and it is determined whether the value is equal to 1;

[0091] If the value is equal to 1, the 29th and 28th bits of the instruction are read and converted to the corresponding decimal value. The decimal result has four possible values ​​from 0 to 3. This divides the 128-bit key required by Zu Chongzhi's algorithm into four segments: 127-96, 95-64, 63-32, and 31-0. These segments are then passed to the logic unit in four steps through the source register rs1 and further written to the internal memory through the logic unit. Similarly, the 128-bit initial vector iv required by Zu Chongzhi's algorithm is divided into four segments: 127-96, 95-64, 63-32, and 31-0. These segments are then passed to the logic unit in four steps through the source register rs2 and further written to the internal memory through the logic unit.

[0092] Otherwise, continue reading the 28th bit of the instruction and determine whether the value is equal to 1;

[0093] If the value is equal to 1, the initialization process logic operation is performed by calling the arithmetic logic unit. Combining the stored values ​​of the two 32-bit wide registers and the 31-bit wide memories numbered 15, 14, 11, 9, 7, 5, 2, 0, the nonlinear function in the Zu Chongzhi algorithm principle is executed to update the data of the two wide registers and obtain the first execution result. The data in the 31-bit wide registers numbered 15, 13, 10, 4, 0 and the first execution result are further processed by the LFSR operation in the algorithm principle. The result is used to update the 16 31-bit wide registers. There is no return value output in this execution stage.

[0094] Otherwise, by calling the arithmetic logic unit to perform the working stage logic operation, combined with the stored values ​​of the two 32-bit wide registers and the 31-bit wide memories numbered 15, 14, 11, 9, 7, 5, 2, 0, the nonlinear function in the algorithm principle is executed to update the data of the two wide registers and obtain the second execution result. The data in the 31-bit wide registers numbered 15, 13, 10, 4, 0 in the internal memory are further processed by the LFSR operation in the algorithm principle. The result is used to update the 16 31-bit wide registers. The return value of this execution stage is the second execution result.

[0095] Pipeline design, as a component of the hardware-software co-process, has a crucial impact on instruction execution efficiency. The three instructions included in this invention employ hardware logic selection based on the VexRiscv main processor and adapted to a four-stage pipeline. Combined with the algorithm principles and actual computation processes, they utilize... Figure 5 The diagram illustrates the correspondence between hardware logic operations and the main stages of the pipeline. Thus, the bit reassembly layer (BR) and the nonlinear function layer (F function) will be fully executed during the pipeline execution stage, the accumulation of multiple data in the LFSR layer (linear feedback shift register) will be completed during the execution stage, and the memory access stage will handle the numerical update operations for all internal memory cell registers.

[0096] Based on the design of the instruction pipeline logic and the analysis of the four stages of the implementation process of Zu Chongzhi's algorithm according to the present invention, the software side is based on C language encoding and uses inline assembly technology to translate the algorithm instructions in the present invention into machine-recognizable instruction codes.

[0097] The key loading operation of Zu Chongzhi's algorithm is implemented through four instructions, which are used to write the key and iv values ​​required for the operation into the hardware logic memory unit by slicing them into segments. The main process code is as follows:

[0098]

[0099] In the initialization function, the 32-round iteration function is implemented using four sets of functions (INIT8) each containing eight iterations, as shown in the code below:

[0100]

[0101] After completing the key loading and initialization operations in the ZUC algorithm using the functions above, the keystream data can be obtained by calling zucwork. A single call to the zucwork command can only retrieve data with a word length of 32 bits; obtaining longer data streams can be achieved through loop calls.

[0102] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for implementing Zu Chongzhi's algorithm based on RISC-V architecture, characterized in that, The three extension instructions for Zuchongzhi algorithm based on the RISC-V architecture definition include: a ZUCSET instruction for defining a key loading operation of the Zuchongzhi algorithm, a ZUCINIT instruction for a Zuchongzhi algorithm initialization stage operation, and a ZUCWORK instruction for Zuchongzhi algorithm working stage 1 and working stage 2 operations; all the three extension instructions are based on an RV32 R-type instruction format, and an opcode selects a custom-0 instruction type; The encoding format of the ZUCSET instruction is as follows: The interval of the 0th to 6th bits of the instruction is an opcode field, the value of which is 0001011, used for indicating that the custom-0 instruction group is adopted; The interval of the 7th to 11th bits of the instruction is an rd field, the value of which is a corresponding index of a destination register rd, used for indicating whether the key loading operation is successful; The interval of the 12th to 14th bits of the instruction is a funct3 field, the value of which is 000, used as a grouping code of the three extension instructions; The interval of the 15th to 19th bits of the instruction is an rs1 field, the value of which is a corresponding index of a source register rs1, used for storing a partial value of a required key of the Zuchongzhi algorithm in the current execution stage; The interval of the 20th to 24th bits of the instruction is an rs2 field, the value of which is a corresponding index of a source register rs2, used for storing a partial value of a required initial vector iv of the Zuchongzhi algorithm in the current execution stage; The 25th to 31st bits of the instruction are a funct7 field, with an encoding format of 01 111, where a 1 in bit 30 is used to flag that the value is encoded as a ZUC SET instruction, and the binary number corresponding to the decimal number pt, is used to flag the current execution phase of the key load operation; The encoding format of the ZUCINIT instruction is as follows: The interval of the 0th to 6th bits of the instruction is an opcode field, the value of which is 0001011, used for indicating that the custom-0 instruction group is adopted; The interval of the 7th to 11th bits of the instruction is an rd field, the value of which is a corresponding index of a destination register rd, used for writing back an operation result generated when the instruction is executed; The interval of the 12th to 14th bits of the instruction is a funct3 field, the value of which is 000, used as a grouping code of the three extension instructions; The interval of the 15th to 19th bits of the instruction is an rs1 field, the value of which is 00000; The interval of the 20th to 24th bits of the instruction is an rs2 field, the value of which is 00000; The interval of the 25th to 31st bits of the instruction is a funct7 field, and the encoding format is 0001111, used for marking that the value is encoded as the ZUCINIT instruction; The encoding format of the ZUCWORK instruction is as follows: The interval of the 0th to 6th bits of the instruction is an opcode field, the value of which is 0001011, used for indicating that the custom-0 instruction group is adopted; The interval of the 7th to 11th bits of the instruction is an rd field, the value of which is a corresponding index of a destination register rd, used for writing back an operation result generated when the instruction is executed; The interval of the 12th to 14th bits of the instruction is a funct3 field, the value of which is 000, used as a grouping code of the three extension instructions; The interval of the 15th to 19th bits of the instruction is an rs1 field, the value of which is 00000; The interval of the 20th to 24th bits of the instruction is an rs2 field, the value of which is 00000; The 25th to 31st bits of the instruction are a funct7 field, and the encoding format is 0000111, used to mark that the value is encoded as a ZUCWORK instruction.

2. The method of claim 1, wherein, The method for defining a ZUCSET instruction for a key loading operation of the Zuchongzhi algorithm is: The calling mode of the ZUCSET instruction is Wherein, the definition instruction has a write-back result, the instruction execution result is stored in the general register of the rd index, and the instruction needs to read the value of the source register rs1, the value of the source register rs2 and the flag bit pt.

3. The method of claim 2, wherein, The method for defining a ZUCINIT instruction for an initialization stage operation of the Zuchongzhi algorithm is: The ZUCINIT instruction is called in the following way wherein the definition instruction has a write back result, the instruction execution result is stored in the general register with the rd index, and the instruction does not need to read the operands rs1, rs2.

4. The method of claim 3, wherein, The method for defining a ZUCWORK instruction for a work stage 1 and work stage 2 operation of the Zuchongzhi algorithm is: The calling mode of the ZUCWORK instruction is Wherein, the definition instruction has write-back result, the instruction execution result is stored in the general register of the rd index, and the instruction does not need to read the operands rs1 and rs2.

5. A RISC-V architecture based Zu Chongzhi algorithm coprocessor, characterized in that, The coprocessor comprises: The controller is configured to receive the instruction sent by the host processor, analyze the instruction, call a corresponding arithmetic operation process in the arithmetic logic unit according to the analysis result, and perform data reading and writing on the internal memory according to the data required by the arithmetic logic unit; The arithmetic logic unit is connected with the controller and the internal memory, and is configured to execute a function on the data in the internal memory and send an output result of the function to the internal memory to update the data in the internal memory, the function corresponding to the implementation principle of the Zuchongzhi algorithm; The internal memory is connected with the arithmetic logic unit, and comprises 16 31-bit width registers and 2 32-bit width registers, and is configured to store data required and generated in the execution process of the Zuchongzhi algorithm. The controller implements the Zuchongzhi algorithm in the following manner: After obtaining the instruction of the host processor, the instruction is analyzed, the value of the 30th bit in the 32-bit instruction word is obtained, and it is judged whether the value is equal to 1; If equal to 1, the values of the 29th and 28th bits of the instruction are continuously read, and the values are converted to corresponding decimals, the decimal result has four values of 0-3, so that the 128-bit key required by the Zuchongzhi algorithm is divided into four segments of 127-96, 95-64, 63-32 and 31-0, and the 128-bit initial vector iv required by the Zuchongzhi algorithm is divided into four segments of 127-96, 95-64, 63-32 and 31-0, and is transmitted into the logic operation unit through the source register rs2 four times, and is further written into the internal memory through the logic operation unit; Otherwise, the value of the 28th bit of the instruction is continuously read, and it is judged whether the value is equal to 1; If equal to 1, the initialization process logic operation is executed by calling the arithmetic logic unit, the storage values of the two 32-bit width registers and the 31-bit width registers numbered 15, 14, 11, 9, 7, 5, 2 and 0 are combined, the nonlinear function in the principle of the Zuchongzhi algorithm is executed to update the data of the two bit width registers, a first execution result is obtained, the data in the 31-bit width registers numbered 15, 13, 10, 4 and 0 is further executed with the first execution result to perform the LFSR operation in the algorithm principle, and the obtained result is used to update the 16 31-bit width registers, and the execution stage has no return value output. Otherwise, the nonlinear function in the algorithm principle is executed to realize the data update of the two bit width registers and the second execution result is obtained by calling the arithmetic logic unit to execute the working stage logic operation in combination with the storage values of the two 32 bit width registers and the 31 bit width memories numbered 15, 14, 11, 9, 7, 5, 2 and 0, and the LFSR operation in the algorithm principle is further executed on the data in the 31 bit width registers numbered 15, 13, 10, 4 and 0 in the internal memory, and the obtained result is used to update the 16 31 bit width registers, and the return value of this execution stage is the second execution result.

6. A device for performing Zu Chongzhi's algorithm, characterized in that, Comprise: a main processor configured to define a plurality of RISC-V extension instructions using the method according to any one of claims 1 to 4, and send the instructions to a coprocessor; an external memory configured to store input data of the Zu Chongzhi algorithm; the coprocessor according to claim 5, configured to receive and parse the instructions sent by the main processor, read the input data of the Zu Chongzhi algorithm from the external memory, and execute the Zu Chongzhi algorithm.

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