Three-dimensional flash memory and methods of forming the same

Abstract

A three-dimensional flash memory includes a substrate, a stack structure, a stop layer, two slit trenches, a plurality of vertical channel structures, and a plurality of slit openings. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductor layers alternately stacked. The stop layer is disposed between the substrate and the stack structure. The two slit trenches penetrate the stack structure to expose the stop layer. The plurality of vertical channel structures are disposed between the two slit trenches and penetrate the stack structure and the stop layer. The plurality of slit openings are discretely disposed between the plurality of vertical channel structures and penetrate the stack structure to expose the stop layer. A method of forming a three-dimensional NAND flash memory is also provided.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory and a method for forming the same, and more particularly to a three-dimensional flash memory and a method for forming the same. BACKGROUND

[0002] Non-volatile memory, such as flash memory, has been widely used in personal computers and other electronic devices due to its advantage of keeping the stored data from disappearing after power-off.

[0003] Currently, three-dimensional flash memories commonly used in the industry include NOR flash memory and NAND flash memory. In addition, another type of three-dimensional flash memory is AND flash memory, which can be applied in multi-dimensional flash memory arrays to have high integration and high area utilization, and has the advantage of fast operation speed. Therefore, the development of three-dimensional flash memory has gradually become the current trend.

[0004] DISCLOSURE

[0005] The present application provides a three-dimensional flash memory comprising a substrate, a stack structure, two adjacent slit trenches, a plurality of vertical channel structures, and a plurality of slit openings. The stack structure is disposed on the substrate. The stack structure comprises a plurality of dielectric layers and a plurality of conductor layers alternately stacked. The two adjacent slit trenches penetrate the stack structure. The two adjacent slit trenches have an average width 30w. The plurality of vertical channel structures are disposed between the two adjacent slit trenches and penetrate the stack structure. The plurality of slit openings are discretely disposed between the plurality of vertical channel structures and penetrate the stack structure. An average width W of the plurality of slit openings is greater than or equal to the average width 30w of the two adjacent slit trenches.

[0006] The present application provides a method for forming a three-dimensional flash memory, comprising: forming a stop layer and a stack structure on a substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked; forming a plurality of first openings in the stack structure and the stop layer; forming a plurality of vertical channel structures in the plurality of first openings, respectively; forming a plurality of second openings in the stack structure to expose the stop layer, wherein the plurality of second openings comprise at least two adjacent slit trenches having an average width 30w and a plurality of slit openings having an average width W, the plurality of vertical channel structures are formed between the two slit trenches, and the plurality of slit openings are discretely formed between the plurality of vertical channel structures, wherein the average width W of the plurality of slit openings is greater than or equal to the average width 30w of the two adjacent slit trenches; and performing a gate replacement process through the plurality of second openings to replace the plurality of sacrificial layers with a plurality of conductor layers.

[0007] Based on the above, the present embodiment forms a plurality of slit openings discretely between the plurality of vertical channel structures, so as to increase the removal efficiency of the sacrificial layer and the filling efficiency of the conductor layer in the gate replacement process, thereby improving the yield of the three-dimensional flash memory. In this case, the present embodiment not only solves the process bottleneck of the existing memory, but also increases the number of storage units per unit chip area, thereby improving the integration and area utilization of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4A and Figure 5 is a cross-sectional schematic view of a manufacturing process of a three-dimensional AND flash memory according to an embodiment of the present application.

[0009] Figure 4B is a plan view along the A-A cutting line of Figure 4A .

[0010] Figure 6 is a cross-sectional schematic view of a three-dimensional AND flash memory according to another embodiment of the present application.

[0011] Figure 7A is a cross-sectional schematic view of a three-dimensional NAND flash memory according to other embodiments of the present application.

[0012] Figure 7B is a plan view along the B-B cutting line of Figure 7A .

[0013] Figure 8A illustrates the layout of the arrangement of slit openings according to an embodiment of the present application.

[0014] Figure 8B and Figure 8C illustrate enlarged schematic views of the regions in Figure 8A , respectively.

[0015] Figures 9 to 12 illustrates the layout of the arrangement of slit openings according to various embodiments of the present application.

[0016] REFERENCE NUMERALS

[0017] 1: three-dimensional AND flash memory

[0018] 2: three-dimensional NAND flash memory

[0019] 10: initial structure

[0020] 20, 30: opening

[0021] 30d: average diameter

[0022] 30H, 30S: slot opening

[0023] 30T: slot channel

[0024] 30w: average width

[0025] 34: void

[0026] 35, D1, D2: distance

[0027] 100, 500: substrate

[0028] 102, 104: polysilicon layer

[0029] 106, 516: cap layer

[0030] 108, 508: stop layer

[0031] 110, 210, 510: stack structure

[0032] 112, 512: dielectric layer

[0033] 114: sacrificial layer

[0034] 120, 220, 520: charge storage layer

[0035] 124, 128: oxide layer

[0036] 130, 530: vertical channel structure

[0037] 130d: average diameter

[0038] 130s: upper spacing

[0039] 132, 532: channel layer

[0040] 134, 534: insulating pillar

[0041] 135: dielectric material

[0042] 136: first source / drain pillar

[0043] 138: second source / drain pillar

[0044] 142, 144: polysilicon material

[0045] 154, 554: conductor layer

[0046] 160: memory cell

[0047] 230, 332: dielectric layer

[0048] 330: composite structure

[0049] 334: conductor feature

[0050] 531: conductive plug

[0051] A1, A2, A3: removal limit area

[0052] AR: array region

[0053] E1: first electrical path

[0054] E2: second electrical path

[0055] L: average length

[0056] K1, K2, K3: removal limit length

[0057] W: average width

[0058] X, Y: direction DETAILED DESCRIPTION

[0059] The present application is illustrated by way of example and not limitation in the figures of the accompanying drawings in which:

[0060] Figure 1 , Figure 2 , Figure 3 , Figure 4A and Figure 5 are cross-sectional schematic diagrams of a fabrication flow of a three-dimensional AND flash memory in accordance with an embodiment of the present application. Figure 4B is a plan view along the A-A cutline of Figure 4A Although the following embodiments are described with respect to a three-dimensional AND flash memory, the present application is not so limited. In other embodiments, the resulting memory structure can also be a three-dimensional NAND flash memory or a three-dimensional NOR flash memory.

[0061] Referring to Figure 1 , initially, an initial structure 10 is provided. Specifically, the initial structure 10 can include a substrate 100, a cap layer 106, a stop layer 108, a stack structure 110, and a vertical channel structure 130.

[0062] In one embodiment, substrate 100 includes a dielectric substrate. The dielectric substrate may be a dielectric layer formed on a silicon substrate, such as a silicon oxide layer. In one embodiment, capping layer 106 is made of a dielectric material, such as silicon oxide. In one embodiment, stop layer 108 is made of doped polysilicon. For example, stop layer 108 may be a P-type doped (P+) polysilicon layer.

[0063] The stacked structure 110 may include a plurality of dielectric layers 112 and a plurality of sacrificial layers 114 stacked alternately.

[0064] In one embodiment, the dielectric layer 112 and the sacrificial layer 114 can be different dielectric materials. For example, the dielectric layer 112 can be a silicon oxide layer; the sacrificial layer 114 can be a silicon nitride layer. The number of dielectric layers 112 and sacrificial layers 114 can be adjusted as needed, and the present invention is not limited thereto.

[0065] The vertical channel structure 130 can be formed in the opening 20. For example... Figure 1 As shown, the opening 20 (also referred to as the first opening) penetrates the stacked structure 110, the stop layer 108, the capping layer 106, and extends partially into the substrate 100. Specifically, the vertical channel structure 130 may include a channel layer 132, an insulating pillar 134, a dielectric material 135, a first source / drain pillar 136, and a second source / drain pillar 138. The first source / drain pillar 136 and the second source / drain pillar 138 penetrate the dielectric material 135 and extend partially into the substrate 100. In this embodiment, the polysilicon materials 142, 144 and the polysilicon layers 102, 104 have the same material, such as N-type doped (N+) polysilicon material. In this case, the first source / drain pillar 136 may include a polysilicon layer 102 (also referred to as the first portion) embedded in the substrate 100 and a polysilicon material 142 (also referred to as the second portion) disposed on the polysilicon layer 102. Similarly, the second source / drain post 138 may also include a polysilicon layer 104 (also referred to as the first portion) embedded in the substrate 100 and a polysilicon material 144 (also referred to as the second portion) disposed on the polysilicon layer 104. In this embodiment, the cross-sectional area of ​​the polysilicon layers 102 and 104 may be smaller than the cross-sectional area of ​​the polysilicon materials 142 and 144. That is, the perimeter of the polysilicon layers 102 and 104 may be located within the area of ​​the polysilicon materials 142 and 144, such as... Figure 4B As shown. An insulating post 134 is disposed between the first source / drain post 136 and the second source / drain post 138 to separate the first source / drain post 136 and the second source / drain post 138. Additionally, a channel layer 132 is located on the sidewall of the opening 20 and can laterally surround the insulating post 134, the dielectric material 135, the first source / drain post 136, and the second source / drain post 138.

[0066] like Figure 1 As shown, the initial structure 10 may optionally include a plurality of oxide layers 124, 128. Oxide layer 124 may be disposed between sacrificial layer 114 and channel layer 132, while oxide layer 128 may be disposed between stop layer 108 and channel layer 132. Oxide layer 124 may be formed by oxidizing the sidewalls of sacrificial layer 114, while oxide layer 128 may be formed by oxidizing the sidewalls of stop layer 108. In one embodiment, oxide layer 124 and oxide layer 128 are made of different materials. For example, oxide layer 124 may be a silicon oxynitride layer, while oxide layer 128 may be a silicon oxide layer. In one embodiment, the oxidation process includes thermal oxidation, wet oxidation, or a combination thereof. Notably, since the oxidation rate of stop layer 108 is faster than that of sacrificial layer 114, the thickness of oxide layer 128 may be greater than the thickness of oxide layer 124.

[0067] After forming the vertical channel structure 130, a gate replacement process can be performed to replace the sacrificial layer 114 in the stacked structure 110 with the conductor layer 154, such as... Figures 2 to 4B As shown.

[0068] First, please refer to Figure 2 An opening 30 (also referred to as a second opening) is formed in the stacked structure 110 adjacent to the vertical channel structure 130. The opening 30 extends through the stacked structure 110 to rest on and expose the stop layer 108. Although Figure 2 The bottom surface of the illustrated opening 30 is flush with the top surface of the stop layer 108, but this is not a limitation of the invention. In other embodiments, the bottom surface of the opening 30 may be higher or lower than the top surface of the stop layer 108.

[0069] It is worth noting that, in this embodiment, the opening 30 includes at least two slit channels 30T and a plurality of slit openings 30H, such as Figure 8A As shown. Specifically, from a cross-sectional perspective, the slot channel 30T can penetrate the stacked structure 110 and expose the stop layer 108, as... Figure 2 As shown by label 30. From Figure 8AFrom a top-viewing angle, the slit channels 30T can extend along the X direction and be arranged along the Y direction to divide the multiple vertical channel structures 130 into multiple array regions AR arranged along the Y direction. In this embodiment, the vertical channel structures 130 are formed between two slit channels 30T. On the other hand, slit openings 30H can be discretely formed between the vertical channel structures 130 of each array region AR. In this embodiment, the shape of the slit openings 30H can be dot-shaped. In this case, the average diameter 30d of the slit openings 30H can be greater than or equal to the average width 30w of the slit channels 30T, i.e., 30d ≥ 30w. The average diameter 30d of the slit openings 30H can be greater than or equal to the average diameter 130d of the vertical channel structures 130, i.e., 30d ≥ 130d. In one embodiment, the average diameter 130d of the vertical channel structures 130 can be between 100 nm and 350 nm.

[0070] Refer back Figure 8A Generally, without the slit aperture 30H, the distance 35 between two adjacent slit channels 30T can be between 1 μm and 20 μm, or less than 200 times the average diameter 130d of the vertical channel structure 130. If the distance 35 between two adjacent slit channels 30T is too large, subsequent etching processes may fail to completely remove the sacrificial layer 114 in the middle region of the array region AR. In this case, silicon nitride residue will appear in the middle region of the array region AR, leading to poor filling of subsequent conductor layers (or gates). Therefore, in the conventional method, the distance 35 between two adjacent slit channels 30T cannot be increased to accommodate more vertical channel structures 130, thus failing to improve the integration density of memory devices.

[0071] On the other hand, when Figure 2 The higher the stacked structure 110 is, the wider the upper part of the opening 20 will be than the lower part due to the aspect ratio. When the upper width of the opening 20 is too large, the upper spacing 130s between two adjacent vertical channel structures 130 (or two adjacent openings 20) will be affected. Figure 8A The area shown (as shown) may become too small, which could prevent subsequent etching processes from completely removing the sacrificial layer 114. In this case, silicon nitride residue may also occur in the region between two adjacent vertical channel structures 130, leading to poor filling of subsequent conductor layers (or gates).

[0072] To address the aforementioned issues, this embodiment discretely forms multiple slit openings 30H between multiple vertical channel structures 130 to increase the removal efficiency of the sacrificial layer 114 and the conductor layer 154 in the gate replacement process. Figure 4A) to improve the fill efficiency of the memory element, and thus to improve the yield of the memory element. In this case, the distance 35 between two adjacent slit trenches 30T can be greater than or equal to 20 μm, and thus more vertical channel structures 130 can be accommodated. Therefore, the present embodiment can also improve the integration of the memory element.

[0073] Next, please refer to Figure 3 , an etching process is performed through the openings 30 to remove the sacrificial layer 114 to form a plurality of voids 34 between the dielectric layers 112. The voids 34 laterally expose the oxide layer 124. That is, the voids 34 are defined by the dielectric layers 112 and the oxide layer 124. It is worth noting that the oxide layer 124 can be regarded as an etch stop layer for the etching process to remove the sacrificial layer 114 to avoid over-etching and thus to damage the channel layer 132. In one embodiment, the etching process can be a wet etching process. For example, when the sacrificial layer 114 is silicon nitride, the etching process can be performed by using an etching solution containing phosphoric acid, and the etching solution is poured into the openings 30 (including the slit trenches 30T and the slit openings 30H) to remove the sacrificial layer 114. Since the etching solution has a high etching selectivity to the sacrificial layer 114, the sacrificial layer 114 can be completely removed, while the dielectric layers 112, the stop layer 108 and the cap layer 106 are not removed or only a small amount of them is removed.

[0074] Figure 8B An enlarged schematic view of the region 40 in Figure 8A is shown. In one embodiment, as shown in Figure 8B , a first portion of the plurality of slit openings 30H has a removal limit length K1 at a first removal limit area A1 of the sacrificial layer 114 removed in the gate replacement process. A second portion of the plurality of slit openings 30H has a removal limit length K2 at a second removal limit area A2 of the sacrificial layer 114 removed in the gate replacement process. The first removal limit area A1 and the second removal limit area A2 partially overlap. That is, the sum of the removal limit lengths of the adjacent two slit openings 30H removed in the gate replacement process (i.e., equivalent to a total removal limit diameter 2(K1+K2)) can be greater than the distance D1 between the adjacent two slit openings 30H, i.e., 2(K1+K2) > D1. In this case, the present embodiment can ensure that the sacrificial layer 114 located in the middle region of the array region AR is completely removed through the slit openings 30H.

[0075] Figure 8C An enlarged schematic view of the region 50 in Figure 8A is shown. In one embodiment, as shown in Figure 8B and Figure 8CAs shown, the removal limit area A1 / A2 of one of the multiple slit openings 30H in the gate replacement process for removing the sacrificial layer 114 partially overlaps with the removal limit area A3 of one of the two slit channels 30T in the gate replacement process for removing the sacrificial layer 114. That is, the sum of the removal limit lengths (K1+K3) of the sacrificial layer 114 from the slit opening 30H to the slit channel 30T in the gate replacement process can be greater than the distance D2 between the slit opening 30H and the slit channel 30T, i.e., K1+K3>D2.

[0076] from Figures 8A to 8C As can be seen, in this embodiment, the slot openings 30H discretely configured between two adjacent slot channels 30T can be used to remove the sacrificial layer 114 located in the middle region of the array region AR, while the slot channels 30T are used to remove the sacrificial layer 114 located in the peripheral region of the array region AR. With the slot openings 30H and slot channels 30T combined, this embodiment ensures that all sacrificial layers 114 located in the array region AR are completely removed through the slot openings 30H and slot channels 30T. Therefore, this embodiment not only solves the conventional silicon nitride residue problem but also increases the number of vertical channel structures 130 in the array region AR, thereby improving the memory integration density and area utilization.

[0077] Figures 9 to 12 The diagram illustrates the arrangement of slit openings according to various embodiments of the present invention.

[0078] Although Figure 8A The illustration shows the slit openings 30H arranged in an alternating pattern along the X direction, but the invention is not limited thereto. In other embodiments, the slit openings 30H may also be arranged in a single line along the X direction, such as... Figure 9 As shown. In an alternative embodiment, the slit opening 30H can also be arranged in a double-line or multi-line arrangement along the X direction, such as... Figure 10 As shown.

[0079] Although Figures 8A to 10 The slit opening 30H is depicted as a dot shape, but this invention is not limited thereto. In other embodiments, the slit opening 30S may also be strip-shaped. Specifically, as shown... Figure 11 As shown, the average length L of the multiple slit openings 30S is greater than three times the average width W of the multiple slit openings 30S, i.e., L > 3W. The average width W of the slit openings 30S can be greater than or equal to the average width 30w of the slit channel 30T, i.e., W ≥ 30w. The average width W of the slit openings 30S can be greater than or equal to the average diameter 130d of the vertical channel structure 130, i.e., W ≥ 130d. In this embodiment, the strip-shaped slit openings 30S can be regarded as slit channels with shorter lengths. Therefore, when performing... Figure 2During the step of forming the opening 30, the slit opening 30S can reduce the loading effect of this step so that the slit opening 30S and the slit channel 30T can stop on the stop layer 108 almost simultaneously. That is, the slit opening 30S and the slit channel 30T can have the same depth and cross-sectional profile.

[0080] In addition, although Figure 11 The illustration shows the slit openings 30S arranged in a single line along the X direction, but the invention is not limited thereto. In other embodiments, the slit openings 30S may also be arranged in an alternating pattern along the X direction, such as... Figure 12 As shown. In an alternative embodiment, the slit openings 30S may also be arranged in a double-line or multi-line arrangement along the X direction. In another embodiment, the dot-shaped slit channels 30T and the strip-shaped slit openings 30S may also be arranged as shown. Figure 11 The same layout of the slit openings shown.

[0081] Please refer back to this. Figure 4A and Figure 4B A charge storage layer 120 and a conductor layer 154 are sequentially formed in the gap 34, thereby completing the three-dimensional AND-gate flash memory 1 of the present invention. Specifically, as Figure 4A As shown, the charge storage layer 120 conformally covers the voids 34 to surround the conductor layer 154. In one embodiment, the charge storage layer 120 may be a composite layer consisting of a tunneling layer, a charge storage layer, and a barrier layer. The tunneling layer, the charge storage layer, and the barrier layer may be considered as oxide / nitride / oxide (ONO), respectively. In one embodiment, the material of the conductor layer 154 is, for example, polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix), or cobalt silicide (CoSix). Furthermore, after forming the charge storage layer 120 and before forming the conductor layer 154, a buffer layer and a barrier layer may be sequentially formed between the charge storage layer 120 and the conductor layer 154. The material of the buffer layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as alumina (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or combinations thereof. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0082] In this embodiment, the three-dimensional AND-gate flash memory 1 has a plurality of storage cells 160. Specifically, as... Figure 4A As shown, the three-dimensional AND-gate flash memory 1 has four memory cells 160 stacked on top of each other. However, the invention is not limited thereto; in other embodiments, the number of memory cells 160 can be adjusted according to the number of conductor layers 154 in the stacked structure 210. Furthermore, although... Figure 4A and Figure 4BOnly one vertical channel structure 130 is shown, but the present application is not limited thereto. In alternative embodiments, the three-dimensional AND flash memory 1 can include a plurality of vertical channel structures 130, and these vertical channel structures 130 can be arranged in an array in the top view, as shown in Figure 8A

[0083] To operate the three-dimensional AND flash memory 1, after the three-dimensional AND flash memory 1 is fabricated, conductive lines can be formed over the three-dimensional AND flash memory 1 to electrically connect to the three-dimensional AND flash memory 1. In the present embodiment, some of the conductive lines formed over and electrically connected to the first source / drain pillars 136 as the source are source lines, and other conductive lines formed over and electrically connected to the second source / drain pillars 138 as the drain are bit lines, and these source lines and bit lines are arranged parallel to each other without contacting each other.

[0084] The operation of the memory cell 160 in the three-dimensional AND flash memory 1 is described below.

[0085] For the three-dimensional AND flash memory 1, each memory cell 160 can be operated individually. The write (program) operation, read operation, or erase operation can be performed by applying operating voltages to the first source / drain pillar 136, the second source / drain pillar 138, and the corresponding conductor layer 154 (which can be considered as a gate or word line) of the memory cell 160. During the read operation, as shown in Figure 4B th ) of the corresponding memory cell 160, the channel region in the channel layer 132 of the vertical channel structure 130 intersecting the selected conductor layer 154 (which can be considered as a gate or word line) is turned on. In this case, current flows from the bit line into the second source / drain pillar 138 (which can be considered as a drain pillar), through the turned-on channel region (e.g., the directions indicated by arrows El, E2), to the first source / drain pillar 136 (which can be considered as a source pillar), and finally to the source line. Each memory cell 160 on the same vertical channel structure 130 is electrically connected in parallel.

[0086] Referring to Figure 5 , after the gate replacement process, a dielectric material can be formed to fill the opening 30 and extend to cover the top surface of the stack structure 210. Then, a planarization process (e.g., a CMP process) is performed to remove the excess dielectric material on the top surface of the stack structure 210, thereby forming a dielectric layer 230 in the opening 30. In this case, the top surface of the dielectric layer 230 can be coplanar with the top surface of the stack structure 210. In one embodiment, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0087] ​​In another embodiment, after the gate replacement process, a dielectric material can be conformally formed to fill the opening 30 and extend to cover the top surface of the stacked structure 210. A conductor material is then formed on the dielectric material. Next, a planarization process (e.g., CMP) is performed to remove excess dielectric and conductor material from the top surface of the stacked structure 210, thereby forming a composite structure 330 in the opening 30. In this case, the top surface of the composite structure 330 may be coplanar with the top surface of the stacked structure 210. Figure 6 As shown, the composite structure 330 includes a conductor feature 334 and a dielectric layer 332 covering the conductor feature 334. In one embodiment, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, while the conductor material includes polycrystalline silicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi). x ) or cobalt silicide (CoSi) x In this embodiment, dielectric layer 332 can be used to electrically isolate conductor feature 334 from conductor layer 154 (or stop layer 108).

[0088] The three-dimensional AND gate flash memory 1 in the above embodiment uses an oxide / nitride / oxide last (ONOlast) process to form the charge storage layer 220. However, the present invention is not limited thereto. In other embodiments, the three-dimensional AND gate flash memory 2 can also use an ONO first (ONO first) process to form the charge storage layer 220. For details, please refer to the following paragraphs.

[0089] Figure 7A and Figure 7B These are cross-sectional and planar schematic diagrams of a three-dimensional NAND flash memory according to other embodiments of the present invention.

[0090] Please refer to Figure 7A A three-dimensional NAND flash memory 2 is provided. The 3D NAND flash memory 2 includes a substrate 500. A stop layer 508 is formed on the substrate 500. The stop layer 508 includes a polysilicon layer, which can serve as a common source plane (or common source line) of the 3D NAND flash memory 2. A stacked structure 510 is formed above the stop layer 508. The stacked structure 510 includes a plurality of alternately stacked dielectric layers 512 and a plurality of conductor layers 554. The conductor layers 554 can be regarded as gates or word lines. A vertical channel structure 530 may include a charge storage layer 520, a channel layer 532, and an insulating pillar 534. Reference Figure 7AThe insulating pillar 534 can penetrate the cap layer 516, the stack structure 510, and the stop layer 508, and partially extend into the substrate 500. The channel layer 532 is in physical contact with the conductive plug 531. The channel layer 532 can cover the sidewall and the bottom surface of the insulating pillar 534, and the conductive plug 531 can seal the top surface of the insulating pillar 534. In this case, the channel layer 532 can completely cover all surfaces of the insulating pillar 534. The charge storage layer 520 can be disposed between the channel layer 532 and the stack structure 510. The charge storage layer 520 between the channel layer 532 and the stop layer 508 is removed. The charge storage layer 520 directly contacts the stop layer 508.

[0091] Figure 7B is a schematic view along the plane of the B-B cutline of Figure 7A The channel layer 532 laterally surrounds the insulating pillar 534. The charge storage layer 520 laterally surrounds the channel layer 532. The materials of the insulating pillar 534, the channel layer 532, and the charge storage layer 520 are the same as those of the insulating pillar 134, the channel layer 132, and the charge storage layer 120 described in the previous paragraph, respectively.

[0092] In summary, the present embodiment of the present application forms a plurality of slit openings between the plurality of vertical channel structures to increase the removal efficiency of the sacrificial layer and the filling efficiency of the conductor layer in the gate replacement process, thereby improving the yield of the three-dimensional flash memory. In this case, the present embodiment not only solves the process bottleneck of the existing memory, but also increases the number of storage units per unit chip area, thereby improving the integration and area utilization of the memory.

Claims

1. A three-dimensional flash memory, comprising: Comprising: a substrate; a stack structure disposed on the substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of conductor layers stacked alternately; a stop layer disposed between the substrate and the stack structure; two adjacent slit channels, extending through the stack structure, wherein the two adjacent slit channels have an average width W sc ; a plurality of vertical channel structures disposed between the adjacent two slit trenches and penetrating through the stack structure, each vertical channel structure comprising a first source / drain pillar and a second source / drain pillar surrounded by a channel layer; and the adjacent two slit trenches extend along a first direction, and the plurality of slit openings are arranged along the first direction. a plurality of slit openings, discretely disposed between the plurality of vertical channel structures, and extending through the stack structure, wherein an average width W of the plurality of slit openings so greater than or equal to the average width W of the adjacent two slit channels sc wherein an oxide layer is disposed between the channel layer and the stop layer.

2. The three-dimensional flash memory of claim 1, wherein, The plurality of slit openings are strip-shaped, and an average length of the plurality of slit openings is greater than three times of an average width of the plurality of slit openings.

3. The three-dimensional flash memory of claim 1, wherein, A distance between the adjacent two slit trenches is between 1 μm and 20 μm.

4. The three-dimensional flash memory of claim 3, wherein, The slit openings have a dielectric layer electrically isolating the stop layer.

5. The 3D flash memory of claim 1, wherein, A shape of the plurality of slit openings under a top view angle comprises a dot shape, a strip shape, or a combination thereof.

6. The 3D flash memory of claim 1, wherein, When the shape of the plurality of slit openings is the dot shape, an average diameter of the plurality of slit openings is greater than or equal to an average width of the two slit trenches, and the average diameter of the plurality of slit openings is greater than or equal to an average diameter of the plurality of vertical channel structures.

7. The 3D flash memory of claim 1, wherein, The average width of the plurality of slit openings is greater than or equal to the average diameter of the plurality of vertical channel structures.

8. The 3D flash memory of claim 1, wherein, Comprising:

9. A method of forming a three-dimensional flash memory, comprising: forming a stop layer and a stack structure on a substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of sacrificial layers stacked alternately, the stop layer being formed between the substrate and the stack structure; forming a plurality of first openings in the stack structure and the stop layer; forming a plurality of vertical channel structures in the plurality of first openings respectively, the plurality of vertical channel structures being formed between adjacent two slit trenches and penetrating through the stack structure, each vertical channel structure comprising a first source / drain pillar and a second source / drain pillar surrounded by a channel layer; and performing a gate replacement process through the plurality of second openings to replace the plurality of sacrificial layers with a plurality of conductor layers. forming a plurality of second openings exposing the stop layer in the stack structure, wherein the plurality of second openings comprises at least two adjacent slit trenches having an average width W sc and a plurality of slit openings having an average width W so , the plurality of vertical channel structures formed between the two slit trenches, and the plurality of slit openings discretely formed between the plurality of vertical channel structures, wherein the average width W so of the plurality of slit openings is greater than or equal to the average width W sc of the two adjacent slit trenches, and wherein an oxide layer is disposed between the channel layer and the stop layer; ​ ​ 10. The method of claim 9, wherein the average width W of the plurality of slit apertures so greater than or equal to the average diameter of the plurality of vertical channel structures.

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