Memory device and method of forming the same

Abstract

Some embodiments relate to a memory device and a method of forming the same. The memory device includes a transistor having a first source / drain (S / D) region and a second S / D region; a first S / D contact disposed over the first S / D region, the first S / D contact extending longitudinally along a first direction; a second S / D contact disposed over the second S / D region; a first via landing on the first S / D contact, the first via extending longitudinally along a second direction different from the first direction; a second via landing on the second S / D contact, the first via having a length measured along the second direction that is greater than a length of the second via; a first wire connected to the first via; a second wire connected to the second via; and a memory structure disposed over the transistor and connected to the second wire.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each with smaller and more complex circuitry than the previous one. In the course of IC development, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or wire) that can be produced using manufacturing processes) has decreased. This scaling down process typically yields benefits through increased production efficiency and reduced associated costs. This shrinkage also increases the complexity of handling and manufacturing ICs.

[0003] One advancement in IC design and manufacturing is the development of non-volatile memory (NVM), particularly magnetic random access memory (MRAM). MRAM offers performance comparable to volatile static random access memory (SRAM) and density and lower power consumption comparable to volatile dynamic random access memory (DRAM). Compared to NVM flash memory, MRAM can provide faster access times and suffers less degradation over time. An MRAM cell is formed by a magnetic tunnel junction (MTJ), which consists of two ferromagnetic layers separated by a thin insulating barrier, and operates by electrons tunneling through the insulating barrier between the two ferromagnetic layers. In operation, the variable state of an MRAM cell (e.g., a logic "0" or "1") is typically read by measuring the resistance of the MTJ. Due to the magnetic tunneling effect, the resistance of the MTJ varies with the magnetic polarity. When a bias voltage is applied to the combined structure of the top metal line (e.g., bit line), the MTJ, the control transistor configured to drive the MTJ, and the bottom metal line (e.g., common source line), the series resistance of the combined structure can be obtained by measuring the current flowing through it. The series resistance includes the resistance of the MTJ and additional resistance. The additional resistance should be reduced to or maintained at the lowest possible desired value to improve the sensitivity and speed of the MRAM cell. While existing methods in MRAM device formation are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. For example, the wiring resistance associated with the control transistor is a significant contributor to the additional resistance in the MRAM cell, and if its value is high, it can degrade the performance of the memory circuitry. Therefore, there is a need for improvements in this area. Summary of the Invention

[0004] According to one aspect of an embodiment of this application, a memory device is provided, comprising: a transistor having a first source / drain (S / D) region and a second source / drain region; a first source / drain contact disposed above the first source / drain region, wherein the first source / drain contact extends longitudinally along a first direction; a second source / drain contact disposed above the second source / drain region; a first via resting on the first source / drain contact, wherein the first via extends longitudinally along a second direction different from the first direction; a second via resting on the second source / drain contact, wherein the first via has a length greater than that measured along the second direction; a first wire connected to the first via; a second wire connected to the second via; and a memory structure disposed above the transistor and coupled to the second wire.

[0005] According to another aspect of the embodiments of this application, a memory device is provided, comprising: an active region having a first source region, a second source region, and a drain region sandwiched between the first source region and the second source region; a first contact coupled to the first source region and a second contact coupled to the second source region, wherein each of the first contact and the second contact extends longitudinally along a first direction; a via extending longitudinally along a second direction different from the first direction, wherein the via contacts the first contact and the second contact; a wire extending longitudinally along the second direction and coupled to the via; and a magnetic tunnel junction (MTJ) disposed over the active region, wherein the MTJ has an electrode coupled to the drain region.

[0006] According to one aspect of an embodiment of this application, a method for forming a memory device is provided, comprising: forming an active region on a substrate; forming a first source region and a second source region in the active region; forming a first contact over the first source region and a second contact over the second source region; forming a dielectric layer over the first and second contacts; forming a trench in the dielectric layer, wherein the trench extends continuously from the first contact to the second contact in a top view and exposes the first and second contacts; filling the trench with a conductive material to form a via rail; forming a conductor in the dielectric layer, wherein the conductor contacts the via rail; and forming a memory structure over the conductor. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 This is an illustration of a memory system according to some embodiments;

[0009] Figure 2 This is a perspective view of a memory cell according to some embodiments;

[0010] Figure 3 A schematic diagram of a memory array according to some embodiments is shown;

[0011] Figure 4 A cross-sectional view of a semiconductor device having a memory array including an MTJ, according to some embodiments, is shown;

[0012] Figure 5 A top view of a semiconductor device having a memory array including an MTJ, according to some embodiments, is shown;

[0013] Figure 6A , Figure 6B , Figure 6C , Figure 7A and Figure 7B Illustrations are shown according to some embodiments Figure 5 A cross-sectional view of a semiconductor device in a semiconductor device;

[0014] Figure 8 A flowchart of a method for forming a semiconductor device having a memory array including an MTJ, according to some embodiments, is shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to readily describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Moreover, when numbers or ranges of numbers are described using terms such as “about,” “approximately,” etc., the term covers numbers included within certain variations (e.g., + / - 10% or other variations) based on the knowledge of those skilled in the art disclosed herein, unless otherwise stated. For example, the term “about 5 nm” may cover a size range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, etc.

[0017] This invention generally relates to semiconductor devices and manufacturing methods. More specifically, this invention relates to providing semiconductor devices having an array of magnetic random access memory (MRAM) devices (or cells) in which wiring resistance associated with transistors configured to control corresponding magnetic tunnel junctions (MTJs) is reduced. In some embodiments of the invention, the MTJs are disposed within the metallization layer of a multilayer interconnect (or MLI). The MTJs are connected to corresponding control transistors for read / write control. Vias connecting the source contacts of the transistors to wires in the bottom metallization layer (e.g., MO) of the MLI are formed as tracks, which expands the contact area between the via and the source contacts, as well as the contact area between the via and the wires, thereby reducing wiring resistance. By reducing wiring resistance, the sensitivity and speed of the MRAM device are improved.

[0018] Figure 1 This is an illustration of a memory system 100 according to some embodiments. The memory system 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of memory circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be connected to a corresponding word line WL and a corresponding bit line BL. The memory controller 105 may write data to or read data from the memory array 120 according to electrical signals through the word line WL and the bit line BL. In other embodiments, the memory system 100 includes a larger... Figure 1 Show more, fewer, or different components.

[0019] Memory array 120 is a hardware component for storing data. In one aspect, memory array 120 is implemented as a semiconductor memory device. Memory array 120 includes a plurality of memory circuits or memory cells 125. Memory array 120 includes: bit lines BL0, BL1…BLK, each extending along a first direction (e.g., the X direction); and word lines WL0, WL1…WLJ, each extending along a second direction (e.g., the Y direction). Word lines WL and bit lines BL can be conductive metals or conductive rails. In one aspect, each memory cell 125 is connected to a corresponding word line WL and a corresponding bit line BL, and can be operated according to the voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In one aspect, each memory cell 125 includes cross-connected transistors and MTJs. Each memory cell 125 can be a magnetic random access memory (MRAM) cell with MTJs. In some embodiments, memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0020] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bit line controller 112, a word line controller 114, and a timing controller 110. In one configuration, the word line controller 114 is circuitry that provides voltage or current through one or more word lines WL of the memory array 120, while the bit line controller 112 is circuitry that provides or senses voltage or current through one or more bit lines BL of the memory array 120. In one configuration, the timing controller 110 is circuitry that provides control signals or clock signals to synchronize the operation of the bit line controller 112 and the word line controller 114. The bit line controller 112 may be connected to the bit line BL of the memory array 120, while the word line controller 114 may be connected to the word line WL of the memory array 120. In one example, to write data to memory cell 125, word line controller 114 provides voltage or current to memory cell 125 via word line WL connected to memory cell 125, while bit line controller 112 applies a bias voltage to memory cell 125 via bit line BL connected to memory cell 125. In another example, to read data from memory cell 125, word line controller 114 provides voltage or current to memory cell 125 via word line WL connected to memory cell 125, while bit line controller 112 senses the voltage or current corresponding to the data stored in memory cell 125 via bit line BL connected to memory cell 125. In some embodiments, memory controller 105 includes a voltage or current corresponding to the data stored in memory cell 125. Figure 1 Show more, fewer, or different components.

[0021] Figure 2 It is shown as such Figure 1 A perspective view of an example memory cell 125, a building block of the memory array 120 shown. Specifically, Figure 2 A memory cell 125 is shown, which is an MRAM cell having an MTJ 180 (or MTJ stack 180). The MTJ 180 includes an upper magnetic plate 182 (or top magnetic plate) and a lower magnetic plate 184 (or bottom magnetic plate), which are separated by a thin insulating layer 186 (also called a tunnel barrier layer). One of the two magnetic plates (e.g., the lower magnetic plate 184) includes a magnetic layer pinned (therefore called a pinned layer or reference layer) to an antiferromagnetic layer (called a pinned layer), while the other magnetic plate (e.g., the upper magnetic plate 182) is a "free" magnetic layer (also called a free layer) whose magnetic field can be changed to one of two or more values ​​to store one of two or more corresponding data states.

[0022] The MTJ 180 uses tunneling magnetoresistance to store a magnetic field on an upper magnetic plate 182 and a lower magnetic plate 184. For a sufficiently thin insulating layer 186 (e.g., about 10 nm or less), electrons can tunnel from the upper magnetic plate 182 to the lower magnetic plate 184. Data can be written to the cell in several ways. In one method, a current flows between the upper magnetic plate 182 and the lower magnetic plate 184, inducing a magnetic field stored in the free layer (e.g., the upper magnetic plate 182). In another method, spin-transfer torque (STT) is used, where a spin-aligned or polarized electron flow is used to alter the magnetic field within the free layer relative to the reference layer. Other methods can be used to write data. However, all data writing methods involve altering the magnetic field within the free layer relative to the reference layer.

[0023] Due to the magnetic tunneling effect, the resistance of the MTJ 180 varies depending on the magnetic fields stored in the upper magnetic plate 182 and the lower magnetic plate 184. For example, when the magnetic fields of the upper magnetic plate 182 and the lower magnetic plate 184 are in the same direction (parallel), the MTJ 180 is in a low-resistance state (i.e., logic "0" state). The resistance of the MTJ 180 in the low-resistance state is denoted as Rp. When the magnetic fields of the upper magnetic plate 182 and the lower magnetic plate 184 are in opposite directions (antiparallel), the MTJ 180 is in a high-resistance state (i.e., logic "1" state). The resistance of the MTJ 180 in the high-resistance state is denoted as Rap. The direction of the magnetic field of the upper magnetic plate 182 can be changed by passing current through the MTJ 180. By measuring the resistance Rp or Rap between the upper magnetic plate 182 and the lower magnetic plate 184, the read circuit connected to the MTJ 180 can distinguish between the states of "0" and "1".

[0024] Figure 2Further illustrated, the upper magnetic plate 182 of the MTJ 180 is connected to the bit line (BL), the lower magnetic plate 184 of the MTJ 180 is connected to the drain (or source) of the transistor 190, the source (or drain) of the transistor 190 is connected to the source line (SL), and the gate of the transistor 190 is connected to the word line (WL). That is, the MTJ 180 is sandwiched between a metal mesh of word lines and source lines. The MTJ 180 can be accessed (e.g., read or written) via the bit line and source line. When data is written to or read from memory cell 125, the word line is asserted to turn on the transistor 190, and an appropriate bias is applied to the bit line to write or read the corresponding value from the corresponding memory cell 125. With appropriate bias driving, the current flowing through the combined structure of the bit line, MTJ 180, transistor 190, and source line can be measured. Therefore, the series resistance of the combined structure can be obtained from the values ​​of bias voltage and current, and the resistance of MTJ 180 can be derived. When the wiring resistance (denoted as Rs) from the bit line to the drain (or source) of transistor 190 and from the source line to the source (or drain) of transistor 190 is not ideal, the derived resistance of MTJ 180 is actually the low resistance of MTJ itself plus the wiring resistance under the low resistance state (i.e., Rp+Rs), and the high resistance of MTJ itself plus the wiring resistance under the high resistance state (i.e., Rap+Rs).

[0025] The operating speed and read / write margin of memory cell 125 can be benchmarked using tunnel magnetoresistive ratio (TMR), which is defined as follows:

[0026] TMR = ((Rap+Rs)-(Rp+Rs)) / (Rp+Rs) = (Rap-Rp) / (Rp+Rs). Since the wiring resistance Rs is in the denominator of the TMR expression, the wiring resistance reduces the TMR. Accordingly, the associated resistances, besides the resistance of the MTJ itself, should be reduced to or kept as low as possible to ensure the sensitivity and speed of the memory cell. However, due to vias in the memory cell, such as those connecting the source / drain regions of transistor 190 to the corresponding source lines and bit lines, a significant portion of the wiring resistance is present. It is necessary to reduce the wiring resistance associated with these vias to achieve greater read / write margins and faster read / write operations for the memory cell.

[0027] Figure 3 A schematic diagram of a memory array 300 according to one embodiment is shown. The memory array 300 includes a plurality of memory cells 302, which can be implemented as follows: Figure 1 and Figure 2The memory cell 125 is shown. For simplicity, each memory cell 302 includes an MTJ 304, shown as a free layer FL and a corresponding pinned layer PL. Figure 3 As shown, the memory array 300 includes MTJs 304 organized in an array (e.g., by rows and columns) and has bit lines (e.g., BL0, BL1), word lines (e.g., WL0, WL1), and a common source line (e.g., CSL). Each MTJ 304 is connected between a bit line and the drain of a corresponding transistor 306. The gate of transistor 306 is connected to the word line, and the source of transistor 306 is connected to the common source line. When transistor 306 is turned on, the current flowing through the drain and source of transistor 306 is determined by the resistance of the MTJ 304 (e.g., a high resistance Rap or a low resistance Rp), and the current is used to determine whether a "0" or a "1" is stored in the MTJ 304. Figure 3 As shown, one MTJ 304 is associated with one transistor 306. In some alternative embodiments, one MTJ 304 may be associated with two or more transistors connected in parallel. The parallel transistor configuration reduces the channel resistance contributed by the transistors. Additionally, in Figure 3 In this example, four bits are stored by four MTJ 304s. Those skilled in the art will readily understand that the memory array 300 may include more than... Figure 3 More MTJ 304s are shown to store a predetermined number of data bits.

[0028] Figure 4 An embodiment is shown. Figure 3 A schematic cross-sectional view of the memory array 300. For simplicity, Figure 4 Only a portion of the memory array 300 is shown, in particular Figure 3 The memory cell 302 is shown in the dashed rectangle.

[0029] like Figure 4 As shown, memory cell 302 includes a first transistor T1 and a second transistor T2 disposed on substrate 402. In one embodiment, transistors T1 and T2 are field-effect transistors (FETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In some embodiments, transistors T1 and T2 are formed as planar FETs or non-planar FETs. In further embodiments, each of transistors T1 and T2 is a FinFET device. A FinFET may have one or more non-planar gate structures for partially or completely surrounding one or more channel regions. Figure 4As shown, the first transistor T1 has a gate structure 404G-1, which is disposed above the substrate 402 between the source region 404S-1 and the drain region 404D. The second transistor T2 has a gate structure 404G-2, which is disposed above the substrate 402 between the source region 404S-2 and the drain region 404D. The drain region 404D is a common drain region shared by transistors T1 and T2. The source regions 404S-1, 404S-2, and drain region 404D are collectively referred to as the source / drain region 404. Each of the gate structures 404G-1 and 404G-2 includes a gate electrode 408, which is separated from the substrate 402 by a gate dielectric 406. In some embodiments, the gate electrode 408 may comprise polysilicon. In such embodiments, the gate dielectric 406 may include a dielectric material, such as an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), etc. In other embodiments, the gate electrode 408 may include a metal, such as aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, etc. In such embodiments, the gate dielectric 406 may include a high-k dielectric material, such as hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, aluminum oxide, zirconium oxide, etc.

[0030] Source / drain contacts MD are formed above source / drain regions 404. Specifically, source contacts MD-S are formed above source regions 404S-1 and 404S-2 in the interlayer dielectric (ILD) layer. Drain contacts MD-D are formed above a common drain region 404D in the ILD layer. Multiple intermetallic dielectric (IMD) layers (e.g., IMD0 to IMD6) are formed above the ILD layers, wherein each IMD layer has conductors (e.g., M0 to M6) and vias (e.g., VD and V0 to V5). Figure 4 In the example, via VD connects the source contact MD-S and the drain contact MD-D to the corresponding conductor M0 formed in the IMD layer IMD0. Similarly, gate via VG connects gate structures 414G-1 and 414G-2 to the corresponding conductor M0 formed in the IMD layer IMD0. Via V0 connects conductor M0 to conductor M1 formed in the IMD layer IMD1. Via V1 connects conductor M1 to conductor M2 formed in the IMD layer IMD2. Via V2 connects conductor M2 to conductor M3 formed in the IMD layer IMD3. Via V3 connects conductor M3 to conductor M4 formed in the IMD layer IMD4. Figure 4 In the example, MTJ structure 420 is formed in IMD layer IMD5. Figure 4The MTJ structure 420 shown is a simplified schematic diagram illustrating the bottom electrode via (BEVA) 422, MTJ 424, and top electrode via (TEVA) 426. BEVA 422 connects conductor M4 to MTJ 424. TEVA 426 connects MTJ 424 to via V5 formed in the IMD layer IMD6. Via V5 connects TEVA 426 to conductor M6 formed in the IMD layer IMD6. Two conductors M0 connected to the two source regions 404S-1 and 404S-2 are further connected together to form a common source line (CSL). Two conductors M1 connected to the two gate structures 404G-1 and 404G-2 are further connected together as word lines (WL). Accordingly, transistors T1 and T2 are connected in parallel. The parallel configuration of transistors T1 and T2 reduces the channel resistance by half when transistors T1 and T2 are turned on. Although channel resistance can be reduced by arranging transistors in parallel, vias (VD) can still be a major contributor to wiring resistance, especially since the cross-sectional area of ​​such vias is typically small.

[0031] exist Figure 4 In the illustrated embodiment, the word lines WL (e.g., WL0, WL1) of the memory array are formed in IMD layer IMD1, the common source line CSL is formed in IMD layer IMD0, the bit lines BL (e.g., BL0, BL1) are formed in IMD layer IMD6, and the MTJ structure is formed in IMD layer IMD5. Of course, these are merely examples and not limiting. Word lines, bit lines, common source lines, and MTJ structures can be formed in other IMD layers, and these and other variations are fully intended to be included within the scope of this invention.

[0032] Figure 5 This is a layout or top view 500 of a portion of a memory array including an MTJ according to some embodiments. In some embodiments, the memory array includes gate structures 404G-1, 404G-2, 404G-3, and 404G-4 (collectively referred to as gate structures 404G) elongated along the Y direction, and active regions 430-1 and 430-2 (collectively referred to as active regions 430) elongated along the X direction. These components can be arranged and used as described above regarding... Figure 3 The memory array 300 is described. In one aspect, the memory array 300 includes more than Figure 5 This can show more, fewer, or different components. For example, memory array 300 includes... Figure 5 Other components not shown (such as wiring metal, through-hole contacts).

[0033] In the illustrated embodiment, transistors T1 to T8 are formed at the intersection of gate structures 404G-1, 404G-2, 404G-3, 404G-4 and active regions 430-1, 430-2. For example, transistor T1 is formed at the intersection of active region 430-1 and gate structure 404G-1. For example, transistor T2 is formed at the intersection of active region 430-1 and gate structure 404G-2. In some embodiments, transistors T1 and T2 are formed as planar FETs or non-planar FETs. In further embodiments, each of transistors T1 and T2 is a FinFET device. Transistor T1 includes a source region 404S-1 and a drain region 404D. Transistor T2 includes a source region 404S-2 and a drain region 404D. Transistors T1 and T2 share the drain region 404D. The source regions and common drain regions of the other transistors T3 to T8 are similarly set in layout 500, and will not be described in detail here for the sake of simplicity.

[0034] The memory array includes source contacts MD-S-1, MD-S-2, and MD-S-3 (collectively referred to as source contacts MD-S) elongated along the Y direction. Each source contact MD-S extends through active regions 430-1 and 430-2 and contacts source regions formed in active regions 430-1 and 430-2. Accordingly, source regions associated with the same gate structure in different active regions are connected together via corresponding source contacts MD-S. In one example, each source contact MD-S has a width of approximately 15 nm to approximately 25 nm along the X direction. The memory array also includes drain contacts MD-D-1, MD-D-2, MD-D-3, and MD-D-4 (collectively referred to as drain contacts MD-D) elongated along the Y direction. Each drain contact MD-D extends through a corresponding common drain region. For example, drain contact MD-D-1 contacts the common drain region of transistors T1 and T2, drain contact MD-D-2 contacts the common drain region of transistors T3 and T4, drain contact MD-D-3 contacts the common drain region of transistors T5 and T6, and drain contact MD-D-4 contacts the common drain region of transistors T7 and T8. In one example, each drain contact MD-D has a length of approximately 35 nm to approximately 50 nm along the Y direction and a width of approximately 15 nm to approximately 25 nm along the X direction.

[0035] The memory array includes conductors M0-1, M0-2, M0-3, M0-4, M0-5, M0-6, and M0-7 (collectively referred to as conductors M0) formed in the IMD layer IMD0 and elongated along the X direction. Conductor M0-1 extends through gate structures 404G-1, 404G-2, 404G-3, and 404G-4. Gate via VG-1 connects gate structure 404G-1 to conductor M0-1. Gate via VG-2 connects gate structure 404G-2 to conductor M0-1. (The remaining text appears to be unrelated and likely refers to a separate section.) Figure 5 As depicted, conductor M0-1 is further connected to conductor M1, serving as a word line formed in the IMD layer IMD1, such as... Figure 4 As shown.

[0036] Conductor M0-2 extends through source contacts MD-S-1, MD-S-2, and MD-S-3. Conductor M0-2 serves as the common source line (CSL). In addition to connecting each source contact individually to conductor M0-2 via multiple vias VD, a via rail VDR-1 is formed between source contacts MD-S-1, MD-S-2, MD-S-3 and conductor M0-2. Via rail VDR-1 connects each source contact MD-S-1, MD-S-2, MD-S-3 to conductor M0-2. In the illustrated embodiment, via rail VDR-1 has the same length as conductor M0-2 along the X direction and a width smaller than conductor M0-2 along the Y direction. In one example, conductor M0-2 has a width of approximately 25 nm to approximately 35 nm, while via rail VDR-2 has a width of approximately 15 nm to approximately 20 nm. By using a continuous via rail instead of multiple separate vias, the contact area between the via and the conductor M0-2, as well as the contact area between the via and the source contact MD-S, is increased. This results in lower wiring resistance for the common source line. In some cases, implementing a via rail can reduce the wiring resistance for the common source line by approximately 15%. Similarly, the conductor M0-3 extends through the source contacts MD-S-1, MD-S-2, and MD-S-3, and the via rail VDR-2 connects each source contact MD-S-1, MD-S-2, and MD-S-3 to the conductor M0-3.

[0037] Each of the wires M0-4, M0-5, M0-6, and M0-7 extends through the corresponding drain contact MD-D. In the top view, wires M0-4 and M0-7 also overlap with the source contact MD-S-2. In the top view, wire M0-5 overlaps with the source contact MD-S-1. In the top view, wire M0-6 overlaps with the source contact MD-S-3. In one example, each of the wires M0-4, M0-5, M0-6, and M0-7 has a length of approximately 70 nm to approximately 95 nm along the X direction and a width of approximately 12 nm to approximately 25 nm along the W direction. That is, the width of wires M0-4, M0-5, M0-6, and M0-7 is less than the width of wire M0-2. Multiple vias VD-1, VD-2, VD-3, and VD-4 (collectively referred to as vias VD) connect the drain contact MD-D to the corresponding conductors M0-4, M0-5, M0-6, and M0-7. ​​Specifically, via VD-1 connects the drain contact MD-D-1 to conductor M0-4, via VD-2 connects the drain contact MD-D-2 to conductor M0-6, via VD-3 connects the drain contact MD-D-3 to conductor M0-5, and via VD-4 connects the drain contact MD-D-4 to conductor M0-7. ​​Each via VD has an extended width along the X-direction, which is greater than the width of the corresponding drain contact MD-D along the X-direction. The extended width increases the contact area between the via VD and the corresponding drain contact MD-D and helps reduce wiring resistance. Vias VDs with extended widths are also called slots VDs. In the illustrated embodiment, the width of the through-hole VD along the Y direction is substantially the same as the width of the wires M0-4, M0-5, M0-6, and M0-7. ​​In some embodiments, the slot VD has a square space in the top view, with an extended width on all four sides. In some alternative embodiments, the slot VD has a rectangular shape in the top view, such as... Figure 5 As shown. Wires M0-4, M0-5, M0-6, and M0-7 connect the drain contact MD-D to the MTJ formed in the higher IMD layer (e.g., IMD5). In layout 500, the four MTJs covering the four associated drain contacts MD-D are... Figure 5 The middle part is represented by four dashed boxes.

[0038] Now focus on reference Figure 6A , Figure 6B , Figure 6C . Figure 6A It shows the direction along the XZ plane. Figure 5 The cross-sectional view of a portion of the memory array shown is taken along line A-A. Figure 6B It shows the direction along the XZ plane. Figure 5 The cross-sectional view of a portion of the memory array shown is taken along the B-B line. Figure 6CIt shows the direction along the YZ plane. Figure 5 The cross-sectional view of a portion of the memory array shown is taken along the C-C line.

[0039] In some embodiments, substrate 402 may be a semiconductor substrate, such as a silicon substrate. Substrate 402 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 402 may include various doping configurations according to design requirements known in the art. For example, different doping profiles (e.g., n-wells, p-wells) may be formed on substrate 402 in regions designed for different device types (e.g., n-type field-effect transistors (NFETs), p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 402 may have isolation components (e.g., shallow trench isolation (STI) components) whose intervention provides regions for different device types. Substrate 402 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 402 may include compound semiconductors and / or alloy semiconductors. Additionally, substrate 402 may optionally include an epitaxial layer (epi-layer) that may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or may have other suitable enhancing features.

[0040] In some embodiments, active regions 430-1 and 430-2 are fin structures designed to form fin field-effect transistors (FinFETs). Active regions 430-1 and 430-2 may protrude from substrate 402 and extend parallel to each other along the X-direction. The fin structures can be formed by patterning substrate 402 using one or more photolithography processes, including dual patterning or multi-patterning processes. Active regions 430-1 and 430-2 are separated by an isolation structure 410. Isolation structure 410 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. Isolation structure 410 may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or localized oxidation of silicon (LOCOS) structures.

[0041] A gate structure 404G is formed over a substrate 402 and extends through an active region 430. Each gate structure 404G includes a gate stack having a gate dielectric and a gate electrode disposed on the gate dielectric. The gate dielectric includes a dielectric material, such as silicon oxide, germanium oxide, a high-k dielectric material layer, or a combination thereof. In another embodiment, the gate dielectric includes an interface layer (e.g., a silicon oxide layer or a germanium oxide layer) and a high-k dielectric material layer disposed on the interface layer. The gate electrode includes a conductive material layer, such as doped polysilicon, a metal, a metal alloy, or a combination thereof. The gate structure 404G can be formed by steps including forming a gate dielectric layer, forming a gate electrode layer disposed on the gate dielectric layer, and patterning the gate electrode layer and the gate dielectric layer. The formation of the gate structure 404G may also include a gate replacement step to replace a previously formed gate stack with a high-k dielectric and a metal. Gate replacement may include a gate-final operation or a high-k-final operation, wherein the gate dielectric and the gate electrode are replaced in a later manufacturing stage. The gate structure 404G may also include gate spacers formed on the sidewalls of the gate structure 404G by steps including deposition and anisotropic etching.

[0042] In some embodiments, each of the source region 404S and drain region 404D includes an epitaxial source / drain component formed over the active region 430-1 or 430-2 in the respective source or drain region. For NFETs, the epitaxial source / drain component may be n-type doped. For PFETs, the epitaxial source / drain component may be p-type doped. For example, for NFETs, the epitaxial source / drain component may include silicon and be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof; while for PFETs, the epitaxial source / drain component may include silicon germanium or germanium and be doped with boron, other p-type dopants, or combinations thereof. The epitaxial source / drain component can be formed by epitaxially growing (some) semiconductor material (e.g., Si, SiGe) over the active regions 430-1 and 430-2, for example, using CVD deposition techniques (e.g., vapor phase epitaxy), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof.

[0043] An ILD layer is formed over the substrate 402 and the gate structure 404G. An IMD0 layer is formed over the ILD layer. Both the ILD and IMD0 layers can be formed using any suitable dielectric material, such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The ILD and IMD0 layers can be formed using any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or combinations thereof.

[0044] Each source contact MD-S extends continuously along the Y direction through multiple source regions 404S formed in active regions 430-1 and 430-2. Each drain contact MD-D extends along the Y direction through a corresponding drain region 404D, but does not extend into adjacent active regions. In some embodiments, the source contacts MD-S and drain contacts MD-D are formed by forming trenches in the ILD layer and filling the trenches with a conductive material, such as titanium nitride (TiN), tantalum (Ta), titanium (Ti), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), molybdenum (Mo), titanium silicide (TiSi), tungsten silicide (WSi), platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi), or combinations thereof. A chemical mechanical polishing (CMP) process can then be performed to remove excess conductive material and expose the ILD layer.

[0045] Through-hole rails VDR-1 and VDR-2 extend continuously along the X direction and connect multiple source contacts MD-S together. In some embodiments, through-hole rails VDR-1 and VDR-2 are formed by forming trenches in the IMD0 layer and filling the trenches with a conductive material, such as titanium nitride (TiN), tantalum (Ta), titanium (Ti), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), molybdenum (Mo), titanium silicide (TiSi), tungsten silicide (WSi), platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi), or combinations thereof. Through-holes VD-1 and VD-2 are individually located on corresponding drain contacts MD-D. In some embodiments, through-holes VD-1 and VD-2 are formed by forming grooves in the IMD0 layer and filling the grooves with a conductive material. The conductive materials used for vias VD-1 and VD-2 can be similar to those used for via rails VDR-1 and VDR-2. In some embodiments, via rails VDR-1 and VDR-2, and vias VD-1 and VD-2 are formed together with conductors M0 in the IMD0 layer using a damascene or dual damascene process. Conductors M0 can be made of conductive materials such as cobalt (Co), aluminum (Al), copper (Cu), tungsten (W), or combinations thereof.

[0046] refer to Figure 6A By using continuous vias that pass through multiple source contacts, instead of isolating vias above each source contact, the contact area between the vias and the source contacts, and between the vias and the conductor M0, is increased. Accordingly, the wiring resistance along the common source line path is reduced. (Reference) Figure 6B The through-hole VD has an extended width W measured at its bottom. VDThe extended width W VD The width W of the drain contact MD-D, as measured at its top, is greater than the width of the drain contact MD-D. MD Accordingly, the entire top surface of the drain contact MD-D is used to contact the via VD, contributing to reduced contact resistance, which also helps reduce some of the wiring resistance in the memory cell. Additionally, the extended width W... VD Greater than width W MD Approximately 5% to approximately 30%. If it is less than approximately 5%, inaccurate coverage may cause misalignment between the via VD and the drain contact MD-D; if it is greater than approximately 30%, the via VD may become too wide and obscure the adjacent gate structure 404G, which may affect the function of the gate structure or cause an electrical short circuit. In some embodiments, the edge of the via VD is offset from the gate structure 404G. In some alternative embodiments, the edge of the via VD is located directly above the adjacent gate structure 404G, such as... Figure 6B As shown. As discussed above, the extended width W VD Not greater than width W MD 30% of the, providing a balance between the size of the via VD and the performance of the 404G gate structure. (Reference) Figure 6C The through-hole rail VDR has a width W measured at its top. VDR The width W VDR The width W of the wire M0 measured at its bottom is smaller than the width of the wire. M0 In some embodiments, the width W VDR Less than width W M0 Approximately 40% to approximately 60%. If the width W VDR Less than width W M0 If the width exceeds 60%, the through-hole rail VDR may become too narrow, leading to higher contact resistance. If the width W... VDR Less than width W M0 If the via rail VDR is less than 40%, it may become too wide and could accidentally short-circuit to the adjacent wire M0 used for drain connection.

[0047] Figure 7A and Figure 7B It shows Figure 6B and Figure 6C Alternative embodiment of the cross-sectional view shown. Figure 7A It shows the direction along the XZ plane. Figure 5 The cross-sectional view of a portion of the memory array shown is taken along the B-B line. Figure 7B It shows the direction along the YZ plane. Figure 5 The diagram shows a cross-sectional view of a portion of the memory array taken along the C-C line. For ease of understanding, the reference numerals are repeated, and for brevity, similar aspects will not be repeated below. Figure 7A and Figure 6B One difference between the embodiments is that the via VD has an inverted trapezoidal shape, which allows a larger top surface to contact the conductor M0 while maintaining the extended width W of the bottom surface. VD Not greater than width W MD 30%. The larger top surface of the through-hole VD increases the contact area and reduces the contact resistance. The inverted trapezoidal shape can be formed by a first etching process that forms tapered sidewalls during the formation of the groove. Figure 7B and Figure 6C One difference between the embodiments is that the through-hole rail VDR has a trapezoidal shape, which allows a larger bottom surface to contact the source contact MD-S while maintaining the width W of the top surface. VDR Less than width W M0 At least 40%. The larger bottom surface of the via rail VDR increases the contact area and reduces the contact resistance. The trapezoidal shape can be formed by extending the lower part of the trench during trench formation using a second etching process. The first and second etching processes can be performed separately to allow via VDs with inverted trapezoidal shapes and via rail VDRs with trapezoidal shapes to coexist in a single structure.

[0048] Figure 8 A flowchart of a method 800 for forming a semiconductor device with an MRAM array is shown. Many aspects of semiconductor devices are related to... Figure 1 The aspects of the illustrated memory system 100 are the same as or similar to those shown. Although method 800 is illustrated and described below as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be interpreted in a limiting sense. For example, some actions may occur in a different order, and / or simultaneously with other actions or events besides those illustrated and / or described herein. Furthermore, implementing one or more aspects or embodiments described herein may not require all the illustrated actions. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0049] In operation 802, an active region is formed on the substrate, for example... Figure 5 The active region 430 is used in operation 804. A gate structure is formed through the active region, for example... Figure 5 The gate structure is 404G. In operation 806, source / drain regions are formed in the active regions located on both sides of the gate structure, for example... Figure 5 The source region 404S and drain region 404D are shown in Figure 808. In operation 808, an ILD layer is formed over the gate structure and the source / drain regions, for example... Figures 6A-6C The ILD layer in the middle. In operation 810, source and drain contacts are formed in the ILD layer, for example... Figure 5The source contact MD-S and drain contact MD-D are shown in Figure 812. In operation 812, an IMD0 layer is formed above the ILD layer, for example... Figures 6B-6C The IMD0 layer in the middle. In operation 814, a slot is formed above the drain contact and a through-hole rail is formed above the source contact, for example... Figure 5 The slotted hole VD and through-hole rail VDR are used. In operation 816, conductors are formed in the IMD0 layer, for example... Figure 5 The conductor M0 overlaps with the via rail VDR, providing a common source line for the memory array. In operation 818, other IMD layers are formed above the IMD0 layer, and an MTJ structure is formed in one of the higher IMD layers, for example... Figure 4 The IMD1 to IMD6 and MTJ structure 420 in the middle.

[0050] While not intended to be limiting, one or more embodiments of the present invention provide numerous benefits for semiconductor devices and their fabrication. For example, embodiments of the present invention provide a semiconductor device having an array of MRAM cells with MTJs. Through-hole rails and vias have been implemented to reduce wiring resistance and improve the sensitivity and speed of the MRAM cells. Furthermore, the fabrication of such a semiconductor device can be readily integrated into existing semiconductor manufacturing processes.

[0051] In one exemplary aspect, the present invention relates to a memory device. The memory device includes: a transistor having a first source / drain (S / D) region and a second S / D region; a first S / D contact disposed above the first S / D region and extending longitudinally along a first direction; a second S / D contact disposed above the second S / D region; a first via resting on the first S / D contact and extending longitudinally along a second direction different from the first direction; a second via resting on the second S / D contact, the first via having a length greater than that measured along the second direction; a first conductor connected to the first via; a second conductor connected to the second via; and a memory structure disposed above the transistor and connected to the second conductor. In some embodiments, the memory structure is a magnetic tunnel junction (MTJ). In some embodiments, the MTJ has a bottom electrode connected to the second conductor. In some embodiments, the first conductor is located directly above the first via and extends longitudinally along the second direction. In some embodiments, the width of the first conductor, measured along the first direction, is greater than the width of the first via. In some embodiments, the first S / D region is a source region, the second S / D region is a drain region, a first conductor is connected to a common source line of the memory device, and a second conductor is connected to a bit line of the memory device. In some embodiments, the transistor has a length measured along a second direction from the outer edge of the first S / D region to the outer edge of the second S / D region, and wherein the length of the first via is greater than the length of the transistor. In some embodiments, the second via has a width measured along the second direction that is greater than the width of the second S / D contact. In some embodiments, the width of the second via is greater than about 5% to about 30% of the width of the second S / D contact. In some embodiments, the first via and the first conductor have the same length measured along the second direction.

[0052] In another exemplary aspect, the present invention relates to a memory device. The memory device includes: an active region having a first source region, a second source region, and a drain region sandwiched between the first and second source regions; a first contact connected to the first source region and a second contact connected to the second source region, each of the first and second contacts extending longitudinally along a first direction; a via extending longitudinally along a second direction different from the first direction, the via contacting the first and second contacts; a conductor extending longitudinally along the second direction and connected to the via; and a magnetic tunnel junction (MTJ) disposed above the active region, wherein the MTJ has an electrode connected to the drain region. In some embodiments, the conductor is located directly above the via. In some embodiments, the via has a width smaller than that of the conductor, measured along the first direction. In some embodiments, the width of the via is smaller than about 40% to about 60% of that of the conductor. In some embodiments, the via is a first via, and the memory device further includes: a third contact connected to the drain region; and a second via contacting the third contact, the second via having a width larger than that of the third contact, measured along the second direction. In some embodiments, the first via is wider than the second via along the second direction.

[0053] In another exemplary aspect, the present invention relates to a method. The method includes: forming an active region on a substrate; forming a first source region and a second source region in the active region; forming a first contact over the first source region and a second contact over the second source region; forming a dielectric layer over the first and second contacts; forming a trench in the dielectric layer, the trench extending continuously from the first contact to the second contact in a top view and exposing the first and second contacts; filling the trench with a conductive material to form a via rail; forming a conductor in the dielectric layer, the conductor contacting the via rail; and forming a memory structure over the conductor. In some embodiments, the first and second contacts extend longitudinally along a first direction, and the via rail and conductor extend longitudinally along a second direction perpendicular to the first direction. In some embodiments, the conductor completely covers the via rail in a top view. In some embodiments, the method further includes forming a drain region in the active region, the drain region being located between the first and second source regions; forming a third contact over the drain region; and forming a via contacting the third contact, the via having a width greater than that of the third contact.

[0054] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: A transistor having an active region including a first source / drain region and a second source / drain region; A first source / drain contact is disposed above the first source / drain region, wherein the first source / drain contact extends longitudinally along a first direction, and the active region extends longitudinally along a second direction different from the first direction, wherein, in a top view of the memory device, the first source / drain contact extends beyond the boundary of the active region along the first direction. The second source / drain contact is disposed above the second source / drain region; A first through hole is located on the first source / drain contact, wherein the first through hole extends longitudinally along the second direction; The second through-hole is located on the second source / drain contact, wherein the first through-hole has a length greater than that of the second through-hole, as measured along the second direction; A first wire is connected to the first through hole; A second wire is connected to the second through hole; and A memory structure is disposed on the transistor and coupled to the second wire.

2. The memory device according to claim 1, wherein, The memory structure is a magnetic tunnel junction.

3. The memory device according to claim 2, wherein, The magnetic tunnel junction has a bottom electrode connected to the second conductor.

4. The memory device according to claim 1, wherein, The first wire is located directly above the first through hole, and the first wire extends longitudinally along the second direction.

5. The memory device according to claim 4, wherein, The width of the first conductor, measured along the first direction, is greater than the width of the first through hole.

6. The memory device according to claim 1, wherein, The first source / drain region is a source region, the second source / drain region is a drain region, the first wire is connected to the common source line of the memory device, and the second wire is connected to the bit line of the memory device.

7. The memory device according to claim 1, wherein, The transistor has a length measured along the second direction from the outer edge of the first source / drain region to the outer edge of the second source / drain region, and wherein the length of the first via is greater than the length of the transistor.

8. The memory device according to claim 1, wherein, The second through hole has a width that is greater than the width of the second source / drain contact, as measured along the second direction.

9. The memory device according to claim 8, wherein, The width of the second through hole is 5% to 30% greater than the width of the second source / drain contact.

10. The memory device according to claim 1, wherein, The first through hole and the first wire have the same length as measured along the second direction.

11. A memory device, comprising: The active region has a first source region, a second source region, and a drain region sandwiched between the first source region and the second source region; A first gate structure is disposed between the first source region and the drain region; A second gate structure is disposed between the second source region and the drain region; A first contact coupled to the first source region and a second contact coupled to the second source region, wherein each of the first contact and the second contact extends longitudinally along a first direction; A through hole extends longitudinally along a second direction different from the first direction, wherein the through hole contacts the first contact and the second contact; A conductive wire, extending longitudinally along the second direction, and crossing the first gate structure and the second gate structure in a top view of the memory device, wherein the conductive wire is connected to the top surface of the via; and A magnetic tunnel junction is disposed above the active region, wherein the magnetic tunnel junction has an electrode coupled to the drain region.

12. The memory device according to claim 11, wherein, The wire is located directly above the through hole.

13. The memory device according to claim 11, wherein, The through hole has a width smaller than that of the wire when measured along the first direction.

14. The memory device according to claim 13, wherein, The width of the through hole is less than 40% to 60% of the width of the wire.

15. The memory device of claim 11, wherein, The through hole is the first through hole, and it also includes: A third contact is coupled to the drain region; and The second through hole contacts the third contact member, wherein the second through hole has a width greater than that of the third contact member when measured along the second direction.

16. The memory device according to claim 15, wherein, Along the second direction, the first through hole is wider than the second through hole.

17. A method of forming a memory device, comprising: An active region is formed on the substrate; A first source region and a second source region are formed in the active region; A drain region is formed in the active region, and the drain region is located between the first source region and the second source region; A first gate structure is formed between the first source region and the drain region, and a second gate structure is formed between the second source region and the drain region; A first contact is formed above the first source region, and a second contact is formed above the second source region; A dielectric layer is formed over the first contact and the second contact; A trench is formed in the dielectric layer, wherein the trench extends continuously from the first contact to the second contact in a top view and exposes the first contact and the second contact; The trench is filled with a conductive material to form a through-hole rail; A conductor is formed in the dielectric layer, wherein the conductor contacts the top surface of the via rail, and in the top view, the conductor crosses the first gate structure and the second gate structure; and A memory structure is formed on the wire.

18. The method according to claim 17, wherein, The first contact and the second contact extend longitudinally along a first direction, and the through-hole rail and the wire extend longitudinally along a second direction perpendicular to the first direction.

19. The method of claim 17, wherein, The conductor completely covers the through-hole rail in the top view.

20. The method of claim 17, further comprising: A third contact is formed above the drain region; as well as A through hole is formed to contact the third contact member, wherein the through hole has a width greater than that of the third contact member.

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