Memory cell, memory cell array, and method of operating a memory cell

Abstract

Embodiments of the invention provide a storage cell including a storage circuit and a multiplication circuit. The multiplication circuit includes an output node configured to output an output signal, a first transistor, and an initialization circuit. The first transistor connects the output node with the storage circuit and is configured to receive at least a second signal. The initialization circuit is connected to the first transistor through the output node and is configured to initialize the multiplication circuit in response to at least a third signal or a fourth signal. The storage circuit is configured to store a first value of a first signal of a first storage node. The multiplication circuit is connected to the storage circuit. The multiplication circuit is configured to generate the output signal in response to the first signal and the second signal. The output signal corresponds to a product of the first signal and the second signal. Embodiments of the invention also provide a storage cell array. Embodiments of the invention also provide a method of operating a storage cell.

Description

Technical Field

[0001] The embodiments disclosed herein generally relate to the semiconductor field, and more specifically, to memory cells, memory cell arrays, and methods of operating memory cells. Background Technology

[0002] Recent developments in the field of artificial intelligence have spawned a variety of products and / or applications, including but not limited to speech recognition, image processing, machine learning, and natural language processing. These products and / or applications typically use neural networks to process large amounts of data for learning, training, cognitive computing, and more. Summary of the Invention

[0003] One aspect of the present invention provides a storage unit comprising: a storage circuit configured to store a first value of a first signal of a first storage node; a multiplication circuit connected to the storage circuit, the multiplication circuit being configured to generate an output signal in response to the first signal and a second signal, the output signal corresponding to the product of the first signal and the second signal, the multiplication circuit comprising: an output node configured to output the output signal; a first transistor connected to the output node and the storage circuit and configured to receive at least the second signal; and an initialization circuit connected to the first transistor through the output node and configured to initialize the multiplication circuit in response to at least a third signal or a fourth signal.

[0004] Another aspect of the present invention provides a memory cell array comprising: a first set of memory circuits configured to store weight data, the first set of memory circuits including: a first memory circuit configured to store a first weight value of a first signal of a first memory node; a first set of multiplication circuits configured to perform in-memory computation (CIM) operations between the weight data and input data, the first set of multiplication circuits including: a first multiplication circuit connected to the first memory circuit, the first multiplication circuit being configured to generate an output signal in response to the first signal and a second signal, the output signal corresponding to a product operation of the in-memory computation between the first signal and the second signal, the first multiplication circuit including: a first output node configured to output the output signal; a first transistor connected to the first output node and the first memory circuit and configured to receive at least the second signal; and an initialization circuit connected to the first transistor through the first output node and configured to initialize the first multiplication circuit in response to at least a third signal or a fourth signal, wherein each multiplication circuit in the first set of multiplication circuits corresponds to each memory circuit in the first set of memory circuits.

[0005] Another aspect of the present invention provides a method of operating a memory cell, the method comprising: performing a write operation on the memory cell, the memory cell including a memory circuit and a multiplication circuit, the write operation comprising: storing a first value of a first signal in a first memory node of the memory circuit, the first signal corresponding to a first weight; performing an in-memory computation (CIM) operation between the first signal and a second signal via the multiplication circuit, the multiplication circuit including a first transistor and an initialization circuit, wherein performing the in-memory computation operation between the first signal and the second signal comprises: initializing an output signal of the multiplication circuit via the initialization circuit in response to at least a third signal or a fourth signal; and setting the output signal by the first transistor during a sensing phase of the memory circuit in response to at least a second signal. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram of a storage device according to some embodiments.

[0008] Figure 2A This is a schematic diagram of a storage device according to some embodiments.

[0009] Figure 2B This is a schematic diagram of a neural network according to some embodiments.

[0010] Figure 2C This is a schematic diagram of an integrated circuit (IC) device according to some embodiments.

[0011] Figure 3 This is a circuit diagram of a memory cell according to some embodiments.

[0012] Figure 4 This is a circuit diagram of a memory cell according to some embodiments.

[0013] Figure 5A According to some embodiments Figure 5C The truth table of the storage cell array shown.

[0014] Figures 5B to 5C This is a corresponding diagram of a storage cell array according to some embodiments.

[0015] Figures 5D to 5E According to some embodiments Figures 5B to 5C The waveform diagram corresponding to the shown memory cell array.

[0016] Figure 6 This is a circuit diagram of a memory cell according to some embodiments.

[0017] Figure 7A This is a flowchart of a method for operating circuits according to some embodiments.

[0018] Figure 7B This is a flowchart of a method for operating circuits according to some embodiments. Detailed Implementation

[0019] This disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0021] According to some embodiments, the memory cell array includes a plurality of memory cells. In some embodiments, each of the plurality of memory cells includes a storage circuit and a multiplication circuit.

[0022] In some embodiments, the multiplication circuit is connected to the storage circuit.

[0023] In some embodiments, the storage circuit is configured to store a first value of a first signal of a first storage node.

[0024] In some embodiments, the multiplication circuit is configured to generate an output signal in response to a first signal and a second signal. In some embodiments, the output signal corresponds to the product of the first signal and the second signal. In some embodiments, the output signal is generated by a computing-in-memory (CIM) operation between the first signal and the second signal.

[0025] In some embodiments, the multiplication circuit includes an output node configured to output an output signal, a first transistor, and an initialization circuit.

[0026] In some embodiments, the first transistor is connected to the output node and the storage circuit. In some embodiments, the first transistor is configured to receive at least a second signal.

[0027] In some embodiments, the initialization circuit is connected to the first transistor via an output node. In some embodiments, the initialization circuit is configured to initialize the multiplication circuit in response to at least a third or a fourth signal.

[0028] In some embodiments, the memory cell array is part of a CIM macro configured to perform CIM operations, which can be used in neural network applications and other applications. In some embodiments, including multiplication circuitry within each memory cell of the memory cell array allows for a reduction in the number of transistors in the multiplication circuitry of the CIM macro, thereby reducing the size of the CIM macro compared to other methods.

[0029] Figure 1 This is a block diagram of a memory device 100 according to some embodiments. A memory device is an integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuitry for other functions besides the memory device itself.

[0030] Storage device 100 includes a storage macro 110 and a storage controller 120. Storage macro 110 includes a storage array 112, one or more weighted buffers 114, and output circuitry 115. Storage controller 120 includes a word line driver 122, a bit line driver 124, an anti-phase line driver 125, control circuitry 126, and an input buffer 128. In some embodiments, one or more elements of storage controller 120 are included in storage macro 110, and / or one or more elements of storage macro 110 (other than storage array 112) are included in storage controller 120.

[0031] Macros have reusable configurations and can be used with IC devices of various types or designs. In some embodiments, macros are understood in the context of an architectural hierarchy similar to a subroutine / procedure called by a main program (or other subroutines) to perform a given computational function. In this situation, the IC device uses macros to perform one or more given functions. Thus, in this situation and in terms of architectural hierarchy, the IC device is similar to a main program, and the macro is similar to a subroutine / procedure. In some embodiments, macros are soft macros. In some embodiments, macros are hard macros. In some embodiments, macros are soft macros described digitally in register-transfer-level (RTL) code. In some embodiments, synthesis, placement, and routing have not been performed on the macro, making it possible to synthesize, place, and route soft macros for various process nodes. In some embodiments, macros are hard macros described digitally in a binary file format (e.g., Graphical Database System II (GDSII) stream format), where the binary file format represents the planar geometry, text labels, other information, etc., of one or more layout diagrams of the macro represented in a hierarchical form. In some embodiments, synthesis, placement, and routing have been performed on the macro, making the hard macro specific to a particular process node.

[0032] A storage macro is a macro that includes storage units, which are addressable to allow data to be written to or read from the storage units. In some embodiments, a storage macro also includes circuitry configured to provide access to the storage units and / or perform further functions associated with the storage units. For example, storage macro 110 includes a storage unit MC, as described herein, which forms circuitry configured to provide CIM functionality associated with the storage unit MC. In at least one embodiment, the storage macro configured to provide CIM functionality is referred to as a CIM macro. The described macro configuration is one example. Other configurations are within the scope of various embodiments.

[0033] The storage cells MC of the storage macro 110 are arranged in multiple columns and rows of the storage array 112. The storage controller 120 is electrically connected to the storage cells MC and is configured to control the operation of the storage cells MC, including but not limited to read operations, write operations, etc.

[0034] The storage array 112 also includes multiple word lines (also called "address lines") WL1 to WLr extending along rows, multiple bit lines (also called "data lines") BL1 to BLt extending along columns of storage cells MC, and multiple anti-phase lines (also called "anti-phase data lines") BLB1 to BLBt extending along columns of storage cells MC, where r and t are natural numbers. Each storage cell MC is electrically connected to the storage controller 120 via at least one of the word lines, at least one of the bit lines, and at least one of the anti-phase lines. In some example operations, the word lines are configured to transmit the address of a storage cell MC to be read, or to transmit the address of a storage cell MC to be written, etc. In at least one embodiment, a set of word lines is configured to be used as both read word lines and write word lines. In some embodiments, the bit lines and anti-phase lines are used to transmit data read from or written to storage cells MC indicated by corresponding word lines, etc.

[0035] In some embodiments, read bit lines and / or inverted read bit lines are configured to transmit data read from a memory cell MC indicated by a corresponding word line, and write bit lines and / or inverted write bit lines are configured to transmit data to be written to a memory cell MC indicated by a corresponding word line, etc.

[0036] Word lines are generally referred to herein as WL, bit lines as BL, and anti-phase lines as BLB. Various numbers of word lines, bit lines, and / or anti-phase lines in memory array 112 are within the scope of various embodiments. Indicative memory types of memory cells MC include, but are not limited to, static random access memory (SRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), phase-change RAM (PCRAM), spin-transfer torque RAM (STTRAM), floating-gate metal-oxide-semiconductor field-effect transistors (FGMOS), spintronic, etc. In one or more exemplary embodiments described herein, the memory cell MC includes SRAM memory cells.

[0037] exist Figure 1 In an instance configuration, the storage unit MC is a single-port storage unit. In some embodiments, the port of the storage unit is represented by a set of word lines WL / bit lines BL / anti-phase lines BLB (here referred to as the WL / BL / BLB set) configured to provide access to the storage unit in read operations (i.e., read access) and / or write operations (i.e., write access). A single-port storage unit has one WL / BL / BLB set, which is configured for both read and write access, but not simultaneously. A multi-port storage unit has multiple WL / BL / BLB sets, each configured for read-only access, write-only access, or both read and write access. An instance of a single-port storage unit is referenced. Figure 1 , Figure 3 , Figure 4 , Figures 5A to 5E , Figure 6 and Figures 7A to 7B To describe. Other configurations or other numbers of ports for the storage cells in storage array 112 are within the scope of this disclosure. For example, in some embodiments, one or more references Figure 1 , Figure 3 , Figure 4 , Figures 5A to 5E , Figure 6 and Figures 7A to 7B The single-port storage unit described can be replaced by the corresponding multi-port storage unit.

[0038] Storage array 112 includes multiple storage segments. In some embodiments, a storage segment includes storage rows, storage columns, storage repositories, etc. A storage row includes multiple storage cells connected to the same word line WL. A storage column (also referred to as a "storage string") includes multiple storage cells connected to the same bit line BL and the same bit line BLB. A storage repository includes multiple storage rows and / or multiple storage columns. In at least one embodiment, a storage block includes a portion of storage array 112 having multiple storage rows and multiple storage columns. In some embodiments, a storage segment includes multiple storage blocks. In an example, a first storage segment 105 includes a storage column of storage cells MC connected to bit line BL1 and anti-phase line BLB1, a second storage segment 107 includes a storage column of storage cells MC connected to bit line BL2 and anti-phase line BLB2, etc. Other ways of dividing storage array 112 into multiple storage segments are within the scope of various embodiments.

[0039] Each storage unit MC includes a storage section 117a (shown only in storage unit 117 for ease of explanation) and a calculation section 117b (shown only in storage unit 117 for ease of explanation). Each storage unit MC is configured to store a weight data W and is configured to perform CIM operation on this weight data W and a received data D_IN. Each storage section 117a corresponds to each calculation section 117b.

[0040] Each storage section 117a of the storage unit MC is configured to store a weight data W, and each calculation section 117b of the storage unit MC is configured to perform CIM operation on the weight data W and a received data D_IN.

[0041] In one or more exemplary embodiments described herein, the storage unit MC is a single-bit storage unit, i.e., each storage unit is configured to store one bit of weight data W and calculate the corresponding bit of the output signal Dout based on a CIM operation of this weight data bit W and the bits of the received data D_IN. This is one example, and it is within the scope of various embodiments that each of multiple storage units is configured to store multiple bits of weight data W and perform a corresponding CIM operation on the corresponding multiple bits of weight data W. In some embodiments, a unit storage unit is also referred to as a bit unit. For example, storage unit 113 connected to word line WL1, bit line BLt, and anti-phase line BLBt is configured to store a copy of weight data W1,t and perform a CIM operation on this copy of weight data W1,t and the corresponding received input data in the received input data D_IN. The combination of multiple weight data W stored in multiple storage units constitutes the weight value to be used in the CIM operation. For simplicity, a weight data stored in one storage unit MC, multiple weight data stored in multiple storage units MC, or all weight data stored in all storage units MC of storage array 112 are referred to herein as weight data W.

[0042] Each computational section 117b of the storage unit MC is connected to the output of the input buffer 128 and is configured to receive input data D_IN. Figure 1 In the example configuration, input data D_IN is provided from input buffer 128 in storage controller 120. In one or more embodiments, input data D_IN is output data (e.g., output data D_OUT) provided from another storage macro (not shown) of storage device 100. In some embodiments, as described herein, input data D_IN is provided serially to computation section 117b in the form of a bit stream.

[0043] The computation section 117b of the storage unit MC is configured to generate output data DO corresponding to a CIM operation performed on the input data D_IN and weight data W read from one or more storage units MC, based on the input data D_IN from the input buffer 128. Examples of CIM operations include, but are not limited to, mathematical operations, logical operations, and combinations thereof. In at least one embodiment, the computation section 117b includes a multiply-accumulate (MAC) circuit, and the CIM operation includes multiplication of one or more multi-bit weight values ​​with one or more multi-bit input data values. Additional computation sections or circuits configured to perform CIM operations other than multiplication are within the scope of various embodiments. The output data DO is provided as input data to the output circuit 115.

[0044] Weight buffer 114 is connected to storage array 112 and configured to temporarily store new weight data to be updated to storage array 112. In some embodiments, weight buffer 114 is located outside storage macro 110. In some embodiments as described herein, each storage segment is connected to a corresponding weight buffer. In one or more embodiments as described herein, a common weight buffer is connected to several storage segments. Weight buffer 114 is connected to storage cells MC in storage array 112 via bit line BL and anti-phase line BLB. In a weight data update operation, new weight data is written from weight buffer 114 and via the corresponding bit line BL and the corresponding anti-phase line BLB to one or more storage cells MC. Figure 1 The diagram schematically illustrates that a weight buffer 114 is connected to a memory controller 120 to receive new weight data and / or control signals specifying when and / or in which memory cells (MCs) the new weight data will be updated. In at least one embodiment, new weight data is received from external circuitry outside the memory device 100, such as a processor as described herein. The new weight data is received via one or more input / output (I / O) circuits (not shown) of the memory controller 120 and forwarded to the weight buffer 114. Inspirational weight buffers include, but are not limited to, registers, memory cells, or other circuit elements configured for data storage.

[0045] Output circuit 115 has an input connected to bit line BL / inverting line BLB to receive output data DO from one or more memory cells MC. Output circuit 115 is configured to latch the output data DO received from memory array 112 from bit line BL / inverting line BLB, and provides an output signal D_OUT at the output of output circuit 115. Examples of output circuits 115 include registers, flip-flops, latches, etc.

[0046] In some embodiments, output data D_OUT is provided as input data to another storage macro (not shown) of storage device 100. In one or more embodiments, output data D_OUT is connected to external circuitry outside storage device 100, such as the processor described herein, via one or more I / O output circuits (not shown) of storage controller 120.

[0047] exist Figure 1In an exemplary configuration, controller 120 includes word line driver 122, bit line driver 124, anti-phase line driver 125, control circuitry 126, and input buffer 128. In at least one embodiment, controller 120 further includes one or more clock generators for providing clock signals to various components of storage device 100, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations within storage device 100.

[0048] Word line driver 122 is connected to memory array 112 via word line WL. Word line driver 122 is configured to decode the row address of the memory cell MC selected for access in a read or write operation. Word line driver 122 is configured to provide voltage to the selected word line WL corresponding to the decoded row address, and to provide different voltages to other unselected word lines WL.

[0049] Bit line driver 124 is connected to memory array 112 via bit line BL. Bit line driver 124 is configured to decode the column address of the memory cell MC selected for access in a read or write operation. Bit line driver 124 is configured to provide voltage to the selected bit line BL corresponding to the decoded column address, and to provide different voltages to other unselected bit lines BL.

[0050] The anti-phase line driver 125 is connected to the memory array 112 via an anti-phase line BLB. The anti-phase line driver 125 is configured to decode the column address of the memory cell MC selected for access during a read or write operation. The anti-phase line driver 125 is configured to provide voltage to the selected bit line BLB corresponding to the decoded column address, and to provide different voltages to the other unselected bit lines BLB.

[0051] Control circuitry 126 is connected to one or more of the memory cell MC, weight buffer 114, output circuit 115, word line driver 122, bit line driver 124, anti-phase line driver 125, and input buffer 128 to coordinate the operation of these circuits, drivers, and / or buffers in the overall operation of the memory device 100. For example, control circuitry 126 is configured to generate various control signals for controlling the operation of one or more of the memory cell MC, weight buffer 114, output circuit 115, word line driver 122, bit line driver 124, anti-phase line driver 125, and input buffer 128.

[0052] Input buffer 128 is configured to receive input data from external circuitry outside the storage device 100, such as a processor as described herein. The input data is received via one or more I / O circuits (not shown) of the storage controller 120 and forwarded to the storage array 112 via input buffer 128. Indicative input buffers include, but are not limited to, registers, memory cells, or other circuitry configured for data storage.

[0053] In at least one embodiment, a CIM storage device, such as storage device 100, is superior to other methods of moving data back and forth between memory and processor, because such back-and-forth data movement, which can be a bottleneck for performance and energy efficiency, can be avoided. Examples of CIM applications include, but are not limited to, artificial intelligence, image recognition, neural networks for machine learning, etc. In one or more embodiments, storage device 100 makes it possible to perform weighted data updates and CIM operations simultaneously.

[0054] Each storage cell MC includes a storage section 117a (shown only in storage cell 117 for ease of explanation) and a calculation section 117b (shown only in storage cell 117 for ease of explanation). Each storage cell MC is configured to store a copy of weight data W and is configured to perform CIM calculation on this weight data W and a received copy of data D_IN.

[0055] Each storage section 117a of the storage unit MC is configured to store a weight data W, and each calculation section 117b of the storage unit MC is configured to perform CIM operation on the weight data W and a received data D_IN.

[0056] In some embodiments, including a computation portion 117b within each memory cell MC in the memory array 112 makes it possible to reduce the number of transistors in the computation portion 117b of the CIM macro, thereby reducing the size of the memory macro 110 compared to other methods.

[0057] In some embodiments, including a computation portion 117b within each storage cell MC in the storage array 112 makes it possible to reduce the distance between the computation portion 117b and the storage portion 117a of each storage cell MC in the CIM macro, thereby reducing data loss or corruption between the computation portion 117b and the storage portion 117a of the storage array 112 compared to other methods.

[0058] In some embodiments, each memory cell MC in the memory array 112 includes a computation section 117b such that input data DIN can be transmitted through a smaller number of transistor devices in the computation section 117b of the CIM macro, thereby reducing the latency associated with logic devices of other methods having a larger number of transistors compared to this disclosure.

[0059] As a result, in at least one embodiment, one or more advantages can be achieved, including but not limited to reduced processing time, reduced power consumption, reduced chip area, reduced manufacturing costs, and improved performance.

[0060] Figure 2A This is a schematic diagram of a storage device 200A according to some embodiments.

[0061] Storage device 200A includes storage macros 202, 204, 206, 208 and a storage controller 220. In some embodiments, one or more of storage macros 202, 204, 206, 208 correspond to storage macro 110, and / or storage controller 220 corresponds to storage controller 120. Figure 2A In the illustrated exemplary configuration, storage controller 220 is a general-purpose storage controller for storage macros 202, 204, 206, and 208. In at least one embodiment, at least one of storage macros 202, 204, 206, and 208 has its own storage controller. The number of four storage macros in storage device 200A is exemplary. Other configurations are within the scope of various embodiments.

[0062] Memory macros 202, 204, 206, and 208 are connected sequentially, with the output data of the preceding memory macro serving as the input data for the subsequent memory macro. For example, input data DIN is input into memory macro 202. Memory macro 202 is based on the input data DIN and weight data W stored in it (e.g., ...). Figure 1(As shown) Perform one or more CIM operations and generate output data DOUT2 as the result of the CIM operation. Output data DOUT2 is provided as input data DIN4 of storage macro 204. Storage macro 204 performs one or more CIM operations based on input data DIN4 and weight data W stored in storage macro 204, and generates output data DOUT4 as the result of the CIM operation. Output data DOUT4 is provided as input data DIN6 of storage macro 206. Storage macro 206 performs one or more CIM operations based on input data DIN6 and weight data W stored in storage macro 206, and generates output data DOUT6 as the result of the CIM operation. Output data DOUT6 is provided as input data DIN8 of storage macro 208. Storage macro 208 performs one or more CIM operations based on input data DIN8 and weight data W stored in storage macro 208, and generates output data DOUT as the result of the CIM operation. One or more of the input data DIN, DIN4, DIN6, and DIN8 correspond to the information about... Figure 1 The input data D_IN and / or one or more of the output data DOUT2, DOUT4, DOUT6, and DOUT described correspond to information about... Figure 1 The output data D_OUT is described, therefore a similar detailed description is omitted. In at least one embodiment, the configuration of the described storage macros 202, 204, 206, 208 implements a neural network. In at least one embodiment, one or more advantages described herein may be achieved by storage device 200A.

[0063] Figure 2B This is a schematic diagram of a neural network 200B according to some embodiments.

[0064] Neural network 200B comprises multiple layers A through E, each layer containing multiple nodes (or neurons). Nodes in successive layers of neural network 200B are connected to each other via connection matrices or connection arrays. For example, nodes in layers A and B are connected via connections in matrix 212, nodes in layers B and C are connected via connections in matrix 214, nodes in layers C and D are connected via connections in matrix 216, and nodes in layers D and E are connected via connections in matrix 218. Layer A is the input layer configured to receive input data 211. Input data 211 propagates through the neural network 200B from one layer to the next via the corresponding connection matrices between layers. As the data propagates through neural network 200B, it undergoes one or more computations and is output as output data 219 from layer E, which is the output layer of neural network 200B. Layers B, C, and D between input layer A and output layer E are sometimes referred to as hidden layers or intermediate layers. Figure 2BThe number of layers, the number of connection matrices, and the number of nodes in each layer are examples. Other configurations are within the scope of various embodiments. For example, in at least one embodiment, the neural network 200B does not include hidden layers and has an input layer connected to the output layer via a connection matrix. In one or more embodiments, the neural network 200B has one, two, or more hidden layers.

[0065] In some embodiments, matrices 212, 214, 216, and 218 are correspondingly implemented by storage macros 202, 204, 206, and 208, with input data 211 corresponding to input data DIN and output data 219 corresponding to output data DOUT; therefore, a similar detailed description is omitted. Specifically, in matrix 212, the connection between a node in layer A and another node in layer B has a corresponding weight. For example, the connection between node A1 and node B1 has a weight W(A1, B1) corresponding to the weight values ​​stored in the storage array of storage macro 202. Storage macros 204, 206, and 208 are configured in a similar manner. When machine learning is performed using the neural network 200B, the weight data W in one or more of the storage macros 202, 204, 206, and 208 is updated, for example, by a processor and via storage controller 220. According to some embodiments, one or more advantages described herein can be achieved in the neural network 200B implemented wholly or partially by one or more storage macros and / or storage devices.

[0066] Figure 2C This is a schematic diagram of an integrated circuit (IC) device 200C according to some embodiments.

[0067] IC device 200C is Figure 1 storage device 100 or Figure 2A An embodiment of the storage device 200A is described, therefore a similar detailed description is omitted.

[0068] IC device 200C includes one or more hardware processors 232 and one or more memory devices 234 connected to the processors 232 via one or more buses 236. In some embodiments, the one or more hardware processors 232 may be used as... Figure 1 One or more components in controller 120. Figure 2A The memory controller 220 is used in the memory, therefore a similar detailed description is omitted. In some embodiments, one or more memory devices 234 may be used as... Figure 1 One or more components in storage macro 110 or Figure 2A The storage macros are one or more of 202, 204, 206 and 208, so a similar detailed description is omitted.

[0069] In some embodiments, the IC device 200C includes one or more additional circuits, including but not limited to a cellular transceiver, a Global Positioning System (GPS) receiver, and one or more network interface circuits for Wi-Fi, USB, Bluetooth, etc. Examples of the processor 232 include, but are not limited to, a central processing unit (CPU), a multi-core CPU, a neural processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), other programmable logic devices, a multimedia processor, an image signal processor (ISP), etc. Examples of the storage device 234 include one or more storage devices and / or storage macros described herein. In at least one embodiment, each processor 232 is connected to a corresponding storage device in the storage device 234.

[0070] Because one or more memory devices 234 are CIM memory devices, various calculations are performed within the memory devices, which reduces the computational workload of the corresponding processor, reduces memory access time, and improves performance. In at least one embodiment, the IC device 200C is a system-on-a-chip (SoC). In at least one embodiment, one or more of the advantages described herein can be achieved by the IC device 200C.

[0071] Figure 3 This is a circuit diagram of a storage unit 300 according to some embodiments.

[0072] Storage unit 300 is shown in schematic diagram. Figure 1 An embodiment of one or more storage cells MC in the storage array 112 of the storage macro 110 is described, and therefore a similar detailed description is omitted.

[0073] and Figure 1 , Figures 2A to 2C , Figure 3 , Figure 4 , Figures 5A to 5E and Figure 6 In one or more figures (as shown below), identical or similar components are designated with the same reference numerals, therefore their detailed descriptions are omitted. For ease of explanation, Figure 1 , Figures 2A to 2C , Figure 3 , Figure 4 , Figures 5A to 5E and Figure 6 Some of the marked components were not in Figure 1 , Figures 2A to 2C , Figure 3 , Figure 4 , Figures 5A to 5E and Figure 6 Each of them is marked. In some embodiments, Figure 1 , Figures 2A to 2C , Figure 3 , Figure 4 , Figures 5A to 5E and Figure 6 Including those not in Figure 1 , Figures 2A to 2C , Figure 3 , Figure 4 , Figures 5A to 5E and Figure 6 The additional components shown in the figure.

[0074] Storage unit 300 can be used as Figure 1 The storage macro 110 is one or more storage cells MC in the storage array 112, therefore a similar detailed description is omitted.

[0075] Storage unit 300 can be used as Figure 2A One or more storage cells in storage macros 202, 204, 206, and 208, or Figure 2C One or more storage cells in the intermediate storage device 234, therefore a similar detailed description is omitted.

[0076] The storage unit 300 includes a storage circuit 302 and a multiplication circuit 304.

[0077] Storage circuit 302 can be used as Figure 1 One or more memory cells MC, one or more memory portions 117a, and multiplication circuit 304 can be used as Figure 1 One or more memory cells MC and one or more computing portions 117b, therefore a similar detailed description is omitted.

[0078] Storage circuit 302 is connected to multiplication circuit 304. Storage circuit 302 is configured to store the logic value ("1" or "0") of signal Q at storage node ND. In some embodiments, signal Q corresponds to Figure 1 One or more weighted data, the output signal Dout corresponds to Figure 1 One or more output data DOs, therefore a similar detailed description is omitted.

[0079] In some embodiments, the storage circuit 302, also referred to as a storage cell or storage cell storage portion, is configured to store the logic value ("1" or "0") of signal Q at storage node ND and the logic value ("0" or "1") of signal QB at storage node NDB. In some embodiments, the storage circuit 302 is configured to store data from... Figure 2B One or more weight values ​​or weight data W.

[0080] Storage circuit 302 is a six-transistor (6T) single-port (SP) SRAM memory cell for illustration. In some embodiments, storage circuit 302 employs multiple transistors in addition to six. In some embodiments, storage circuit 302 employs multiple ports instead of one. Other types of memory for storage circuit 302 are within the scope of various embodiments.

[0081] The storage circuit 302 includes two P-type metal-oxide-semiconductor (PMOS) transistors P1 and P2, and four N-type metal-oxide-semiconductor (NMOS) transistors N1, N2, N3, and N4. Transistors P1, P2, N1, and N2 form a cross-latch or a pair of cross-connected inverters. For example, PMOS transistor P1 and NMOS transistor N1 form a first inverter, while PMOS transistor P2 and NMOS transistor N2 form a second inverter.

[0082] The source terminal of each of PMOS transistors P1 and P2 is configured as voltage supply node NODE_1. Each voltage supply node NODE_1 is connected to a first voltage source VDDI. The drain terminal of PMOS transistor P1, the drain terminal of NMOS transistor N1, the gate terminal of PMOS transistor P2, the gate terminal of NMOS transistor N2, and the source terminal of NMOS transistor N3 are all connected together at storage node ND. At least the drain terminals of PMOS transistor P1 and NMOS transistor N1 are configured as storage node ND. Storage node ND has a signal Q.

[0083] The drain terminals of PMOS transistor P2, NMOS transistor N2, PMOS transistor P1, NMOS transistor N1, NMOS transistor N4, and PMOS transistor P3 are all connected together at the memory node NDB. At least the drain terminals of PMOS transistor P2 and NMOS transistor N2 are configured as the memory node NDB. The memory node NDB has a signal QB.

[0084] The source terminals of each of NMOS transistors N1 and N2 are configured as a power supply reference voltage node (unlabeled) and connected to a reference voltage source VSSI. The reference voltage source VSSI has a reference voltage VSS. In some embodiments, the source terminals of each of NMOS transistors N1 and N2 are connected together.

[0085] Word line WL is connected to the gate terminal of each of NMOS transistors N3 and N4. Word line WL is also called the write control line because NMOS transistors N3 and N4 are configured to be controlled by signals on word line WL to transfer data between bit lines BL, BLB and the corresponding nodes ND, NDB.

[0086] The drain terminal of NMOS transistor N3 is connected to bit line BL. The drain terminal of NMOS transistor N4 is connected to bit line BLB. Bit lines BL and BLB are configured as data inputs and outputs of storage circuit 302. In some embodiments, during a write operation, applying a logic value to the first bit line BL and applying the opposite logic value to the other bit line BLB enables the logic values ​​on bit lines BL and BLB to be written to storage circuit 302. Each of bit lines BL and BLB is referred to as a data line because the data carried on bit lines BL and BLB is written to and read from the corresponding nodes ND and NDB.

[0087] The word line WL corresponds to Figure 1 One or more word lines WL1, WL2, ..., WLr, and bit line BL corresponds to Figure 1 One or more bit lines BL1, BL2, ..., BLT, and the anti-phase line BLB corresponds to Figure 1 The text contains one or more anti-phase lines BLB1, BLB2, ..., BLBt, therefore a similar detailed description is omitted.

[0088] Multiplication circuit 304 is connected to storage circuit 302. Multiplication circuit 304 is configured to generate output signal Dout in response to input signal DIN and at least signal QB or signal Q. In some embodiments, input signal DIN corresponds to... Figure 1 The input data is one or more D_IN, so a similar detailed description is omitted.

[0089] Multiplication circuit 304 is configured to perform a CIM operation on signal Q and input signal DIN, thereby generating an output signal Dout. In other words, the output signal Dout corresponds to the CIM operation on signal Q and input signal DIN. In some embodiments, the CIM operation is an AND operation, and the output signal Dout corresponds to the AND operation between signal Q and input signal DIN. In some embodiments, the output signal Dout corresponds to the product of signal Q and input signal DIN. Other types of CIM operations are within the scope of this disclosure.

[0090] The multiplication circuit 304 includes a PMOS transistor P3, an initialization circuit 306, and an output node ND1. The voltage of the output node Nd1 corresponds to the output signal Dout.

[0091] In some embodiments, the multiplication circuit 304 has an initialization mode and a sensing mode. Each initialization mode is associated with a corresponding sensing mode, and vice versa.

[0092] During initialization mode, initialization circuit 306 is configured to initialize multiplication circuit 304 in response to initialization signal SINI and signal S1.

[0093] During sensing mode, multiplication circuit 304 is configured to set output signal Dout in response to input signal DIN and at least signal QB or signal Q. In some embodiments, sensing mode is associated with a read operation of storage circuit 302, and multiplication circuit 304 reads data (e.g., signal Q or QB) stored in storage circuit 302 to generate output signal Dout. In some embodiments, during sensing mode, initialization circuit 306 is disabled or turned off by initialization signal SINI.

[0094] In some embodiments, during sensing mode, multiplication circuit 304 is configured to set the voltage of output node ND1 of multiplication circuit 304 in response to input signal DIN and at least signal QB or signal Q, thereby setting the voltage of output signal Dout.

[0095] PMOS transistor P3 is connected to output node ND1, initialization circuit 306, and storage circuit 302. PMOS transistor P3 is configured to receive input signal DIN and at least signal QB or signal Q. In some embodiments, during sensing in a mode, PMOS transistor P3 is configured to set the voltage of output node ND1 of multiplication circuit 304 in response to input signal DIN and at least signal QB or signal Q.

[0096] The drain terminal of PMOS transistor P3 is connected to node Nd2 and is configured to receive the input signal DIN. The source terminal of PMOS transistor P3 is connected to initialization circuit 306 and output node Nd1.

[0097] The gate terminal of PMOS transistor P3 is connected to each of the following: storage node NDB, the drain terminal of PMOS transistor P2, the drain terminal of NMOS transistor N2, the gate terminal of PMOS transistor P1, the gate terminal of NMOS transistor N1, and the source terminal of NMOS transistor N4. The gate terminal of PMOS transistor P3 is the input node of multiplication circuit 304, used to receive signal QB. PMOS transistor P3 is turned on or off in response to signal QB.

[0098] In some embodiments, during the sensing mode, PMOS transistor P3 turns on in response to signal QB being a logic low value ("0"), thereby electrically connecting nodes Nd2 and Nd1 and setting the voltage of node Nd1 to be equal to the input signal Din.

[0099] In some embodiments, during the sensing mode, PMOS transistor P3 is turned off in response to signal QB being a logic high value ("1"), thereby electrically disconnecting nodes Nd2 and Nd1, and the voltage of node Nd1 is set based on the initialization value set by initialization circuit 306 during the initialization phase. In other words, during the sensing mode, when PMOS transistor P3 is turned off, the voltage of node Nd1 is maintained at the initialization value set by initialization circuit 306 during the initialization phase.

[0100] Initialization circuit 306 is connected to PMOS transistor P3 via output node ND1. During initialization mode, initialization circuit 306 is enabled or turned on and configured to set output signal Dout to an initial value in response to initialization signal SINI and signal S1. In some embodiments, initialization of multiplication circuit 304 corresponds to resetting multiplication circuit 304 to an initial value. In some embodiments, initialization signal SINI corresponds to an enable signal that enables or disables initialization circuit 306.

[0101] In some embodiments, the initialization value is a logic low value ("0"). In some embodiments, the initialization value is a logic high value ("1"). In some embodiments, signal S1 is equal to the reference voltage VSS. In some embodiments, signal S1 is equal to the power supply voltage VDD.

[0102] In some embodiments, the storage unit 300 implements at least the above-mentioned Figure 1 and Figures 2A to 2C The benefits discussed are similar to those discussed.

[0103] Other transistor terminals used for each NMOS transistor N1, N2, N3, or N4, or each PMOS transistor P1, P2, or P3, are within the scope of this disclosure. For example, references to the drain and source of the same transistor in this disclosure may be changed to the source and drain of the same transistor.

[0104] Other configurations, number of transistors, or transistor types in memory cell 300 are within the scope of this disclosure.

[0105] Figure 4 This is a circuit diagram of a storage unit 400 according to some embodiments.

[0106] Storage unit 400 is shown in the form of a schematic diagram. Figure 1 An embodiment of one or more storage cells MC in the storage array 112 of the storage macro 110 is described, and therefore a similar detailed description is omitted.

[0107] Storage unit 400 is Figure 3 The embodiment of storage unit 300 is described in detail below, therefore similar detailed descriptions are omitted.

[0108] Storage unit 400 includes storage circuit 302 and multiplication circuit 404. Multiplication circuit 404 is... Figure 3 The embodiment of the multiplication circuit 304 is given, therefore a similar detailed description is omitted.

[0109] The multiplication circuit 404 includes a PMOS transistor P3, an initialization circuit 406, and an output node ND1. The initialization circuit 406 is... Figure 3 The embodiment of the initialization circuit 306 is described in detail below, therefore a similar detailed description is omitted.

[0110] The initialization circuit 406 includes an NMOS transistor N5.

[0111] The source terminal of NMOS transistor N5 is connected to node Nd3 and the reference voltage source VSSI. The source terminal of NMOS transistor N5 is configured to receive the reference voltage VSS (e.g., signal S1).

[0112] The drain terminal of NMOS transistor N5 is connected to the drain terminal of PMOS transistor P3 and the output node Nd1.

[0113] The gate terminal of NMOS transistor N5 is the input node of initialization circuit 406 and is configured to receive initialization signal SINI. NMOS transistor N5 turns on or off in response to initialization signal SINI. The gate terminal of NMOS transistor N5 is connected to the source of initialization signal SINI.

[0114] During the initialization mode, NMOS transistor N5 is enabled or turned on and configured to set the output signal Dout to an initial value in response to the initialization signal SINI. In some embodiments, initializing the multiplication circuit 404 corresponds to resetting the multiplication circuit 404 to its initial value.

[0115] In some embodiments, during the initialization mode, NMOS transistor N5 is turned on in response to the initialization signal SINI being a logic high value ("1"), thereby electrically connecting node Nd3 and node Nd1 and setting the voltage of voltage node Nd1 to be equal to signal S1 (e.g., reference voltage VSS).

[0116] In some embodiments, during the initialization mode, the input signal DIN is set to a logic low value ("0") to prevent node Nd2 from having a different logic value than signal S1 (e.g., reference voltage VSS), thereby preventing logic value conflicts between nodes Nd3 and Nd2.

[0117] In some embodiments, before or after the initialization mode (e.g., sensing mode), NMOS transistor N5 is turned off in response to the initialization signal SINI being a logic low value ("0"), thereby electrically disconnecting nodes Nd3 and Nd1 from each other. In some embodiments, before or after the initialization mode, the voltage of node Nd1 may be set by PMOS transistor P3 in response to the value of the input signal DIN. In some embodiments, before or after the initialization mode, if PMOS transistor P3 is turned on, the voltage of node Nd1 may be set by PMOS transistor P3 in response to the value of the input signal DIN. In some embodiments, before or after the initialization mode, if PMOS transistor P3 is turned off, the voltage of node Nd1 is equal to the initialization value set by NMOS transistor N5 during the initialization phase.

[0118] In some embodiments, the storage unit 400 implements at least the above-mentioned Figure 1 , Figures 2A to 2C , Figure 3 and Figure 4 The benefits discussed are similar to those discussed.

[0119] Other transistor terminals of the NMOS transistor N5 in this application are within the scope of this disclosure. For example, references to the drain and source of the same transistor in this disclosure can be changed to the source and drain of the same transistor.

[0120] Other configurations, number of transistors, or transistor types in memory cell 400 are within the scope of this disclosure.

[0121] Figure 5A According to some embodiments Figure 5C The truth table 500A of the storage cell array 501 shown is provided. The values ​​and formats of table 500A are provided as examples, and other values ​​and / or formats of truth table 500A are within the scope of this disclosure.

[0122] In some embodiments, truth table 500A corresponds to the state in sensing mode. Figure 5C The storage cell array 501 of Figure 500C. In some embodiments, the truth table 500A is at least in sensing mode. Figure 3 Storage unit 300, Figure 4 Storage unit 400 or Figure 6 The truth table of storage unit 600.

[0123] In some embodiments, truth table 500A corresponds to the truth table of an AND gate, wherein the input of the AND gate is configured to receive input signals DIN and Q, and the output of the AND gate is configured to output signal Dout. In other words, the output signal Dout corresponds to the AND operation between the input signals DIN and Q.

[0124] The values ​​for truth table 500A are below. Figures 5C to 5E The description of Figure 500C is provided in the text.

[0125] like Figure 5A As shown in the first row and second column of the truth table 500A, if the input signal DIN is logic 1 and the signal Q is logic 1, then the output signal Dout is logic 1 (for example, also shown as "condition A").

[0126] like Figure 5A As shown in the second row and second column of the truth table 500A, if the input signal DIN is logic 0 and the signal Q is logic 1, then the output signal Dout is logic 0 (for example, also shown as "condition B").

[0127] like Figure 5A As shown in the first row and third column of the truth table 500A, if the input signal DIN is logic 1 and the signal Q is logic 0, then the output signal Dout is logic 0 (for example, also shown as "condition C").

[0128] like Figure 5A As shown in the second row and third column of the truth table 500A, if the input signal DIN is logic 0 and the signal Q is logic 0, then the output signal Dout is logic 0 (for example, also shown as "Status D").

[0129] Other values ​​and arrangements in truth table 500A are within the scope of this disclosure.

[0130] Figures 5B to 5C The corresponding figures 500B to 500C are based on some embodiments of the memory cell array 501.

[0131] Figure 5B Figure 500B is an example of an initialization mode of a memory cell array 501 according to some embodiments. Figure 5C Figure 500C is an example of a sensing mode of a memory cell array 501 according to some embodiments.

[0132] Storage cell array 501 is Figure 1 An embodiment of two rows and two columns of storage cells in the storage array 112 of the storage macro 110 is described, and therefore a similar detailed description is omitted.

[0133] The storage cell array 501 includes storage cells 502a, 502b, 502c and 502d.

[0134] Each memory cell 502a, 502b, 502c, and 502d corresponds to Figure 4The memory cell 400 is described in detail below, therefore a similar detailed description is omitted. For ease of explanation, the transmission gate transistors (e.g., NMOS transistors N3 and N4) of the memory cell 400 are not shown in the diagram. Figures 5B to 5C As shown in the image.

[0135] Storage cell 502a is in the first row and first column of storage cell array 501, storage cell 502b is in the second row and first column of storage cell array 501, storage cell 502c is in the first row and second column of storage cell array 501, and storage cell 502d is in the second row and second column of storage cell array 501.

[0136] Each memory cell 502a, 502b, 502c, and 502d is associated with... Figure 5A The truth table 500A in the document corresponds to states A, B, C, and D, so a similar detailed description is omitted.

[0137] Storage units 502a and 502c are configured to receive the input signal DIN, and storage units 502b and 502d are configured to receive the input signal DIN. Storage units 502a, 502b, 502c, and 502d are configured to receive the signal SINI. Storage units 502a, 502b, 502c, and 502d are configured to output corresponding output signals Dout1, Dout2, Dout3, and Dout4. Storage units 502a, 502b, 502c, and 502d are configured to store corresponding signals SQ1, Q2, Q3, and Q4.

[0138] In some embodiments, FIG500B is an example of the initialization mode of the memory cell array 501, therefore Figure 5B The initialization signal SINI is equal to logic 1. In some embodiments, during the initialization mode, input signals DIN and DIN are set to uninitialized values ​​(e.g., logic low values ​​("0")) to prevent node Nd2 from having a different logic value than signal S1 (e.g., reference voltage VSS), thereby preventing conflicts between the logic values ​​of nodes Nd3 and Nd2. In some embodiments, input signals DIN and DIN are set to uninitialized values ​​by the storage controller 120.

[0139] In some embodiments, FIG500C is an example of a sensing mode of the memory cell array 501, therefore Figure 5C The initialization signal SINI is equal to logic 1.

[0140] Further operation of the memory cell array 501 in Figures 500B and 500C is as follows: Figure 5D Timing diagram 500D and Figure 5E The timing diagram is described in 500E.

[0141] Figures 5D to 5E According to some embodiments Figures 5B to 5C The waveforms 500D to 500E corresponding to the memory cell array 501.

[0142] In some embodiments, waveform 500D is an example of the initialization mode and sensing mode of storage units 502a and 502c corresponding to conditions A and C.

[0143] In some embodiments, waveform 500E is an example of the initialization mode and sensing mode of storage units 502b and 502d corresponding to states B and D.

[0144] The initialization mode begins at times T1 and T2, and the sensing mode begins at times T2 and T3. In some embodiments, the initialization mode and the sensing mode alternate with each other.

[0145] At time T1, the initialization signal SINI is equal to logic 1, and each of the input signals DIN and DIN 0 is equal to logic 0. In response to the initialization signal SINI being equal to logic 1, each NMOS transistor N5 in the corresponding memory cells 502a, 502b, 502c, and 502d is turned on, thereby setting the voltages of the output signals Dout1, Dout2, Dout3, and Dout4 to be equal to logic 0 (e.g., the reference voltage VSS).

[0146] At time T2, the initialization signal SINI changes to logic 0, and the input signal DIN changes to logic 1.

[0147] At time T2, the input signal DIN is equal to logic 0, signal Q1 is equal to logic 1, signal Q2 is equal to logic 0, signal Q3 is equal to logic 1, and signal Q4 is equal to logic 0.

[0148] In response to the initialization signal SINI being equal to logic 0, each NMOS transistor N5 in the corresponding memory cells 502a, 502b, 502c, and 502d is turned off, thereby disconnecting node Nd3 in the corresponding memory cells 502a, 502b, 502c, and 502d from node Nd1 in the corresponding memory cells 502a, 502b, 502c, and 502d.

[0149] As shown in condition A, in response to signal Q1 equaling logic 1 and signal QB1 equaling logic 0, the PMOS transistor P3 in memory cell 502a is turned on, thereby connecting node Nd2 in memory cell 502a to the corresponding node Nd1 in memory cell 502a, and thus setting the output signal Dout1 to equal the input signal DIN. In response to the input signal DIN equaling logic 1, the output signal Dout1 is set to equal logic 1.

[0150] As shown in condition C, in response to signal Q2 equaling logic 1 and signal QB2 equaling logic 0, the PMOS transistor P3 in memory cell 502b is turned on, thereby connecting node Nd2 in memory cell 502b to the corresponding node Nd1 in memory cell 502b, thus setting the output signal Dout2 to equal the input signal DIN. In response to the input signal DIN equaling logic 0, the output signal Dout2 is set to equal logic 0.

[0151] As shown in condition B, in response to signal Q3 being equal to logic 0 and signal QB3 being equal to logic 1, the PMOS transistor P3 in memory cell 502c is turned off, thereby disconnecting node Nd2 in memory cell 502c from node Nd1 in the corresponding memory cell 502c, and thus output signal Dout3 being equal to the initial value (e.g., reference voltage VSS or logic 0).

[0152] As shown in condition D, in response to signal Q4 being equal to logic 0 and signal QB4 being equal to logic 1, the PMOS transistor P3 in memory cell 502d is turned off, thereby disconnecting node Nd2 in memory cell 502d from the corresponding node Nd1 in memory cell 502d, and thus output signal Dout4 being equal to the initial value (e.g., reference voltage VSS or logic 0).

[0153] At time T3, the initialization signal SINI changes to logic 1, and each of the input signals DIN and DIN 0 becomes logic 0. In response to the initialization signal SINI becoming logic 1, each NMOS transistor N5 in the corresponding memory cells 502a, 502b, 502c, and 502d is turned on, thereby setting the voltages of the output signals Dout1, Dout2, Dout3, and Dout4 to logic 0 (e.g., the reference voltage VSS).

[0154] Although in some embodiments. Figures 5B to 5C The storage cell array 501 is described as storage cells in different rows and columns, with each of states A, B, C, and D corresponding to storage cells in the same column and row with different input signals (e.g., input signals DIN and Q).

[0155] In some embodiments, the storage cell array 501 implements at least the above-mentioned Figure 1 , Figures 2A to 2C , Figure 3 and Figure 4 The benefits discussed are similar to those discussed.

[0156] Other configurations of the storage cell array 501 are within the scope of this disclosure.

[0157] Other configurations of waveforms 500D and 500E are within the scope of this disclosure.

[0158] Figure 6 This is a circuit diagram of a storage unit 600 according to some embodiments.

[0159] Storage unit 600 is shown in the form of a schematic diagram. Figure 1 An embodiment of one or more storage cells MC in the storage array 112 of the storage macro 110 is described, and therefore a similar detailed description is omitted.

[0160] Storage unit 600 is Figure 4 A variant of storage unit 400, therefore a similar detailed description is omitted. Figure 4 Compared to the 400 storage units, Figure 6 The 604 multiplication circuit replaced Figure 4 The multiplication circuit 404 is used, so a similar detailed description is omitted.

[0161] The storage unit 600 includes a storage circuit 302 and a multiplication circuit 604.

[0162] and Figure 4 Compared to the 404 multiplication circuit, Figure 6 The multiplication circuit 604 uses NMOS transistor N6 instead of Figure 4 The PMOS transistor P3 of the multiplication circuit 404 is omitted from the detailed description.

[0163] The multiplication circuit 604 includes an NMOS transistor N6, an initialization circuit 406, and an output node ND1.

[0164] The drain terminal of PMOS transistor P1, the drain terminal of NMOS transistor N1, the gate terminal of PMOS transistor P2, the gate terminal of NMOS transistor N2, the source terminal of NMOS transistor N3, and the gate terminal of NMOS transistor N6 are all connected together at the storage node ND.

[0165] The drain terminal of PMOS transistor P2, the drain terminal of NMOS transistor N2, the gate terminal of PMOS transistor P1, the gate terminal of NMOS transistor N1, and the source terminal of NMOS transistor N4 are connected together at the memory node NDB.

[0166] NMOS transistor N6 is connected to output node ND1, initialization circuit 406, and storage circuit 302. NMOS transistor N6 is configured to receive input signal DIN and signal Q. In some embodiments, during sensing mode, NMOS transistor N6 is configured to set the voltage of output node ND1 of multiplication circuit 604 in response to input signal DIN and at least signal QB or signal Q.

[0167] The drain terminal of NMOS transistor N6 is connected to node Nd2 and is configured to receive the input signal DIN. The source terminal of NMOS transistor N6 is connected to the drain terminal of NMOS transistor N5 in initialization circuit 406 and the output node Nd1.

[0168] The gate terminal of NMOS transistor N6 is connected to each of the drain terminal of PMOS transistor P1, the drain terminal of NMOS transistor N1, the gate terminal of PMOS transistor P2, the gate terminal of NMOS transistor N2, and the source terminal of NMOS transistor N3. The gate terminal of NMOS transistor N6 is the input node of multiplier circuit 604 and is configured to receive signal Q. NMOS transistor N6 is turned on or off in response to signal Q.

[0169] In some embodiments, during the sensing mode, NMOS transistor N6 is turned on in response to signal Q being a logic high value ("1"), thereby electrically connecting nodes Nd2 and Nd1 and setting the voltage of node Nd1 to be equal to the input signal Din.

[0170] In some embodiments, during the sensing mode, NMOS transistor N6 is turned off in response to signal Q being a logic low value ("0"), thereby electrically disconnecting node Nd2 from node Nd1, and the voltage of node Nd1 is set based on the initialization value set by initialization circuit 406 during the initialization phase. In other words, during the sensing mode, when NMOS transistor N6 is off, the voltage of node Nd1 is maintained at the initialization value set by initialization circuit 406 during the initialization phase.

[0171] In some embodiments, the storage unit 600 implements the above-mentioned at least Figure 1 , Figures 2A to 2C , Figure 3 , Figure 4 and Figures 5A to 5E The benefits discussed are similar to those discussed.

[0172] Other transistor terminals of the NMOS transistor N6 in this application are within the scope of this disclosure. For example, references to the drain and source of the same transistor in this disclosure can be changed to the source and drain of the same transistor.

[0173] Other configurations, number of transistors, or transistor types in memory cell 600 are within the scope of this disclosure.

[0174] Figure 7A This is a flowchart of a method 700A for operating circuitry according to some embodiments. In some embodiments, Figure 7A This is a flowchart of the method for operating the storage circuit 700A, the storage circuit being such as... Figure 2AStorage device 200A, Figure 2B Neural network 200B, Figure 2C IC device 200C, Figure 3 Storage unit 300, Figure 4 Storage cell 400, storage cell array 501 of Figures 500B to 500C Figures 5B to 5C , Figure 6 The storage unit is 600.

[0175] It should be understood that additional operations can be performed. Figures 7A to 7B The methods 700A to 700B described herein are performed before, during, and / or after the methods described herein, and only a few other processes may be briefly described herein. In some embodiments, the order of other operations of methods 700A to 700B is within the scope of this disclosure. Methods 700A to 700B include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, ordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of methods 700A to 700B are not performed.

[0176] In operation 702 of method 700A, a write operation to the memory cell is performed. In some embodiments, operation 702 is performed by the memory controller 120.

[0177] In some embodiments, the storage unit of method 700A includes one or more storage units of storage array 112, storing at least macros 202, 204, 206 or 208, storage device 234, storage unit 117 or storage unit 300, 400 or 600.

[0178] In some embodiments, the storage unit of methods 700A to 700B includes a storage circuit and a multiplication circuit. In some embodiments, the storage circuit of methods 700A to 700B includes at least a storage portion 117a or a storage circuit 302. In some embodiments, the multiplication circuit of methods 700A to 700B includes at least a calculation portion 117b, a multiplication circuit 304, a multiplication circuit 404, or a multiplication circuit 604.

[0179] In some embodiments, operation 702 includes operation 704.

[0180] In operation 704 of method 700A, the first value of the first signal is stored in the first storage node of the storage circuit.

[0181] In some embodiments, the first signal of methods 700A to 700B includes at least a signal Q or QB or weight data W. In some embodiments, the first signal corresponds to a first weight. In some embodiments, the first weight of methods 700A to 700B includes at least one or more weight data W. In some embodiments, the first value of the first signal of methods 700A to 700B includes at least logic 0 or logic 1.

[0182] In operation 706 of method 700A, a CIM operation is performed between the first signal and the second signal to generate an output signal. In some embodiments, operation 706 includes performing a read operation of the memory cell.

[0183] In some embodiments, the output signals of methods 700A to 700B include at least the output signal Dout or the output signal DO. In some embodiments, the CIM operation of methods 700A to 700B includes at least the AND operation of truth table 500A. In some embodiments, the second signal of methods 700A to 700B includes at least the input signal DIN or the input data D_IN.

[0184] In some embodiments, operation 706 is performed by a multiplication circuit. In some embodiments, the multiplication circuit includes a first transistor and an initialization circuit.

[0185] In some embodiments, the first transistor in methods 700A to 700B includes at least a PMOS transistor P3. In some embodiments, the first transistor in methods 700A to 700B includes at least an NMOS transistor N6.

[0186] In some embodiments, the initialization circuits of methods 700A to 700B include at least initialization circuit 306 or 406. In some embodiments, the initialization circuits of methods 700A to 700B include at least NMOS transistor N5.

[0187] In some embodiments, operation 706 includes at least operation 708 or 710.

[0188] In operation 708 of method 700A, the output signal of the multiplication circuit is initialized in response to at least a third signal or a fourth signal. In some embodiments, operation 706 is performed by an initialization circuit.

[0189] In some embodiments, the third signal of methods 700A to 700B includes at least an initialization signal SINI. In some embodiments, the fourth signal of methods 700A to 700B includes at least a reference voltage VSS.

[0190] In operation 710 of method 700A, during the sensing phase of the storage circuit, the output signal is set at least in response to the second signal. In some embodiments, operation 706 is performed by the first transistor.

[0191] In some embodiments, method 700A is repeated after operation 710.

[0192] Figure 7B This is a flowchart of a method 700B for operating circuitry according to some embodiments. In some embodiments, Figure 7B It is an operation of the storage circuit (e.g.) Figure 1 Storage device 100, Figure 2A Storage device 200A, Figure 2B Neural network 200B, Figure 2C IC device 200C, Figure 3 Storage unit 300, Figure 4 400 storage units Figures 5B to 5C Figures 500B to 500C show the memory cell array 501. Figure 6 The flowchart of method 700B for storage unit 600).

[0193] In some embodiments, method 700B is an embodiment of operation 706, and therefore a similar detailed description is omitted.

[0194] Method 700B includes at least operation 708 or 710 (as described above).

[0195] In operation 708 of method 700B, the output signal of the multiplication circuit is initialized in response to at least the third or fourth signal. Operation 708 of method 700B includes at least operations 720, 722, or 724.

[0196] In operation 720 of method 700A, the second signal is set to an initial value during the initialization phase of the storage circuit. In some embodiments, operation 720 is performed by an initialization circuit or a second transistor.

[0197] In some embodiments, the initialization circuit of methods 700A to 700B includes a second transistor. In some embodiments, the second transistor of methods 700A to 700B includes at least an NMOS transistor N5. In some embodiments, the initialization value of methods 700A to 700B is logic 0. In some embodiments, the initialization value of methods 700A to 700B is logic 1.

[0198] In operation 722 of method 700A, the second transistor is turned on in response to the third signal, thereby electrically connecting the first node of the multiplication circuit to the output node of the multiplication circuit. In some embodiments, operation 722 is performed in response to the third signal being logic 1.

[0199] In some embodiments, the first node of methods 700A to 700B includes at least node Nd3.

[0200] In some embodiments, the output nodes of methods 700A to 700B include at least node Nd1.

[0201] In operation 724 of method 700A, the value of the output signal is set to be equal to the value of the fourth signal. In some embodiments, the value of the output signal is set to be equal to the value of the reference voltage VSS or logic 0.

[0202] In operation 710 of method 700B, during the sensing phase of the storage circuit, the output signal is set at least in response to the second signal. Operation 710 of method 700B includes at least operations 726, 728, or 730.

[0203] In operation 726 of method 700B, the second transistor is turned off in response to a third signal, thereby electrically disconnecting the first node and the output node from each other. In some embodiments, operation 726 is performed in response to the third signal being logic 0.

[0204] In operation 728 of method 700B, the second signal is set to an uninitialized value during the sensing phase of the storage circuit. In some embodiments, the uninitialized value includes logic 0 or logic 1. In some embodiments, the uninitialized value is the data value of the input signal DIN during the sensing phase of the storage circuit.

[0205] In some embodiments, the second signal is set to an uninitialized value by the storage controller 120.

[0206] In operation 730 of method 700B, the value of the output signal is set in response to the on or off state of the first transistor.

[0207] In some embodiments, operation 730 of method 700B includes turning on at least the first transistor in response to the first signal or the inverted first signal QB, thereby electrically connecting the second node of the multiplication circuit to the output node circuit of the multiplier, and setting the value of the output signal to be equal to the value of the second signal.

[0208] In some embodiments, the second node of methods 700A to 700B includes at least node Nd2.

[0209] In some embodiments, operation 730 of method 700B includes at least turning off the first transistor in response to the first signal or the inverted first signal, thereby electrically disconnecting the second node and the output node from each other, and maintaining the value of the output signal equal to the value of the fourth signal.

[0210] By operating methods 700A to 700B, the storage circuit operates to achieve the above regarding at least Figure 1 , Figures 2A to 2C , Figure 3 , Figure 4 , Figures 5A to 5E and Figure 6 The benefits discussed.

[0211] Although methods 700A to 700B are described above with reference to a single storage cell of storage array 112, it should be understood that in some embodiments, methods 700A to 700B are applicable to every row and every column of storage device 100.

[0212] also, Figures 3 to 4 , Figures 5B to 5C and Figure 6 The various PMOS or NMOS transistors shown, having specific dopant types (e.g., N-type or P-type), are for illustrative purposes. The embodiments disclosed herein are not limited to specific transistor types. Figures 3 to 4 , Figures 5B to 5C and Figure 6 One or more of the PMOS or NMOS transistors shown can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are for illustrative purposes only. The embodiments of this disclosure are not limited to specific logic values ​​when a signal is activated and / or deactivated. Different logic values ​​are chosen within the range of various embodiments. Figures 3 to 4 , Figures 5B to 5C and Figure 6 The number of transistors varies across various embodiments.

[0213] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to influence various modifications, equivalent substitutions, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in the appended claims and their equivalent substitutions.

[0214] One aspect of this specification relates to a storage unit. The storage unit includes a storage circuit and a multiplication circuit. The multiplication circuit includes an output node configured to output an output signal, a first transistor, and an initialization circuit. The first transistor is connected to the output node and the storage circuit and is configured to receive at least a second signal. The initialization circuit is connected to the first transistor through the output node and is configured to initialize the multiplication circuit in response to at least a third or fourth signal. The storage circuit is configured to store a first value of a first signal of the first storage node. The multiplication circuit is connected to the storage circuit. The multiplication circuit is configured to generate an output signal in response to the first and second signals. The output signal corresponds to the product of the first and second signals.

[0215] One aspect of the present invention provides a storage unit comprising: a storage circuit configured to store a first value of a first signal of a first storage node; a multiplication circuit connected to the storage circuit, the multiplication circuit being configured to generate an output signal in response to the first signal and a second signal, the output signal corresponding to the product of the first signal and the second signal, the multiplication circuit comprising: an output node configured to output the output signal; a first transistor connected to the output node and the storage circuit and configured to receive at least the second signal; and an initialization circuit connected to the first transistor through the output node and configured to initialize the multiplication circuit in response to at least a third signal or a fourth signal.

[0216] In some embodiments, the initialization circuit configured to initialize the multiplication circuit includes: the initialization circuit is further configured to set the output signal in response to at least the third signal or the fourth signal during the initialization phase of the storage circuit.

[0217] In some embodiments, the initialization circuit includes: a second transistor of a first type, the second transistor including: a first source / drain terminal connected to the output node and the first transistor; a second source / drain terminal connected to a reference voltage source having a reference voltage corresponding to the third signal; and a first gate terminal configured to receive the fourth signal.

[0218] In some embodiments, the first transistor is further configured to set the output signal in response to at least the second signal during the sensing phase of the storage circuit.

[0219] In some embodiments, the first transistor is a P-type transistor, and the first transistor includes: a first source / drain terminal connected to the output node and the initialization circuit; a second source / drain terminal configured to receive the second signal; and a first gate terminal connected to a second memory node of the memory circuit and configured to receive a fifth signal from the memory circuit, the fifth signal corresponding to the voltage of the second memory node.

[0220] In some embodiments, the fifth signal is out of phase with the first signal.

[0221] In some embodiments, the first transistor is an N-type transistor, and the first transistor includes: a first source / drain terminal connected to the output node and the initialization circuit; a second source / drain terminal configured to receive the second signal; and a first gate terminal connected to the first memory node of the memory circuit and configured to receive the first signal from the memory circuit, the first signal corresponding to the voltage of the first memory node.

[0222] In some embodiments, the memory cell corresponds to an 8-transistor (8T) static random access (SRAM) cell.

[0223] In some embodiments, the storage circuit includes: a first bit line; a second bit line; a first word line; a first cross-connected inverter; a second cross-connected inverter connected to the first cross-connected inverter; a first transmission gate transistor connected to the first bit line, the first word line, and the first cross-connected inverter; and a second transmission gate transistor connected to the second bit line, the first word line, and the second cross-connected inverter.

[0224] Another aspect of this specification relates to a storage unit. The storage unit includes a first set of storage circuits configured to store weight data, and a first set of multiplication circuits configured to perform a CIM operation between the weight data and input data. In some embodiments, each multiplication circuit of the first set of multiplication circuits corresponds to each storage circuit of the first set of storage circuits. In some embodiments, the first set of storage circuits includes a first storage circuit configured to store a first weight value of a first signal of a first storage node. In some embodiments, the first set of multiplication circuits includes a first multiplication circuit connected to the first storage circuit. In some embodiments, the first multiplication circuit is configured to generate an output signal in response to a first signal and a second signal. In some embodiments, the output signal corresponds to a CIM product operation between the first signal and the second signal. In some embodiments, the first multiplication circuit includes a first output node configured to output an output signal, a first transistor connected to the first output node and the first storage circuit and configured to receive at least a second signal, and an initialization circuit connected to the first transistor through the first output node and configured to initialize the first multiplication circuit in response to at least a third signal or a fourth signal.

[0225] Another aspect of this specification provides a memory cell array comprising: a first set of memory circuits configured to store weight data, the first set of memory circuits including: a first memory circuit configured to store a first weight value of a first signal of a first memory node; a first set of multiplication circuits configured to perform in-memory computation (CIM) operations between the weight data and input data, the first set of multiplication circuits including: a first multiplication circuit connected to the first memory circuit, the first multiplication circuit being configured to generate an output signal in response to the first signal and a second signal, the output signal corresponding to a product operation of the in-memory computation between the first signal and the second signal, the first multiplication circuit including: a first output node configured to output the output signal; a first transistor connected to the first output node and the first memory circuit and configured to receive at least the second signal; and an initialization circuit connected to the first transistor through the first output node and configured to initialize the first multiplication circuit in response to at least a third signal or a fourth signal, wherein each multiplication circuit in the first set of multiplication circuits corresponds to each memory circuit in the first set of memory circuits.

[0226] In some embodiments, the in-memory product operation between the first signal and the second signal corresponds to the AND operation between the first signal and the second signal.

[0227] In some embodiments, the first transistor is further configured to set the output signal in response to at least the second signal during the sensing phase of the first storage circuit.

[0228] In some embodiments, the first transistor is an N-type transistor, the first transistor comprising: a first source / drain terminal connected to the first output node and the initialization circuit; a second source / drain terminal configured to receive the second signal; and a first gate terminal connected to the first memory node of the first memory circuit and configured to receive the first signal from the first memory circuit, the first signal corresponding to the voltage of the first memory node.

[0229] In some embodiments, the first transistor is a P-type transistor, and the first transistor includes: a first source / drain terminal connected to the first output node and the initialization circuit; a second source / drain terminal configured to receive the second signal; and a first gate terminal connected to a second storage node of the first storage circuit and configured to receive a fifth signal from the first storage circuit, the fifth signal corresponding to the voltage of the second storage node, wherein the fifth signal is inverted from the first signal.

[0230] In some embodiments, the initialization circuit configured to initialize the first multiplication circuit includes: the initialization circuit is further configured to set the output signal in response to at least the third signal or the fourth signal during the initialization phase of the first storage circuit.

[0231] In some embodiments, the initialization circuit includes: a second transistor of a first type, the second transistor including: a first source / drain terminal connected to the first output node and the first transistor; a second source / drain terminal connected to a reference voltage source having a reference voltage corresponding to the third signal; and a first gate terminal configured to receive the fourth signal.

[0232] In some embodiments, the memory cell array corresponds to an array of 8-transistor (8T) static random access (SRAM) cells. Another aspect of this specification relates to a method of operating a memory cell. The method includes performing a write operation on the memory cell and performing an in-memory computation (CIM) operation between a first signal and a second signal via a multiplication circuit. In some embodiments, the memory cell includes a memory circuit and a multiplication circuit. In some embodiments, performing the write operation on the memory cell includes storing a first value of a first signal in a first memory node of the memory circuit, wherein the first signal corresponds to a first weight. In some embodiments, the multiplication circuit includes a first transistor and an initialization circuit. In some embodiments, performing the CIM operation between the first signal and the second signal includes initializing the output signal of the multiplication circuit via the initialization circuit in response to at least a third or fourth signal, and, during a sensing phase of the memory circuit, setting the output signal via the first transistor in response to at least a second signal.

[0233] Another aspect of the present invention provides a method for operating a memory cell, the method comprising: performing a write operation on the memory cell, the memory cell including a memory circuit and a multiplication circuit, the write operation comprising: storing a first value of a first signal in a first memory node of the memory circuit, the first signal corresponding to a first weight; performing an in-memory computation (CIM) operation between the first signal and a second signal via the multiplication circuit, the multiplication circuit including a first transistor and an initialization circuit, wherein performing the in-memory computation operation between the first signal and the second signal comprises: initializing an output signal of the multiplication circuit via the initialization circuit in response to at least a third signal or a fourth signal; and setting the output signal by the first transistor during a sensing phase of the memory circuit in response to at least a second signal.

[0234] In some embodiments, initializing the output signal of the multiplication circuit includes: setting the second signal to an initial value during the initialization phase of the storage circuit, the initialization circuit including a second transistor; turning on the second transistor in response to the third signal, thereby electrically connecting a first node of the multiplication circuit to an output node of the multiplication circuit; and setting the value of the output signal to be equal to the value of the fourth signal.

[0235] In some embodiments, setting the output signal during the sensing phase of the storage circuit includes: turning off the second transistor in response to the third signal, thereby electrically disconnecting the first node and the output node from each other; setting the second signal to an uninitialized value during the sensing phase of the storage circuit; and setting the value of the output signal in response to turning the first transistor on or off.

[0236] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A storage unit, comprising: The storage circuit is configured to store the first value of the first signal of the first storage node; A multiplication circuit, connected to the storage circuit, is configured to generate an output signal in response to the first signal and the second signal, the output signal corresponding to the product of the first signal and the second signal, the multiplication circuit comprising: An output node is configured to output the output signal; A first transistor, connected to the output node and the storage circuit, is configured to receive at least the second signal; and An initialization circuit, connected to the first transistor via the output node, is configured to initialize the multiplication circuit in response to at least a third or fourth signal.

2. The storage unit according to claim 1, wherein, The initialization circuit configured to initialize the multiplication circuit includes: The initialization circuit is also configured to set the output signal in response to at least the third signal or the fourth signal during the initialization phase of the storage circuit.

3. The storage unit according to claim 2, wherein, The initialization circuit includes: The second transistor of the first type includes: The first source / drain terminal is connected to the output node and the first transistor; The second source / drain terminal is connected to a reference voltage source having a reference voltage corresponding to the third signal; and The first gate terminal is configured to receive the fourth signal.

4. The storage unit according to claim 1, wherein, The first transistor is also configured to set the output signal in response to at least the second signal during the sensing phase of the storage circuit.

5. The storage unit according to claim 4, wherein, The first transistor is a P-type transistor, and the first transistor includes: The first source / drain terminal is connected to the output node and the initialization circuit; A second source / drain terminal is configured to receive the second signal; and A first gate terminal is connected to a second storage node of the storage circuit and is configured to receive a fifth signal from the storage circuit, the fifth signal corresponding to the voltage of the second storage node.

6. The storage unit according to claim 5, wherein, The fifth signal is the inverse of the first signal.

7. The storage unit according to claim 4, wherein, The first transistor is an N-type transistor, and the first transistor includes: The first source / drain terminal is connected to the output node and the initialization circuit; A second source / drain terminal is configured to receive the second signal; and A first gate terminal is connected to the first memory node of the memory circuit and is configured to receive a first signal from the memory circuit, the first signal corresponding to the voltage of the first memory node.

8. The storage unit according to claim 1, wherein, The memory cell corresponds to an 8-transistor (8T) static random access (SRAM) cell.

9. The storage unit according to claim 1, wherein, The storage circuit includes: First line; Second line; First letter line; The first cross-connected inverter; The second cross-connected inverter is connected to the first cross-connected inverter; A first transmission gate transistor is connected to the first bit line, the first word line, and the first cross-connected inverter; and The second transmission gate transistor is connected to the second bit line, the first word line, and the second cross-connected inverter.

10. A storage cell array, comprising: The first set of storage circuits is configured to store weight data, and the first set of storage circuits includes: The first storage circuit is configured to store a first weight value of a first signal of a first storage node; A first set of multiplication circuits is configured to perform in-memory computation (CIM) operations between the weighted data and the input data. The first set of multiplication circuits includes: A first multiplication circuit, connected to the first storage circuit, is configured to generate an output signal in response to a first signal and a second signal, the output signal corresponding to a product operation calculated in memory between the first signal and the second signal. The first multiplication circuit includes: The first output node is configured to output the output signal; A first transistor, connected to the first output node and the first storage circuit, is configured to receive at least the second signal; and An initialization circuit, connected to the first transistor via the first output node, is configured to initialize the first multiplication circuit in response to at least a third or fourth signal. Each multiplication circuit in the first group of multiplication circuits corresponds to each storage circuit in the first group of storage circuits.

11. The storage cell array according to claim 10, wherein, The in-memory product operation between the first signal and the second signal corresponds to the AND operation between the first signal and the second signal.

12. The storage cell array according to claim 10, wherein, The first transistor is also configured to set the output signal in response to at least the second signal during the sensing phase of the first storage circuit.

13. The storage cell array according to claim 12, wherein, The first transistor is an N-type transistor, and the first transistor includes: The first source / drain terminal is connected to the first output node and the initialization circuit; A second source / drain terminal is configured to receive the second signal; and A first gate terminal is connected to the first memory node of the first memory circuit and is configured to receive a first signal from the first memory circuit, the first signal corresponding to the voltage of the first memory node.

14. The storage cell array according to claim 12, wherein, The first transistor is a P-type transistor, and the first transistor includes: The first source / drain terminal is connected to the first output node and the initialization circuit; A second source / drain terminal is configured to receive the second signal; and A first gate terminal is connected to a second memory node of the first memory circuit and is configured to receive a fifth signal from the first memory circuit, the fifth signal corresponding to the voltage of the second memory node. The fifth signal is the inverse of the first signal.

15. The storage cell array according to claim 10, wherein, The initialization circuit configured to initialize the first multiplication circuit includes: The initialization circuit is also configured to set the output signal in response to at least the third signal or the fourth signal during the initialization phase of the first storage circuit.

16. The storage cell array according to claim 15, wherein, The initialization circuit includes: The second transistor of the first type includes: The first source / drain terminal is connected to the first output node and the first transistor; The second source / drain terminal is connected to a reference voltage source having a reference voltage corresponding to the third signal; and The first gate terminal is configured to receive the fourth signal.

17. The storage cell array according to claim 10, wherein, The memory cell array corresponds to an array of 8-transistor (8T) static random access (SRAM) cells.

18. A method of operating a storage unit, the method comprising: Performing a write operation on the storage unit, the storage unit including a storage circuit and a multiplication circuit, the write operation on the storage unit includes: The first value of the first signal is stored in the first storage node of the storage circuit, and the first signal corresponds to the first weight. The multiplication circuit performs an in-memory computation (CIM) operation between the first signal and the second signal. The multiplication circuit includes a first transistor and an initialization circuit. Performing the in-memory computation operation between the first signal and the second signal includes: In response to at least a third or fourth signal, the output signal of the multiplication circuit is initialized by the initialization circuit; and In response to at least a second signal, the output signal is set by the first transistor during the sensing phase of the storage circuit.

19. The method according to claim 18, wherein, The output signal for initializing the multiplication circuit includes: During the initialization phase of the storage circuit, the second signal is set to an initial value, the initialization circuit including a second transistor; In response to the third signal, the second transistor is turned on, thereby electrically connecting the first node of the multiplication circuit to the output node of the multiplication circuit; and Set the value of the output signal to be equal to the value of the fourth signal.

20. The method according to claim 19, wherein, Setting the output signal during the sensing phase of the storage circuit includes: In response to the third signal, the second transistor is turned off, thereby electrically disconnecting the first node and the output node from each other; During the sensing phase of the storage circuit, the second signal is set to an uninitialized value; and The value of the output signal is set in response to turning the first transistor on or off.

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