Field programmable gate array circuit, data processing method

Abstract

The embodiment of the present application discloses a field programmable logic gate array circuit, a data processing method and a circuit design method. The field programmable logic gate array circuit comprises a communication interface, at least one function module, the function module comprises a plurality of function operator modules and a switching matrix module, the switching matrix module comprises a plurality of switching matrices, the function operator module is connected with the switching matrix, wherein one or more switching matrices are connected between any two function operator modules; and the communication interface is directly or indirectly connected with at least part of the switching matrices. The present application can avoid re-designing the complete flow of the FPGA, and improve the flexibility of the FPGA.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, and particularly relates to a field programmable logic gate array circuit, a data processing method and a circuit design method. BACKGROUND

[0002] FPGA (Field Programmable Gate Array) is a kind of digital logic circuit, and the most basic unit of a digital logic system is an AND gate, an OR gate, a NOT gate and the like, a gate circuit is composed of diodes, transistors and resistors and the like, and then the AND gate, the OR gate and the NOT gate constitute various flip-flops to realize state memory. The FPGA is a digital integrated circuit (IC) composed of configurable or programmable logic blocks, and the logic blocks are connected by configurable interconnection resources. Design engineers can program and configure such devices to complete various tasks.

[0003] At present, the logic operation function of the function module in the FPGA is relatively single, and the flexibility is poor. When the FPGA needs to reconfigure the logic operation function of the function module, the FPGA needs to be reprogrammed for front-end algorithm planning, coding, simulation, comprehensive layout and wiring, and design convergence, which is time-consuming and laborious, and low in efficiency. SUMMARY

[0004] In view of the defects in the prior art, the present application provides a field programmable logic gate array circuit, a data processing method and a circuit design method, aiming at solving the technical problem of poor flexibility of the FPGA in the prior art.

[0005] To solve the above problems, in a first aspect, the present application provides a field programmable logic gate array circuit, comprising:

[0006] a communication interface;

[0007] at least one function module, the function module comprising a plurality of function operator modules and a switching matrix module, the switching matrix module comprising a plurality of switching matrices; wherein one or more switching matrices are connected between any two function operator modules; and the communication interface is directly or indirectly connected to at least part of the switching matrices.

[0008] Further, in the field programmable logic gate array circuit, the plurality of functional operator modules include a first functional operator module, a second functional operator module, and a third functional operator module, the first functional operator module and the second functional operator module each include a plurality of operator modules, two adjacent exchange matrices are connected, each operator module in the first functional operator module is connected with one exchange matrix, each operator module in the second functional operator module is connected with two adjacent exchange matrices, and the third functional operator is connected with each exchange matrix.

[0009] Further, in the field programmable logic gate array circuit, the exchange matrix module includes a first exchange matrix, a second exchange matrix, a third exchange matrix, and a fourth exchange matrix; the first functional operator module includes a first operator module, a second operator module, a third operator module, and a fourth operator module, and the second functional operator module includes a fifth operator module, a sixth operator module, a seventh operator module, and an eighth operator module.

[0010] The first exchange matrix is connected with the second exchange matrix, the third exchange matrix, the first operator module, the fifth operator module, the sixth operator module, and the third functional operator module respectively.

[0011] The second exchange matrix is connected with the second operator module, the fifth operator module, the seventh operator module, and the third functional operator module respectively.

[0012] The third exchange matrix is connected with the third operator module, the sixth operator module, the eighth operator module, and the third functional operator module respectively.

[0013] The fourth exchange matrix is connected with the second exchange matrix, the third exchange matrix, the fourth operator module, the seventh operator module, the eighth operator module, and the third functional operator module respectively.

[0014] Further, in the field programmable logic gate array circuit, the exchange matrix module further includes a fifth exchange matrix, a sixth exchange matrix, a seventh exchange matrix, and an eighth exchange matrix, the fifth operator module includes a first operator and a second operator, the sixth operator module includes a third operator and a fourth operator, the seventh operator module includes a fifth operator and a sixth operator, and the eighth operator module includes a seventh operator and an eighth operator.

[0015] The first operator is connected with the first exchange matrix and the fifth exchange matrix respectively.

[0016] The second operator is connected with the second exchange matrix and the fifth exchange matrix respectively.

[0017] The third operator is connected with the first exchange matrix and the sixth exchange matrix respectively;

[0018] The fourth operator is connected with the fourth exchange matrix and the sixth exchange matrix respectively;

[0019] The fifth operator is connected with the second exchange matrix and the seventh exchange matrix respectively;

[0020] The sixth operator is connected with the fourth exchange matrix and the seventh exchange matrix respectively;

[0021] The seventh operator is connected with the third exchange matrix and the eighth exchange matrix respectively;

[0022] The seventh operator is connected with the fourth exchange matrix and the eighth exchange matrix respectively;

[0023] The third functional operator module is connected with the first exchange matrix, the second exchange matrix, the third exchange matrix, the fourth exchange matrix, the fifth exchange matrix, the sixth exchange matrix, the seventh exchange matrix and the eighth exchange matrix respectively;

[0024] The fifth exchange matrix is connected with the first exchange matrix and the second exchange matrix respectively;

[0025] The sixth exchange matrix is connected with the first exchange matrix and the third exchange matrix respectively;

[0026] The seventh exchange matrix is connected with the second exchange matrix and the fourth exchange matrix respectively;

[0027] The eighth exchange matrix is connected with the third exchange matrix and the fourth exchange matrix respectively.

[0028] Further, in the field programmable logic gate array circuit, the plurality of functional operator modules include at least one of the following: a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, a delay unit.

[0029] Further, in the field programmable logic gate array circuit, the exchange matrix module receives at least one input signal inputted externally through the communication interface; the exchange matrix module outputs at least one output signal to the outside through the communication interface.

[0030] Further, in the field programmable logic gate array circuit, the function module is configured to perform a target logic operation on a target signal input into the function module, the target logic operation comprises N sub-logic operations, N function operator modules in the function module are configured to perform the N sub-logic operations respectively, and the switch matrix module is configured to configure communication links of connection ends of the N function operator modules to perform the target logic operation on the target signal.

[0031] In a second aspect, the embodiments of the present application further provide a data processing method applied to the field programmable logic gate array circuit in the first aspect.

[0032] The data processing method comprises:

[0033] The communication interface receives an externally inputted to-be-processed signal;

[0034] The function module acquires a target signal and performs the target logic operation to obtain a first processing result of the target signal; the target signal is the to-be-processed signal or a signal obtained based on the to-be-processed signal;

[0035] The communication interface outputs the first processing result or a second processing result obtained based on the first processing result.

[0036] In a third aspect, the embodiments of the present application further provide a circuit design method, which comprises:

[0037] designing a circuit on a target circuit board as the field programmable logic gate array circuit in the first aspect;

[0038] determining a first target logic operation to be performed by the function module on a first target signal; the first target logic operation comprises N sub-logic operations, and N function operator modules in the plurality of function operator modules are capable of performing the N sub-logic operations respectively;

[0039] by configuring the switch matrix module, the communication links of the connection ends of the N function operator modules are configured to be capable of performing a processing process of the first target logic operation on the first target signal.

[0040] Further, in the circuit design method, the designing of the circuit on the target circuit board as the field programmable logic gate array circuit in the first aspect comprises:

[0041] acquiring operator demand information, the operator demand information being used to represent quantity requirements of various types of function operator modules;

[0042] According to the operator requirement information, the circuit on the circuit board is designed as the field programmable logic gate array circuit of the first aspect.

[0043] The field programmable logic gate array circuit provided by the embodiment of the present application avoids the complete flow design of the FPGA, and improves the flexibility of the FPGA. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0045] Figure 1 The module block diagram of the field programmable logic gate array circuit provided by the embodiment of the present application is shown in the figure.

[0046] Figure 2 The schematic block diagram of the functional module provided by the embodiment of the present application is shown in the figure.

[0047] Figure 3 Another schematic block diagram of the functional module provided by the embodiment of the present application is shown in the figure.

[0048] Figure 4 The link diagram of the logical operation of the functional module provided by the embodiment of the present application is shown in the figure.

[0049] Figure 5 Another link diagram of the logical operation of the functional module provided by the embodiment of the present application is shown in the figure.

[0050] Figure 6 Another link diagram of the logical operation of the functional module provided by the embodiment of the present application is shown in the figure.

[0051] Figure 7 The schematic block diagram of the data processing method provided by the embodiment of the present application is shown in the figure.

[0052] Figure 8 The schematic block diagram of the circuit design method provided by the embodiment of the present application is shown in the figure.

[0053] Figure 9 Another schematic block diagram of the circuit design method provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application.

[0055] It should be understood that the terms "comprising" and "including" as used in the specification and the appended claims indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0056] It should also be understood that the terms used in the present application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0057] It should be further understood that the term "and / or" as used in the present application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0058] Please refer to Figure 1 , Figure 1 The module block diagram of the field programmable logic gate array circuit provided by the embodiments of the present application is shown.

[0059] As Figure 1 shown, a field programmable logic gate array circuit comprises:

[0060] a communication interface 10;

[0061] at least one functional module 20, the functional module 20 comprising a plurality of functional operator modules and a switching matrix module, the switching matrix module comprising a plurality of switching matrices; wherein one or more switching matrices are connected between any two functional operator modules; the communication interface 10 is directly or indirectly connected to at least part of the switching matrices.

[0062] Specifically, the functional module 20 is configured to perform a target logic operation on a target signal input to the functional module 20, the target logic operation comprising N sub-logic operations, N functional operator modules in the functional module 20 performing the N sub-logic operations respectively, and the switching matrix module is configured to configure the communication links of the connection ends of the N functional operator modules to perform the target logic operation on the target signal.

[0063] The functional operator module includes at least one of the following: a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit. There are three types of functional operator modules in the functional module 20, one of which is connected to only one of the switching matrices in the switching matrix module, another is connected to two adjacent switching matrices in the switching matrix module, and the third is connected to all the switching matrices in the switching matrix module.

[0064] The present application can not only directly implement a general algorithm in the FPGA through the functional module 20, but also implement a complete algorithm with high performance. When the functional module 20 needs to perform a target logic operation on an input target signal, only the switching matrix in the switching matrix module needs to be connected to the required functional operator module, so that the functional operator module can receive the corresponding signal and perform the corresponding logic operation, thereby enabling the functional module 20 to implement the logic operation on the target signal, without the need to re-plan, encode, simulate, synthesize layout and wiring, and design convergence for the front-end algorithm of the FPGA, greatly improving the flexibility of the FPGA.

[0065] In some embodiments, as shown in Figure 2 The functional operator module includes a first functional operator module, a second functional operator module, and a third functional operator module, the first functional operator module and the second functional operator module each include a plurality of operator modules, and the switching matrix module includes a plurality of switching matrices; each operator module in the first functional operator module is connected to one of the switching matrices, each operator module in the second functional operator module is connected to two adjacent switching matrices, and the third functional operator is connected to each of the switching matrices.

[0066] Specifically, the first functional operator module, the operator modules in the second functional operator, and the third functional operator module are connected through one or more switching matrices, and the operator modules are not directly connected to each other or to the third functional operator module.

[0067] The first functional operator module and the second functional operator module include a plurality of operator modules, and the third functional operator module can include one operator module or a plurality of operator modules. The operator module is an operator with a logic operation function, and each operator module includes at least one of the following: a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit.

[0068] In the embodiment, the first functional operator module and the second functional operator module can be composed of any one of a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit, or a plurality of operators, and the third functional operator module can be any one of a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit.

[0069] It should be noted that the selection of the first functional operator module, the second functional operator module, and the third functional operator module in the present application is based on the statistics of operators required by different algorithms, and the combination is obtained according to the operator usage probability. The statistics is based on the control, operation, and model requirements of all vehicle-mounted devices.

[0070] In addition, in the embodiment, the FPGA includes at least one functional module 20, and the functional module 20 is connected with the switching matrix module. The number of the functional module 20 in the FPGA can be determined according to the size of the FPGA and the complexity of the algorithm to be implemented.

[0071] The present application sets the first functional operator module, the second functional operator module, and the third functional operator module in the functional module 20 in the FPGA, and the first functional operator module and the second functional operator module each include a plurality of operator modules. Each operator module in the first functional operator module is connected with a switching matrix, each operator module in the second functional operator module is connected with two adjacent switching matrices, and the third functional operator is connected with each switching matrix. Not only can the general algorithm be implemented in the FPGA, but also the complete algorithm with high performance can be implemented. At the same time, the relative positions between the switching matrix and the operator modules are relatively fixed, which ensures the unity of the timing and logic in the functional module 20, and also avoids the complete flow design of the FPGA, thereby improving the flexibility of the FPGA.

[0072] In some embodiments, the functional operator module and the switching matrix module are connected and configured through a configuration module. Specifically, the connection between each operator module in the first functional operator module and the second functional operator module and each switching matrix in the switching matrix module can be connected and configured through the configuration module, so that a specific function can be implemented in the functional module 20.

[0073] At the same time, the input end of the switching matrix can be connected with the input end or the output end of each operator module, and the output end of the switching matrix can also be connected with the input end or the output end of each operator module. The specific connection mode can be connected and configured by the configuration module according to the actual application.

[0074] It can be understood that the input and output ends of each operator module are connected to the corresponding switching matrix, and the switching matrix is configured by the configuration module. The signal can be input to the operator module, the output signal can be received from the operator module, or both the signal can be input to the operator module and the output signal can be received from the operator module.

[0075] In some embodiments, as shown in Figure 2 The switching matrix module includes a first switching matrix, a second switching matrix, a third switching matrix, and a fourth switching matrix; the first functional operator module includes a first operator module, a second operator module, a third operator module, and a fourth operator module, and the second functional operator module includes a fifth operator module, a sixth operator module, a seventh operator module, and an eighth operator module; wherein the first switching matrix is connected with the second switching matrix, the third switching matrix, the first operator module, the fifth operator module, the sixth operator module, and the third functional operator module respectively; the second switching matrix is connected with the second operator module, the fifth operator module, the seventh operator module, and the third functional operator module respectively; the third switching matrix is connected with the third operator module, the sixth operator module, the eighth operator module, and the third functional operator module respectively; and the fourth switching matrix is connected with the second switching matrix, the third switching matrix, the fourth operator module, the seventh operator module, the eighth operator module, and the third functional operator module respectively.

[0076] Specifically, the first operator module, the second operator module, the third operator module, and the fourth operator module can be any one of a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit, and the fifth operator module, the sixth operator module, the seventh operator module, and the eighth operator module can be any one or multiple of a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit.

[0077] In some embodiments, as shown in Figure 3As shown, the switching matrix module further comprises a fifth switching matrix, a sixth switching matrix, a seventh switching matrix, and an eighth switching matrix, the fifth operator module comprises a first operator and a second operator, the sixth operator module comprises a third operator and a fourth operator, the seventh operator module comprises a fifth operator and a sixth operator, and the eighth operator module comprises a seventh operator and an eighth operator; wherein the first operator is connected with the first switching matrix and the fifth switching matrix respectively; the second operator is connected with the second switching matrix and the fifth switching matrix respectively; the third operator is connected with the first switching matrix and the sixth switching matrix respectively; the fourth operator is connected with the fourth switching matrix and the sixth switching matrix respectively; the fifth operator is connected with the second switching matrix and the seventh switching matrix respectively; the sixth operator is connected with the fourth switching matrix and the seventh switching matrix respectively; the seventh operator is connected with the third switching matrix and the eighth switching matrix respectively; the seventh operator is connected with the fourth switching matrix and the eighth switching matrix respectively; the third functional operator module is connected with the first switching matrix, the second switching matrix, the third switching matrix, the fourth switching matrix, the fifth switching matrix, the sixth switching matrix, the seventh switching matrix, and the eighth switching matrix respectively; the fifth switching matrix is connected with the first switching matrix and the second switching matrix respectively; the sixth switching matrix is connected with the first switching matrix and the third switching matrix respectively; the seventh switching matrix is connected with the second switching matrix and the fourth switching matrix respectively; and the eighth switching matrix is connected with the third switching matrix and the fourth switching matrix respectively.

[0078] Specifically, the first operator module, the second operator module, the third operator module, and the fourth operator module can be any one of a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit, and the first operator, the second operator, the third operator, the fourth operator, the fifth operator, the sixth operator, the seventh operator, and the eighth operator can be any one or multiple of a multiplier, a flip-flop, a filter, a convolution kernel, an accumulator, an adder, a subtractor, and a delay unit.

[0079] In some embodiments, the switching matrix module receives at least one input signal inputted externally through the communication interface 10, and outputs at least one output signal to the outside through the communication interface 10. Wherein, one or more input signals can be inputted to the switching matrix module from the outside of the FPGA, and one or more output signals can be outputted from the functional module 20 after logical operation.

[0080] Specifically, when the switching matrix module receives one input signal inputted externally through the communication interface 10 and outputs one output signal to the outside, as shown in FIG. 2, the first switching matrix, the second switching matrix, the third switching matrix, the fourth switching matrix, the fifth switching matrix, the sixth switching matrix, the seventh switching matrix, and the eighth switching matrix are all in the state of being connected with the third functional operator module.Figure 4 As shown, the input signal Iin can be input to the first operator module for processing through the first switching matrix, the first operator module processes the input signal Iin, and then the processed signal can be input to the second functional operator module for processing through the first switching matrix, the second functional operator module processes the signal, and then the processed signal can be input to the seventh operator module for processing through the fourth switching matrix, and after the processing in the seventh operator module is completed, the generated signal Iout can be input to the external chip through the fourth switching matrix.

[0081] When the switching matrix module receives one input signal input by the external chip through the communication interface 10 and outputs multiple output signals to the external chip, as shown in Figure 5 As shown, the input signal Iin can be input to the first operator module for processing through the first switching matrix, the first operator module processes the input signal Iin, and then the processed signal can be input to the second functional operator module for processing through the first switching matrix, the second functional operator module processes the signal, and then the processed signal can be input to the seventh operator module for processing through the fourth switching matrix, and after the processing in the seventh operator module is completed, the generated signal Iout can be input to the external chip through the fourth switching matrix.

[0082] When the switching matrix module receives one input signal input by the external chip through the communication interface 10 and outputs multiple output signals to the external chip, as shown in Figure 6As shown, the input signal Iin1 can be input into the first operator module through the first switching matrix, and after the first operator module processes the input signal Iin1, the processed signal can be input into the fifth operator module through the first switching matrix. After the fifth operator module completes the processing, the processed signal can be input into the second functional operator module through the first switching matrix. After the second functional operator module completes the processing, two signals can be generated. One of the two signals can be input into the third operator module through the second switching matrix, the first switching matrix and the third switching matrix. After the third operator module completes the processing, the generated signal Iout2 can be input into an external chip through the third switching matrix and the fourth switching matrix. The other of the two signals can be input into the second operator module through the second switching matrix for processing. After the second operator module completes the processing, the generated signal Iout3 can be input into the external chip through the second switching matrix and the fourth switching matrix. The input signal Iin1 can also be input into the fifth operator module through the first switching matrix. After the fifth operator module processes the input signal Iin1, the processed signal can be input into the fifth operator module again through the first switching matrix. After the fifth operator module completes the processing, the processed signal can be input into the second functional operator module through the first switching matrix. After the second functional operator module completes the processing, the processed signal can be input into the seventh operator module through the fourth switching matrix. At the same time, the input signal Iin2 can be input into the fourth operator module through the first switching matrix, the third switching matrix and the fourth switching matrix for processing. After the fourth operator module processes the input signal Iin2, the processed signal can also be input into the seventh operator module through the fourth switching matrix. The seventh operator module processes the signal generated by the input signal Iin1 and the signal generated by the input signal Iin2, and the generated signal Iout4 can be input into the external chip through the fourth matrix. Similarly, the input signal Iin1 can be input into the sixth operator module through the first switching matrix, and the input signal Iin1 can be processed in the sixth operator module. After the sixth operator module completes the processing, the generated signal Iout1 can be input into the external chip through the third switching matrix and the fourth switching matrix.

[0083] In some embodiments, the present application also provides a data processing method, wherein the field programmable logic gate array circuit comprises: a communication interface 10; at least one functional module 20, the functional module 20 comprising a plurality of functional operator modules and switching matrix modules, the switching matrix modules comprising a plurality of switching matrices; wherein one or more switching matrices are connected between any two functional operator modules; and the communication interface 10 is directly or indirectly connected to at least part of the switching matrices.

[0084] As shown in the figure, Figure 7 The data processing method comprises:

[0085] S110, receiving an external input signal to be processed according to the communication interface 10;

[0086] S120, the function module 20 acquires a target signal and performs the target logic operation to obtain a first processing result of the target signal; the target signal is the to-be-processed signal or a signal obtained based on the to-be-processed signal;

[0087] S130, the communication interface 10 outputs the first processing result or a second processing result obtained based on the first processing result.

[0088] Specifically, before data processing by the FPGA circuit provided in the present application, the function operator module needs to be selected according to the specific application scenario and the specific function implemented by the application scenario, and the connection between the function operator and the switching matrix module is configured according to the configuration module, so that when the communication interface 10 receives the to-be-processed signal input by the external chip, the function module 20 in the FPGA circuit can perform corresponding logic operation, so as to obtain the processing result of the to-be-processed signal, and can be output to the outside of the FPGA in turn through the switching matrix and the communication interface 10.

[0089] In some embodiments, as shown in Figure 8 The present application also provides a circuit design method, which comprises:

[0090] S210, designing a circuit on a target circuit board as the field programmable logic gate array circuit described above;

[0091] S220, determining a first target logic operation to be performed by the function module 20 on a first target signal; the first target logic operation comprises N sub-logic operations, and N function operator modules in the plurality of function operator modules can respectively execute the N sub-logic operations;

[0092] S230, configuring the communication link of the connection end of the N function operator modules as a processing process capable of performing the first target logic operation on the first target signal by configuring the switching matrix module.

[0093] Specifically, the first target signal is a signal on which the function module 20 needs to perform a target logic operation, and the number and type of function operator modules can be determined through the first target signal. The required function operator modules are connected through the switching matrix in the switching matrix module, so that the signals to be processed by each function operator module can enter the corresponding function operator module through the switching matrix to perform corresponding logic operation, thereby realizing the execution of the first target logic operation on the first target signal by the function module 20.

[0094] In some embodiments, when the functional module 20 needs to perform a second target logic operation on a second target signal, after determining M sub-logic operations required by the second target logic operation, it is determined in the functional module 20 that M functional operator modules required by the M sub-logic operations can perform each sub-logic operation in the second target logic operation, and then the communication link of the connection end of each functional operator module is configured by the switching matrix in the switching matrix module to be able to perform the second target logic operation on the second target signal, so as to realize that the functional operator module performs the second target logic operation on the second target signal.

[0095] It can be understood that, whether the functional module 20 performs a first target logic operation on a first target signal or performs a second target logic operation on a second target signal, it only needs to pre-design the circuit on the target circuit board as the field programmable logic gate array circuit provided in the present application, then determine the sub-logic operations required by the corresponding target logic operation, and determine the functional operator module processing each sub-logic operation in the functional module 20, and at the same time, the communication link of the connection end of each functional operator module is configured by the switching matrix in the switching matrix module to be able to perform the corresponding target logic operation on each target signal.

[0096] It should be noted that the first target signal and the second target signal are only part of the specific embodiments exemplified in the present application, and the present application can also perform a third target logic operation on a third target signal or a fourth target logic operation on a fourth target signal, etc. The functional module 20 performs the corresponding target logic operation on each target signal can be selected according to the actual application, and the present embodiment is not limited.

[0097] In some embodiments, as shown in Figure 9 Step S210 includes steps S211 and S212.

[0098] S211, obtaining operator demand information, the operator demand information being used to represent the quantity requirement of each type of functional operator module;

[0099] S212, according to the operator demand information, designing the circuit on the circuit board as the field programmable logic gate array circuit described above.

[0100] Specifically, the operator demand information can be determined according to the application scenario in which the FPGA circuit is used, and is obtained by combining the use probability of each operator in the application scenario. For example, in a vehicle application scenario, the use probability of each operator in the vehicle application can be determined by counting the control, operation and model demand of all vehicle devices, so as to determine the quantity requirement of each type of functional operator module in the FPGA circuit to complete the design of the FPGA circuit.

[0101] It can be understood that the FPGA circuit designed by the method is designed based on the application scene where the FPGA circuit is located, and the FPGA circuit can implement a general algorithm in the corresponding application scene, so that the FPGA does not need to be designed with a complete flow in the same application scene, thereby greatly improving the flexibility of the FPGA.

[0102] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements shall be encompassed within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A field-programmable gate array circuit, characterized in that, include: Communication interface; At least one functional module, the functional module comprising multiple functional operator modules and a switching matrix module, the switching matrix module comprising multiple switching matrices; wherein, any two of the functional operator modules are connected to one or more of the switching matrices; the communication interface is directly or indirectly connected to at least a portion of the switching matrices; the switching matrix module receives at least one input signal from an external source through the communication interface; The plurality of functional operator modules include a first functional operator module, a second functional operator module, and a third functional operator module, and the exchange matrix module includes a first exchange matrix, a second exchange matrix, a third exchange matrix, a fourth exchange matrix, a fifth exchange matrix, a sixth exchange matrix, a seventh exchange matrix, and an eighth exchange matrix; The second functional operator module includes a fifth operator module, a sixth operator module, a seventh operator module, and an eighth operator module; The fifth operator module includes a first operator and a second operator; the sixth operator module includes a third operator and a fourth operator; the seventh operator module includes a fifth operator and a sixth operator; and the eighth operator module includes a seventh operator and an eighth operator. The first operator is connected to the first exchange matrix and the fifth exchange matrix, respectively; the second operator is connected to the second exchange matrix and the fifth exchange matrix, respectively; the third operator is connected to the first exchange matrix and the sixth exchange matrix, respectively; the fourth operator is connected to the fourth exchange matrix and the sixth exchange matrix, respectively; the fifth operator is connected to the second exchange matrix and the seventh exchange matrix, respectively; the sixth operator is connected to the fourth exchange matrix and the seventh exchange matrix, respectively; the seventh operator is connected to the third exchange matrix and the eighth exchange matrix, respectively; the seventh operator is connected to the fourth exchange matrix and the eighth exchange matrix, respectively. The third functional operator module is connected to the first exchange matrix, the second exchange matrix, the third exchange matrix, the fourth exchange matrix, the fifth exchange matrix, the sixth exchange matrix, the seventh exchange matrix, and the eighth exchange matrix, respectively. The fifth exchange matrix is ​​connected to the first exchange matrix and the second exchange matrix respectively; the sixth exchange matrix is ​​connected to the first exchange matrix and the third exchange matrix respectively; the seventh exchange matrix is ​​connected to the second exchange matrix and the fourth exchange matrix respectively; and the eighth exchange matrix is ​​connected to the third exchange matrix and the fourth exchange matrix respectively.

2. The field-programmable gate array circuit according to claim 1, characterized in that, The first functional operator module includes multiple operator modules, and adjacent exchange matrices are connected. Each operator module in the first functional operator module is connected to one exchange matrix. Each operator module in the second functional operator module is connected to two adjacent exchange matrices. The third functional operator is connected to each of the exchange matrices.

3. The field-programmable gate array circuit according to claim 1, characterized in that, The first functional operator module includes a first operator module, a second operator module, a third operator module, and a fourth operator module; The first exchange matrix is ​​connected to the second exchange matrix, the third exchange matrix, the first operator module, the fifth operator module, the sixth operator module, and the third functional operator module, respectively. The second exchange matrix is ​​connected to the second operator module, the fifth operator module, the seventh operator module, and the third functional operator module, respectively. The third exchange matrix is ​​connected to the third operator module, the sixth operator module, the eighth operator module, and the third functional operator module, respectively. The fourth exchange matrix is ​​connected to the second exchange matrix, the third exchange matrix, the fourth operator module, the seventh operator module, the eighth operator module, and the third functional operator module, respectively.

4. The field-programmable gate array circuit according to claim 1, characterized in that, The functional operator module includes at least one of the following: multiplier, trigger, filter, convolution kernel, accumulator, adder, subtractor, and delay unit.

5. The field-programmable gate array circuit according to claim 1, characterized in that, The switching matrix module outputs at least one output signal to the outside through the communication interface.

6. The field-programmable gate array circuit according to any one of claims 1 to 5, characterized in that, The functional module is used to perform target logic operations on the target signal input to the functional module. The target logic operation includes N sub-logic operations. The N functional operator modules in the functional module execute the N sub-logic operations respectively. The exchange matrix module is used to configure the communication link of the connection end of the N functional operator modules to perform the target logic operation on the target signal.

7. A data processing method, characterized in that, Applied to the field-programmable gate array circuit of claim 6; The data processing method includes: The communication interface receives externally input signals to be processed; The functional module acquires the target signal and performs the target logic operation to obtain a first processing result of the target signal; the target signal is the signal to be processed or a signal obtained based on the signal to be processed. The communication interface outputs the first processing result or a second processing result obtained based on the first processing result.

8. A circuit design method, characterized in that, include: The circuit on the target circuit board is designed as the field-programmable gate array circuit as described in any one of claims 1 to 5; The first target logic operation for the first target signal to be executed by the functional module is determined; the first target logic operation includes N sub-logic operations, and each of the N functional operator modules can execute the N sub-logic operations. By configuring the exchange matrix module, the communication links at the connection ends of the N functional operator modules are configured to perform the first target logic operation on the first target signal.

9. The circuit design method according to claim 8, characterized in that, The step of designing the circuit on the target circuit board as the field-programmable gate array circuit according to any one of claims 1 to 5 includes: Obtain operator requirement information, which indicates the quantity requirements of various functional operator modules; Based on the operator requirement information, the circuit on the circuit board is designed as a field-programmable gate array circuit as described in any one of claims 1 to 5.

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