A matrix multiplication operation circuit based on a memristor array and a method of using the same

Abstract

The application relates to a matrix multiplication operation circuit based on a memristor array and a use method thereof.The technical scheme is as follows: the application comprises a sampling delay circuit (101), a resistance adjusting circuit (102), a matrix element storage module (103), a first-stage operation circuit (104), a matrix element storage and operation module (105), a second-stage operation circuit (106), a matrix operation result storage module (107), a matrix resistor (108) and a matrix switch circuit (109). When performing matrix multiplication operation, a matrix represented by the matrix element storage module (103) and a matrix represented by the matrix element storage and operation module (105) complete multiplication operation, and the operation result is saved into the matrix operation result storage module (107) through the resistance adjusting circuit (102), and the process of data transmission between a memory and an operation device is omitted in the calculation process.The application can perform matrix multiplication operation on any two real number matrices containing positive and negative elements, and the operation is simple and fast.

Description

Technical Field

[0001] This invention belongs to the field of matrix multiplication circuit technology. Specifically, it relates to a matrix multiplication circuit based on a memristor array. Background Technology

[0002] Matrix multiplication is widely used in various fields such as physics research, image processing, linear programming, and signal processing. Improving the speed of matrix multiplication can enhance the data processing speed in these applications. Currently, large-scale matrix multiplication operations are implemented in computers using matrix multiplication programs, but their speed is limited by two factors: First, frequent data transfers between the arithmetic logic unit (ALU) and memory during matrix multiplication consume a significant amount of time, hindering speed improvements. Second, computer programs can only perform operations between two data points at a time, further increasing the computation time. Therefore, addressing these two issues to improve the speed of matrix multiplication is a focus for those skilled in the art.

[0003] A memristor array is a combinational circuit of memristors that can store multiple analog quantities in the form of resistors. Multiplication and accumulation operations can be performed in parallel by applying voltage to each row of the memristor array, thus avoiding the time consumption caused by data transfer between the arithmetic logic unit (ALU) and the memory. Furthermore, memristor arrays can perform operations on multiple sets of data simultaneously, solving the slow speed problem caused by computers sequentially executing operations on single sets of data. In matrix multiplication circuits, the matrix elements have the same arrangement as the memristors in the memristor array, and the memristor array can complete vector-matrix multiplication operations within one computation cycle. Therefore, circuits based on memristor arrays are of great value in the research of matrix multiplication circuits.

[0004] Nourazar M et al. (Nourazar M, Rashtchi V, Azarpeyvand A, et al. Memristor-based approximate matrix multiplier[J]. Analog Integrated Circuits and Signal Processing, 2017, 93(3):363-373) designed a matrix multiplication circuit by combining digital circuits and memristor arrays. This circuit uses the conductance of each memristor in the memristor array to represent an element in the matrix, and the voltage applied to each row of the memristor array to represent the vector being multiplied by the matrix. During the operation, the controller applies the voltage representing the vector element to the corresponding row of the memristor array, and simultaneously reads the output voltage of the memristor array as the result of the vector-matrix multiplication operation. Then, the matrix-to-matrix multiplication operation is completed through multiple vector-matrix multiplications. Although this matrix multiplication circuit can significantly improve the efficiency of matrix multiplication through analog operation, each vector-matrix multiplication operation in the implementation process requires the controller to perform input and read operations, which limits the speed of matrix multiplication. In addition, the method for adjusting the resistance of each memristor in this circuit is quite complicated, which also leads to more time being spent on adjusting the resistance of the memristors.

[0005] Zhang Y et al. (Zhang Y, Wang X, Friedman E G. Memristor-based circuit design for multilayer neural networks[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 65(2): 677-686) designed a multilayer artificial neural network hardware circuit using multiple memristor arrays. This circuit uses a memristor array to represent one layer of the neural network, and the synaptic weights of the neural network are represented by the conductance values ​​of each memristor in the array. When a voltage is applied to each row of the memristor array, its output voltage is the result of the vector matrix multiplication operation, which is then applied as the input voltage to each row of the next memristor array, thus completing the vector matrix multiplication operation in each layer of the neural network sequentially. Although this circuit improves the speed of matrix multiplication through analog calculation, since it can only perform vector matrix multiplication, a voltage needs to be reapplied to each row of the memristor array after each operation, making it difficult to further improve the operation speed.

[0006] Cai RZ et al. (Ruizhe Cai, Ao Ren, Sucheta Soundarajan, Yanzhi Wang. A low-computation-complexity, energy-efficient, and high-performance linear program solver based on primal dual interior point method using memristor crossbars[J]. Nano Communication Networks, 2018, 18:62-71) designed a linear equation solver based on a memristor array. The conductance of each memristor in the memristor array and the voltage applied to each row of the array represent the coefficients and solution vectors in the coefficient matrix of the equation system, respectively. Then, the memristor array is used to perform vector and matrix multiplication operations, and an external controller performs comparisons and iterations to obtain the optimal solution to the equation. Although the entire system simulates the computation process, the algorithm implementation requires an external controller; therefore, the computation speed of this method is constrained by the controller's processing speed. Furthermore, the memristor array in this circuit can only store positive numbers and cannot directly compute matrices containing negative numbers.

[0007] Ran Decheng et al. (Ran Decheng, Wu Dong, Qian Lei. Design of a matrix multiplication accelerator for deep learning inference [J]. Computer Engineering, 2019, 45(10):40-45. DOI:10.19678 / j.issn.1000-3428.0052372.) designed a matrix multiplication circuit for deep learning inference. This circuit mainly completes matrix multiplication operations through multiple sets of digital circuit modules. Although this method can improve the speed of matrix multiplication operations to a certain extent, its control function is implemented through software, which makes the matrix operation speed always affected by the computer performance, and cannot achieve a greater improvement. Summary of the Invention

[0008] The present invention aims to overcome the shortcomings of the prior art and proposes a matrix multiplication circuit based on a memristor array that is fast in operation and simple in operation. This circuit can perform matrix multiplication on any two real matrix containing positive and negative elements.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0010] For the sake of simplicity, the matrix multiplication circuit based on memristor array will be referred to simply as the matrix multiplication circuit, and the physical meanings of the letters in the matrix multiplication circuit will be uniformly described as follows:

[0011] i, j, and k are natural numbers greater than or equal to 2, and M, N, and L are natural numbers that satisfy the following related inequalities:

[0012] 1≤i≤M;

[0013] 1≤j≤N;

[0014] 1≤k≤L.

[0015] The matrix multiplication circuit includes M sampling delay circuits, 2N+L resistance adjustment circuits, a matrix element storage module, N first-level operation circuits, a matrix element storage and operation module, L second-level operation circuits, a matrix operation result storage module, a matrix resistor, and a matrix switch circuit.

[0016] In the matrix multiplication circuit:

[0017] The terminals CLK of the first sampling delay circuit, ..., the terminals CLK of the i-th sampling delay circuit, ..., the terminals CLK of the M-th sampling delay circuit, and the terminal V of the matrix multiplication circuit. CLK1 Connect the terminals D of the first sampling delay circuit respectively. N Terminal D of the second sampling delay circuit IN Connect the terminals D of the (i-1)th sampling delay circuit. N Terminal D of the i-th sampling delay circuit IN Connect to terminal D of the (M-1)th sampling delay circuit. N Terminal D of the Mth sampling delay circuit IN Connection; Terminal D of the first sampling delay circuit IN Terminal V of the matrix multiplication circuit DIN connect.

[0018] Terminals CLK of the 11th resistance adjustment circuit, ..., terminals CLK of the 1jth resistance adjustment circuit, ..., terminals CLK of the 1Nth resistance adjustment circuit, terminals CLK of the 21st resistance adjustment circuit, ..., terminals CLK of the 2jth resistance adjustment circuit, ..., terminals CLK of the 2Nth resistance adjustment circuit, terminals CLK of the 31st resistance adjustment circuit, ..., terminals CLK of the 3kth resistance adjustment circuit, ..., terminals CLK of the 3lth resistance adjustment circuit and terminals V of the matrix multiplication circuit. CLK2 Connect them separately.

[0019] Terminals W0 of the 11th resistance adjustment circuit, ..., terminals W0 of the 1jth resistance adjustment circuit, ..., terminals W0 of the 1Nth resistance adjustment circuit, terminals W0 of the 21st resistance adjustment circuit, ..., terminals W0 of the 2jth resistance adjustment circuit, ..., terminals W0 of the 2Nth resistance adjustment circuit, and terminals V of the matrix multiplication circuit.W0 Connect the terminals W0, ..., W0, ..., W0 of the 31st resistance adjustment circuit, the 3k resistance adjustment circuit, and the 3L resistance adjustment circuit to the terminal S1 of the matrix switch circuit respectively. Connect the terminals W0, ..., W0, ..., W0 of the 31st resistance adjustment circuit, the 3k resistance adjustment circuit, and the 3L resistance adjustment circuit to the terminal R0 of the matrix resistor respectively.

[0020] Terminal W of the 11th resistance adjustment circuit REF Terminal W of the first j-th resistance adjustment circuit REF Terminal W of the 1N resistance adjustment circuit REF Terminal W of the 21st resistance adjustment circuit REF Terminal W of the second resistance adjustment circuit REF Terminal W of the 2Nth resistance adjustment circuit REF Terminal W of the 31st resistance adjustment circuit REF Terminal W of the 3k resistance adjustment circuit REF ...Terminal W of the 3L resistance adjustment circuit REF Terminal V of the matrix multiplication circuit WREF Connect them separately.

[0021] Terminals W1 of the 11th resistance adjustment circuit, ..., terminals W1 of the 1jth resistance adjustment circuit, ..., terminals W1 of the 1Nth resistance adjustment circuit, terminals W1 of the 21st resistance adjustment circuit, ..., terminals W1 of the 2jth resistance adjustment circuit, ..., terminals W1 of the 2Nth resistance adjustment circuit, terminals W1 of the 31st resistance adjustment circuit, ..., terminals W1 of the 3kth resistance adjustment circuit, ..., terminals W1 of the 3Lth resistance adjustment circuit and terminals V of the matrix multiplication operation circuit. W1 Connect them separately.

[0022] Terminal W of the 11th resistance adjustment circuit IN Terminal V of the matrix multiplication circuit WA1 Connect the terminals W of the first j-th resistance adjustment circuit. IN Terminal V of the matrix multiplication circuit WA j connects to, ..., the terminal W of the 1Nth resistance adjustment circuit. IN Terminal V of the matrix multiplication circuit WAN Connection; Terminal W of the 21st resistance adjustment circuit IN Terminal V of the matrix multiplication circuit WB1 Connect, ..., to terminal W of the second resistance adjustment circuit. IN Terminal V of the matrix multiplication circuit WBj Connect to terminal W of the 2Nth resistance adjustment circuit.IN Terminal V of the matrix multiplication circuit WBN Connection; Terminal W of the 31st resistance adjustment circuit IN Terminal O of the first secondary operational circuit BOUT Connect the terminals W of the 3k resistance adjustment circuit. IN Terminal O of the k-th second-level operational circuit BOUT Connection, ..., terminal W in the 3L resistance adjustment circuit IN Terminal O of the Lth secondary operational circuit BOUT connect.

[0023] Terminal A of the matrix element storage module W1 Terminal W of the 11th resistance adjustment circuit OUT Connection, ..., terminal A of the matrix element storage module Wj Terminal W of the first j-th resistance adjustment circuit OUT Connection, ..., terminal A of the matrix element storage module WN Terminal W of the 1N resistance adjustment circuit OUT Connection; Terminal A of the matrix element storage module D1 Terminal D of the first sampling delay circuit OUT Connection, ..., terminal A of the matrix element storage module Di Terminal D of the i-th sampling delay circuit OUT Connection, ..., terminal A of the matrix element storage module DM Terminal D of the Mth sampling delay circuit OUT Connection; Terminal A of the matrix element storage module OUT1 Terminal O of the first-stage operational circuit AIN Connection, ..., terminal A of the matrix element storage module OUTj Terminal O of the j-th stage operational circuit AIN Connection, ..., terminal A of the matrix element storage module OUTN Terminal O of the Nth stage operational circuit AIN Connection; Terminal A of the matrix element storage module WS1 A WSi A WSM Terminal V of the matrix multiplication circuit AWS1 ... V AWSi ... V AWSM Corresponding connections; terminals A1 and A of the matrix element storage module. S1 A RES A S2 Terminal V of the matrix multiplication circuit A1 V S1 V RES V S2Corresponding connection.

[0024] Terminal O of the first-stage operational circuit ASTD Terminal O of the j-th level operational circuit ASTD Terminal O of the Nth level operational circuit ASTD The terminals V of the matrix multiplication circuit are respectively connected to the terminals V. ASTD Connection; Terminal O of the first-stage operational circuit AOUT Terminal B of the matrix element storage and operation module IN1 Connect to, ..., the terminal O of the j-th level operational circuit. AOUT Terminal B of the matrix element storage and operation module INj Terminal O of the Nth level operational circuit AOUT Terminal B of the matrix element storage and operation module INN connect.

[0025] Terminal B of the matrix element storage and operation module W1 Terminal W of the 21st resistance adjustment circuit OUT Terminal B of the matrix element storage and operation module is connected to... Wj Terminal W of the second resistance adjustment circuit OUT Terminal B of the matrix element storage and operation module is connected to... WN Terminal W of the 2N resistance adjustment circuit OUT Connection; Terminal B of the matrix element storage and operation module OUT11 B OUT12 Terminal O of the first secondary operational circuit BIN1 O BIN2 Corresponding connection, ..., terminal B of the matrix element storage and operation module. OUTk1 B OUTk2 Terminal O of the k-th second-level operational circuit BIN1 O BIN2 Corresponding connection, ..., terminal B of the matrix element storage and operation module. OUTL1 B OUTL2 Terminal O of the Lth secondary operational circuit BIN1 O BIN2 Connection; Terminal B of the matrix element storage and operation module S1 Terminal V of the matrix multiplication circuit S1 Corresponding connection.

[0026] Terminal O of the first-level operational circuit BRES O BSTD O BS1 O BS2 O BSEL1 O BSEL2 Terminal V of the matrix multiplication circuitRES V BSTD V S1 V S2 V BS11 V BS12 Corresponding connections, ..., terminals O of the kth second-level operational circuit BRES O BSTD O BS1 O BS2 O BSEL1 O BSEL2 Terminal V of the matrix multiplication circuit RES V BSTD V S1 V S2 V BSk1 V BSk2 Corresponding connections, ..., terminals O of the Lth secondary operational circuit BRES O BSTD O BS1 O BS2 O BSEL1 O BSEL2 Terminal V of the matrix multiplication circuit RES V BSTD V S1 V S2 V BSL1 V BSL2 Corresponding connection.

[0027] Terminal C of the matrix operation result storage module D1 Terminal D of the first sampling delay circuit OUT Connect to terminal C of the matrix operation result storage module. Di Terminal D of the i-th sampling delay circuit OUT Connect to terminal C of the matrix operation result storage module. DM Terminal D of the Mth sampling delay circuit OUT Connection; Terminal C of the matrix operation result storage module W1 Terminal W of the 31st resistance adjustment circuit OUT Connect to terminal C of the matrix operation result storage module. Wk Terminal W of the 3k resistance adjustment circuit OUT Connect to terminal C of the matrix operation result storage module. WL Terminal W of the 3L resistance adjustment circuit OUT Connection; Terminal C of the matrix operation result storage module S1 Terminal V of the matrix multiplication circuit CS1 Terminal C of the module for connecting and storing matrix operation results S2 Terminal V of the matrix multiplication circuit S2Terminal C of the module for connecting and storing matrix operation results RES Terminal V of the matrix multiplication circuit RES connect.

[0028] The matrix resistor terminal R1 is connected to GND; the matrix switch circuit terminal S0 is connected to the matrix multiplication operation circuit terminal V. s0 Connect the SEL terminal of the matrix switching circuit to the V terminal of the matrix multiplication operation circuit. CLK1 connect.

[0029] The M sampling delay circuits in the matrix multiplication operation circuit are identical; each sampling delay circuit includes a first operational amplifier, a sampling delay NMOS transistor, a second operational amplifier, a sampling delay PMOS transistor, a third operational amplifier, a second sampling delay resistor, a first sampling delay resistor, a second capacitor, and a first capacitor.

[0030] Terminal F of the first operational amplifier + Terminal D of the sampling delay circuit IN Connection, terminal F of the first operational amplifier O The sampling delay NMOS transistor's drain and the first operational amplifier's terminal F are respectively connected to the sampling delay NMOS transistor's drain. - Connections: The gates of the sampling delay NMOS transistor and the sampling delay PMOS transistor are connected to the terminal CLK of the sampling delay circuit, respectively. The source of the sampling delay NMOS transistor is connected to the terminal C0 of the first capacitor and the terminal F of the second operational amplifier, respectively. + Connection; Terminal F of the second operational amplifier O The sampling delay PMOS transistor source and the second operational amplifier terminal F are respectively connected to the sampling delay PMOS transistor source and terminal F. - Connections: The drain of the sampling delay PMOS transistor is connected to terminal C0 of the second capacitor and terminal D of the sampling delay circuit, respectively. N and the terminal F of the third operational amplifier + Connection; Terminal F of the third operational amplifier - The terminal R0 of the first sampling delay resistor and the terminal R0 of the second sampling delay resistor are connected respectively, and the terminal F of the third operational amplifier is connected to... O The terminals R1 of the second sampling delay resistor and D of the sampling delay circuit are connected respectively. OUT Connections: Terminal C1 of the first capacitor, terminal C1 of the second capacitor, and terminal R1 of the first sampling delay resistor are connected to GND respectively.

[0031] The matrix multiplication operation circuit has 2N+L identical resistance adjustment circuits; each resistance adjustment circuit includes a first counter, a D flip-flop, a fourth operational amplifier, a resistance adjustment NMOS transistor, a resistance adjustment PMOS transistor, a resistance adjustment logic NOT gate, a second counter, and an analog-to-digital converter.

[0032] The terminals CLK of the first counter, CLK of the second counter, and CLK of the analog-to-digital converter are connected to the terminal CLK of the resistance adjustment circuit. The terminals MAX / MIN of the first counter are connected to the terminals CTEN of the first counter, CLK of the D flip-flop, and LOAD of the second counter. The terminal LOAD of the first counter is connected to the terminals D / U of the second counter, D of the D flip-flop, and W0 of the resistance adjustment circuit. The terminals D / U, A0, ..., A of the first counter are connected to the terminals A0, A0, ..., A0 of the second counter. i A1, A2, ..., A7 are connected to GND respectively; the terminal Q of the D flip-flop... + With terminal F of the 4th operational amplifier - Connect the Q terminal of the D flip-flop. - The terminal CTEN of the second counter is connected, and the terminal R of the D flip-flop is connected to the terminal N of the resistance-adjusting NOT gate. OUT Connection; Terminal F of the 4th operational amplifier O With terminal F of the 4th operational amplifier + The drain of the resistance-adjustable NMOS transistor is connected to the source of the resistance-adjustable PMOS transistor and the terminal W of the resistance adjustment circuit. OUT The gates of the resistance-adjusting NMOS transistor and the PMOS transistor, and the terminal W1 of the resistance adjustment circuit are connected respectively; the drain of the resistance-adjusting PMOS transistor is connected to GND; the terminal N of the resistance-adjusting NOT gate is connected respectively. IN Connect to the MAX / MIN terminals of the second counter; the terminals A0, ..., A of the second counter are... i ..., A7 and the terminals D0, ..., D of the analog-to-digital converter i ... D7 corresponds to the connection; the analog-to-digital converter terminal V ADIN Terminal W of the resistance adjustment circuit IN Connection, terminal V of the analog-to-digital converter ADREF Terminal W of the resistance adjustment circuit REF connect.

[0033] The matrix element storage module in the matrix multiplication operation circuit includes 2×M element storage NMOS transistors, M+1 element storage gates, 2×N storage switch circuits, element storage logic NOT gates, and M×N element storage memristors.

[0034] The gate of the 11th element storage NMOS transistor, ..., the gate of the 1ith element storage NMOS transistor, ..., the gate of the 1Mth element storage NMOS transistor and terminal A of the matrix element storage module. D1 A Di A DMCorrespondingly, the drains of the 11th element storage NMOS transistor, ..., the drains of the 1i element storage NMOS transistor, ..., the drains of the 1M element storage NMOS transistor are connected to terminal A1 of the matrix element storage module. The sources of the 11th element storage NMOS transistor, ..., the sources of the 1i element storage NMOS transistor, ..., the sources of the 1M element storage NMOS transistor are connected to terminals 0_CHAN of the 11th element storage selector, ..., the 0_CHAN of the 1i element storage selector, ..., the 0_CHAN of the 1M element storage selector.

[0035] The gates of the 21st element storage NMOS transistor, ..., the gates of the 2i element storage NMOS transistors, ..., the gates of the 2M element storage NMOS transistors, and terminal A of the matrix element storage module. WS1 A WSi A WSM Correspondingly, the sources of the 21st element storage NMOS transistor, ..., the 2i element storage NMOS transistor, ..., and the 2M element storage NMOS transistor are connected to the OUT terminal of the 2nd element storage selector, respectively. The drains of the 21st element storage NMOS transistor, ..., the 2i element storage NMOS transistor, ..., and the 2M element storage NMOS transistor are connected to the 1_CHAN terminals of the 11th element storage selector, ..., the 1_CHAN terminals of the 1i element storage selector, ..., and the 1_CHAN terminal of the 1M element storage selector.

[0036] Terminals SEL of the 11th element storage selector, ..., terminals SEL of the 1ith element storage selector, ..., terminals SEL of the 1Mth element storage selector, terminals SEL of the 11th storage switch circuit, ..., terminals SEL of the 1jth storage switch circuit, ..., terminals SEL of the Nth storage switch circuit, and terminal N of the element storage NOT gate. IN Terminal A of the matrix element storage module respectively S1 Connections; the N elements in the first row store the terminals R of the memristor. M1 Connect to the OUT terminal of the 11th element memory selector, ..., the R terminal of the N element memory resistors in the i-th row. M1 The terminals R of the N elements in the M-th row are respectively connected to the OUT terminal of the 1i-th element memory selector, ..., the N-th element memory memristor. M1 Connect to the OUT terminal of the 1M element storage gate respectively.

[0037] Terminal 1_CHAN of the second element storage selector is connected to GND, and terminal 0_CHAN of the second element storage selector is connected to terminal A of the matrix element storage module. RESConnect the second element storage selector's terminal SEL to the matrix element storage module's terminal A. S2 connect.

[0038] Terminals S1 of the 11th storage switch circuit, ..., terminals S1 of the 1jth storage switch circuit, ..., terminals S1 of the 1Nth storage switch circuit, and terminal A of the matrix element storage module. W1 A Wj A WN Corresponding connections are made between terminals S0 of the 21st storage switch circuit, ..., terminals S0 of the 2jth storage switch circuit, ..., terminals S0 of the 2Nth storage switch circuit and terminal A of the matrix element storage module. OUT1 A OUTj A OUTN Correspondingly, the terminals SEL of the 21st storage switch circuit, ..., the terminals SEL of the 2jth storage switch circuit, ..., the terminals SEL of the 2Nth storage switch circuit are respectively connected to the terminal N of the element storage logic NOT gate. OUT connect.

[0039] The M elements in column 1 store the terminals R of the memristor. M0 The terminals S0 of the 11th storage switch circuit and R of the M elements in the 1st column of the memory resistor are respectively connected to the terminals of the memory resistor. M0 The terminals S1, ..., R of the M elements in the j-th column of the memory resistor are respectively connected to the terminals of the 21st memory switch circuit. M0 The terminals S0 of the 1j-th storage switch circuit and R of the M elements in the j-th column storing memristors are respectively connected. M0 The terminals S1, ..., R of the M elements in the Nth column of the memory resistor are respectively connected to the terminals of the 2jth storage switch circuit. M0 The terminals S0 of the 1Nth storage switch circuit and the terminals R of the M elements in the Nth column storing memristors are respectively connected. M0 They are respectively connected to terminal S1 of the 2Nth storage switch circuit.

[0040] The matrix multiplication circuit has N identical first-level operation circuits; each first-level operation circuit includes a first-level operation resistor, a second-level operation resistor, a fourth-level operation resistor, a sixth operational amplifier, a sixth-level operation resistor, a third-level operation resistor, a fifth operational amplifier, and a fifth-level operation resistor.

[0041] Terminal F of the 5th operational amplifier - Terminal O of the first-level operational circuit AIN Connect to the terminal R0 of the first stage operational resistor, and the terminal F of the fifth operational amplifier. + Connect to terminal R0 of the fifth operational resistor, and terminal F of the fifth operational amplifier.O The first-stage operational resistor is connected to terminal R1 and the third-stage operational resistor to terminal R0 respectively; the second-stage operational resistor to terminal O is connected to terminal O of the first-stage operational circuit. ASTD Connect the terminals R1 of the second-stage operational resistor to R1 of the third-stage operational resistor, R0 of the fourth-stage operational resistor, and F of the sixth operational amplifier. - Connect them separately; Terminal F of the 6th operational amplifier + Connect to terminal R0 of the sixth stage operational resistor, and terminal F of the sixth operational amplifier. O The terminal R1 of the fourth stage operational resistor and the terminal O of the first stage operational circuit. AOUT Connect them separately; connect the terminals R1 of the fifth and sixth operational resistors to GND respectively.

[0042] The matrix element storage and operation module in the matrix multiplication operation circuit includes 2×N operation switch circuits, operation logic NOT gates, and N×L×2 operation memristors.

[0043] The terminals R of the 2×L operational memristors in the first row M0 Connect to terminal S1 of the 11th operational switch circuit, ..., and to terminal R of the 2×L operational memristors in the j-th row. M0 Connect to terminal S1 of the 1j operational switch circuit, ..., to terminal R of the 2×L operational memristors in the Nth row. M0 They are respectively connected to terminals S1 of the 1N operational switch circuit.

[0044] The terminals R of the 2×L operational memristors in the first row M0 Connect to terminal S0 of the 21st operational switch circuit, ..., and to terminal R of the 2×L operational memristors in the j-th row. M0 Connect to the terminals S0 of the 2jth operational switch circuit, ..., and to the terminals R of the 2×L operational memristors in the Nth row. M0 They are respectively connected to the terminal S0 of the 2Nth operational switch circuit.

[0045] Terminal S0 of the 11th operational switch circuit is connected to terminal B of the matrix element storage and operation module. IN1 Connect, ..., the terminal S0 of the first operational switch circuit to the terminal B of the matrix element storage and operation module. INj Connect, ..., the terminal S0 of the 1Nth operational switch circuit to the terminal B of the matrix element storage and operation module. INN The terminals SEL of the 11th operational switch circuit, ..., the terminals SEL of the 1jth operational switch circuit, ..., the terminals SEL of the 1Nth operational switch circuit are respectively connected to the terminal N of the operational logic NOT gate. OUT connect.

[0046] Terminal S1 of the 21st operational switch circuit is connected to terminal B of the matrix element storage and operation module. W1 Connect, ..., terminal S1 of the 2j operation switch circuit to terminal B of the matrix element storage and operation module. Wj Connect, ..., terminal S1 of the 2Nth operational switch circuit to terminal B of the matrix element storage and operation module. WN The terminals SEL of the 21st operational switch circuit, ..., the terminals SEL of the 2jth operational switch circuit, ..., the terminals SEL of the 2Nth operational switch circuit are respectively connected to the terminal N of the operational logic NOT gate. IN The terminals SEL of the 21st operational switch circuit, ..., the terminals SEL of the 2jth operational switch circuit, ..., the terminals SEL of the 2Nth operational switch circuit are respectively connected to the terminal B of the matrix element storage and operation module. S1 connect.

[0047] The terminals R of the N operational memristors in column 1 M1 Terminal B of the matrix element storage and operation module respectively OUT11 Connect the terminals R of the N operational memristors in column 2. M1 Terminal B of the matrix element storage and operation module respectively OUT12 Connect the terminals R of the N operational memristors in column 2×k-1, ... M1 Terminal B of the matrix element storage and operation module respectively OUTk1 Connect the terminals R of the N operational memristors in column 2×k. M1 Terminal B of the matrix element storage and operation module respectively OUTk2 Connect the terminals R of the N operational memristors in column 2×L-1, ... M1 Terminal B of the matrix element storage and operation module respectively OUTL1 Connect the terminals R of the N operational memristors in column 2×L. M1 Terminal B of the matrix element storage and operation module respectively OUTL2 connect.

[0048] The matrix multiplication circuit has L identical secondary operational circuits; each secondary operational circuit includes a secondary operational selector A, a secondary operational NMOS transistor A, a first secondary operational resistor, a seventh operational amplifier, a second secondary operational resistor, a fourth secondary operational resistor, a third secondary operational resistor, an eighth secondary operational resistor, a tenth secondary operational resistor, a tenth operational amplifier, an eleventh secondary operational resistor, a ninth secondary operational resistor, a ninth operational amplifier, a seventh secondary operational resistor, a sixth secondary operational resistor, an eighth operational amplifier, a fifth secondary operational resistor, a secondary operational selector C, a twelfth secondary operational resistor, a secondary operational NMOS transistor B, and a secondary operational selector B.

[0049] The terminal OUT of the second-level operational selector A is connected to the terminal O of the second-level operational circuit. BIN1 The terminals 1_CHAN of the second-stage operational selector A are connected to the drain of the second-stage operational NMOS transistor A, and the terminals 0_CHAN of the second-stage operational selector A are connected to the terminal F of the 7th operational amplifier. - The terminals R0 of the second-stage operational resistor are connected to the terminals SEL of the second-stage operational selector A and SEL of the second-stage operational selector B, and terminals O of the second-stage operational circuit. BS1 Connect them separately.

[0050] The gate of the secondary operational NMOS transistor A and the terminal O of the secondary operational circuit. BSEL1 The source of the second-level operational NMOS transistor A is connected to the source of the second-level operational NMOS transistor B and the OUT terminal of the second-level operational selector C, respectively.

[0051] Terminals R1 of the first, eighth, eleventh, and fifth operational resistors, and terminal 1_CHAN of the second operational selector C, are connected to GND.

[0052] Terminal F of the 7th operational amplifier + Connected to terminal R0 of the first secondary operational resistor, and terminal F of the seventh operational amplifier. O Connect to terminals R1 of the second-level operational resistor and R0 of the third-level operational resistor, respectively.

[0053] Terminal F of the 10th operational amplifier + Connect to terminal R0 of the 11th operational resistor, and terminal F of the 10th operational amplifier. - The terminal R1 of the third operational resistor, the terminal R0 of the tenth operational resistor, and the terminal F of the ninth operational resistor are connected respectively. o The terminals R1 of the 10th secondary operational resistor and O of the secondary operational circuit are connected. BOUTConnect them separately.

[0054] Terminal F of the 9th operational amplifier + Connect to terminal R0 of the 8th operational resistor, and terminal F of the 9th operational amplifier. - Connect to terminals R1 of the 6th second-stage operational resistor, R1 of the 12th second-stage operational resistor, and R0 of the 7th second-stage operational resistor, respectively. Terminal F of the 9th operational amplifier... O The terminal R1 of the 7th and 9th operational resistors is connected to the terminal B of the operational circuit. STD connect.

[0055] Terminal F of the 8th operational amplifier + Connect to terminal R0 of the fifth operational resistor, and terminal F of the eighth operational amplifier. - The terminal R0 of the fourth operational resistor and the terminal 0_CHAN of the second operational selector B are connected respectively, and the terminal F of the eighth operational amplifier is connected. O Connect to terminal R1 of the fourth secondary operational resistor and terminal R0 of the sixth secondary operational resistor, respectively.

[0056] The terminal SEL of the second-level operational selector C is connected to the terminal O of the second-level operational circuit. BS2 Connect terminal 0_CHAN of the secondary operational selector C to terminal B of the secondary operational circuit. RES connect.

[0057] The OUT terminal of the second-level operational selector B is connected to the O terminal of the second-level operational circuit. BIN2 The connection is as follows: Terminal 1_CHAN of the secondary operational selector B is connected to the drain of the secondary operational NMOS transistor B; the gate of the secondary operational NMOS transistor B is connected to terminal O of the secondary operational circuit. BSEL2 connect.

[0058] The matrix operation result storage module in the matrix multiplication circuit includes M×L result storage memristors, M×L result storage NMOS transistors, M result switching circuits, result storage logic NOT gates, and result storage selectors.

[0059] The M results in column 1 are stored at the terminals R of the memristor. M0 Terminal C of the matrix operation result storage module respectively W1 Connect the terminals R of the M results stored in the k-th column of the memristor. M0 Terminal C of the matrix operation result storage module respectively Wk Connect, ..., the terminal R of the Mth result storage memristor in column L. M0 Terminal C of the matrix operation result storage module respectively WLConnection; the M results in column 1 are stored at the terminal R of the memristor. M1 The terminals R of the M result storage memristors in the k-th column are connected to the drains of their respective result storage NMOS transistors, ... M1 Connected to the drain of their respective result storage NMOS transistors, ..., the terminals R of the M result storage memristors in the Lth column. M1 Connect to the drain of the corresponding result storage NMOS transistor.

[0060] The sources of the M×L result storage NMOS transistors are connected to the OUT terminal of the result storage selector, and the gates of the L result storage NMOS transistors in the first row are connected to the C terminal of the matrix operation result storage module. D1 The gates of the L result storage NMOS transistors in the i-th row are connected to the terminals C of the matrix operation result storage module, respectively. Di The gates of the L result storage NMOS transistors in the Mth row are connected to the terminals C of the matrix operation result storage module, respectively. DM Connections: The gates of the L result storage NMOS transistors in the first row are connected to the terminal S0 of the first result switching circuit, ..., the gates of the L result storage NMOS transistors in the i-th row are connected to the terminal S0 of the i-th result switching circuit, ..., the gates of the L result storage NMOS transistors in the M-th row are connected to the terminal S0 of the M-th result switching circuit.

[0061] Terminals S1 of the first result switching circuit, ..., terminals S1 of the i-th result switching circuit, ..., terminals S1 of the M-th result switching circuit are respectively connected to terminals C of the matrix operation result storage module. S1 The terminals SEL of the first result switching circuit, ..., the terminals SEL of the i-th result switching circuit, ..., the terminals SEL of the M-th result switching circuit are respectively connected to the terminal N of the result storage logic NOT gate. OUT connect.

[0062] The result is stored at the terminal N of the NOT gate. IN Terminal SEL of the result storage gating and terminal C of the matrix operation result storage module. S2 Connect them separately; connect terminal 1_CHAN of the result storage gantry to GND, and connect terminal 0_CHAN of the result storage gantry to terminal C of the matrix operation result storage module. RES connect.

[0063] The matrix switching circuit in the matrix multiplication operation circuit includes matrix switch NMOS transistor A and matrix switch NMOS transistor B.

[0064] The drain of matrix switch NMOS transistor A is connected to terminal S0 of matrix switch circuit; the source of matrix switch NMOS transistor A is connected to the source of matrix switch NMOS transistor B; the gate of matrix switch NMOS transistor A is connected to terminal SEL of matrix switch circuit and the gate of matrix switch NMOS transistor B respectively; the drain of matrix switch NMOS transistor B is connected to terminal S1 of matrix switch circuit.

[0065] The 2N storage switch circuits in the matrix element storage module, the 2N operation switch circuits in the matrix element storage and operation module, and the M result switch circuits in the matrix operation result storage module are all the same as the matrix switch circuits in the matrix multiplication operation circuit based on memristor array.

[0066] The first operational amplifier is any one of a general-purpose, high-speed, or low-power operational amplifier; the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth operational amplifiers are the same.

[0067] The M×N element storage memristors in the matrix element storage module, the N×L×2 operational memristors in the matrix element storage and operation module, and the M×L result storage memristors in the matrix operation result storage module are the same; all of the M×N element storage memristors in the matrix element storage module, the N×L×2 operational memristors in the matrix element storage and operation module, and the M×L result storage memristors in the matrix operation result storage module are memristors with threshold voltages.

[0068] The resistance values ​​of the second-level operational resistor, the third-level operational resistor, and the fourth-level operational resistor are the same.

[0069] The resistance values ​​of the second and fourth operational resistors are the same.

[0070] A method for using a matrix multiplication circuit based on a memristor array, comprising the following steps:

[0071] Step 1: Reset all memristors

[0072] At terminal V of the matrix multiplication circuit W1 V S2 A corresponding low-level voltage signal U is applied between the terminal GND and the terminal GND. W1 U S2 At terminal V of the matrix multiplication circuit S1 V RES V AWS1 ... V AWSi ... V AWSMV BS11 V BS12 ... V BSk1 V BSk2 ... V BSL1 V BSL2 V CS1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. S1 U RES U AWS1 ... U AWSi ... U AWSM U BS11 U BS12 ... U BSk1 U BSk2 ... U BSL1 U BSL2 U CS1 .

[0073] Step 2: Write data to the matrix element storage module

[0074] At terminal V of the matrix multiplication circuit W0 V W1 V S1 V S2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. W0 U W1 U S1 U S2 At terminal U of the matrix multiplication circuit WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF At terminal V of the matrix multiplication circuit CLK2 Apply a clock voltage signal U between the terminal GND and the terminal GND. CLK2 At terminal V of the matrix multiplication circuit AWS1 ... V AWSi ... V AWSM A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS1 ... U AWSi ... U AWSM At terminal V of the matrix multiplication circuit WA1 ... V WAj ... V WAN Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 ... U WAj ... U WAN .

[0075] Step 3: Write data to the matrix element storage and operation module

[0076] At terminal V of the matrix multiplication circuit W0 V W1 V S1 V S2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. W0 U W1 U S1 U S2 At terminal V of the matrix multiplication circuit WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF At terminal V of the matrix multiplication circuit CLK2 Apply a clock voltage signal U between the terminal GND and the terminal GND. CLLK2 At terminal V of the matrix multiplication circuit BS11 V BS12 ... V BSk1 V BSk2 ... V BSL1 V BSL2 A corresponding high-level voltage signal U is sequentially applied between the terminal GND and the terminal GND. BS11 U BS12 ... U BSk1 U BSk2 ... U BSL1 U BSL2 Meanwhile, at terminal V of the matrix multiplication circuit WB1 ... V WBj ... V WBN Apply a resistance-adjustable voltage signal U between the terminals GND and GND respectively. WB1 ... U WBj ... U WBN .

[0077] Step 4: Perform matrix multiplication.

[0078] At terminal V of the matrix multiplication circuit S1 A low-level voltage signal U is applied between the terminal GND and the terminal GND. S1 At terminal V of the matrix multiplication circuit S2 V S0 V W1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. S2 U S0 U W1 At terminal U of the matrix multiplication circuit WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF At terminal V of the matrix multiplication circuit A1 V ASTD V BSTD Apply the corresponding operational voltage signal U between the terminal GND and the terminal GND.A1 U ASTD U BSTD At terminal V of the matrix multiplication circuit CLK1 V CLK2 Apply the corresponding clock voltage signal U between the terminal GND and the terminal GND. CLK1 U CLK2 At terminal V of the matrix multiplication circuit DIN A pulse voltage signal U is applied between the terminal GND and the terminal GND. DIN .

[0079] By adopting the above technical solution, the present invention has the following positive effects:

[0080] In this invention, only the corresponding voltage signal needs to be input to reset each memristor array, and all memristors in the matrix multiplication circuit can be adjusted to a high-impedance state; only the voltage corresponding to the matrix element needs to be input into the resistance adjustment circuit, and in conjunction with the corresponding high-level voltage control signal, the elements in the matrix to be calculated can be saved into the memristor array. Therefore, this invention is simple to operate.

[0081] In this invention, the high-level voltage signal output by the sampling delay circuit enables the sequential selection of each row of element storage memristors in the matrix element storage module and the matrix operation result storage module. This causes the matrix element storage module to output the voltage corresponding to the conductance of the selected row element storage memristor. The voltage output by the matrix element storage module is then applied to each row of the memristor array in the matrix element storage and operation module. The matrix element storage and operation module then outputs the voltage of the corresponding vector-matrix multiplication result. This voltage is then stored in the element storage memristor of the selected row in the memristor array of the matrix operation result storage module through a resistance adjustment circuit. The process of data transmission between the memory and the arithmetic unit is eliminated during the calculation process. Data storage and operation are completed in the memristor array, thereby improving the speed of matrix multiplication.

[0082] In this invention, the difference between the conductances of two memristors is used to represent a corresponding matrix element in the matrix element storage and operation module. This expands the range of values ​​represented by the conductances of the memristors in the matrix element storage and operation module from positive numbers to positive, negative numbers and zero. Therefore, it is possible to perform matrix multiplication on any two real number matrices containing positive and negative elements.

[0083] Therefore, this invention is not only simple to operate and fast to calculate, but also capable of performing matrix multiplication on any two real number matrices containing positive and negative elements. Attached Figure Description

[0084] Figure 1 This is a schematic diagram of one structure of the present invention;

[0085] Figure 2 for Figure 1 A schematic diagram of a sampling delay circuit 101;

[0086] Figure 3 for Figure 1 A schematic diagram of a medium resistance adjustment circuit 102;

[0087] Figure 4 for Figure 1 A schematic diagram of a matrix element storage module 103;

[0088] Figure 5 for Figure 1 A schematic diagram of a single-level operational circuit 104;

[0089] Figure 6 for Figure 1 A schematic diagram of a matrix element storage and operation module 105;

[0090] Figure 7 for Figure 1 A schematic diagram of a two-level operational circuit 106;

[0091] Figure 8 for Figure 1 A schematic diagram of a matrix operation result storage module 107;

[0092] Figure 9 for Figure 1 A schematic diagram of a switching circuit 109. Detailed Implementation

[0093] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of protection thereof.

[0094] Example 1

[0095] A matrix multiplication circuit based on a memristor array and its usage method are disclosed. The matrix multiplication circuit based on the memristor array is simply referred to as a matrix multiplication circuit.

[0096] like Figure 1 As shown, the matrix multiplication operation circuit includes M sampling delay circuits 101, 2N+L resistance adjustment circuits 102, a matrix element storage module 103, N first-level operation circuits 104, a matrix element storage and operation module 105, L second-level operation circuits 106, a matrix operation result storage module 107, a matrix resistor 108, and a matrix switch circuit 109.

[0097] In the matrix multiplication circuit:

[0098] like Figure 1 As shown, the terminals CLK of the first sampling delay circuit 101, ..., the terminals CLK of the i-th sampling delay circuit 101, ..., the terminals CLK of the M-th sampling delay circuit 101 are connected to the terminal V of the matrix multiplication operation circuit. CLK1 Connect to terminals D of the first sampling delay circuit 101 respectively. N Terminal D of the second sampling delay circuit 101 IN Connect to terminal D of the (i-1)th sampling delay circuit 101. N Terminal D of the i-th sampling delay circuit 101 IN Connect to terminal D of the (M-1)th sampling delay circuit 101. N Terminal D of the Mth sampling delay circuit 101 IN Connection; Terminal D of the first sampling delay circuit 101 IN Terminal V of the matrix multiplication circuit DIN connect.

[0099] like Figure 1 As shown, the terminals CLK of the 11th resistance adjustment circuit 102, ..., the terminals CLK of the 1jth resistance adjustment circuit 102, ..., the terminals CLK of the 1Nth resistance adjustment circuit 102, the terminals CLK of the 21st resistance adjustment circuit 102, ..., the terminals CLK of the 2jth resistance adjustment circuit 102, ..., the terminals CLK of the 2Nth resistance adjustment circuit 102, the terminals CLK of the 31st resistance adjustment circuit 102, ..., the terminals CLK of the 3kth resistance adjustment circuit 102, ..., the terminals CLK of the 3lth resistance adjustment circuit 102 are connected to the terminal V of the matrix multiplication operation circuit. CLK2 Connect them separately.

[0100] like Figure 1 As shown, the terminals W0 of the 11th resistance adjustment circuit 102, ..., the 1jth resistance adjustment circuit 102, ..., the 1Nth resistance adjustment circuit 102, the 21st resistance adjustment circuit 102, ..., the 2jth resistance adjustment circuit 102, ..., the 2Nth resistance adjustment circuit 102 are connected to the terminal V of the matrix multiplication operation circuit. W0 The terminals W0, ..., W0, ..., W0 of the 31st resistance adjustment circuit 102, the 3k resistance adjustment circuit 102, and the 3L resistance adjustment circuit 102 are respectively connected to the terminal S1 of the matrix switch circuit 109. The terminals W0, ..., W0, ..., W0 of the 31st resistance adjustment circuit 102, the 3k resistance adjustment circuit 102, and the 3L resistance adjustment circuit 102 are respectively connected to the terminal R0 of the matrix resistor 108.

[0101] like Figure 1As shown, terminal W of the 11th resistance adjustment circuit 102 REF Terminal W of the first resistance adjustment circuit 102 REF Terminal W of the 1N resistance adjustment circuit 102 REF Terminal W of the 21st resistance adjustment circuit 102 REF ..., Terminal W of the second resistance adjustment circuit 102 REF Terminal W of the 2Nth resistance adjustment circuit 102 REF Terminal W of the 31st resistance adjustment circuit 102 REF ..., Terminal W of the 3k resistance adjustment circuit 102 REF ...Terminal W of the 3L resistance adjustment circuit 102 REF Terminal V of the matrix multiplication circuit WREF Connect them separately.

[0102] like Figure 1 As shown, the terminals W1 of the 11th resistance adjustment circuit 102, ..., the terminals W1 of the 1jth resistance adjustment circuit 102, ..., the terminals W1 of the 1Nth resistance adjustment circuit 102, the terminals W1 of the 21st resistance adjustment circuit 102, ..., the terminals W1 of the 2jth resistance adjustment circuit 102, ..., the terminals W1 of the 2Nth resistance adjustment circuit 102, the terminals W1 of the 31st resistance adjustment circuit 102, ..., the terminals W1 of the 3kth resistance adjustment circuit 102, ..., the terminals W1 of the 3Lth resistance adjustment circuit 102 are connected to the terminal V of the matrix multiplication operation circuit. W1 Connect them separately.

[0103] like Figure 1 As shown, terminal W of the 11th resistance adjustment circuit 102 IN Terminal V of the matrix multiplication circuit WA1 Connect to, ..., the terminal W of the first resistance adjustment circuit 102. IN Terminal V of the matrix multiplication circuit WAj Connect to terminal W of the 1N resistance adjustment circuit 102. IN Terminal V of the matrix multiplication circuit WAN Connection; Terminal W of the 21st resistance adjustment circuit 102 IN Terminal V of the matrix multiplication circuit WB1 Connect to, ..., the terminal W of the second resistance adjustment circuit 102. IN Terminal V of the matrix multiplication circuit WBj Connect to terminal W of the 2Nth resistance adjustment circuit 102. IN Terminal V of the matrix multiplication circuit WBN Connection; Terminal W of the 31st resistance adjustment circuit 102IN Terminal O of the first secondary operational circuit 106 BOUT Connect to terminal W of the 3k resistance adjustment circuit 102. IN Terminal O of the k-th second-level operational circuit 106 BOUT Connection, ..., terminal W in the 3L resistance adjustment circuit 102 IN Terminal O of the Lth secondary operational circuit 106 BOUT connect.

[0104] like Figure 1 As shown, terminal A of matrix element storage module 103 W1 Terminal W of the 11th resistance adjustment circuit 102 OUT Connection, ..., terminal A of matrix element storage module 103 Wj Terminal W of the first resistance adjustment circuit 102 OUT Connection, ..., terminal A of matrix element storage module 103 WN Terminal W of the first N resistance adjustment circuit 102 OUT Connection; Terminal A of matrix element storage module 103 D1 Terminal D of the first sampling delay circuit 101 OUT Connection, ..., terminal A of matrix element storage module 103 Di Terminal D of the i-th sampling delay circuit 101 OUT Connection, ..., terminal A of matrix element storage module 103 DM Terminal D of the Mth sampling delay circuit 101 OUT Connection; Terminal A of matrix element storage module 103 OUT1 Terminal O of the first-stage operational circuit 104 AIN Connection, ..., terminal A of matrix element storage module 103 OUTj Terminal O of the j-th stage operational circuit 104 AIN Connection, ..., terminal A of matrix element storage module 103 OUTN Terminal O of the Nth stage operational circuit 104 AIN Connection; Terminal A of matrix element storage module 103 WS1 A WSi A WSM Terminal V of the matrix multiplication circuit AWS1 ... V AWSi ... V AWSM Corresponding connection; terminals A1 and A2 of matrix element storage module 103 S1 A RES A S2 Terminal V of the matrix multiplication circuit A1 VS1 V RES V S2 Corresponding connection.

[0105] like Figure 1 As shown, the terminal O of the first-stage operational circuit 104 ASTD Terminal O of the j-th level operational circuit 104 ASTD Terminal O of the Nth level operational circuit 104 ASTD The terminals V of the matrix multiplication circuit are respectively connected to the terminals V. ASTD Connection; Terminal O of the first-stage operational circuit 104 AOUT Terminal B of the matrix element storage and operation module 105 IN1 Connect to, ..., terminal O of the j-th level operational circuit 104 AOUT Terminal B of the matrix element storage and operation module 105 INj Terminal O of the Nth level operational circuit 104 AOUT Terminal B of the matrix element storage and operation module 105 INN connect.

[0106] like Figure 1 As shown, terminal B of the matrix element storage and operation module 105 W1 Terminal W of the 21st resistance adjustment circuit 102 OUT Connect to terminal B of the matrix element storage and operation module 105. Wj Terminal W of the second resistance adjustment circuit 102 OUT Connect to terminal B of the matrix element storage and operation module 105. WN Terminal W of the 2N resistance adjustment circuit 102 OUT Connection; Terminal B of matrix element storage and operation module 105 OUT11 B OUT12 Terminal O of the first secondary operational circuit 106 BIN1 O BIN2 Corresponding connection, ..., terminal B of matrix element storage and operation module 105 OUTk1 B OUTk2 Terminal O of the k-th second-level operational circuit 106 BIN1 O BIN2 Corresponding connection, ..., terminal B of matrix element storage and operation module 105 OUTL1 B OUTL2 Terminal O of the Lth secondary operational circuit 106 BIN1 O BIN2 Connection; Terminal B of matrix element storage and operation module 105 S1 Terminal V of the matrix multiplication circuit S1 Corresponding connection.

[0107] like Figure 1 As shown, terminal O of the first secondary operational circuit 106 BRES O BSTD O BS1 O BS2 O BSEL1 O BSEL2 Terminal V of the matrix multiplication circuit RES V BSTD V S1 V S2 V BS11 V BS12 Corresponding connections, ..., terminal O of the kth second-level operational circuit 106 BRES O BSTD O BS1 O BS2 O BSEL1 O BSEL2 Terminal V of the matrix multiplication circuit RES V BSTD V S1 V S2 V BSk1 V BSk2 Corresponding connection, ..., terminal O of the Lth secondary operational circuit 106 BRES O BSTD O BS1 O BS2 O BSEL1 O BSEL2 Terminal V of the matrix multiplication circuit RES V BSTD V S1 V S2 V BSL1 V BSL2 Corresponding connection.

[0108] like Figure 1 As shown, terminal C of the matrix operation result storage module 107 D1 Terminal D of the first sampling delay circuit 101 OUT Connect to terminal C of matrix operation result storage module 107. Di Terminal D of the i-th sampling delay circuit 101 OUT Connect to terminal C of matrix operation result storage module 107. DM Terminal D of the Mth sampling delay circuit 101 OUT Connection; Terminal C of matrix operation result storage module 107 W1 Terminal W of the 31st resistance adjustment circuit 102 OUT Connect to terminal C of matrix operation result storage module 107.Wk Terminal W of the 3k resistance adjustment circuit 102 OUT Connect to terminal C of matrix operation result storage module 107. WL Terminal W of the 3L resistance adjustment circuit 102 OUT Connection; Terminal C of matrix operation result storage module 107 S1 Terminal V of the matrix multiplication circuit CS1 Terminal C of the matrix operation result storage module 107 is connected. S2 Terminal V of the matrix multiplication circuit S2 Terminal C of the matrix operation result storage module 107 is connected. RES Terminal V of the matrix multiplication circuit RES connect.

[0109] like Figure 1 As shown, terminal R1 of matrix resistor 108 is connected to GND; terminal S0 of matrix switch circuit 109 is connected to terminal V of matrix multiplication circuit. s0 Connect the terminal SEL of the matrix switch circuit 109 to the terminal V of the matrix multiplication operation circuit. CLK1 connect.

[0110] like Figure 2 As shown, the M sampling delay circuits 101 in the matrix multiplication operation circuit are identical; each sampling delay circuit 101 includes a first operational amplifier 201, a sampling delay NMOS transistor 202, a second operational amplifier 203, a sampling delay PMOS transistor 204, a third operational amplifier 205, a second sampling delay resistor 206, a first sampling delay resistor 207, a second capacitor 208, and a first capacitor 209.

[0111] like Figure 2 As shown, terminal F of the first operational amplifier 201 + Terminal D of sampling delay circuit 101 IN Connection, terminal F of the first operational amplifier 201 O The sampling delay NMOS transistor 202 and the terminal F of the first operational amplifier 201 are respectively connected to the drain of the sampling delay NMOS transistor 202. - Connections: The gates of the sampling delay NMOS transistor 202 and the sampling delay PMOS transistor 204 are connected to the terminal CLK of the sampling delay circuit 101, respectively. The source of the sampling delay NMOS transistor 202 is connected to the terminal C0 of the first capacitor 209 and the terminal F of the second operational amplifier 203, respectively. + Connection; Terminal F of the second operational amplifier 203 O The sampling delay PMOS transistor 204 and the terminal F of the second operational amplifier 203 are respectively connected to the source of the sampling delay PMOS transistor 204. -Connections; the drain of the sampling delay PMOS transistor 204 is connected to terminal C0 of the second capacitor 208 and terminal D of the sampling delay circuit 101, respectively. N and the terminal F of the third operational amplifier 205 + Connection; Terminal F of the third operational amplifier 205 - The terminal R0 of the first sampling delay resistor 207 and the terminal R0 of the second sampling delay resistor 206 are respectively connected to the terminal F of the third operational amplifier 205. O The terminals R1 of the second sampling delay resistor 206 and D of the sampling delay circuit 101 are connected respectively. OUT Connections: Terminal C1 of the first capacitor 209, terminal C1 of the second capacitor 208, and terminal R1 of the first sampling delay resistor 207 are respectively connected to GND.

[0112] like Figure 3 As shown, the 2N+L resistance adjustment circuits 102 in the matrix multiplication operation circuit are identical; each resistance adjustment circuit 102 includes a first counter 301, a D flip-flop 302, a fourth operational amplifier 303, a resistance adjustment NMOS transistor 304, a resistance adjustment PMOS transistor 305, a resistance adjustment logic NOT gate 306, a second counter 307, and an analog-to-digital converter 308.

[0113] like Figure 3 As shown, the terminals CLK of the first counter 301, CLK of the second counter 307, and CLK of the analog-to-digital converter 308 are connected to the terminal CLK of the resistance adjustment circuit 102. The terminals MAX / MIN of the first counter 301 are connected to the terminals CTEN of the first counter 301, CLK of the D flip-flop 302, and LOAD of the second counter 307. The terminal LOAD of the first counter 301 is connected to the terminals D / U of the second counter 307, D of the D flip-flop 302, and W0 of the resistance adjustment circuit 102. The terminals D / U, A0, ..., A of the first counter 301 are connected to the terminals A0, A0, ..., A0 of the second counter 301. i A7, ..., are connected to GND respectively; terminal Q of D flip-flop 302 + Terminal F of the fourth operational amplifier 303 - Connect the terminal Q of the D flip-flop 302. - The terminal CTEN of the second counter 307 is connected to the terminal R of the D flip-flop 302 and the terminal N of the resistance-adjusting NOT gate 306. OUT Connection; Terminal F of the fourth operational amplifier 303 O Terminal F of the fourth operational amplifier 303 +The drain of the resistance-adjustable NMOS transistor 304 is connected to the source of the resistance-adjustable PMOS transistor 305 and the terminal W of the resistance adjustment circuit 102. OUT The gates of the resistance-adjusting NMOS transistor 304 and the PMOS transistor 305, and the terminal W1 of the resistance adjustment circuit 102 are connected respectively; the drain of the PMOS transistor 305 is connected to GND; the terminal N of the resistance-adjusting NOT gate 306 is connected to... IN Connect to terminals MAX / MIN of the second counter 307; terminals A0, ..., A of the second counter 307. i ..., A7 and terminals D0, ..., D of analog-to-digital converter 308 i ... D7 corresponds to the connection; terminal V of analog-to-digital converter 308 ADIN Terminal W of the resistance adjustment circuit 102 IN Connect to terminal V of analog-to-digital converter 308 ADREF Terminal W of the resistance adjustment circuit 102 REF connect.

[0114] like Figure 4 As shown, the matrix element storage module 103 in the matrix multiplication operation circuit includes 2×M element storage NMOS transistors 401, M+1 element storage selectors 402, 2×N storage switch circuits 403, element storage logic NOT gates 404, and M×N element storage memristors 405.

[0115] like Figure 4 As shown, the gates of the 11th element storage NMOS transistor 401, ..., the 1ith element storage NMOS transistor 401, ..., the 1Mth element storage NMOS transistor 401 are connected to terminal A of the matrix element storage module 103. D1 A Di A DM Correspondingly, the drains of the 11th element storage NMOS transistor 401, ..., the drains of the 1i element storage NMOS transistor 401, ..., the drains of the 1M element storage NMOS transistor 401 are connected to terminal A1 of the matrix element storage module 103, respectively. The sources of the 11th element storage NMOS transistor 401, ..., the sources of the 1i element storage NMOS transistor 401, ..., the sources of the 1M element storage NMOS transistor 401 are correspondingly connected to terminals 0_CHAN of the 11th element storage selector 402, ..., the 0_CHAN of the 1i element storage selector 402, ..., the 0_CHAN of the 1M element storage selector 402.

[0116] like Figure 4As shown, the gates of the 21st element storage NMOS transistor 401, ..., the 2i element storage NMOS transistor 401, ..., the 2M element storage NMOS transistor 401 are connected to terminal A of the matrix element storage module 103. WS1 A WSi A WSM Correspondingly, the source of the 21st element storage NMOS transistor 401, ..., the source of the 2i element storage NMOS transistor 401, ..., the source of the 2M element storage NMOS transistor 401 are respectively connected to the OUT terminal of the 2nd element storage selector 402. The drain of the 21st element storage NMOS transistor 401, ..., the drain of the 2i element storage NMOS transistor 401, ..., the drain of the 2M element storage NMOS transistor 401 are correspondingly connected to the 1_CHAN terminal of the 11th element storage selector 402, ..., the 1_CHAN terminal of the 1i element storage selector 402, ..., the 1_CHAN terminal of the 1M element storage selector 402.

[0117] like Figure 4 As shown, the terminals SEL of the 11th element storage selector 402, ..., the terminals SEL of the 1ith element storage selector 402, ..., the terminals SEL of the 1Mth element storage selector 402, the terminals SEL of the 11th storage switch circuit 403, ..., the terminals SEL of the 1jth storage switch circuit 403, ..., the terminals SEL of the 1Nth storage switch circuit 403, and the terminal N of the element storage logic NOT gate 404 are shown. IN Terminal A of matrix element storage module 103 respectively S1 Connections; the N elements in the first row store the terminals R of the memristor 405. M1 The terminals R of the N-element memory memory resistors 405 in the i-th row are respectively connected to the OUT terminal of the 11th element memory selector 402, ..., respectively. M1 The terminals R of the N-th element memory memory resistor 405 in the M-th row are respectively connected to the OUT terminal of the 1i-th element memory selector 402, ..., respectively. M1 Each is connected to the OUT terminal of the 1M element storage selector 402.

[0118] like Figure 4 As shown, terminal 1_CHAN of the second element storage selector 402 is connected to GND, and terminal 0_CHAN of the second element storage selector 402 is connected to terminal A of the matrix element storage module 103. RES The connection is made between terminal SEL of the second element storage selector 402 and terminal A of the matrix element storage module 103. S2 connect.

[0119] like Figure 4As shown, the terminals S1 of the 11th storage switch circuit 403, ..., the terminals S1 of the 1jth storage switch circuit 403, ..., the terminals S1 of the 1Nth storage switch circuit 403 are connected to the terminal A of the matrix element storage module 103. W1 A Wj A WN Corresponding connections are made between terminals S0 of the 21st storage switch circuit 403, ..., terminals S0 of the 2jth storage switch circuit 403, ..., terminals S0 of the 2Nth storage switch circuit 403 and terminal A of the matrix element storage module 103. OUT1 A OUTj A OUTN Correspondingly, the terminals SEL of the 21st storage switch circuit 403, ..., the terminals SEL of the 2jth storage switch circuit 403, ..., the terminals SEL of the 2Nth storage switch circuit 403 are respectively connected to the terminal N of the element storage logic NOT gate 404. OUT connect.

[0120] like Figure 4 As shown, the M elements in the first column store the terminals R of the memristor 405. M0 The terminals S0 of the 11th storage switch circuit 403 and R of the M elements of the first column storage memristor 405 are respectively connected to the terminal S0 of the first storage switch circuit 403. M0 The terminals S1, ..., R of the M elements of the j-th column memory resistor 405 are respectively connected to the terminal S1 of the 21st storage switch circuit 403. M0 The terminals S0 of the first j-th storage switch circuit 403 and R of the M elements of the j-th column storage memristor 405 are respectively connected to the terminal S0 of the first j-th storage switch circuit 403. M0 The terminals S1 of the second-j storage switch circuit 403, ..., and R of the M elements of the Nth column storage memristor 405 are respectively connected to the terminals S1, ... M0 The terminals S0 of the 1Nth storage switch circuit 403 and R of the M elements of the Nth column storage memristor 405 are respectively connected to the terminals of the memory switch circuit 403. M0 They are respectively connected to terminals S1 of the 2Nth storage switch circuit 403.

[0121] like Figure 5 As shown, the N first-level operation circuits 104 in the matrix multiplication operation circuit are identical; each first-level operation circuit 104 includes a first-level operation resistor 501, a second-level operation resistor 502, a fourth-level operation resistor 503, a sixth-level operation amplifier 504, a sixth-level operation resistor 505, a third-level operation resistor 506, a fifth-level operation amplifier 507, and a fifth-level operation resistor 508.

[0122] like Figure 5 As shown, terminal F of the fifth operational amplifier 507 - Terminal O of the first-level operational circuit 104AIN The terminal R0 of the first-stage operational resistor 501 is connected to the terminal F of the fifth operational amplifier 507. + The terminal R0 of the fifth operational resistor 508 is connected to the terminal F of the fifth operational amplifier 507. O The first-stage operational resistor 501 is connected to terminal R1, and the third-stage operational resistor 506 is connected to terminal R0; the second-stage operational resistor 502 is connected to terminal O of the first-stage operational circuit 104. ASTD Connect the terminals R1 of the second-stage operational resistor 502 to R1 of the third-stage operational resistor 506, R0 of the fourth-stage operational resistor 503, and F of the sixth operational amplifier 504. - Connect to terminals F of operational amplifier 504 respectively. + The terminal R0 of the sixth operational resistor 505 is connected to the terminal F of the sixth operational amplifier 504. O Terminal R1 of the fourth operational resistor 503 and terminal O of the first operational circuit 104 AOUT Connect them separately; connect the terminals R1 of the fifth operational resistor 508 and the sixth operational resistor 505 to GND respectively.

[0123] like Figure 6 As shown, the matrix element storage and operation module 105 in the matrix multiplication operation circuit includes 2×N operation switch circuits 601, operation logic NOT gates 602, and N×L×2 operation memristors 603.

[0124] like Figure 6 As shown, the terminals R of the 2×L operational memristors 603 in the first row M0 Connected to terminal S1 of the 11th operational switch circuit 601, ..., and terminal R of the 2×L operational memristors 603 in the j-th row. M0 The terminals S1 of the first operational switch circuit 601, ..., and R of the 2×L operational memristors 603 in the Nth row are respectively connected to the terminals S1 of the first operational switch circuit 601, ... M0 They are respectively connected to terminals S1 of the 1N operational switch circuit 601.

[0125] like Figure 6 As shown, the terminals R of the 2×L operational memristors 603 in the first row M0 The terminals S0 of the 21st operational switch circuit 601, ..., and R of the 2×L operational memristors 603 in the j-th row are respectively connected to the terminals S0 of the 21st operational switch circuit 601. M0 The terminals S0 of the 2jth operational switch circuit 601, ..., and the terminals R of the 2×L operational memristors 603 in the Nth row are respectively connected to the terminals S0 of the 2jth operational switch circuit 601. M0 They are respectively connected to terminals S0 of the 2N operational switch circuit 601.

[0126] like Figure 6 As shown, terminal S0 of the 11th operational switch circuit 601 is connected to terminal B of the matrix element storage and operation module 105. IN1 Connect, ..., terminal S0 of the first operational switch circuit 601 to terminal B of the matrix element storage and operation module 105. INj Connect, ..., terminal S0 of the 1Nth operational switch circuit 601 to terminal B of the matrix element storage and operation module 105. INN The terminals SEL of the 11th operational switch circuit 601, ..., the terminals SEL of the 1jth operational switch circuit 601, ..., the terminals SEL of the 1Nth operational switch circuit 601 are respectively connected to the terminal N of the operational logic NOT gate 602. OUT connect.

[0127] like Figure 6 As shown, terminal S1 of the 21st operational switch circuit 601 is connected to terminal B of the matrix element storage and operation module 105. W1 Connect, ..., terminal S1 of the second operational switch circuit 601 to terminal B of the matrix element storage and operation module 105. Wj Connect, ..., terminal S1 of the 2Nth operational switch circuit 601 to terminal B of the matrix element storage and operation module 105. WN The terminals SEL of the 21st operational switch circuit 601, ..., the terminals SEL of the 2jth operational switch circuit 601, ..., the terminals SEL of the 2Nth operational switch circuit 601 are respectively connected to the terminal N of the operational logic NOT gate 602. IN The terminals SEL of the 21st operational switch circuit 601, ..., the terminals SEL of the 2jth operational switch circuit 601, ..., the terminals SEL of the 2Nth operational switch circuit 601 are respectively connected to the terminal B of the matrix element storage and operation module 105. S1 connect.

[0128] like Figure 6 As shown, the terminals R of the N operational memristors 603 in the first column M1 Terminal B of the matrix element storage and operation module 105 respectively OUT11 Connect the terminals R of the N operational memristors 603 in column 2. M1 Terminal B of the matrix element storage and operation module 105 respectively OUT12 Connect the terminals R of the N operational memristors 603 in the 2×k-1th column. M1 Terminal B of the matrix element storage and operation module 105 respectively OUTk1 Connect the terminals R of the N operational memristors 603 in column 2×k. M1 Terminal B of the matrix element storage and operation module 105 respectively OUTk2Connect the terminals R of the N operational memristors 603 in column 2×L-1, ... M1 Terminal B of the matrix element storage and operation module 105 respectively OUTL1 Connect the terminals R of the N operational memristors 603 in column 2×L. M1 Terminal B of the matrix element storage and operation module 105 respectively OUTL2 connect.

[0129] like Figure 7 As shown, the L secondary operational circuits 106 in the matrix multiplication operation circuit are identical; each secondary operational circuit 106 includes a secondary operational selector A701, a secondary operational NMOS transistor A702, a first secondary operational resistor 703, a seventh operational amplifier 704, a second secondary operational resistor 705, a fourth secondary operational resistor 706, a third secondary operational resistor 707, an eighth secondary operational resistor 708, a tenth secondary operational resistor 709, a tenth operational amplifier 710, an eleventh secondary operational resistor 711, a ninth secondary operational resistor 712, a ninth operational amplifier 713, a seventh secondary operational resistor 714, a sixth secondary operational resistor 715, an eighth operational amplifier 716, a fifth secondary operational resistor 717, a secondary operational selector C718, a twelfth secondary operational resistor 719, a secondary operational NMOS transistor B720, and a secondary operational selector B721.

[0130] like Figure 7 As shown, the terminal OUT of the secondary operational selector A701 is connected to the terminal O of the secondary operational circuit 106. BIN1 The connection is as follows: Terminal 1_CHAN of the second-stage operational selector A701 is connected to the drain of the second-stage operational NMOS transistor A702; Terminal 0_CHAN of the second-stage operational selector A701 is connected to Terminal F of the 7th operational amplifier 704. - The terminals R0 of the second-stage operational resistor 705 and the second-stage operational selector A701 are connected to each other, as are the terminals SEL of the second-stage operational selector B721 and the terminal O of the second-stage operational circuit 106. BS1 Connect them separately.

[0131] like Figure 7 As shown, the gate of the secondary operational NMOS transistor A702 is connected to terminal O of the secondary operational circuit 106. BSEL1 The source of the second-level operational NMOS transistor A702 is connected to the source of the second-level operational NMOS transistor B720 and the OUT terminal of the second-level operational selector C718, respectively.

[0132] like Figure 7As shown, the terminals R1 of the first secondary operational resistor 703, the eighth secondary operational resistor 708, the eleventh secondary operational resistor 711, the fifth secondary operational resistor 717, and the terminal 1_CHAN of the secondary operational selector C718 are all connected to GND.

[0133] like Figure 7 As shown, terminal F of the 7th operational amplifier 704 + The terminal R0 of the first secondary operational resistor 703 is connected to the terminal F of the seventh operational amplifier 704. O It is connected to terminal R1 of the second secondary operational resistor 705 and terminal R0 of the third secondary operational resistor 707, respectively.

[0134] like Figure 7 As shown, terminal F of the 10th operational amplifier 710 + Connected to terminal R0 of the 11th operational resistor 711, and terminal F of the 10th operational amplifier 710 - The terminal R1 of the third operational resistor 707, the terminal R0 of the tenth operational resistor 709, and the terminal R0 of the ninth operational resistor 712 are respectively connected to the terminal F of the tenth operational amplifier 710. o Terminal R1 of the 10th secondary operational resistor 709 and terminal O of the secondary operational circuit 106 BOUT Connect them separately.

[0135] like Figure 7 As shown, terminal F of the 9th operational amplifier 713 + Connected to terminal R0 of the 8th operational resistor 708, and terminal F of the 9th operational amplifier 713. - The terminal R1 of the 6th operational resistor 715, the terminal R1 of the 12th operational resistor 719, and the terminal R0 of the 7th operational resistor 714 are respectively connected to the terminal F of the 9th operational amplifier 713. O The terminal R1 of the 7th secondary operational resistor 714 and the terminal R1 of the 9th secondary operational resistor 712 are connected respectively; the terminal R0 of the 12th secondary operational resistor 719 is connected to the terminal B of the secondary operational circuit 106. STD connect.

[0136] like Figure 7 As shown, terminal F of the 8th operational amplifier 716 + Connected to terminal R0 of the fifth operational resistor 717, and terminal F of the eighth operational amplifier 716. - The terminal R0 of the fourth operational resistor 706 and the terminal 0_CHAN of the second operational selector B721 are connected respectively, and the terminal F of the eighth operational amplifier 716 is connected to the terminal R0 of the second operational resistor 706 and the terminal F of the second operational selector B721. OConnect to terminal R1 of the fourth secondary operational resistor 706 and terminal R0 of the sixth secondary operational resistor 715, respectively.

[0137] like Figure 7 As shown, the SEL terminal of the secondary operational selector C718 is connected to the O terminal of the secondary operational circuit 106. BS2 Connect terminal 0_CHAN of the secondary operational selector C718 to terminal B of the secondary operational circuit 106. RES connect.

[0138] like Figure 7 As shown, terminal OUT of the secondary operational selector B721 is connected to terminal O of the secondary operational circuit 106. BIN2 The connection is as follows: Terminal 1_CHAN of the secondary operational selector B721 is connected to the drain of the secondary operational NMOS transistor B720; the gate of the secondary operational NMOS transistor B720 is connected to terminal O of the secondary operational circuit 106. BSEL2 connect.

[0139] like Figure 8 As shown, the matrix operation result storage module 107 in the matrix multiplication operation circuit includes M×L result storage memristors 801, M×L result storage NMOS transistors 802, M result switching circuits 803, result storage logic NOT gates 804, and result storage selectors 805.

[0140] like Figure 8 As shown, the terminals R of the M result storage memristors 801 in the first column are... M0 Terminal C of the matrix operation result storage module 107 is respectively connected to the terminal C W1 Connect, ..., the Mth result of the kth column is stored at terminal R of memristor 801. M0 Terminal C of the matrix operation result storage module 107 is respectively connected to the terminal C Wk Connect, ..., the Mth result of the Lth column is stored at terminal R of memristor 801. M0 Terminal C of the matrix operation result storage module 107 is respectively connected to the terminal C WL Connection; Terminal R of the M results stored in column 1 of memristor 801 M1 The terminals R of the M result storage memristors 801 in the k-th column are connected to the drains of their respective result storage NMOS transistors 802, ... M1 The terminals R of the M result storage memristors 801 in the Lth column are connected to the drains of their respective result storage NMOS transistors 802, ... M1 Connect to the drain of the corresponding result storage NMOS transistor 802.

[0141] like Figure 8As shown, the sources of the M×L result storage NMOS transistors 802 are connected to the OUT terminal of the result storage selector 805, and the gates of the L result storage NMOS transistors 802 in the first row are connected to the C terminal of the matrix operation result storage module 107. D1 The gates of the L result storage NMOS transistors 802 in the i-th row are connected to terminals C of the matrix operation result storage module 107, respectively. Di The gates of the Lth result storage NMOS transistor 802 in the Mth row are connected to the terminals C of the matrix operation result storage module 107, respectively. DM Connections: The gates of the L result storage NMOS transistors 802 in the first row are respectively connected to the terminal S0 of the first result switching circuit 803, ..., the gates of the L result storage NMOS transistors 802 in the i-th row are respectively connected to the terminal S0 of the i-th result switching circuit 803, ..., the gates of the L result storage NMOS transistors 802 in the M-th row are respectively connected to the terminal S0 of the M-th result switching circuit 803.

[0142] like Figure 8 As shown, terminals S1 of the first result switching circuit 803, ..., terminals S1 of the i-th result switching circuit 803, ..., terminals S1 of the M-th result switching circuit 803 are respectively connected to terminals C of the matrix operation result storage module 107. S1 The terminals SEL of the first result switch circuit 803, ..., the terminals SEL of the i-th result switch circuit 803, ..., the terminals SEL of the M-th result switch circuit 803 are respectively connected to the terminal N of the result storage logic NOT gate 804. OUT connect.

[0143] like Figure 8 As shown, the result is stored at terminal N of the NOT gate 804. IN Terminal SEL of the result storage gating 805 and terminal C of the matrix operation result storage module 107 S2 Connect them separately; terminal 1_CHAN of the result storage selector 805 is connected to GND, and terminal 0_CHAN of the result storage selector 805 is connected to terminal C of the matrix operation result storage module 107. RES connect.

[0144] like Figure 9 As shown, the matrix switching circuit 109 in the matrix multiplication operation circuit includes matrix switching NMOS transistor A901 and matrix switching NMOS transistor B902.

[0145] like Figure 9As shown, the drain of matrix switch NMOS transistor A901 is connected to terminal S0 of matrix switch circuit 109, the source of matrix switch NMOS transistor A901 is connected to the source of matrix switch NMOS transistor B902, the gate of matrix switch NMOS transistor A901 is connected to terminal SEL of matrix switch circuit 109 and the gate of matrix switch NMOS transistor B902 respectively; the drain of matrix switch NMOS transistor B902 is connected to terminal S1 of matrix switch circuit 109.

[0146] In this embodiment:

[0147] The 2N storage switch circuits 403 in the matrix element storage module 103, the 2N operation switch circuits 601 in the matrix element storage and operation module 105, and the M result switch circuits 803 in the matrix operation result storage module 107 are all the same as the matrix switch circuit 109 in the matrix multiplication operation circuit based on memristor array.

[0148] The first operational amplifier 201 is any one of a general-purpose, high-speed, or low-power operational amplifier; the first operational amplifier 201 is the same as the second operational amplifier 203, the third operational amplifier 205, the fourth operational amplifier 303, the fifth operational amplifier 507, the sixth operational amplifier 504, the seventh operational amplifier 704, the eighth operational amplifier 716, the ninth operational amplifier 713, and the tenth operational amplifier 710.

[0149] The M×N element storage memristors 405 in the matrix element storage module 103, the N×L×2 operational memristors 603 in the matrix element storage and operation module 105, and the M×L result storage memristors 801 in the matrix operation result storage module 107 are the same; the M×N element storage memristors 405 in the matrix element storage module 103, the N×L×2 operational memristors 603 in the matrix element storage and operation module 105, and the M×L result storage memristors 801 in the matrix operation result storage module 107 are all memristors with threshold voltages.

[0150] The resistance values ​​of the second-stage operational resistor 502, the third-stage operational resistor 506, and the fourth-stage operational resistor 503 are the same.

[0151] The second-level operational resistor 705 and the fourth-level operational resistor 706 have the same resistance value.

[0152] In this embodiment: M, N, and L are 6, 6, and 6 respectively.

[0153] This embodiment describes the usage method of the matrix multiplication circuit based on a memristor array. The steps of the usage method are as follows:

[0154] Step 1: Reset all memristors

[0155] At terminal V of the matrix multiplication circuit W1 V S2 A corresponding low-level voltage signal U is applied between the terminal GND and the terminal GND. W1 =0V,U S2 =0V, at terminal V of the matrix multiplication circuit. S1 V RES V AWS1 ... V AWSi ... V AWSM V BS11 V BS12 ... V BSk1 V BSk2 ... V BSL1 V BSL2 V CS1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. S1 =5V, U RES =3.5V, U AWS1 =5V, ..., U AWSi =5V, ..., U AWSM =5V, U BS11 =5V, U BS12 =5V, ..., U BSk1 =5V, U BSk2 =5V, ..., U BSL1 =5V, U BSL2 =5V, U CS1 =5V.

[0156] At this time, at terminal V of the matrix multiplication circuit RES V AWS1 ... V AWSi ... V AWSM V BS11 V BS12 ... V BSk1 V BSk2 ... V BSL1 V BSL2 V CS1 Input the corresponding high-level voltage signal U RES U AWS1 ... U AWSi ... U AWSM U BS11 U BS12 ... U BSk1 U BSk2 ... U BSL1 U BSL2 U CS1This ensures that the 21st element storage NMOS transistor 401, ..., the 2ith element storage NMOS transistor 401, ..., the 2Mth element storage NMOS transistor 401 in the matrix element storage module 103, the respective secondary operation NMOS transistors A702 and B720 in each secondary operation circuit 106, and the row result storage NMOS transistors 802 in the matrix operation result storage module 107 are all in the on state, and the high-level voltage signal U... RES The terminals R of all memristors in the matrix element storage module 103, the matrix element storage and operation module 105, and the matrix operation result storage module 107 are applied. M1 Above, high-level voltage signal U RES The value is greater than the threshold voltage of element storage memristor 405 and the duration exceeds the maximum time t required to reset element storage memristor 405. max This resets all element storage memristors 405, operational memristors 603, and result storage memristors 801 to a high-impedance state.

[0157] In this embodiment, the resistance of all memristors in the high-resistance state is reset to the set value of 5000Ω.

[0158] Step 2: Write data to the matrix element storage module

[0159] At terminal V of the matrix multiplication circuit W0 V W1 V S1 V S2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. W0 =3.5V, U W1 =5V, U S1 =5V, U S2 =3.5V; at terminal V of the matrix multiplication circuit. WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF =2.4V; at terminal V of the matrix multiplication circuit CLK2 A clock voltage signal U with a frequency of 1000kHz is applied between the terminal GND and the terminal GND. CLK2 At terminal V of the matrix multiplication circuit AWS1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS1 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 V WA4 V WA5 V WA6 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0.8V, U WA2=0.8V, U WA3 =0.8V, U WA4 =0.8V, U WA5 =0.8V, U WA6 =0.8V, at the V terminal of the matrix multiplication circuit. AWS2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS2 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 V WA4 V WA5 V WA6 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0.0449V, U WA2 =0.2852V, U WA3 =0.1363V, U WA4 =0.0311V, U WA5 =0.0544V, U WA6 =0.0593V, at terminal V of the matrix multiplication circuit. AWS3 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS3 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 V WA4 V WA5 V WA6 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0.322V, U WA2 =0.1025V, U WA3 =0.1151V, U WA4 =0.0402V, U WA5 =0.0966V, U WA6 =0.0449V, at terminal V of the matrix multiplication circuit. AWS4 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS4 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 V WA4 V WA5 V WA6 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0.0966V, U WA2 =0.0693V, U WA3 =0.0852V, U WA4=0.0311V, U WA5 =0.0449V, U WA6 =0.0132V, at terminal V of the matrix multiplication circuit. WAS5 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS5 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 V WA4 V WA5 V WA6 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0V,U WA2 =0.0966V, U WA3 =0.0642V, U WA4 =0.1441V, U WA5 =0.1815V, U WA6 =0.171V, at terminal V of the matrix multiplication circuit. AWS6 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS6 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 V WA4 V WA5 V WA6 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0.2208V, U WA2 =0.0449V, U WA3 =0.0966V, U WA4 =0.1441V, U WA5 =0.0176V, U WA6 =0.0221V.

[0160] At this time, the 21st element storage NMOS transistor 401 in the matrix element storage module 103 is in the on state, and at the same time, the 11th resistance adjustment circuit 102, ..., the 1jth resistance adjustment circuit 102, ..., the 1Nth resistance adjustment circuit 102 respectively output resistance adjustment voltage signals U. WA1 ... U WAj ... U WAN The value corresponds to a pulse voltage signal of duration, which causes the resistance of the memristor 405 storing the first row of elements in the matrix element storage module 103 to be adjusted. The magnitude of the pulse voltage signal is 3.5V, and the duration of the pulse voltage signal is t.

[0161] The duration t of the pulse voltage signal and the resistance adjustment voltage signal U WAj The relationship between their sizes is as follows:

[0162]

[0163] In formula (1):

[0164] U WAj This indicates that terminal W of the first j-th resistance adjustment circuit 102 IN The voltage, V;

[0165] V ref Indicates the reference voltage U WREF The value of V;

[0166] f represents the clock voltage signal U. CLK2 The clock frequency, Hz.

[0167] Following the method for adjusting the resistance value of the first row of element storage memristors 405 in the matrix element storage module 103, the second row, ..., the i-th row, ..., the M-th row of element storage memristors 405 in the matrix element storage module 103 are operated sequentially to achieve the function of adjusting the resistance value of all element storage memristors 405 in the matrix element storage module 103.

[0168] The relationship between the duration t of the voltage applied across the memristor 405 of each element during the resistance adjustment process and its resistance value is as follows:

[0169]

[0170] In formula (2):

[0171] W off The value of the internal state variable w of the memristor 405 model, in nm, represents the maximum value of the element used to store the memristor.

[0172] K off The constant representing the material of the element storage memristor 405 is m / s;

[0173] V i This indicates the magnitude of the pulse voltage signal output by the resistance adjustment circuit 102, in V;

[0174] W off The threshold voltage, in V, represents the element storage memristor 405.

[0175] w represents the state variable of the memristor 405 model used for storage, nm.

[0176] The relationship between the state variable w of the element storage memristor 405 model and the resistance value of the element storage memristor 405 is as follows:

[0177]

[0178] In formula (3):

[0179] R M This indicates the resistance value of the element storage memristor 405, in Ω;

[0180] R on This represents the minimum resistance value, in Ω, of the element storage memristor 405.

[0181] R off This indicates the maximum resistance of the element storage memristor 405, in Ω;

[0182] W on The minimum value of the state variable w of the memristor 405 model, represented by the element used for storage, is nm;

[0183] W off The maximum value of the state variable w of the memristor 405 model, represented by the element used for storage, is nm.

[0184] In this embodiment: W off =10nm; W on =0nm;K off =0.0004m / s; V off =1.5V; R on =1000Ω; R off =5000Ω.

[0185] At this point, the resistance values ​​of the six memristors in the first row of the matrix element storage module 103 have been adjusted sequentially to 1000Ω, 1000Ω, 1000Ω, 1000Ω, 1000Ω, 1000Ω, 1000Ω; the resistance values ​​of the six memristors in the second row of the matrix element storage module 103 have been adjusted sequentially to 4000Ω, 1300Ω, 2400Ω, 4300Ω, 3800Ω, 3700Ω; and the resistance values ​​of the six memristors in the third row of the matrix element storage module 103 have been adjusted sequentially to 1200Ω, 2900Ω, 2700Ω, 4100Ω, 3000Ω, 4000Ω, 1 ... The resistance values ​​of the six memristors in the fourth row of the matrix element storage module 103 are adjusted to 3000Ω, 3500Ω, 3200Ω, 4300Ω, 4000Ω, and 4700Ω respectively. The resistance values ​​of the six memristors in the fifth row of the matrix element storage module 103 are adjusted to 5000Ω, 3000Ω, 3600Ω, 2300Ω, 1900Ω, and 2000Ω respectively. The resistance values ​​of the six memristors in the sixth row of the matrix element storage module 103 are adjusted to 1600Ω, 4000Ω, 3000Ω, 2300Ω, 4600Ω, and 4500Ω respectively.

[0186] Step 3: Write data to the matrix element storage and operation module

[0187] At terminal V of the matrix multiplication circuit W0 V W1 V S1 V S2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. W0 =3.5V, U W1 =5V, U S1 =5V, U S2 =3.5V, at terminal V of the matrix multiplication circuit. WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF =2.4V, at terminal V of the matrix multiplication circuit. CLK2 A clock voltage signal U with a frequency of 1000kHz is applied between the terminal GND and the terminal GND. CLK2 .

[0188] At terminal V of the matrix multiplication circuit BS11 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS11 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U is applied between the terminals GND and GND, each with a voltage of 0V. WB1 ... U WBj ... U WBN At terminal V of the matrix multiplication circuit BS12 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS12 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.322V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... U WBN .

[0189] At terminal V of the matrix multiplication circuit BS21 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS21 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.238V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... UWBN At terminal V of the matrix multiplication circuit BS22 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS22 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U is applied between the terminals GND and GND, each with a voltage of 0V. WB1 ... U WBj ... U WBN .

[0190] At terminal V of the matrix multiplication circuit BS31 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS31 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.0852V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... U WBN At terminal V of the matrix multiplication circuit BS32 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS32 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.238V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... U WBN .

[0191] At terminal V of the matrix multiplication circuit BS41 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS41 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.1289V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... U WBN At terminal V of the matrix multiplication circuit BS42 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS42 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... VWBN A resistance-adjustable voltage signal U, each with a voltage of 0.0221V, is applied between the terminal GND and the ground. WB1 ... U WBj ... U WBN .

[0192] At terminal V of the matrix multiplication circuit BS51 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS51 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.0449V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... U WBN At terminal V of the matrix multiplication circuit BS52 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS52 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.238V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... U WBN .

[0193] At terminal V of the matrix multiplication circuit BS61 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS61 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.1614V, is applied between the terminal GND and the ground terminal. WB1 ... U WBj ... U WBN At terminal V of the matrix multiplication circuit BS62 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS62 =5V, at terminal V of the matrix multiplication circuit. WB1 ... V WBj ... V WBN A resistance-adjustable voltage signal U, each with a voltage of 0.0221V, is applied between the terminal GND and the ground. WB1 ... U WBj ... U WBN .

[0194] At this time, the secondary operational NMOS transistor A702 in the first secondary operational circuit 106 is in the on state. The 21st resistance adjustment circuit 102, ..., the 2jth resistance adjustment circuit 102, ..., the 2Nth resistance adjustment circuit 102 respectively complete the same operation as the resistance adjustment circuit 102 in step two, and output the resistance adjustment voltage signal U in sequence. WB1 ... U WBj ... U WBN The pulse voltage signal corresponding to the voltage duration causes the resistance value of the first column operational memristor 603 in the matrix element storage and operation module 105 to be adjusted.

[0195] Correspondingly, the second-level operational NMOS transistor B720 in the first-level operational circuit 106 is in the on state, and the pulse voltage signals of corresponding duration output by the second-level resistance adjustment circuit 102, ..., the second-level resistance adjustment circuit 102, ..., the second-level resistance adjustment circuit 102 of the second-level resistance adjustment circuit 102 cause the resistance of the second-level operational memristor 603 in the matrix element storage and operation module 105 to be adjusted.

[0196] Following the method for adjusting the resistance values ​​of the operational memristors 603 in the first column of the matrix element storage and operation module 105, the operational memristors 603 in the third, fourth, ..., second × k-1, second × k, ..., second × L-1, and second × L columns of the matrix element storage and operation module 105 are operated sequentially to achieve the function of adjusting the resistance values ​​of all operational memristors 603 in the matrix element storage and operation module 105.

[0197] In step three, the difference between the conductance of each operational memristor 603 in the first column and the conductance of the corresponding operational memristor 603 in the second column of the matrix element storage and operation module 105 represents the value of the corresponding element in the first column of the matrix, and so on. Similarly, the difference between the conductance of each operational memristor 603 in the second × L-1 column and the conductance of the corresponding operational memristor 603 in the second × L column represents the value of the corresponding element in the L column of the matrix.

[0198] The matrix element B represented by the conductance of the operational memristor 603 in the j-th row and 2×k-1-th column of the matrix element storage and operation module 105 and the conductance of the operational memristor 603 in the j-th row and 2×k-th column are used to represent the matrix element B. jk :

[0199]

[0200] In equation (4):

[0201] R Mj2×k-1 The value of the operational memristor 603 in the j-th row and 2×k-1-th column of the matrix element storage and operation module 105 is expressed in Ω.

[0202] R Mj2×k The value in Ω represents the resistance of the operational memristor 603 in the j-th row and 2×k-th column of the matrix element storage and operation module 105.

[0203] In Equation 4, when R Mj2×k-1 Equal to R Mj2×k At that time, matrix element B jk =0; when R Mj2×k-1 Greater than R Mj2×k At that time, matrix element B jk It is negative; when R Mj2×k-1 Less than R Mj2×k At that time, matrix element B jk It is a positive number.

[0204] At this point, the resistance values ​​of the six memristors in column 1 of matrix element storage and operation module 105 have been adjusted to 5000Ω; the resistance values ​​of the six memristors in column 2 have been adjusted to 1200Ω; the resistance values ​​of the six memristors in column 3 have been adjusted to 1500Ω; the resistance values ​​of the six memristors in column 4 have been adjusted to 5000Ω; the resistance values ​​of the six memristors in column 5 have been adjusted to 3200Ω; and the resistance values ​​of the six memristors in column 6 have been adjusted... The resistance of the six memristors in column 7 was adjusted to 1500Ω; the resistance of the six memristors in column 8 was adjusted to 4500Ω; the resistance of the six memristors in column 9 was adjusted to 4000Ω; the resistance of the six memristors in column 10 was adjusted to 1500Ω; the resistance of the six memristors in column 11 was adjusted to 2100Ω; and the resistance of the six memristors in column 12 was adjusted to 4500Ω.

[0205] Step 4: Perform matrix multiplication.

[0206] At terminal V of the matrix multiplication circuit S1 A low-level voltage signal U is applied between the terminal GND and the terminal GND. S1 =0V; at terminal V of the matrix multiplication circuit. S2 V S0 V W1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. S2 =3.5V, U S0 =3.5V, U W1 =5V; at terminal V of the matrix multiplication circuit. WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF =2.4V; at terminal V of the matrix multiplication circuit A1 V ASTD V BSTD Apply the corresponding operational voltage signal U between the terminal GND and the terminal GND. A1 =1V,UASTD =0.5V, U BSTD =4.8V; at terminal V of the matrix multiplication circuit CLK1 V CLK2 Apply the corresponding clock voltage signal U between the terminal GND and the terminal GND. CLK1 U CLK2 The clock voltage signal U CLK1 The clock period is 500Hz, and the clock voltage signal U CLK2 The clock period is 1000kHz; at terminal V of the matrix multiplication circuit DIN A pulse voltage signal U with a duration of 1ms is applied between the terminal GND and the terminal GND. DIN =0.5V.

[0207] In this embodiment: the resistance values ​​of the second-level operational resistor 502, the third-level operational resistor 506, and the fourth-level operational resistor 503 are all 1000Ω; the resistance values ​​of the seventh-level operational resistor 714, the sixth-level operational resistor 715, and the twelfth-level operational resistor 719 are all 1000Ω.

[0208] When the terminal V of the matrix multiplication circuit CLK1 Input clock voltage signal U CLK1 During the first high-level signal, all sampling delay NMOS transistors 202 in the sampling delay circuit 101 are in the ON state, and all sampling delay PMOS transistors 204 are in the OFF state. At this time, the signal from terminal V of the matrix multiplication circuit is transmitted through the circuit. DIN Applied pulse voltage U DIN This causes the first capacitor 209 in the first sampling delay circuit 101 to begin charging; when the terminal V of the matrix multiplication operation circuit... CLK1 Input clock voltage signal U CLK1 When the first signal is low, all sampling delay NMOS transistors 202 in the sampling delay circuit 101 are in the off state, and all sampling delay PMOS transistors 204 are in the on state. At this time, the first capacitor 209 in the first sampling delay circuit 101 begins to discharge, causing terminal D of the first sampling delay circuit 101 to discharge. OUT and D N The output is high, and at the same time, the second capacitor 208 in the first sampling delay circuit 101 begins to charge.

[0209] When the terminal V of the matrix multiplication circuit CLK1 Input clock voltage signal U CLK1 When the second signal is high, all sampling delay NMOS transistors 202 in the sampling delay circuit 101 are in the on state, and all sampling delay PMOS transistors 204 are in the off state. At this time, the second capacitor 208 in the first sampling delay circuit 101 begins to discharge, causing terminal D of the first sampling delay circuit 101 to discharge.OUT and D N Continue to output a high level, while simultaneously sampling the terminal D of delay circuit 101. N The high-level voltage signal output causes the first capacitor 209 in the second sampling delay circuit 101 to start charging.

[0210] Repeat the above process in this step, and connect the matrix multiplication circuit to terminal V. A1 V ASTD V BSTD An operational voltage signal U is applied between the terminal GND and the terminal GND respectively. A1 U ASTD U BSTD At terminal V of the matrix multiplication circuit CLK1 Input clock voltage signal U CLK1 During this period, the terminals D of the first sampling delay circuit 101, ..., the i-th sampling delay circuit 101, ..., the M-th sampling delay circuit 101 OUT High-level voltage signals are output sequentially.

[0211] When the terminal D of the first sampling delay circuit 101 OUT When a high-level voltage signal is output, both the 11th element storage NMOS transistor 401 and the 1st row result storage NMOS transistor 802 are in the ON state, causing the R terminal of the 1st row element storage memristor 405 to be ON. M1 The voltage at that point is the operational voltage signal U. A1 The value of the first-level arithmetic circuit 104, ..., the j-th level arithmetic circuit 104, ..., the N-th level arithmetic circuit 104 terminal O AOUT The output voltages are V in sequence. AOUT1 ... V AOUTj ... V AOUTN ;in:

[0212] Terminal O of the first-level operational circuit 104 AOUT Output voltage V AOUT1 :

[0213]

[0214] In equation (5):

[0215] R 11 R represents the resistance value of the first-stage operational resistor 501 in the first-stage operational circuit 104. 11 =1500Ω;

[0216] R M11 R represents the resistance value of the memristor 405, which stores the element in the first row and first column of the matrix element storage module 103. M11 =1000Ω;

[0217] U A1 This indicates the terminal V of the matrix multiplication operation circuit. A1 The applied voltage, U A1 =1V;

[0218] U ASTD This indicates the terminal V of the matrix multiplication operation circuit. ASTD The applied voltage, U ASTD =0.5V.

[0219] Then, terminal O of the first-stage operational circuit 104 AOUT Output voltage V AOUT1 =1V.

[0220] Similarly: Terminal O in the second-level operational circuit 104, ..., the j-th-level operational circuit 104, ..., the N-th-level operational circuit 104 AOUT The output voltages are 1V, 1V, 1V, 1V, 1V in sequence.

[0221] From terminal V of the matrix multiplication circuit ASTD Apply operational voltage signal U ASTD Then, terminals O of the first-level operational circuit 104, ..., the j-th-level operational circuit 104, ..., the N-th-level operational circuit 104 AOUT The output voltage is converted into the output voltage of the matrix element storage module 103 and the operation voltage signal U. ASTD The voltage difference transforms the matrix elements, represented by the conductance of each storage memristor 405 in the matrix element storage module 103, which contain positive and negative numbers, into corresponding positive and negative voltages. The applied operational voltage signal U... ASTD :

[0222]

[0223] In formula (6):

[0224] R 11 This indicates the resistance value of the first-stage operational resistor 501, R. 11 =1500Ω;

[0225] R on R represents the minimum resistance of the element storage memristor 405. on =1000Ω;

[0226] R off R represents the maximum resistance of the element storage memristor 405. off =5000Ω;

[0227] U A1 This indicates the terminal V of the matrix multiplication operation circuit. A1The applied voltage, U A1 =1V.

[0228] Then, the applied operational voltage signal U ASTD =0.5V.

[0229] Because the output terminals O of N first-level operational circuits 104 AOUT Simultaneously output voltage V AOUT1 ... V AOUTj ... V AOUTN Then, the output terminals O of the L secondary operational circuits 106 BOUT Simultaneously output voltage V BOUT1 ... V BOUTk ... V BOUTL .in,

[0230] Output terminal O of the first secondary operational circuit 106 BOUT Output voltage V BOUT1 :

[0231]

[0232] In equation (7):

[0233] R 22 R represents the resistance value of the second-stage operational resistor 705. 22 =1000Ω;

[0234] R 23 R represents the resistance value of the third secondary operational resistor 707. 23 =9600Ω;

[0235] R 24 This indicates the resistance value of the fourth secondary operational resistor 706, R. 24 =1000Ω;

[0236] R 29 R represents the resistance value of the 9th second-level operational resistor 712. 29 =9600Ω;

[0237] R 210 This indicates the resistance value of the 10th second-stage operational resistor 709, R. 210 =800Ω;

[0238] N represents the number of 104 first-level operational circuits, N = 6;

[0239] R M11 R M12 ... R Mj1 R Mj2 ... R MN1 R MN2The values ​​R represent the resistance values ​​of the memristors in the following rows and columns: row 1, column 1, row 1, column 2, ..., row j, column 1, row j, column 2, ..., row N, column N, column 2, respectively. M11 R M12 ... R Mj1 R Mj2 ... R MN1 R MN2 The resistance values ​​are 5000Ω, 1200Ω, 5000Ω, 1200Ω, 5000Ω, 1200Ω, 5000Ω, 1200Ω, 5000Ω, 1200Ω, 5000Ω, 1200Ω, 5000Ω, 1200Ω;

[0240] U BSTD This indicates the terminal V of the matrix multiplication operation circuit. BSTD The applied operational voltage signal, U BSTD = 4.8V. Therefore, the applied operational voltage signal V BOUT1 =0.0833V.

[0241] Since all the secondary operational circuits 106 can output bipolar voltages corresponding to the positive and negative operation results, the voltage at terminal V of the matrix multiplication circuit is... BSTD Apply a positive voltage U BSTD This ensures that all output voltages of the secondary operation circuit 106 are positive, so that the result of the matrix multiplication operation can be saved to the matrix operation result storage module 107.

[0242] Among them, the applied operational voltage signal U BSTD :

[0243]

[0244] In equation (8):

[0245] R 11 This indicates the resistance value of the first-stage operational resistor 501, R. 11 =1500Ω;

[0246] R 24 This indicates the resistance value of the fourth secondary operational resistor 706, R. 24 =1000Ω;

[0247] N represents the number of 106 first-level operational circuits, N = 6;

[0248] R on R represents the minimum resistance of the element storage memristor 405. on =1000Ω;

[0249] R offR represents the maximum resistance of the element storage memristor 405. off =5000Ω;

[0250] U A1 This indicates the terminal V of the matrix multiplication operation circuit. A1 The applied voltage, U A1 =1V;

[0251] U ASTD This indicates the terminal V of the matrix multiplication operation circuit. ASTD The applied voltage, U ASTD =0.5V.

[0252] Then, the applied operational voltage signal U BSTD =4.8V.

[0253] Similarly: Terminal O in the second-level operational circuit 104, ..., the kth-level operational circuit 104, ..., the Lth-level operational circuit 104 BOUT The output voltages are 0.633V, 0.223V, 0.489V, 0.192V, and 0.527V in sequence.

[0254] The 31st resistance adjustment circuit 102, ..., the 3kth resistance adjustment circuit 102, ..., the 3Lth resistance adjustment circuit 102 sequentially output V. BOUT1 ... V BOUTk ... V BOUTL The corresponding pulse voltage signal of the specified duration is used to ensure that the NMOS transistors 802 storing the results of the first row in the matrix operation result storage module 107 are all in the ON state, causing the resistance value of the memristor 801 storing the results of the first row in the matrix operation result storage module 107 to be equal to the voltage V output by the first secondary operation circuit 106, ..., the kth secondary operation circuit 106, ..., the Lth secondary operation circuit 106. BOUT1 ... V BOUTk ... V BOUTL They were adjusted at the same time.

[0255] Similarly, repeat the above process until terminal D of the Mth sampling delay circuit 101 is reached. OUT After outputting a high-level voltage signal, the matrix multiplication operation in this embodiment ends, and the matrix multiplication result storage module 107 stores the result of the matrix multiplication operation:

[0256] The resistance values ​​of the memory resistor 801 storing the results in the first column of the first row, ..., the kth column, ..., the Lth column are 3234Ω, 1006Ω, 1587Ω, 1031Ω, 1812Ω, and 1020Ω, respectively.

[0257] The resistance values ​​of the memory resistor 801 storing the results in the 1st, ..., kth, ..., Lth columns of the 2nd row are 1100Ω, 1073Ω, 1092Ω, 1079Ω, 1094Ω, and 1078Ω, respectively.

[0258] The resistance values ​​of the memory resistor 801 storing the results in the 1st, ..., kth, ..., Lth columns of the 3rd row are 1117Ω, 1065Ω, 1101Ω, 1076Ω, 1104Ω, and 1073Ω, respectively.

[0259] The resistance values ​​of the memory resistor 801 storing the results in the 1st, ..., kth, ..., Lth columns of the 4th row are 1060Ω, 1107Ω, 1069Ω, 1092Ω, 1067Ω, and 1096Ω, respectively.

[0260] The resistance values ​​of the memory resistor 801 storing the results in the 1st, ..., kth, ..., Lth columns of the 5th row are 1107Ω, 1070Ω, 1096Ω, 1078Ω, 1098Ω, and 1076Ω, respectively.

[0261] The resistance values ​​of the memory resistor 801 storing the results in the 1st, ..., kth, ..., Lth columns of the 6th row are 1090Ω, 1079Ω, 1087Ω, 1082Ω, 1088Ω, and 1081Ω, respectively.

[0262] Example 2

[0263] A matrix multiplication circuit based on a memristor array and its usage method are disclosed. The matrix multiplication circuit based on the memristor array is simply referred to as a matrix multiplication circuit.

[0264] The matrix multiplication circuit described in this embodiment is the same as the matrix multiplication circuit described in Embodiment 1, except that M, N, and L are 2, 3, and 2 respectively.

[0265] This embodiment describes the usage method of the matrix multiplication circuit based on a memristor array. The steps of the usage method are as follows:

[0266] Step 1: Reset all memristors

[0267] At terminal V of the matrix multiplication circuit W1 V S2 A corresponding low-level voltage signal U is applied between the terminal GND and the terminal GND. W1 =0V,U S2 =0V, at terminal V of the matrix multiplication circuit. S1 V RES V AWS1 ... V AWSi ... V AWSM V BS11 V BS12... V BSk1 V BSk2 ... V BSL1 V BSL2 V CS1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. S1 =5V, U RES =3.5V, U AWS1 =5V, ..., U AWSi =5V, ..., U AWSM =5V, U BS11 =5V, U BS12 =5V, ..., U BSk1 =5V, U BSk2 =5V, ..., U BSL1 =5V, U BSL2 =5V, U CS1 =5V.

[0268] At this point, all element storage memristors 405, operational memristors 603, and result storage memristors 801 are reset to a high-resistance state. In this embodiment, the resistance value of all memristors in the high-resistance state is reset to the set value of 5000Ω.

[0269] Step 2: Write data to the matrix element storage module

[0270] At terminal V of the matrix multiplication circuit W0 V W1 V S1 V S2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. W0 =3.5V, U W1 =5V, U S1 =5V, U S2 =3.5V; at terminal V of the matrix multiplication circuit. WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF =2.4V; at terminal V of the matrix multiplication circuit CLK2 A clock voltage signal U with a frequency of 1000kHz is applied between the terminal GND and the terminal GND. CLK2 At terminal V of the matrix multiplication circuit AWS1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS1 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0.8V, U WA2 =0.0966V, U WA3=0V, at terminal V of the matrix multiplication circuit. AWS2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. AWS2 =5V, at terminal V of the matrix multiplication circuit. WA1 V WA2 V WA3 Apply a voltage signal U with corresponding resistance adjustment between the terminal GND and the terminal GND. WA1 =0.171V, U WA2 =0.0221V, U WA3 =0.0693V.

[0271] At this point, the resistance values ​​of the three memristors in the first row of the matrix element storage module 103 are adjusted to 1000Ω, 3000Ω, and 5000Ω respectively; and the resistance values ​​of the three memristors in the second row are adjusted to 2000Ω, 4500Ω, and 3500Ω respectively.

[0272] Step 3: Write data to the matrix element storage and operation module

[0273] At terminal V of the matrix multiplication circuit W0 V W1 V S1 V S2 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. W0 =3.5V, U W1 =5V, U S1 =5V, U S2 =3.5V, at terminal V of the matrix multiplication circuit. WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF =2.4V, at terminal V of the matrix multiplication circuit. CLK2 A clock voltage signal U with a frequency of 1000kHz is applied between the terminal GND and the terminal GND. CLK2 .

[0274] At terminal V of the matrix multiplication circuit BS11 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS11 =5V, at terminal V of the matrix multiplication circuit. WB1 V WB2 V WB3 Apply corresponding resistance-adjustable voltage signals U between terminals GND and GND. WB1 =0.171V, U WB2 =0.238V, U WB3 =0.0798V, at terminal V of the matrix multiplication circuit. BS12 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS12 =5V, at terminal V of the matrix multiplication circuit.WB1 V WB2 V WB3 Apply corresponding resistance-adjustable voltage signals U between terminals GND and GND. WB1 =0.1151V, U WB2 =0.0449V, U WB3 =0.322V.

[0275] At terminal V of the matrix multiplication circuit BS21 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS21 =5V, at terminal V of the matrix multiplication circuit. WB1 V WB2 V WB3 Apply corresponding resistance-adjustable voltage signals U between terminals GND and GND. WB1 =0.0642V, U WB2 =0.1289V, U WB3 =0V, at terminal V of the matrix multiplication circuit. BS22 A high-level voltage signal U is applied between the terminal GND and the terminal GND. BS22 =5V, at terminal V of the matrix multiplication circuit. WB1 V WB2 V WB3 Apply corresponding resistance-adjustable voltage signals U between terminals GND and GND. WB1 =0.8V, U WB2 =0.0544V, U WB3 =0.0221V.

[0276] At this point, the resistance values ​​of the three memristors in the first column of the matrix element storage and operation module 105 have been adjusted to 2000Ω, 1500Ω, and 3300Ω respectively; the resistance values ​​of the three memristors in the second column have been adjusted to 2700Ω, 4000Ω, and 1200Ω respectively; the resistance values ​​of the three memristors in the third column have been adjusted to 3600Ω, 2500Ω, and 5000Ω respectively; and the resistance values ​​of the three memristors in the fourth column have been adjusted to 1000Ω, 3800Ω, and 4500Ω respectively.

[0277] Step 4: Perform matrix multiplication.

[0278] At terminal V of the matrix multiplication circuit S1 A low-level voltage signal U is applied between the terminal GND and the terminal GND. S1 =0V; at terminal V of the matrix multiplication circuit. S2 V S0 V W1 A corresponding high-level voltage signal U is applied between the terminal GND and the terminal GND. S2 =3.5V, U S0 =3.5V, UW1 =5V; at terminal V of the matrix multiplication circuit. WREF A reference voltage signal U is applied between the terminal GND and the terminal GND. WREF =2.4V; at terminal V of the matrix multiplication circuit A1 V ASTD V BSTD Apply the corresponding operational voltage signal U between the terminal GND and the terminal GND. A1 =1V,U ASTD =0.5V, U BSTD =2.4V; at terminal V of the matrix multiplication circuit CLK1 V CLK2 Apply the corresponding clock voltage signal U between the terminal GND and the terminal GND. CLK1 U CLK2 The clock voltage signal U CLK1 The clock period is 500Hz, and the clock voltage signal U CLK2 The clock period is 1000kHz; at terminal V of the matrix multiplication circuit DIN A pulse voltage signal U with a duration of 1ms is applied between the terminal GND and the terminal GND. DIN =0.5V.

[0279] At this point, the resistance values ​​of the first row of the matrix operation result storage module 107, the first row of the result storage memristor 801, are adjusted to 1067Ω and 2350Ω respectively; the resistance values ​​of the second row of the result storage memristor 801 in the matrix operation result storage module 107 are adjusted to 1745Ω and 1885Ω respectively.

[0280] This specific implementation method has the following positive effects:

[0281] In this specific embodiment, when only the corresponding voltage signal is input, the memristor array can be reset, and all memristors in the matrix multiplication circuit can be adjusted to a high-impedance state; when only the voltage corresponding to the matrix element is input to the resistance adjustment circuit 102, and in conjunction with the corresponding high-level voltage control signal, the elements in the matrix to be calculated can be saved to the memristor array. Therefore, this specific embodiment is simple to operate.

[0282] In this specific embodiment, the high-level voltage signal output by the sampling delay circuit 101 enables the sequential selection of each row of element storage memristors 405 in the matrix element storage module 103 and the matrix operation result storage module 107. This causes the matrix element storage module 103 to output the voltage corresponding to the conductance of the selected row element storage memristor 405. After the voltage output by the matrix element storage module 103 is applied to each row of the memristor array in the matrix element storage and operation module 105, the matrix element storage and operation module 105 outputs the voltage of the corresponding vector and matrix multiplication result. This voltage is then stored in the element storage memristor 405 of the selected row in the memristor array of the matrix operation result storage module 107 through the resistance adjustment circuit 102. The process of data transmission between the memory and the arithmetic unit is eliminated during the calculation process. Data storage and operation are completed in the memristor array, thereby improving the speed of matrix multiplication.

[0283] In this specific embodiment, the difference between the conductances of two memristors is used to represent a corresponding matrix element in the matrix element storage and operation module 105. This expands the range of values ​​represented by the conductances of the memristors in the matrix element storage and operation module 105 from positive numbers to positive, negative numbers and zero. Therefore, it is possible to perform matrix multiplication on any two real number matrices containing positive and negative elements.

[0284] Therefore, this specific implementation method is not only simple to operate and fast to operate, but also capable of performing matrix multiplication operations on any two real number matrices containing positive and negative elements.

Claims

1. A method for using a matrix multiplication circuit based on a memristor array, characterized in that... The steps for using this method are as follows: The matrix multiplication circuit based on memristor array is simply referred to as the matrix multiplication circuit. The physical meanings represented by the letters in the matrix multiplication circuit are uniformly described as follows: i, j, and k are natural numbers greater than or equal to 2, and M, N, and L are natural numbers that satisfy the following related inequalities: 1≤i≤M, 1≤j≤N, 1≤k≤L; Step 1: Reset all memristors At the terminals of the matrix multiplication circuit , Apply a corresponding low-level voltage signal between the terminal GND and the terminal GND. , At the terminals of the matrix multiplication circuit , , ... ... , , ... , ... , , Apply a corresponding high-level voltage signal between the terminal GND and the terminal GND. , , ... ... , , ... , ... , , ; Step 2: Write data to the matrix element storage module At the terminals of the matrix multiplication circuit , , , Apply a corresponding high-level voltage signal between the terminal GND and the terminal GND. , , , At the terminals of the matrix multiplication circuit A reference voltage signal is applied between the terminal GND and the terminal GND. At the terminals of the matrix multiplication circuit Apply a clock voltage signal between the terminal GND and the terminal GND. At the terminals of the matrix multiplication circuit ... ... Apply a corresponding high-level voltage signal between the terminal GND and the terminal GND. ... ... At the terminals of the matrix multiplication circuit ... ... Apply a corresponding resistance adjustment voltage signal between the terminal GND and the terminal GND. ... ... ; Step 3: Write data to the matrix element storage and operation module At the terminals of the matrix multiplication circuit , , , Apply a corresponding high-level voltage signal between the terminal GND and the terminal GND. , , , At the terminals of the matrix multiplication circuit A reference voltage signal is applied between the terminal GND and the terminal GND. At the terminals of the matrix multiplication circuit Apply a clock voltage signal between the terminal GND and the terminal GND. At the terminals of the matrix multiplication circuit , ... , ... , A corresponding high-level voltage signal is sequentially applied between the terminal GND and the terminal GND. , ... , ... , Meanwhile, at the terminals of the matrix multiplication circuit ... ... Apply resistance-adjustable voltage signals between terminals GND and GND respectively. ... ... ; Step 4: Perform matrix multiplication. At the terminals of the matrix multiplication circuit Apply a low-level voltage signal between the terminal GND and the terminal GND. At the terminals of the matrix multiplication circuit , , Apply a corresponding high-level voltage signal between the terminal GND and the terminal GND. , , At the terminals of the matrix multiplication circuit A reference voltage signal is applied between the terminal GND and the terminal GND. At the terminals of the matrix multiplication circuit , , Apply the corresponding operational voltage signal between the terminal GND and the terminal GND. , , At the terminals of the matrix multiplication circuit , Apply a corresponding clock voltage signal between the terminal GND and the terminal GND. , At the terminals of the matrix multiplication circuit Apply a pulse voltage signal between the terminal GND and the terminal GND. .

2. The method of using the matrix multiplication circuit based on memristor array according to claim 1, characterized in that: The matrix multiplication circuit includes M sampling delay circuits, 2N+L resistance adjustment circuits, a matrix element storage module, N first-level operation circuits, a matrix element storage and operation module, L second-level operation circuits, a matrix operation result storage module, a matrix resistor, and a matrix switch circuit. In the matrix multiplication circuit: Terminals of the first sampling delay circuit Terminals of the i-th sampling delay circuit Terminals of the Mth sampling delay circuit Terminals of the matrix multiplication operation circuit Connection; Terminals of the first sampling delay circuit Terminals of the second sampling delay circuit Connect the terminals of the (i-1)th sampling delay circuit. Terminals of the i-th sampling delay circuit Connect the terminals of the (M-1)th sampling delay circuit. Terminals of the Mth sampling delay circuit Connection; Terminals of the first sampling delay circuit Terminals of the matrix multiplication operation circuit connect; Terminals CLK of the 11th resistance adjustment circuit, ..., terminals CLK of the 1jth resistance adjustment circuit, ..., terminals CLK of the 1Nth resistance adjustment circuit, terminals CLK of the 21st resistance adjustment circuit, ..., terminals CLK of the 2jth resistance adjustment circuit, ..., terminals CLK of the 2Nth resistance adjustment circuit, terminals CLK of the 31st resistance adjustment circuit, ..., terminals CLK of the 3kth resistance adjustment circuit, ..., terminals CLK of the 3lth resistance adjustment circuit and terminals of the matrix multiplication operation circuit. connect; Terminals of the 11th resistance adjustment circuit Terminals of the first j-th resistance adjustment circuit Terminals of the 1Nth resistance adjustment circuit Terminals of the 21st resistance adjustment circuit Terminals of the second resistance adjustment circuit Terminals of the 2Nth resistance adjustment circuit Terminals of the matrix multiplication operation circuit Connection; Terminals of the 31st resistance adjustment circuit Terminals of the 3k resistance adjustment circuit Terminals of the 3L resistance adjustment circuit Terminals of the matrix switch circuit Connect the terminals of the 31st resistance adjustment circuit. Terminals of the 3k resistance adjustment circuit Terminals of the 3L resistance adjustment circuit Terminals of the matrix resistor connect; Terminals of the 11th resistance adjustment circuit Terminals of the first j-th resistance adjustment circuit Terminals of the 1Nth resistance adjustment circuit Terminals of the 21st resistance adjustment circuit Terminals of the second resistance adjustment circuit Terminals of the 2Nth resistance adjustment circuit Terminals of the 31st resistance adjustment circuit Terminals of the 3k resistance adjustment circuit ...the terminals of the 3L resistance adjustment circuit Terminals of the matrix multiplication operation circuit connect; Terminals of the 11th resistance adjustment circuit Terminals of the first j-th resistance adjustment circuit Terminals of the 1Nth resistance adjustment circuit Terminals of the 21st resistance adjustment circuit Terminals of the second resistance adjustment circuit Terminals of the 2Nth resistance adjustment circuit Terminals of the 31st resistance adjustment circuit Terminals of the 3k resistance adjustment circuit ...the terminals of the 3L resistance adjustment circuit Terminals of the matrix multiplication operation circuit connect; Terminals of the 11th resistance adjustment circuit Terminals of the matrix multiplication operation circuit Connect the terminals of the first j-th resistance adjustment circuit. Terminals of the matrix multiplication operation circuit Connect the terminals of the 1Nth resistance adjustment circuit. Terminals of the matrix multiplication operation circuit Connection; Terminals of the 21st resistance adjustment circuit Terminals of the matrix multiplication operation circuit Connect the terminals of the second-j resistance adjustment circuit. Terminals of the matrix multiplication operation circuit Connect the terminals of the 2Nth resistance adjustment circuit. Terminals of the matrix multiplication operation circuit Connection; Terminals of the 31st resistance adjustment circuit Terminals of the first secondary operational circuit Connect the terminals of the 3k resistance adjustment circuit. Terminals of the k-th second-level operational circuit Connections to the terminals in the 3L resistance adjustment circuit are as follows: Terminals of the Lth secondary operational circuit connect; Terminals of the matrix element storage module Terminals of the 11th resistance adjustment circuit Connection, ..., terminals of the matrix element storage module Terminals of the first j-th resistance adjustment circuit Connection, ..., terminals of the matrix element storage module Terminals of the 1N resistance adjustment circuit Connection; terminals of the matrix element storage module Terminals of the first sampling delay circuit Connection, ..., terminals of the matrix element storage module Terminals of the i-th sampling delay circuit Connection, ..., terminals of the matrix element storage module Terminals of the Mth sampling delay circuit Connection; terminals of the matrix element storage module Terminals of the first-stage operational circuit Connection, ..., terminals of the matrix element storage module Terminals of the j-th stage operational circuit Connection, ..., terminals of the matrix element storage module Terminals of the Nth stage operational circuit Connection; terminals of the matrix element storage module ... ... Terminals of the matrix multiplication operation circuit ... ... Corresponding connection; terminals of the matrix element storage module , , , Terminals of the matrix multiplication operation circuit , , , Corresponding connection; Terminals of the first-stage operational circuit Terminals of the j-th level operational circuit Terminals of the Nth level operational circuit The terminals of the matrix multiplication circuit are respectively connected to the terminals of the matrix multiplication circuit. Connections; terminals of the first-stage operational circuit Terminals of the matrix element storage and operation module Connections to the terminals of the j-th level operational circuit. Terminals of the matrix element storage and operation module Terminals of the Nth level operational circuit Terminals of the matrix element storage and operation module connect; Terminals of the matrix element storage and operation module Terminals of the 21st resistance adjustment circuit Terminals of the matrix element storage and operation module. Terminals of the 2j resistance adjustment circuit Terminals of the matrix element storage and operation module. Terminals of the 2N resistance adjustment circuit Connection; terminals of the matrix element storage and operation module , Terminals of the first secondary operational circuit , Corresponding connections, ..., terminals of the matrix element storage and operation module. , Terminals of the k-th second-level operational circuit , Corresponding connections, ..., terminals of the matrix element storage and operation module. , Terminals of the Lth secondary operational circuit , Connection; terminals of the matrix element storage and operation module Terminals of the matrix multiplication operation circuit Corresponding connection; Terminals of the first-level operational circuit , , , , , Terminals of the matrix multiplication operation circuit , , , , , Corresponding connections, ..., terminals of the k-th second-level operational circuit. , , , , , Terminals of the matrix multiplication operation circuit , , , , , Connect to the terminals of the Lth second-level operational circuit. , , , , , Terminals of the matrix multiplication operation circuit , , , , , Corresponding connection; Terminal of matrix operation result storage module Terminals of the first sampling delay circuit Connection, ..., terminals of the matrix operation result storage module Terminals of the i-th sampling delay circuit Connection, ..., terminals of the matrix operation result storage module Terminals of the Mth sampling delay circuit Connection; Terminal of the matrix operation result storage module Terminals of the 31st resistance adjustment circuit Connection, ..., terminals of the matrix operation result storage module Terminals of the 3k resistance adjustment circuit Connection, ..., terminals of the matrix operation result storage module Terminals of the 3L resistance adjustment circuit Connection; Terminal of the matrix operation result storage module Terminals of the matrix multiplication operation circuit Terminals of the matrix operation result storage module. Terminals of the matrix multiplication operation circuit Terminals of the matrix operation result storage module. Terminals of the matrix multiplication operation circuit connect; Terminals of matrix resistors Connected to GND; terminals of the matrix switch circuit. Terminals of the matrix multiplication operation circuit Connect the SEL terminal of the matrix switching circuit to the terminal of the matrix multiplication operation circuit. connect; The M sampling delay circuits in the matrix multiplication operation circuit are identical; each sampling delay circuit includes a first operational amplifier, a sampling delay NMOS transistor, a second operational amplifier, a sampling delay PMOS transistor, a third operational amplifier, a second sampling delay resistor, a first sampling delay resistor, a second capacitor, and a first capacitor; Terminals of the first operational amplifier Terminals of the sampling delay circuit Connections to the terminals of the first operational amplifier. The sampling delay NMOS transistor's drain and the terminals of the first operational amplifier. Connections; the gates of the sampling delay NMOS transistor and the sampling delay PMOS transistor, and the terminals of the sampling delay circuit. The sources of the sampling delay NMOS transistors are connected separately to the terminals of the first capacitor. and the terminals of the second operational amplifier Connections; Terminals of the second operational amplifier The source of the sampling delay PMOS transistor and the terminals of the second operational amplifier. Connections; the drain of the sampling delay PMOS transistor is connected to the terminals of the second capacitor. Terminals of the sampling delay circuit and the terminals of the third operational amplifier Connections; Terminals of the third operational amplifier Terminals of the first sampling delay resistor and the terminals of the second sampling delay resistor Connection, terminal of the third operational amplifier Terminals of the second sampling delay resistor and the terminals of the sampling delay circuit Connection; terminals of capacitor 1 Terminals of the second capacitor and the terminals of the first sampling delay resistor Connect to GND respectively; The matrix multiplication operation circuit has 2N+L identical resistance adjustment circuits; each resistance adjustment circuit includes a first counter, a D flip-flop, a fourth operational amplifier, a resistance adjustment NMOS transistor, a resistance adjustment PMOS transistor, a resistance adjustment logic NOT gate, a second counter, and an analog-to-digital converter; The terminals CLK of the first counter, CLK of the second counter, and CLK of the analog-to-digital converter are connected to the terminal CLK of the resistance adjustment circuit. The terminals MAX / MIN of the first counter are connected to the terminals CTEN of the first counter, CLK of the D flip-flop, and LOAD of the second counter. The terminal LOAD of the first counter is connected to the terminals D / U of the second counter, D of the D flip-flop, and the terminal of the resistance adjustment circuit. Connect the first counter's terminals D / U. ... ... Connected to GND; terminals of the D flip-flop Terminals of the 4th operational amplifier Connection, terminals of the D flip-flop The terminal CTEN of the second counter is connected, and the terminal R of the D flip-flop is connected to the terminal of the resistance-adjusting NOT gate. Connections; Terminals of the 4th operational amplifier Terminals of the 4th operational amplifier The drain of the resistance-adjustable NMOS transistor is connected to the source of the resistance-adjustable PMOS transistor and the terminals of the resistance adjustment circuit. Connections are made between the gate of the resistance-adjustable NMOS transistor and the gate of the resistance-adjustable PMOS transistor, and the terminals of the resistance adjustment circuit. Connections; the drain of the resistance-adjustable PMOS transistor is connected to GND; the terminals of the resistance-adjustable NOT gate. Connect to the MAX / MIN terminals of the second counter; the terminals of the second counter ... ... Terminals of the analog-to-digital converter ... ... Corresponding connection; terminals of the analog-to-digital converter Terminals of the resistance adjustment circuit Connection, terminals of the analog-to-digital converter Terminals of the resistance adjustment circuit connect; The matrix element storage module in the matrix multiplication operation circuit includes 2×M element storage NMOS transistors, M+1 element storage selectors, 2×N storage switch circuits, element storage logic NOT gates, and M×N element storage memristors. The gates of the 11th element storage NMOS transistor, ..., the gates of the 1ith element storage NMOS transistor, ..., the gates of the 1Mth element storage NMOS transistor, and the terminals of the matrix element storage module. ... ... Corresponding connections are made between the drains of the 11th element storage NMOS transistor, ..., the 1ith element storage NMOS transistor, ..., the 1Mth element storage NMOS transistor, and the terminals of the matrix element storage module. Connect the source of the 11th element storage NMOS transistor, ..., the source of the 1ith element storage NMOS transistor, ..., the source of the 1Mth element storage NMOS transistor to the terminal of the 11th element storage selector. Terminals of the storage gate for element 1i Terminals of the 1M element storage selector Corresponding connection; The gates of the 21st element storage NMOS transistor, ..., the gates of the 2i element storage NMOS transistors, ..., the gates of the 2M element storage NMOS transistors, and the terminals of the matrix element storage module. ... ... Correspondingly, the sources of the 21st element storage NMOS transistor, ..., the 2i element storage NMOS transistor, ..., and the 2M element storage NMOS transistor are respectively connected to the OUT terminal of the 2nd element storage selector. The drains of the 21st element storage NMOS transistor, ..., the 2i element storage NMOS transistor, ..., and the 2M element storage NMOS transistor are respectively connected to the 1_CHAN terminal of the 11th element storage selector, ..., the 1_CHAN terminal of the 1i element storage selector, ..., and the 1_CHAN terminal of the 1M element storage selector. Terminals SEL of the 11th element storage selector, ..., terminals SEL of the 1ith element storage selector, ..., terminals SEL of the 1Mth element storage selector, terminals SEL of the 11th storage switch circuit, ..., terminals SEL of the 1jth storage switch circuit, ..., terminals SEL of the 1Nth storage switch circuit, and terminals of the element storage NOT gate. The terminals of the matrix element storage module are respectively connected to the terminals of the matrix element storage module. Connections; the N elements in the first row store the terminals of the memristor. The terminals of the N element memory memristors in the i-th row are respectively connected to the OUT terminal of the 11th element memory selector, ..., the terminals of the N element memory memristors in the i-th row. The terminals of the N element memory gates in the Mth row are respectively connected to the OUT terminal of the 1i-th element memory gate, ..., the terminals of the N element memory gates in the Mth row. Connect to the OUT terminal of the 1M element storage selector respectively; Terminal 1_CHAN of the second element storage selector is connected to GND, and terminal 0_CHAN of the second element storage selector is connected to the terminal of the matrix element storage module. Connect the SEL terminal of the second element storage selector to the terminal of the matrix element storage module. connect; Terminals of the 11th storage switch circuit Terminals of the first j-th storage switch circuit Terminals of the 1Nth storage switch circuit Terminals of the matrix element storage module ... ... Corresponding connection, terminals of the 21st storage switch circuit Terminals of the second storage switch circuit Terminals of the 2Nth storage switch circuit Terminals of the matrix element storage module ... ... Correspondingly, the terminals SEL of the 21st storage switch circuit, ..., the terminals SEL of the 2jth storage switch circuit, ..., the terminals SEL of the 2Nth storage switch circuit are respectively connected to the terminals of the element storage logic NOT gate. connect; The M elements in column 1 store the terminals of the memristor. Terminals of the 11th storage switch circuit The M elements in column 1 store the terminals of the memristor. Terminals of the 21st storage switch circuit Connect the terminals of the M elements in the j-th column to store the memristor. Terminals of the first j storage switch circuit The terminals of the memristor are connected in the M elements of the j-th column. The terminals of the second j storage switch circuit are respectively connected to the terminals of the second j storage switch circuit. Connect the terminals of the M elements in the Nth column to store the memristor. Terminals of the 1Nth storage switch circuit The terminals of the memristor are connected in the M elements of the Nth column. Terminals of the 2Nth storage switch circuit connect; The matrix multiplication operation circuit has N identical first-stage operation circuits; each first-stage operation circuit includes a first-stage operation resistor, a second-stage operation resistor, a fourth-stage operation resistor, a sixth operational amplifier, a sixth-stage operation resistor, a third-stage operation resistor, a fifth operational amplifier, and a fifth-stage operation resistor; Terminals of the 5th operational amplifier Terminals of the first-level operational circuit and the terminals of the first stage operational resistor Connect the terminals of the 5th operational amplifier respectively. Terminals of the fifth operational resistor Connection, terminal of operational amplifier #5 Terminals of the first stage operational resistor and the terminals of the third-stage operational resistor Connect the terminals of the second-stage operational resistor respectively. Terminals of the first-level operational circuit Connection, terminals of the second-stage operational resistor Terminals of the third-stage operational resistor Terminals of the fourth stage operational resistor and the terminals of the 6th operational amplifier Connections; Terminals of the 6th operational amplifier Terminals of the 6th stage operational resistor Connection, terminal of operational amplifier #6 Terminals of the fourth stage operational resistor Terminals of the first-level operational circuit Connection; terminals of the fifth operational resistor. and the terminals of the 6th stage operational resistor Connect to GND respectively; The matrix element storage and operation module in the matrix multiplication operation circuit includes 2×N operation switch circuits, operation logic NOT gates, and N×L×2 operation memristors; The terminals of the 2×L operational memristors in the first row The terminals of the 11th operational switch circuit are respectively connected to the terminals of the 11th operational switch circuit. Connect the terminals of the 2×L operational memristors in the j-th row, ... The terminals of the first operational switch circuit are respectively connected to the terminals of the first operational switch circuit. Connect the terminals of the 2×L operational memristors in the Nth row, ... The terminals of the 1Nth operational switching circuit are respectively connected to the terminals of the 1Nth operational switching circuit. connect; The terminals of the 2×L operational memristors in the first row The terminals of the 21st operational switch circuit are respectively connected to the terminals of the 21st operational switch circuit. Connect the terminals of the 2×L operational memristors in the j-th row, ... The terminals of the second operational switch circuit are respectively connected to the terminals of the second operational switch circuit. Connect the terminals of the 2×L operational memristors in the Nth row, ... The terminals of the 2Nth operational switching circuit are respectively connected to connect; Terminals of the 11th operational switch circuit Terminals of the matrix element storage and operation module Connect the terminals of the 1j operational switch circuit. Terminals of the matrix element storage and operation module Connect the terminals of the 1Nth operational switch circuit. Terminals of the matrix element storage and operation module The terminals SEL of the 11th operational switch circuit, ..., the terminals SEL of the 1jth operational switch circuit, ..., the terminals SEL of the 1Nth operational switch circuit are respectively connected to the terminals of the operational logic NOT gate. connect; Terminals of the 21st operational switch circuit Terminals of the matrix element storage and operation module Connect the terminals of the second operational switch circuit. Terminals of the matrix element storage and operation module Connect the terminals of the 2Nth operational switch circuit. Terminals of the matrix element storage and operation module The terminals SEL of the 21st operational switch circuit, ..., the terminals SEL of the 2jth operational switch circuit, ..., the terminals SEL of the 2Nth operational switch circuit are respectively connected to the terminals of the operational logic NOT gate. The terminals SEL of the 21st operational switch circuit, ..., the terminals SEL of the 2jth operational switch circuit, ..., the terminals SEL of the 2Nth operational switch circuit are respectively connected to the terminals of the matrix element storage and operation module. connect; The terminals of the N operational memristors in column 1 Terminals of the matrix element storage and operation modules respectively Connect the terminals of the N operational memristors in column 2. Terminals of the matrix element storage and operation modules respectively Connect the terminals of the N operational memristors in column 2×k-1, ... Terminals of the matrix element storage and operation modules respectively Connect the terminals of the N operational memristors in column 2×k. Terminals of the matrix element storage and operation modules respectively Connect the terminals of the N operational memristors in column 2×L-1, ... Terminals of the matrix element storage and operation modules respectively Connect the terminals of the N operational memristors in column 2×L. Terminals of the matrix element storage and operation modules respectively connect; The matrix multiplication circuit has L identical secondary operational circuits; each secondary operational circuit includes a secondary operational selector A, a secondary operational NMOS transistor A, a first secondary operational resistor, a seventh operational amplifier, a second secondary operational resistor, a fourth secondary operational resistor, a third secondary operational resistor, an eighth secondary operational resistor, a tenth secondary operational resistor, a tenth operational amplifier, an eleventh secondary operational resistor, a ninth secondary operational resistor, a ninth operational amplifier, a seventh secondary operational resistor, a sixth secondary operational resistor, an eighth operational amplifier, a fifth secondary operational resistor, a secondary operational selector C, a twelfth secondary operational resistor, a secondary operational NMOS transistor B, and a secondary operational selector B. The OUT terminal of the second-level operational selector A is connected to the terminal of the second-level operational circuit. The connection is as follows: Terminal 1_CHAN of the second-stage operational selector A is connected to the drain of the second-stage operational NMOS transistor A; Terminal 0_CHAN of the second-stage operational selector A is connected to the terminal of the 7th operational amplifier. and the terminals of the second-stage operational resistor Connect the terminals SEL of the secondary operational selector A to SEL of the secondary operational selector B, and connect them to the terminals of the secondary operational circuit. Connect them separately; The gate of the second-level operational NMOS transistor A and the terminals of the second-level operational circuit. The source of the second-level operational NMOS transistor A is connected to the source of the second-level operational NMOS transistor B and the OUT terminal of the second-level operational selector C, respectively. Terminals of the first-level operational resistor Terminals of the 8th secondary operational resistor Terminals of the 11th secondary operational resistor Terminals of the fifth secondary operational resistor Terminal 1_CHAN of the second-level operational selector C is connected to GND respectively; Terminals of the 7th operational amplifier Terminals of the first secondary operational resistor Connection, terminals of the 7th operational amplifier Terminals of the second-stage operational resistor and the terminals of the third secondary operational resistor connect; Terminals of the 10th operational amplifier Terminals of the 11th secondary operational resistor Connection, terminal of operational amplifier number 10 Terminals of the third secondary operational resistor Terminals of the 10th secondary operational resistor and the terminals of the 9th secondary operational resistor Connection, terminal of operational amplifier number 10 Terminals of the 10th secondary operational resistor Terminals of the secondary operational circuit connect; Terminals of the 9th operational amplifier Terminals of the 8th secondary operational resistor Connection, terminal of operational amplifier No. 9 Terminals of the 6th secondary operational resistor Terminals of the 12th operational resistor and the terminals of the 7th secondary operational resistor Connection, terminal of operational amplifier No. 9 Terminals of the 7th secondary operational resistor and the terminals of the 9th secondary operational resistor Connection; Terminals of the 12th operational resistor Terminals of the secondary operational circuit connect; Terminals of the 8th operational amplifier Terminals of the fifth secondary operational resistor Connection, terminal of operational amplifier #8 Terminals of the fourth secondary operational resistor Connect the terminal 0_CHAN of the second-stage operational selector B to the terminal of the 8th operational amplifier. Terminals of the fourth secondary operational resistor and the terminals of the 6th secondary operational resistor connect; The SEL terminal of the second-level operational selector C is connected to the terminal of the second-level operational circuit. Connect the terminal 0_CHAN of the secondary operational selector C to the terminal of the secondary operational circuit. connect; The OUT terminal of the second-level operational selector B is connected to the terminal of the second-level operational circuit. The connection is as follows: Terminal 1_CHAN of the secondary operational selector B is connected to the drain of the secondary operational NMOS transistor B; the gate of the secondary operational NMOS transistor B is connected to the terminal of the secondary operational circuit. connect; The matrix operation result storage module in the matrix multiplication operation circuit includes M×L result storage memristors, M×L result storage NMOS transistors, M result switching circuits, result storage logic NOT gates, and result storage selectors; The M results in column 1 store the terminals of the memristor. The terminals of the matrix operation result storage module are respectively connected to the terminals of the matrix operation result storage module. Connect the terminals of the M results stored in the k-th column of the memristor. The terminals of the matrix operation result storage module are respectively connected to the terminals of the matrix operation result storage module. Connect the terminals of the Mth result storage memristor in column L, ... The terminals of the matrix operation result storage module are respectively connected to the terminals of the matrix operation result storage module. Connections; the terminals of the M results stored in column 1 of the memristor. The terminals of the M result storage memristors in the k-th column are connected to the drains of their respective result storage NMOS transistors, ... The terminals of the M result storage memristors in the Lth column are connected to the drains of their respective result storage NMOS transistors, ... Connect to the drain of the corresponding result storage NMOS transistor; The sources of the M×L result storage NMOS transistors are connected to the OUT terminal of the result storage selector, and the gates of the L result storage NMOS transistors in the first row are connected to the terminals of the matrix operation result storage module. The gates of the L result storage NMOS transistors in the i-th row are connected to the terminals of the matrix operation result storage module, respectively. The gates of the L result storage NMOS transistors in the Mth row are connected to the terminals of the matrix operation result storage module, respectively. Connections; the gates of the NMOS transistors storing the L results in the first row are respectively connected to the terminals of the first result switching circuit. The gates of the L result storage NMOS transistors in the i-th row are connected to the terminals of the i-th result switching circuit, respectively. The gates of the NMOS transistors storing the L results in the Mth row are connected to the terminals of the Mth result switching circuit, respectively. connect; The first result is the terminals of the switching circuit. Terminals of the i-th result switching circuit Terminals of the Mth result switching circuit The terminals of the matrix operation result storage module are respectively connected to the terminals of the matrix operation result storage module. The first result is the terminals of the switching circuit. The terminals SEL of the i-th result switching circuit, ..., the M-th result switching circuit are respectively connected to the terminals of the result storage logic NOT gate. connect; The result is stored in the terminals of the NOT gate. Terminal SEL of the result storage gating and terminals of the matrix operation result storage module ; Terminal 1_CHAN of the result storage selector is connected to GND, and terminal 0_CHAN of the result storage selector is connected to the terminal of the matrix operation result storage module. connect; The matrix switching circuit in the matrix multiplication operation circuit includes matrix switch NMOS transistor A and matrix switch NMOS transistor B; The drain of NMOS transistor A in the matrix switch and the terminals of the matrix switch circuit. The connections are as follows: the source of matrix switch NMOS transistor A is connected to the source of matrix switch NMOS transistor B; the gate of matrix switch NMOS transistor A is connected to the SEL terminal of the matrix switch circuit and the gate of matrix switch NMOS transistor B, respectively; the drain of matrix switch NMOS transistor B is connected to the terminal of the matrix switch circuit. connect; The 2N storage switch circuits in the matrix element storage module, the 2N operation switch circuits in the matrix element storage and operation module, and the M result switch circuits in the matrix operation result storage module are all the same as the matrix switch circuits in the matrix multiplication operation circuit based on memristor array.

3. The method of using the matrix multiplication circuit based on memristor array according to claim 2, characterized in that... The first operational amplifier is any one of a general-purpose, high-speed, or low-power operational amplifier; the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth operational amplifiers are the same.

4. The method of using the matrix multiplication circuit based on memristor array according to claim 2, characterized in that... The M×N element storage memristors in the matrix element storage module, the N×L×2 operational memristors in the matrix element storage and operation module, and the M×L result storage memristors in the matrix operation result storage module are the same; all of the M×N element storage memristors in the matrix element storage module, the N×L×2 operational memristors in the matrix element storage and operation module, and the M×L result storage memristors in the matrix operation result storage module are memristors with threshold voltages.

5. The method of using the matrix multiplication circuit based on memristor array according to claim 2, characterized in that... The resistance values ​​of the second-level operational resistor, the third-level operational resistor, and the fourth-level operational resistor are the same.

6. The method of using the matrix multiplication circuit based on memristor array according to claim 2, characterized in that... The resistance values ​​of the second and fourth operational resistors are the same.

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