Method for fabricating low-dimensional semiconductor material transistor based on plasma processing

Abstract

The application belongs to the technical field of semiconductor devices, and particularly relates to a preparation method of a low-dimensional semiconductor material transistor based on plasma processing. The method comprises the following steps: providing a workpiece of a low-dimensional semiconductor material structure and preparing a sample; introducing a gas into a vacuum chamber to form plasma by ionization, and reacting with the low-dimensional semiconductor material of a source / drain contact area; depositing an electrode in situ in a vacuum to form a source / drain contact area of the low-dimensional semiconductor material and the electrode; and finally performing a stripping process to complete the preparation of the transistor. The application can reduce the interface state defect density of the low-dimensional semiconductor material and the source / drain contact area of the electrode, the Fermi pinning effect, improve the on-state current density of the transistor, and increase the reliability and device yield of the chip components on the semiconductor material wafer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a method for fabricating transistors using low-dimensional semiconductor materials. Background Technology

[0002] Plasma consists of partially ionized charged atomic nuclei and electrons, as well as unionized neutral particles, and is generally neutral. Its main applications in semiconductor technology are etching and surface cleaning. Plasma processing, a derived material processing technology, is also a mature material processing technique. Plasma processing technology aimed at improving the reliability and yield of chip devices on low-dimensional semiconductor wafers has gradually proven its effectiveness. Meanwhile, transistors fabricated based on low-dimensional semiconductor materials theoretically possess high device mobility and on-state current density; however, actual results differ significantly from theoretical values. One important factor is the formation of a high electrode contact barrier. The conventional contact method between low-dimensional semiconductor transistors and electrodes involves depositing metal electrodes on the surface of the low-dimensional semiconductor material. The contact interface between the metal and the low-dimensional semiconductor material surface may produce uneven van der Waals (vdW) gaps. High-energy metals may also enter the lattice of the low-dimensional semiconductor material in some areas, forming defects. Mismatched plasma atmospheres and energy selections can also cause unintended doping or the formation of unintended defects in low-dimensional semiconductor materials with a thickness of less than 10 nm. These factors together lead to the generation of metal-induced gap states (MIGS) and an undesirable Schottky barrier (SB) in the source / drain contact region, resulting in Fermi level pinning (FLP) and high contact resistance (RC).

[0003] Therefore, a method for effectively fabricating high-current-density low-dimensional semiconductor transistors based on plasma treatment is desired. After plasma treatment, electrodes are deposited in situ in a vacuum to avoid contamination of the activated material surface by impurities. Electrode deposition under clean contact interface conditions reduces the interface state defect density and Fermi pinning effect in the source / drain contact region between the low-dimensional semiconductor material and the electrode, improves the on-state current density of the low-dimensional semiconductor transistor, makes the threshold voltage of the transistor adjustable, and increases the reliability and device yield of chip components on the low-dimensional semiconductor wafer. Summary of the Invention

[0004] The purpose of this invention is to propose a method for fabricating low-dimensional semiconductor transistors with high current density based on plasma processing, so as to effectively improve the on-state current density of low-dimensional semiconductor transistors.

[0005] The method for fabricating low-dimensional semiconductor material transistors based on plasma processing provided by this invention includes the following specific steps:

[0006] (1) Provide a workpiece with a low-dimensional semiconductor material structure and prepare it into a sample; specifically including:

[0007] The source / drain contact area of ​​the low-dimensional semiconductor material and the electrode is patterned using photolithography or masking to form a window in the source / drain contact area, and the sample is fixed on a movable stage in a vacuum process chamber.

[0008] (2) The vacuum process chamber is evacuated to a background vacuum level of less than 5.0E-2 Pa to remove residual gas from the vacuum process chamber.

[0009] (3) Plasma treatment of low-dimensional semiconductor materials is performed in a vacuum process chamber, and electrodes are deposited in situ to form source / drain contact regions between the low-dimensional semiconductor materials and the electrodes; the specific process includes:

[0010] (3.1) Gas is introduced into the vacuum process chamber to ionize the gas and form plasma, which then reacts with the low-dimensional semiconductor material in the source / drain contact region;

[0011] (3.2) Then, an electrode is deposited under the in-situ vacuum to form the source / drain contact region between the low-dimensional semiconductor material and the electrode in the process chamber;

[0012] (3.3) Finally, the stripping process is performed to define the channel of the transistor and complete the fabrication of the transistor.

[0013] Optionally, the low-dimensional semiconductor material includes zero-dimensional, one-dimensional, or two-dimensional materials exhibiting semiconductor properties, and the thickness of the low-dimensional semiconductor material ranges from sub-1 nm to 80 nm of a single atomic layer; the workpiece having a low-dimensional semiconductor material structure includes a substrate and the low-dimensional semiconductor material.

[0014] Optionally, the in-situ vacuum deposition electrode is the same vacuum process chamber environment after the plasma reacts with the low-dimensional semiconductor material and the gas path is closed, or two or more connected process chamber environments that are both vacuum, so that the electrode is deposited in situ after plasma treatment is performed on the source / drain contact area between the low-dimensional semiconductor material and the electrode.

[0015] Optionally, the deposited electrode is achieved by vacuum thermal evaporation, electron beam evaporation, or sputtering deposition, and the thickness of the deposited electrode ranges from 1 nm to 1000 nm, in order to form the source / drain contact region between the low-dimensional semiconductor material and the electrode.

[0016] Optionally, the gas includes one or more of nitrogen (N2), oxygen (O2), hydrogen (H2), argon (Ar), argon / hydrogen mixture (Ar / H2), ammonia (NH3), hydrogen sulfide (H2S), chlorine (Cl2), carbon tetrafluoride (CF4), and sulfur hexafluoride (SF6), which are ionized to form plasma and react with the low-dimensional semiconductor material before the electrode is deposited in situ under vacuum.

[0017] Optionally, the electrode is deposited in situ under vacuum after the gas ionization forms plasma and reacts with the low-dimensional semiconductor material, wherein the process conditions include:

[0018] During plasma processing, the vacuum level of the process chamber ranges from 0.05 Pa to 20 Pa, the gas flow rate ranges from 5 sccm to 500 sccm, the power of the radio frequency power supply for plasmaizing the gas ranges from 1 W to 3500 W, the power supply power for providing bias voltage connected to the stage ranges from 1 W to 4500 W, the plasma processing time ranges from 5 s to 7200 s, the distance between the target material and the device for placing the target material and the sample is 5 cm–250 cm, and the electrode deposition rate ranges from 0.1 Å / s to 100 Å / s.

[0019] Optionally, prior to plasma treatment of the in-situ deposited electrode, the following steps are also included:

[0020] The horizontal and vertical positions and rotation speed of the movable stage within the chamber are set; one or more of the gases are introduced into the vacuum process chamber; the power of the radio frequency power supply that plasmaizes the gas and the power of the bias power supply connected to the stage are set; the corresponding power supply is turned on; and the process time is set; then, under the in-situ vacuum conditions, the electrode is deposited in the source / drain contact region.

[0021] The features and beneficial effects of this invention compared to the prior art are as follows:

[0022] This invention involves plasma treatment of the source / drain contact region of a low-dimensional semiconductor material with an electrode, followed by in-situ vacuum deposition of the electrode. This process prevents the low-dimensional semiconductor material with an active surface from being contaminated by environmental impurities. Simultaneously, the plasma treatment of the low-dimensional semiconductor material improves the energy level matching between the low-dimensional semiconductor material and the electrode interface, thereby reducing the interface state defect density and Fermi pinning effect in the source / drain contact region. This increases the on-state current density of the low-dimensional semiconductor material transistor by two times or more, makes the transistor's threshold voltage adjustable, and enhances the reliability and yield of on-chip devices based on the low-dimensional semiconductor material wafer. It is expected to be applied in future integrated circuit processing and industrial production based on wafer-level low-dimensional semiconductor materials.

[0023] The present invention also has other features and beneficial effects described in the accompanying drawings and detailed embodiments herein, which will be apparent from or will be set forth in detail in the accompanying drawings and detailed embodiments incorporated herein, which together serve to explain the particular principles of the invention. Attached Figure Description

[0024] Figure 1 This is a flowchart of the method for fabricating low-dimensional semiconductor material transistors based on plasma processing according to the present invention.

[0025] Figure 2 This is a schematic diagram of the plasma processing-in-situ vacuum deposition electrode integrated device that relates to the present invention.

[0026] Figure 3 The steps are as follows: (1) is a schematic diagram of providing a substrate; (2) is a schematic diagram of obtaining a low-dimensional semiconductor material on the substrate; (3) is a schematic diagram of the photoresist coating step of the photolithography process selected in the embodiment; and (4) is a schematic diagram of the photoresist window of the source / drain region of the low-dimensional semiconductor material and the electrode selected in the embodiment.

[0027] Figure 4 The following is a schematic diagram of the steps of in-situ vacuum deposition of electrodes after plasma treatment in Example 1, wherein (1) is a schematic diagram of the beginning stage of plasma treatment; (2) is a schematic diagram of plasma treatment after a period of time; (3) is a schematic diagram of in-situ vacuum deposition of electrodes after plasma treatment; and (4) is a schematic diagram of the process after stripping.

[0028] Figure 5 The following is a schematic diagram of the steps of in-situ vacuum deposition of electrodes after plasma treatment in Example 2, wherein (1) is a schematic diagram of the beginning stage of plasma treatment; (2) is a schematic diagram of forming a low-dimensional semiconductor material window after plasma treatment; (3) is a schematic diagram of in-situ vacuum deposition of electrodes after forming a low-dimensional semiconductor material window; and (4) is a schematic diagram after the stripping process.

[0029] Figure 6 The following are structural diagrams of the high current density low-dimensional semiconductor material transistor based on plasma processing according to the present invention, wherein (1) is a front view structural diagram of the transistor prepared in Example 1; (2) is a front view structural diagram of the transistor prepared in Example 2; and (3) is a top view structural diagram of the transistor prepared in the example.

[0030] The diagram is labeled as follows: 1 is the plasma processing chamber, 11 is the power supply providing bias voltage, 12 is the movable stage, 13 is the sample, 14 is the coil, 15 is the RF power supply, 16 is the quartz tube device, 17 is the valve controlling the gas flow rate, 2 is the electrode deposition chamber, 21 is the valve connecting the chambers, 22 is the target material for the electrode to be deposited and the device for placing the target material, 3 is the low-dimensional semiconductor material substrate, 4 is the low-dimensional semiconductor material, 5 is the photoresist, 6 is the plasma, 7 is the low-dimensional semiconductor material region processed by plasma, 8 is the electrode material to be deposited in vacuum, 9 is the deposited electrode material, and 10 is the low-dimensional semiconductor material window formed by plasma processing under bias voltage. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to embodiments and accompanying drawings. It should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components. The terms "upper," "middle," and "lower," and the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Preferred embodiments are provided in this invention to make the invention more thorough and complete, and to fully convey the scope of the invention to those skilled in the art. However, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0032] The present invention provides a method for fabricating low-dimensional semiconductor material transistors based on plasma processing, such as... Figure 1 As shown, it includes the following steps:

[0033] S1. Provide a substrate;

[0034] Specifically, such as Figure 3 As shown in (1), the substrate 3 includes substrates commonly used in the art, which can be one of silicon wafer, quartz glass, sapphire, or flexible PI;

[0035] Preferably, the substrate 3 is a silicon wafer, comprising a silicon layer and a silicon dioxide layer, wherein the silicon layer is p-type heavily doped silicon, and the silicon dioxide layer is silicon dioxide with a thickness of 100 nm to 300 nm grown by thermal oxidation.

[0036] S2, such as Figure 3 (2) As shown, a low-dimensional semiconductor material 4 is grown or transferred on the substrate 3;

[0037] Specifically, low-dimensional semiconductor materials include zero-dimensional, one-dimensional, or two-dimensional materials exhibiting semiconductor properties. Zero-dimensional materials are quantum dots or nanoparticles; one-dimensional semiconductor materials are materials with a one-dimensional carrier transport dimension; and common two-dimensional materials are materials with a two-dimensional carrier transport dimension. The thickness of the low-dimensional semiconductor material is less than 80 nm.

[0038] Preferably, the zero-dimensional semiconductor material is gallium arsenide quantum dot or indium gallium arsenide quantum well; the one-dimensional semiconductor material is carbon nanotube or carbon nanowire; and the two-dimensional semiconductor material is molybdenum disulfide, tungsten disulfide, or graphene with semiconductor properties. The low-dimensional semiconductor material 4 on the substrate 3 is one or more of the above-mentioned low-dimensional semiconductor materials.

[0039] S3. Pattern the source / drain electrode regions of low-dimensional semiconductor materials;

[0040] Specifically, such as Figure 3 As shown in (3), the photolithography process is used to expose the photoresist 5 to form a photoresist window.

[0041] S4. Place the sample to be processed using the process of this invention into the process chamber and evacuate it to a vacuum.

[0042] Specifically, such as Figure 2 As shown, the vacuum level of the etching process chamber 1 and the deposition electrode process chamber 2 can reach below 5.0E-2Pa. The sample 13 is fixed on the movable stage 12 and a vacuum is drawn.

[0043] Preferably, the background vacuum is 1.0E-4 Pa.

[0044] S5. Perform plasma treatment on the sample;

[0045] Specifically, such as Figure 2 As shown, the horizontal position, vertical position and rotation speed of the movable stage 12 in the chamber are set, the valve 17 for controlling the gas flow rate is opened, the gas flow rate is set, and gas is introduced into the plasma processing chamber 1. The radio frequency power supply 15 that plasmaizes the gas is connected to the quartz tube device 16 or directly to the plasma processing chamber 1. The power of the radio frequency power supply 15 that plasmaizes the gas and the power of the power supply device 11 that provides bias voltage connected to the stage are set, the corresponding power supplies are turned on, and the plasma processing time is set.

[0046] Preferably, the power supply device 11 that provides bias voltage and is connected to the stage is in reactive ion etching (RIE) mode or plasma etching (PE) mode.

[0047] Specifically, the gas includes one or more of nitrogen (N2), oxygen (O2), hydrogen (H2), argon (Ar), argon / hydrogen mixture (Ar / H2), ammonia (NH3), hydrogen sulfide (H2S), chlorine (Cl2), carbon tetrafluoride (CF4), and sulfur hexafluoride (SF6); the vacuum degree of the process chamber during plasma treatment ranges from 0.05 Pa to 20 Pa, the gas flow rate ranges from 5 sccm to 500 sccm, the power of the radio frequency power supply for plasmaizing the gas is from 1 W to 3500 W, the power of the bias power supply connected to the stage is from 1 W to 4500 W, and the plasma treatment process time is from 5 s to 7200 s.

[0048] Preferably, the gas intake method for generating plasma is either intake through the quartz tube device 16 or a chamber surround type, with multiple air inlets simultaneously intakeing around the plasma processing chamber 1.

[0049] S6, In-situ vacuum deposition electrode;

[0050] Specifically, such as Figure 2 As shown, after plasma treatment, the gas path, corresponding valves, and corresponding power supply are closed, and the system is evacuated to the background vacuum level. Valve 21 connecting the chambers is opened. Under in-situ vacuum conditions, the distance between the target material and the device for placing the target material and the sample is 5 cm–250 cm, and the electrode deposition rate is 0.1 Å / s to 100 Å / s. Electrode deposition is achieved using vacuum thermal evaporation, electron beam evaporation, or sputtering. The deposition electrode thickness ranges from 1 nm to 1000 nm. The electrode material is a commonly used material in this field, and can be a metal electrode material or a TiN compound electrode material.

[0051] S7, peeling process;

[0052] Specifically, sampling is performed after electrode deposition, such as... Figure 4 (4) and Figure 5 (4) shows the photoresist that removes the masking effect.

[0053] S8. Define the channel of the transistor and complete the transistor fabrication;

[0054] Specifically, such as Figure 6 As shown, low-dimensional semiconductor materials outside the etched channel region are used to fabricate low-dimensional semiconductor material transistors with a back gate structure.

[0055] Example 1, corresponding Figure 1 The preparation method flowchart, corresponding to Figure 2 Integrated equipment, corresponding Figure 3 A device structure diagram showing the steps preceding the formation of the source / drain contact region between the low-dimensional semiconductor material and the electrodes, corresponding to... Figure 4 A schematic diagram of the structure of the in-situ vacuum deposition electrode step after plasma treatment, corresponding to... Figure 6 (1) and Figure 6 (3) Front and top view structural diagrams of low-dimensional semiconductor material transistors:

[0056] like Figure 3 As shown, substrate 3 is a substrate structure in which 280 nm silicon oxide is grown by thermal oxidation on p-type heavily doped silicon. The low-dimensional semiconductor material 4 is a monolayer of molybdenum disulfide grown in situ on silicon oxide by metal-organic chemical vapor deposition, and photoresist is spin-coated to form the photoresist window of the source / drain region of the low-dimensional semiconductor material and the electrode.

[0057] The monolayer molybdenum disulfide sample after the photoresist window is formed is placed in the process chamber and fixed on the movable stage 12. The vacuum degree is 8.0E-5 Pa. The horizontal and vertical positions of the movable stage 12 are both in the middle of the chamber, and the rotation speed is 5 r / min.

[0058] like Figure 2 As shown, nitrogen is introduced, and the gas flow rate in the quartz tube device 16 is set to 100 sccm. The valve 17, connected to the quartz tube device 16, controlling the gas flow rate, is opened. The vacuum level in the plasma processing chamber 1 is adjusted to 3 Pa. The power of the radio frequency power supply 15 connected to the quartz tube, used for gas plasmaization, is set to 10 W. The corresponding power supply is then turned on. Figure 4 (1) and Figure 4 (2) As shown, plasma 6 is nitrogen plasma, and the processing time is 60 s. As the process progresses, the depth of the low-dimensional semiconductor material region 7 treated by plasma increases. After the plasma treatment, the gas path, corresponding valves, and corresponding power supply are closed, and the vacuum is evacuated to the background vacuum level. The valve 21 connecting the chambers is opened. Under in-situ vacuum conditions, the distance between the target material to be deposited and the device for placing the target material and the sample is 100 cm, and the electrode deposition rate is 3 Å / s. Vacuum thermal evaporation deposition process is used to deposit metallic materials such as gold. Figure 4 As shown in (3), the thickness is 100 nm. Samples were taken after electrode deposition, as shown in... Figure 4 (4) shows the photoresist that removes the masking effect.

[0059] Define the channel of the transistor and complete the transistor fabrication. Figure 6 (1) is a front view of the transistor structure in this embodiment. Figure 6 (3) is a top view of the transistor structure in this embodiment.

[0060] Example 2, corresponding Figure 1 The preparation method flowchart, corresponding to Figure 2 Integrated equipment, corresponding Figure 3A device structure diagram showing the steps preceding the formation of the source / drain contact region between the low-dimensional semiconductor material and the electrodes, corresponding to... Figure 5 A schematic diagram of the structure of the in-situ vacuum deposition electrode step after plasma treatment, corresponding to... Figure 6 (1) and Figure 6 (3) Front and top view structural diagrams of low-dimensional semiconductor material transistors:

[0061] like Figure 3 As shown, substrate 3 is a substrate structure in which 280 nm silicon oxide is grown by thermal oxidation on p-type heavily doped silicon. The low-dimensional semiconductor material 4 is a monolayer of molybdenum disulfide grown in situ on silicon oxide by chemical vapor deposition, and photoresist is spin-coated to form the photoresist window of the source / drain region of the low-dimensional semiconductor material and the electrode.

[0062] The monolayer molybdenum disulfide sample after the photoresist window is formed is placed in the process chamber and fixed on the movable stage 12. The vacuum degree is 9E-5 Pa. The horizontal and vertical positions of the movable stage 12 are both in the middle of the chamber, and the rotation speed is 3 r / min.

[0063] like Figure 2 As shown, the introduced gas is argon. The gas inlet, directly connected to the plasma processing chamber 1, is set to a gas flow rate of 300 sccm. The valve 17 controlling the gas flow rate is opened, and the vacuum level of the plasma processing chamber is adjusted to 0.8 Pa. The power supply 11 providing bias voltage is a reactive ion etching (RIE) device, set to a power of 500 W. The RF power supply 15, connected to the quartz tube, which plasmaizes the gas, is also set to a power of 500 W. The corresponding power supplies are turned on. Figure 5 (1) and Figure 5 As shown in (2), plasma 6 is argon plasma, and the processing time is 60 s. As the process proceeds, the depth of the low-dimensional semiconductor material region 7 treated by plasma increases. After a period of time, a low-dimensional semiconductor material window 10 formed by plasma treatment under bias voltage appears. After the plasma treatment is completed, the gas path, corresponding valves, and corresponding power supply are closed, and the vacuum is evacuated to the background vacuum level. The valve 21 connecting the chambers is opened. Under in-situ vacuum conditions, the distance between the target material to be deposited and the device for placing the target material and the sample is 100 cm, and the electrode deposition rate is 10 Å / s. The metal material gold is deposited using vacuum electron beam evaporation process, such as... Figure 5 As shown in (3), the thickness is 100 nm. Samples were taken after electrode deposition, as shown in... Figure 5 (4) shows the photoresist that removes the masking effect.

[0064] Define the channel of the transistor and complete the transistor fabrication. Figure 6 (2) is a front view of the transistor structure in this embodiment. Figure 6(3) is a top view of the transistor structure in this embodiment.

[0065] Table 1 shows the statistical comparison of the performance indicators of the transistors prepared in Examples 1 and 2 with those prepared by prior art.

[0066] Table 1

[0067] .

[0068] Apart from the differences noted in the table, the fabrication process and testing methods for the transistors are completely identical. Therefore, this method can effectively improve the on-state current density of low-dimensional semiconductor transistors and regulate the threshold voltage.

[0069] Example 2 is similar to Example 1, except that the plasma gas, gas flow rate, the power supply device 11 providing bias voltage selected and its set power, the power of the radio frequency power supply 15 and the processing time are chosen, and the transistors fabricated are as follows: Figure 6 (1) and Figure 6 (2) As shown, in Example 1, the electrode and molybdenum disulfide are in contact at the top, while in Example 2, the electrode and molybdenum disulfide are in contact at the edge.

[0070] The specific embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for fabricating a low-dimensional semiconductor material transistor based on plasma processing, characterized in that, The specific steps are: (1) providing a workpiece with a low-dimensional semiconductor material structure and preparing a sample; specifically including: using a photolithography process or a mask process to pattern the low-dimensional semiconductor material and the source / drain contact area of the electrode to form a window in the source / drain contact area, and fixing the sample on a movable sample stage in a vacuum process chamber; (2) performing vacuum treatment on the vacuum process chamber, with a base vacuum degree less than 5.0E-2 Pa, to clean residual gas in the vacuum process chamber; (3) performing plasma treatment on the low-dimensional semiconductor material in the vacuum process chamber, and depositing an electrode in situ under vacuum to form a source / drain contact area of the low-dimensional semiconductor material and the electrode; the specific process includes: (3.1) introducing a gas into the vacuum process chamber to ionize the gas to form a plasma and react with the low-dimensional semiconductor material in the source / drain contact area; (3.2) then, depositing an electrode under the in-situ vacuum to form a source / drain contact area of the low-dimensional semiconductor material and the electrode in the process chamber; (3.3) finally, performing a stripping process to define the channel of the transistor and complete the preparation of the transistor; The electrode is deposited in situ under vacuum after the plasma reacts with the low-dimensional semiconductor material, that is, in the same vacuum process chamber environment after the gas path is closed or in the environment of two or more connected process chambers under vacuum, to deposit the electrode in situ under vacuum after plasma treatment on the low-dimensional semiconductor material and the source / drain contact area of the electrode; The electrode is deposited by vacuum thermal evaporation, electron beam evaporation or sputtering, and the thickness of the deposited electrode ranges from 1 nm to 1000 nm to form the source / drain contact area of the low-dimensional semiconductor material and the electrode; After the gas is ionized to form a plasma and reacts with the low-dimensional semiconductor material, the electrode is deposited in situ under the vacuum, and the process conditions are: During the plasma treatment process, the process chamber vacuum degree ranges from 0.05 Pa to 20 Pa, the gas flow rate ranges from 5 sccm to 500 sccm, the radio frequency power for plasma formation of the gas is 1 W to 3500 W, the power of the bias power supply device connected to the sample stage is 1 W to 4500 W, the plasma treatment process time is 5 s to 7200 s, the distance between the target material for depositing the electrode and the device for placing the target material and the sample is 5 cm - 250 cm, and the electrode deposition rate is 0.1 Å / s to 100 Å / s.

2. The production method according to claim 1, characterized by, The low-dimensional semiconductor material includes zero-dimensional, one-dimensional or two-dimensional materials with semiconductor properties, and the thickness of the low-dimensional semiconductor material ranges from sub-1 nm to 80 nm of a single atomic layer; the workpiece with a low-dimensional semiconductor material structure includes a substrate and the low-dimensional semiconductor material.

3. The preparation method according to claim 2, characterized in that, The gas is one or more of nitrogen, oxygen, hydrogen, argon, argon-hydrogen mixture, ammonia, hydrogen sulfide, chlorine, carbon tetrafluoride, and sulfur hexafluoride; the electrode is deposited in situ under vacuum after the plasma formed by ionization reacts with the low-dimensional semiconductor material.

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