Method and system for monitoring and controlling semiconductor processes

Abstract

A method and system for monitoring and controlling semiconductor processes are provided. The method includes forming at least one active region on a substrate; forming a first patterned photoresist layer on the at least one active region for defining at least two word lines after forming the at least one active region; detecting and measuring a position and a size of the at least one active region and the first patterned photoresist layer, and calculating an estimated area of at least two estimated contact holes in the at least one active region according to a predefined position of at least one bit line; adjusting the predefined position of the at least one bit line according to the estimated area of the at least two estimated contact holes in the at least one active region; and forming a second patterned photoresist layer on the substrate, the second patterned photoresist layer corresponding to the adjusted predefined position of the bit line.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method and system for monitoring and controlling a semiconductor process. BACKGROUND

[0002] Lithography is a key step in semiconductor process, which is used to define the position of each component on a substrate. Therefore, lithography is often the bottleneck of semiconductor process. In lithography, good alignment and control of circuit critical dimension are important to the yield of product.

[0003] Therefore, in semiconductor manufacturing, how to coordinate the process steps, inspect whether the components produce unexpected overlapping phenomenon, and then take corresponding correction method, is an important issue. SUMMARY

[0004] The present invention is directed to a method and system for monitoring and controlling a semiconductor process, which can achieve uniform configuration of contact area of two contact windows in two memory cells sharing one active area.

[0005] According to an embodiment of the present invention, a method for monitoring and controlling a semiconductor process includes the following steps. Forming at least one active area on a substrate; after forming the at least one active area, forming a first patterned photoresistor layer for defining at least two word lines on the at least one active area; detecting and measuring the position and size of the at least one active area and the first patterned photoresistor layer, and calculating the estimated area of at least two estimated contact windows in the at least one active area according to the predefined position of the at least one bit line; adjusting the predefined position of the at least one bit line according to the estimated area of the at least two estimated contact windows in the at least one active area; and forming a second patterned photoresistor layer on the substrate, wherein the second patterned photoresistor layer corresponds to the adjusted predefined position of the at least one bit line.

[0006] According to an embodiment of the present application, a system for monitoring and controlling a semiconductor process includes a semiconductor manufacturing apparatus and a controller. The semiconductor manufacturing apparatus is used to fabricate an integrated circuit on a substrate. The controller is coupled to the semiconductor manufacturing apparatus. The controller controls the semiconductor manufacturing apparatus to form at least one active region on the substrate; after forming the at least one active region, form a first patterned photoresist layer on the at least one active region for defining at least two word lines; detect and measure a position and a dimension of the at least one active region and the first patterned photoresist layer, and calculate an estimated area of at least two estimated contact holes in the at least one active region according to a predefined position of the at least one bit line; adjust the predefined position of the at least one bit line according to the estimated area of the at least two estimated contact holes in the at least one active region; and form a second patterned photoresist layer on the substrate, wherein the second patterned photoresist layer corresponds to the adjusted predefined position of the at least one bit line. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a layout diagram of an active region, a word line and a bit line of a dynamic random access memory according to an embodiment of the present application;

[0008] Figure 2 is a diagram illustrating a relationship between a resistance Rc and an on-state voltage Ion of a contact hole according to an embodiment of the present application;

[0009] Figure 3 is a diagram illustrating an overlay measurement of a contact area of a contact hole in an active region with respect to a word line and a bit line according to an embodiment of the present application;

[0010] Figure 4 is a block diagram of a system for monitoring and controlling a semiconductor process according to an embodiment of the present application;

[0011] Figure 5 is a flowchart of a method for monitoring and controlling a semiconductor process according to an embodiment of the present application;

[0012] Figure 6 is a diagram illustrating an adjustment of a contact area of a contact hole by moving a predefined position of a bit line according to an embodiment of the present application;

[0013] Figure 7 is a diagram illustrating a relationship between a displacement k parameter and an on-state voltage difference of two side contact holes in a memory cell.

[0014] REFERENCE NUMERALS

[0015] 310A, 310B, 310C: arrows;

[0016] 400: a system for monitoring and controlling a semiconductor process;

[0017] 410: semiconductor manufacturing equipment;

[0018] 415: controller;

[0019] 420: lithography apparatus;

[0020] 430: measurement apparatus;

[0021] 440: thin film deposition apparatus;

[0022] 450: etching apparatus;

[0023] 500: method of monitoring and controlling a semiconductor process;

[0024] S510-S595: method of monitoring and controlling a semiconductor process;

[0025] X: X-axis;

[0026] Y: Y-axis;

[0027] WL, WL1-WL4: word line;

[0028] BL: bit line;

[0029] AA, AA1: active area;

[0030] T1, T2: switching transistor;

[0031] CC1, CC2, A1-A4, B1-B4, CC1B, CC2B, CC1C, CC2C, CC1D, CC2D, CC1A, CC2A: contact hole;

[0032] IonD: difference between on voltages of the two contact holes;

[0033] k: displacement k parameter. DETAILED DESCRIPTION

[0034] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0035] Figure 1 is a layout diagram of active areas, word lines and bit lines of a dynamic random access memory according to an embodiment of the present application. In this embodiment, the layout of the dynamic random access memory is that two memory cells share one bit line BL, and the two memory cells are controlled by two word lines WL respectively. When manufacturing the dynamic random access memory, the areas of the contact holes CC1, CC2 corresponding to the two word lines WL in the two memory cells respectively cannot be uniformly arranged due to the inaccuracy of the lithography technology, so that the bridging margin of the contact holes is reduced.

[0036] In Figure 1 The structure of the present embodiment is explained in combination with the photolithography technique in semiconductor process. First, shallow trench isolation (STI) is utilized to form a plurality of active regions AA1 on a substrate, which are separated from each other and configured in a strip shape and arranged in an array. After the active regions AA1 are formed, a patterned photoresist layer for defining word lines WL is formed on the substrate by using the photolithography technique, as a preparation for forming the word lines WL. Then, an etching process is performed to form the word lines WL in the substrate. The word lines WL are presented in a column direction. After the word lines WL are formed, a patterned photoresist layer for defining bit lines BL is formed on the substrate by using the photolithography technique, as a preparation for forming the bit lines BL. Then, an etching process is performed to form the bit lines BL on the substrate. The bit lines BL are presented in a row direction. Based on the aforementioned processes, two storage cells share the active region AA1, and two word lines WL cross the active region AA1, thereby generating two switching transistors T1 and T2, so that the capacitive components of each storage cell can be connected to the bit lines BL through the contact windows CC1 and CC2 and the switching transistors T1 and T2, respectively.

[0037] To know the connection between the contact windows CC1 and CC2 and the corresponding capacitive components, it is necessary to wait until the aforementioned semiconductor process is sequentially stacked in the order of forming the active regions, the word lines WL and the bit lines BL, and then the area of the contact windows CC1 and CC2 can be measured by an electron microscope. However, after knowing the connection of the contact windows CC1 and CC2, the positions of the word lines WL and the bit lines BL in the present semiconductor process cannot be adjusted in real time.

[0038] Figure 2 is a schematic diagram illustrating the relationship between the resistance Rc of the contact window and the on-current Ion according to an embodiment of the present application. The horizontal axis represents the size of the resistance Rc of the contact window, and kΩ is used as the unit. The vertical axis represents the numerical value of the on-current Ion between the contact window and the capacitive component, and μA is used as the unit. The larger the area of the contact window with the capacitive component, the smaller the resistance Rc of the contact window, and the larger the on-current Ion between the contact window and the capacitive component; on the contrary, the smaller the area of the contact window with the capacitive component, the larger the resistance Rc of the contact window, and the smaller the on-current Ion between the contact window and the capacitive component. Therefore, it is desirable to enable the contact windows CC1 and CC2 located in the same active region AA1 to have similar areas, so that the on-currents of the capacitive components of each storage cell connected to the bit lines BL through the switching transistors T1 and T2 in the active region AA1 can be consistent.

[0039] Figure 3This is a schematic diagram illustrating the overlay measurement of the contact areas of contact windows CC1 and CC2 in the active region AA1 with respect to word line WL and bit line BL, according to an embodiment of the present invention. Figure 3 (A) in the middle is Figure 1 A schematic diagram of the active region AA1 and contact windows CC1 and CC2. Figure 3 (B) in the presentation will Figure 3 The diagram shows the offset of the word line WL in (A) by 3nm to the right (i.e., in the positive direction of the X-axis), as indicated by arrow 310B. Calculations based on this embodiment show that the contact window CC2B has an area reduced by approximately 8.5% compared to the contact window CC1B. Figure 3 (C) in the presentation will Figure 3 The diagram shows the position of bit line BL in (A) shifted downwards (i.e., in the negative direction of the Y-axis) by 3 nm, as indicated by arrow 310C. Calculations in this embodiment show that contact window CC2C reduces its area by approximately 18% compared to contact window CC1C. Figure 3 The (D) presentation in the middle will Figure 3 The diagram illustrates that the overlay position of the word line WL in (A) is shifted 3nm to the right (i.e., in the positive direction of the X-axis) (as shown by arrow 310B) and the overlay position of the bit line BL is shifted 3nm downwards (i.e., in the negative direction of the Y-axis) (as shown by arrow 310C). Calculations based on this embodiment show that the contact window CC2D reduces its area by approximately 25% compared to the contact window CC1D.

[0040] Figure 4 This is a block diagram of a system for monitoring and controlling a semiconductor process according to an embodiment of the present invention. The system 400 for monitoring and controlling the semiconductor process includes a semiconductor manufacturing apparatus 410, a measurement apparatus 430, and a controller 415. The semiconductor manufacturing apparatus 410 includes a lithography apparatus 420, a thin film deposition apparatus 440, an etching apparatus 450, and related equipment. The semiconductor manufacturing apparatus 410 is used to manufacture integrated circuits on a substrate using a variety of devices (e.g., devices 420, 440, 450, etc.). The controller 415 is coupled to each of the devices 420, 440, and 450 in the semiconductor manufacturing apparatus 410 and is used to implement the method for monitoring and controlling the semiconductor process described in this embodiment. In some embodiments, the controller 415 is mainly used to control the steps in the lithography apparatus 420, and may also be located within the lithography apparatus 420 of the semiconductor manufacturing apparatus 410. The measuring device 430 includes at least the critical dimension (CD) and overlay registration (RG) of each structure or photoresist layer on the measuring substrate, so as to determine the position and size of each structure or photoresist layer.

[0041] Figure 5is a flowchart of a method of monitoring and controlling a semiconductor process according to an embodiment of the present invention. Please refer to Figure 4 and Figure 5 The semiconductor manufacturing apparatus 410 forms at least one active area on the substrate (step S510). After the formation of the active area, the lithography apparatus 420 forms a first patterned photoresist layer on the active area for defining at least two word lines in step S520. The word lines WL extend along a first direction, and the bit lines BL extend along a second direction, the first direction and the second direction being non-parallel to each other. In this embodiment, the first direction and the second direction are perpendicular to each other.

[0042] In step S530, the measurement apparatus 430 detects and measures the position and size of the at least one active area (e.g., the active area AA1 as shown in FIG. 5) and the first patterned photoresist layer on the substrate. In step S535, the controller 415 calculates the estimated areas of at least two estimated contact windows (e.g., the contact windows CC1 and CC2 as shown in FIG. 5) in the active area according to the predefined position of the at least one bit line BL. In other words, the controller 415 will simulate the estimated areas of the estimated contact windows based on the position and size of the active area and the first patterned photoresist layer formed on the substrate, together with the position (i.e., the "predefined position") at which the bit line BL is expected to be disposed. The measurement apparatus 430 of this embodiment calculates the estimated areas of the estimated contact windows based on the critical dimension (CD) and the overlay (OVL) of the active area / first patterned photoresist layer. Since the lithography apparatus 420 still inevitably produces some errors when forming the first patterned photoresist layer, the position and size of the active area and the first patterned photoresist layer are detected and measured by the measurement apparatus 430 in step S530 so as to interpret the errors produced by the lithography apparatus 420 when forming the first patterned photoresist layer, and the estimated areas of the two estimated contact windows are calculated. Figure 1 Figure 1 In step S540, the controller 415 adjusts the predefined position of the at least one bit line BL according to the estimated areas of the at least two estimated contact windows in the active area. Before step S550, the etching apparatus 450 in the semiconductor manufacturing apparatus 410 forms the word lines WL through the first patterned photoresist layer and the thin film deposition apparatus 440. In step S550, the controller 415 controls the lithography apparatus 420 to form a second patterned photoresist layer on the substrate, the second patterned photoresist layer corresponding to the adjusted predefined position of the bit line BL so as to make the estimated areas of the two estimated contact windows close to each other.

[0043]

[0044] Figure 6 ​​is a schematic diagram of adjusting the contact area of the contact hole according to the pre-defined position of the bit line in an embodiment of the present application. From Figure 6 As can be seen from the upper half of Figure 6 As can be seen from the lower half of

[0045] Referring again to Figure 5 As the adjusted pre-defined position of the bit line BL will inevitably have some errors when formed on the substrate by the photolithography equipment 420 in the form of the second patterned photoresist layer, the embodiment can further detect the adjusted pre-defined position by detecting and measuring the position and size of the second patterned photoresist layer by the measuring equipment 430 in step S560. And, in step S570, the controller 415 recalculates the estimated area of the estimated contact hole in the active area according to the position and size of the word line and the position and size of the aforementioned second patterned photoresist layer. Then, in step S580, the controller 415 determines whether the position of the aforementioned second patterned photoresist layer needs to be adjusted according to the estimated area of the estimated contact hole in the active area. If the controller 415 determines that the position of the second patterned photoresist layer does not need to be adjusted in step S580 (i.e. step S580 is NO), step S585 is performed. In contrast, if the controller 415 determines that the position of the second patterned photoresist layer needs to be adjusted in step S580 (i.e. step S580 is YES), the previously configured second patterned photoresist layer is removed, and the process returns to step S550. In step S550, the second patterned photoresist layer is re-formed, which corresponds to the adjusted pre-defined position of the bit line BL.

[0046] The embodiment can perform steps S550 to S580 repeatedly to fine-tune the second patterned photoresist layer according to the needs of the application of the embodiment, or evaluate whether to modify the parameters in the semiconductor process according to the detection and measurement results in step S560, so as to compensate for the problem of insufficient contact area of the contact hole in the memory cell caused by the errors of the miniaturization technology by adjusting the pre-defined position of the bit line BL, and increase the product yield in the semiconductor process.

[0047] After the second patterned photoresist layer is formed, the etching device 450 in the semiconductor manufacturing apparatus 410 forms the bit lines BL through the second patterned photoresist layer in step S585. In step S590, the semiconductor manufacturing apparatus 410 configures the contact holes on the two contact windows in the active region respectively, so as to be coupled with the corresponding capacitor components of the memory cell, thereby completing the random access memory structure. In step S595, the wafer acceptance test (WAT) is performed on the completed integrated circuit, so as to obtain the relevant electrical parameters of the integrated circuit, and to determine whether the integrated circuit manufactured by the semiconductor process is normal and can be stably operated. The embodiment can obtain the resistance Rc and the on-current Ion of the contact windows CC1 and CC2 through step S595, so as to determine whether the method 500 improves the quality of the product. Figure 1 Figure 5

[0048] In some embodiments consistent with the present application, the controller 415 can adjust the position of the second patterned photoresist layer multiple times in steps S550-S580, and can also go back to step S520 to adjust the first patterned photoresist layer before step S550. In detail, if the controller 415 considers that the first patterned photoresist layer needs to be adjusted to align the predefined position of the word line WL in step S535, the first patterned photoresist layer configured in step S520 needs to be removed, and then a new first patterned photoresist layer is formed, and the remaining steps are continued from step S520.

[0049] In some embodiments consistent with the present application, in addition to detecting and measuring the position and size of the at least one active region on the substrate and the first patterned photoresist layer in step S530, so as to calculate the estimated area of the at least two estimated contact windows in the active region in step S535, the embodiment can also detect and measure the position and size of the at least one active region on the substrate and the word line after etching (that is, the formed word line), so as to calculate the estimated area of the at least two estimated contact windows in the active region.

[0050] ​​The embodiment is to balance the two estimated contact areas. In detail, the embodiment is to make the displacement k parameter (BL OVL-Y shift k) of the bit line on the overlay y-axis irrelevant to the optimized overlay y-axis parameter (OVL-Y optimize). The optimized overlay y-axis parameter (OVL-Y optimize) is calculated by the equation, and the displacement k parameter (BL OVL-Y shift k) is optimized by the wafer acceptance test (WAT). If the displacement k parameter (BL OVL-Y shift k) is still relevant to the area balance of the two estimated contact areas, the user of the embodiment needs to adjust the displacement k parameter (BL OVL-Y shift k) to make the area balance of the two estimated contact areas irrelevant to the displacement k parameter (BL OVL-Y shift k).

[0051] Figure 7 is a graph of the displacement k parameter (BL OVL-Y shift k) and the difference between the two contact voltages in the memory cell. The X-axis represents the displacement k parameter (BL OVL-Y shift k), and the Y-axis represents the difference IonD between the two contact voltages in the memory cell. Figure 7 (A) in (B) still has a positive correlation between the difference IonD between the two contact voltages and the displacement k parameter. The user of the embodiment can optimize the displacement k parameter by the wafer acceptance test (WAT) to make the positive correlation between the difference IonD between the two contact voltages and the displacement k parameter from Figure 7 (A) in (B) gradually adjusted from the positive correlation Figure 7 (B) in (B) is slightly positively correlated, until Figure 7 (C) in (B) is irrelevant. Thus, the user of the embodiment can also optimize the displacement k parameter by the wafer acceptance test (WAT) to reduce the relevance between the displacement k parameter and the difference between the two contact voltages in the memory cell.

[0052] In summary, the method and system for monitoring and controlling semiconductor processes according to the embodiments of the present application can estimate the contact area for connecting to the capacitor assembly by monitoring the position and size of the active area and the first patterned photoresist layer for defining the word line (or the position and size of the formed word line), and then adjust the second patterned photoresist layer for defining the bit line accordingly to make the areas of the two contact windows corresponding to the two memory cells in the same active area as close as possible, thereby increasing the product yield in the semiconductor process.

[0053] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of monitoring and controlling a semiconductor process, characterized by, comprising: forming at least one active region on a substrate; after forming at least one said active region, forming a first patterned photoresist layer on at least one said active region for defining at least two word lines; detecting and measuring a position and a size of at least one said active region and said first patterned photoresist layer, and calculating an estimated area of at least two estimated contact windows in at least one said active region according to a predefined position of at least one bit line; adjusting said predefined position of at least one said bit line according to said estimated area of at least two estimated contact windows in at least one said active region; and forming a second patterned photoresist layer on said substrate, wherein said second patterned photoresist layer corresponds to said predefined position of at least one said bit line after adjustment.

2. The method of claim 1, wherein, further comprising: forming said at least two word lines through said first patterned photoresist layer before forming said second patterned photoresist layer.

3. The method of claim 2, wherein, further comprising: detecting and measuring a position and a size of said second patterned photoresist layer to detect said predefined position after adjustment; recalculating said estimated area of said at least two estimated contact windows in at least one said active region according to a position of forming said at least two word lines and said position and size of said second patterned photoresist layer; and reforming said second patterned photoresist layer according to said estimated area of at least two estimated contact windows in at least one said active region, wherein said second patterned photoresist layer corresponds to said predefined position of at least one said bit line after adjustment.

4. The method of claim 2, wherein, further comprising: detecting and measuring a position and a size of at least one said active region and a position of forming said at least two word lines, and calculating an estimated area of at least two estimated contact windows in at least one said active region according to a predefined position of at least one bit line; adjusting said predefined position of at least one said bit line according to said estimated area of at least two estimated contact windows in at least one said active region.

5. The method of claim 1, wherein, said at least two word lines span across at least one said active region, and at least one said active region comprises two switch transistors, each switch transistor comprising one of said at least two contact windows, wherein at least one said active region is configured with a contact hole on at least two contact windows, wherein said at least two word lines are configured along a first direction, and at least one said bit line is configured along a second direction, wherein said first direction and said second direction are not parallel to each other.

6. The method of claim 1, wherein, further comprising: eliminating said first patterned photoresist layer and forming a new said first patterned photoresist layer to align a predefined position of said at least two word lines.

7. A system for monitoring and controlling a semiconductor process, characterized by comprising: a semiconductor manufacturing apparatus for fabricating an integrated circuit on a substrate; and a controller coupled to said semiconductor manufacturing apparatus, wherein said controller controls said semiconductor manufacturing apparatus to: form at least one active region on said substrate; after forming at least one said active region, form a first patterned photoresist layer on at least one said active region for defining at least two word lines; detecting and measuring a position and a size of at least one said active region and said first patterned photoresist layer, and calculating an estimated area of at least two estimated contact windows in at least one said active region according to a predefined position of at least one bit line; adjusting said predefined position of at least one said bit line according to said estimated area of at least two estimated contact windows in at least one said active region; and form a second patterned photoresist layer on said substrate, wherein said second patterned photoresist layer corresponds to said predefined position of at least one said bit line after adjustment. detecting and measuring positions and dimensions of the at least one active region and the first patterned photoresist layer, and calculating estimated areas of at least two estimated contact holes in the at least one active region according to predefined positions of the at least one bit line; adjusting the predefined positions of the at least one bit line according to the estimated areas of the at least two estimated contact holes in the at least one active region; and forming a second patterned photoresist layer on the substrate, wherein the second patterned photoresist layer corresponds to the adjusted predefined positions of the at least one bit line.

8. The system of claim 7, wherein, The controller is further configured to: form the at least two word lines through the first patterned photoresist layer before forming the second patterned photoresist layer.

9. The system of claim 8, wherein, The controller is further configured to: detect and measure positions and dimensions of the second patterned photoresist layer to detect the adjusted predefined positions; recalculate the estimated areas of the at least two estimated contact holes in the at least one active region according to positions of the at least two word lines formed and positions and dimensions of the second patterned photoresist layer; and re-form a second patterned photoresist layer according to the estimated areas of the at least two estimated contact holes in the at least one active region, wherein the second patterned photoresist layer corresponds to the adjusted predefined positions of the at least one bit line.

10. The system of claim 7, wherein, The at least two word lines span the at least one active region, and the at least one active region comprises two switch transistors, each switch transistor comprising one of the at least two contact holes, wherein at least two contact holes in the at least one active region are configured with contact holes, wherein the at least two word lines are configured along a first direction, and the at least one bit line is configured along a second direction, wherein the first direction and the second direction are not parallel to each other.

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