Trench gate super junction IGBT device and method of manufacturing the same

Abstract

The application discloses a trench gate super junction IGBT device, and a device unit structure comprises: a P-type doped body region is formed in a surface region of an N-type column and a P-type column. A trench gate is located in a top region of the N-type column and passes through the body region. An emitter region is formed on a surface of the body region at a side of the trench gate. A first contact hole at a top of the emitter region is connected to an emitter electrode composed of a front metal layer. A trench isolation structure is formed in an N-type column between the first contact hole and an adjacent P-type column, the trench isolation structure is composed of a first dielectric layer filled in an isolation trench, the isolation trench passes through the body region and divides the body region into a first body region part and a second body region part. The trench isolation structure cuts off a conduction path of the second body region part and the P-type column to the first body region. The application also discloses a manufacturing method of the trench gate super junction IGBT device. The application can realize isolation of the P-type column and the P-type body region, thereby preventing formation of a hole conduction path of the P-type column to the P-type body region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction (SJ) insulated gate bipolar transistor (IGBT) device. This invention also relates to a method for manufacturing a trench gate super junction IGBT device. Background Technology

[0002] IGBT is a voltage-controlled MOS and bipolar composite device that combines the main advantages of both bipolar junction power transistors and power MOSFETs: high input impedance, low input drive power, low on-resistance, large current capacity, and fast switching speed. This makes IGBT one of the important switching components for energy control and conversion in power electronic systems, and its performance directly affects the conversion efficiency, size, and weight of the power electronic system.

[0003] The IGBT structure is very similar to the VDMOS structure. It is formed by changing the N+ doped drain region to a P+ doped collector region on the basis of VDMOS. The collector region can inject holes into the drift region, thereby achieving conductance modulation of the drift region, which can reduce the on-state voltage drop of the device and increase the current density of the device.

[0004] By incorporating a superjunction structure within the drift region of an IGBT device, a superjunction IGBT (SJ-IGBT) device can be obtained. SJ-IGBTs leverage the process capabilities of both SJ and IGBT technologies, combining the characteristics of both devices to significantly improve forward conduction performance and substantially increase power density.

[0005] However, when the P-type pillar of the SJ-IGBT and the P-type body of the IGBT come into contact, a hole conduction path is formed from the P-type pillar, the P-type body, the emitter contact hole at the top of the P-type body, to the emitter. This reduces the modulation of the drift region's conductivity by holes. Therefore, one of the key aspects of SJ-IGBT fabrication is ensuring the mutual isolation between the P-type pillar and the P-type body to prevent the rapid removal of charge carriers. Existing structures use additional N-type epitaxial layers (NEPI) for isolation, which is complex and lacks flexibility.

[0006] like Figure 1 The diagram shown is a structural schematic of an existing trench gate superjunction IGBT device; existing trench gate superjunction IGBT devices include:

[0007] The superjunction structure is composed of multiple N-type pillars and P-type pillars 209 arranged alternately, and one N-type pillar and one adjacent P-type pillar 209 form a corresponding superjunction unit.

[0008] The superjunction structure is formed in an N-type epitaxial layer 202, and a P-type doped collector region 201 is formed at the bottom of the N-type epitaxial layer 202. The back side of the collector region 201 is connected to a collector electrode composed of a back metal layer.

[0009] The P-type pillar 209 is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in the N-type epitaxial layer 202, and the N-type pillar is composed of the N-type epitaxial layer 202 between the P-type pillars 209.

[0010] The N-type epitaxial layer 202 is formed on the surface of a semiconductor substrate (not shown). The semiconductor substrate is removed during a back-side thinning process, therefore... Figure 1 It is not displayed.

[0011] The bottom of the P-shaped column 209 and the top surface of the current collection area 201 are spaced apart.

[0012] A top N-type epitaxial layer 208 is formed on the top of the superjunction structure.

[0013] In the device unit region 201a, a device unit structure of an IGBT device is formed in the top N-type epitaxial layer 208 of the top region of each superjunction unit. The IGBT device is formed by multiple device unit structures connected in parallel.

[0014] The device unit structure includes:

[0015] P-type doped body region 206, which is formed in the surface region of the top N-type epitaxial layer 208.

[0016] The trench gate is composed of a gate dielectric layer 204 and a gate conductive material layer 205 filled in a gate trench 203, wherein the gate trench 203 is located in the top region of the N-type pillar and passes through the body region 206.

[0017] An emission region 207 composed of N+ regions is formed on the surface of the body region 206 on the side of the trench gate.

[0018] A first contact hole 211 is formed on the top of the emission region 207. The bottom of the first contact hole 211 contacts both the emission region 207 and the body region 206. The top of the first contact hole 211 is connected to the emitter composed of the front metal layer 212.

[0019] An N-type doped electric field cessation layer 214 is formed in the N-type epitaxial layer 202 on the front side of the current collector region 201. The doping concentration of the electric field cessation layer 214 is greater than that of the N-type epitaxial layer 202. There is a gap between the top surface of the electric field cessation layer 214 and the bottom surface of the P-type pillar 209.

[0020] The trench gate also extends into the gate lead-out region 201b, in which a second contact hole (not shown) is formed on the top of the gate conductive material layer 205, and the top of the second contact hole is connected to the gate composed of the front metal layer 212.

[0021] A passivation layer 213 is also formed on the surface of the front metal layer 212.

[0022] Both the first contact hole 211 and the second contact hole pass through the interlayer membrane 210.

[0023] Typically, the collector region 201 consists of a P-type doped back ion implantation region formed at the bottom of the N-type epitaxial layer 202 after thinning the back side of the semiconductor substrate. Summary of the Invention

[0024] The technical problem to be solved by this invention is to provide a trench-gate superjunction IGBT device that can achieve isolation between the P-type pillars of the superjunction structure and the P-type body region of the IGBT device, thereby preventing the formation of hole conduction paths from the P-type pillars to the P-type body region, thus enhancing the conductance modulation of the drift region, increasing the current density of the device, and reducing the on-state voltage drop. To this end, this invention also provides a method for manufacturing the trench-gate superjunction IGBT device.

[0025] To solve the above-mentioned technical problems, the trench gate superjunction IGBT device provided by the present invention includes:

[0026] The superjunction structure is composed of multiple alternating N-type pillars and P-type pillars, with one N-type pillar and one adjacent P-type pillar forming a corresponding superjunction unit.

[0027] The superjunction structure is formed in an N-type epitaxial layer, and a P-type doped collector region is formed at the bottom of the N-type epitaxial layer. The back side of the collector region is connected to a collector electrode composed of a back metal layer.

[0028] The bottom of the P-shaped column and the top surface of the current collector area are spaced apart.

[0029] In the device unit region, a device unit structure of an IGBT device is formed in the top region of each of the superjunction units, and the IGBT device is formed by multiple device unit structures connected in parallel.

[0030] The device unit structure includes:

[0031] P-type doped body regions are formed in the surface regions of the N-type pillars and the P-type pillars.

[0032] A trench gate consists of a gate dielectric layer and a gate conductive material layer filled in a gate trench, the gate trench being located in the top region of the N-type pillar and passing through the body region.

[0033] An emission region consisting of N+ regions is formed on the surface of the body region on the side of the trench gate.

[0034] A first contact hole is formed at the top of the emission region, the bottom of the first contact hole contacts both the emission region and the body region, and the top of the first contact hole is connected to the emitter composed of a front metal layer.

[0035] A grooved isolation structure is formed in the N-type post between the first contact hole and the adjacent P-type post. The grooved isolation structure consists of a first dielectric layer filled in the isolation groove. The isolation groove passes through the body region and divides the body region into a first body region portion and a second body region portion.

[0036] The first body region is located between the isolation trench and the trench grid, and the second body region is located between the isolation trench and the P-type post. The first body region is connected to the emitter through the first contact hole.

[0037] The trench isolation structure cuts off the second body region portion and the conduction path from the P-shaped column to the first body region.

[0038] A further improvement is that an N-type doped electric field cessation layer is formed in the N-type epitaxial layer on the front side of the collector region, the doping concentration of the electric field cessation layer is greater than the doping concentration of the N-type epitaxial layer, and there is a gap between the top surface of the electric field cessation layer and the bottom surface of the P-type pillar.

[0039] A further improvement is that the gate dielectric layer includes a gate oxide layer; and the gate conductive material layer includes a polysilicon gate.

[0040] A further improvement is that a body lead-out region composed of P+ regions is also formed on the surface of the first body region.

[0041] A further improvement is that an N-type electrode region for a fast recovery diode is formed at the bottom of the N-type epitaxial layer; the back side of the N-type electrode region is also in contact with the collector, and the collector also serves as the cathode of the fast recovery diode.

[0042] A further improvement is that the trench gate extends into the gate lead-out region, in which a second contact hole is formed on top of the gate conductive material layer, and the top of the second contact hole is connected to the gate composed of the front metal layer.

[0043] A further improvement is that the P-type pillar is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in the N-type epitaxial layer, and the N-type pillar is composed of the N-type epitaxial layer between the P-type pillars.

[0044] A further improvement is that the N-type epitaxial layer is formed on the surface of the semiconductor substrate.

[0045] The semiconductor substrate is P-type doped, and the collector region is composed of the semiconductor substrate after back-side thinning; or, the collector region is composed of a P-type doped back-side ion implantation region formed at the bottom of the N-type epitaxial layer after back-side thinning of the semiconductor substrate.

[0046] To solve the above-mentioned technical problems, the manufacturing method of the trench gate superjunction IGBT device provided by the present invention includes the following steps:

[0047] Step 1: Provide a semiconductor substrate, and form an N-type epitaxial layer on the surface of the semiconductor substrate; form a trench gate in a selected region of the N-type epitaxial layer located in the device cell region; the trench gate consists of a gate dielectric layer and a gate conductive material layer filled in the gate trench.

[0048] Step 2: Form a P-type doped body region in the surface region of the N-type epitaxial layer located in the device cell region; the junction depth of the body region is less than the depth of the gate trench, and the gate trench will pass through the body region.

[0049] Step 3: Form an emission region consisting of N+ regions on the surface of the body region on the side of the trench gate.

[0050] Step 4: Form an isolation trench in a selected area of ​​the N-type epitaxial layer, fill the isolation trench with a first dielectric layer, and form a trench isolation structure from the first dielectric layer.

[0051] In the device unit structure of the IGBT device, the isolation trench passes through the body region and divides the body region into a first body region portion and a second body region portion, wherein the first body region portion is located between the isolation trench and the trench gate.

[0052] Step 5: Forming a superjunction structure, including: forming a superjunction trench in a selected region of the N-type epitaxial layer; filling the superjunction trench with a P-type epitaxial layer to form a P-type pillar; the N-type pillar is composed of the N-type epitaxial layer between the P-type pillars; the superjunction structure is formed by alternating N-type pillars and P-type pillars; one N-type pillar and one adjacent P-type pillar form a corresponding superjunction unit.

[0053] In the device unit region, each device unit structure is located in the top region of the corresponding superjunction unit, and the IGBT device is formed by multiple device unit structures connected in parallel.

[0054] The gate trench is located in the top region of the N-type pillar.

[0055] The second body region is located between the isolation trench and the P-shaped post; the trench isolation structure cuts off the conduction path from the second body region and the P-shaped post to the first body region.

[0056] Step 6: Perform metal interconnect process, including: forming interlayer film, contact holes and front metal layer, and patterning the front metal layer to form source and gate.

[0057] The contact hole passes through the interlayer membrane.

[0058] The contact hole includes a first contact hole located at the top of the emission region; the bottom of the first contact hole contacts both the emission region and the body region, and the top of the first contact hole is connected to the emitter electrode.

[0059] Step 7: Perform the back-side processing, including:

[0060] The semiconductor substrate is thinned on the back side, and after the back side thinning process is completed, a P-type doped collector region is formed at the bottom of the N-type epitaxial layer.

[0061] A back metal layer is formed, which contacts the back side of the current collector region to form a current collector.

[0062] A further improvement includes the following process sequence: step five is placed before step one.

[0063] Further improvements include the following process sequence: step four is placed before step one; or step four is placed after step one and before step two; or step four is placed after step two and before step three; or step four is placed after step five.

[0064] A further improvement is that, in step seven, the back-side process further includes: performing N-type back-side ion implantation to form an electric field cessation layer, wherein the electric field cessation layer is located in the N-type epitaxial layer on the front side of the collector region, the doping concentration of the electric field cessation layer is greater than the doping concentration of the N-type epitaxial layer, and there is a gap between the top surface of the electric field cessation layer and the bottom surface of the P-type pillar.

[0065] A further improvement is that, in step one, the gate dielectric layer includes a gate oxide layer; and the gate conductive material layer includes a polysilicon gate.

[0066] A further improvement is that, in step six, after the opening of the first contact hole is formed and before the metal is filled, P+ ion implantation is performed to form a surface extraction area in the first body region portion.

[0067] A further improvement is that, in step seven, the back-side process also includes:

[0068] N-type backside ion implantation is performed to form the N-type electrode region of the fast recovery diode.

[0069] After the collector is formed, the back side of the N-type electrode region also contacts the collector, and the collector also serves as the cathode of the fast recovery diode.

[0070] A further improvement is that, in step one, the trench gate extends into the gate lead-out region;

[0071] In step six, the contact hole further includes a second contact hole located on top of the gate conductive material layer extending into the gate lead-out region, the top of the second contact hole being connected to the gate.

[0072] This invention introduces a trench isolation structure and divides the body region of the device unit structure into a first body region and a second body region. The first body region is connected to the emitter through a first contact hole, while the second body region is in contact with a P-type post. However, the conduction path from the second body region and the P-type post to the first body region is cut off by the trench isolation structure. Therefore, holes cannot be transmitted from the P-type post to the first body region and finally to the emitter. In other words, this invention can prevent the formation of a hole conduction path from the P-type post to the P-type body region. This enhances the conductance modulation of the drift region and ultimately increases the current density of the device and reduces the on-state voltage drop.

[0073] The trench isolation structure of the present invention is formed by trench etching and filling process, which is simple in structure and easy to manufacture. For example, it is easy to insert into multiple process steps in the entire device manufacturing process, which is very beneficial for adjusting the device process and ultimately improving the device performance. Attached Figure Description

[0074] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0075] Figure 1 This is a schematic diagram of the structure of an existing trench gate superjunction IGBT device;

[0076] Figure 2 This is a schematic diagram of the trench gate superjunction IGBT device according to an embodiment of the present invention;

[0077] Figures 3A-3F This is a schematic diagram of the device structure in each step of the manufacturing method of the trench gate superjunction IGBT device according to an embodiment of the present invention. Detailed Implementation

[0078] like Figure 2 The diagram shown is a structural schematic of a trench gate superjunction IGBT device according to an embodiment of the present invention; the trench gate superjunction IGBT device according to an embodiment of the present invention includes:

[0079] The superjunction structure is composed of multiple N-type pillars and P-type pillars 109 arranged alternately, and one N-type pillar and one adjacent P-type pillar 109 form a corresponding superjunction unit.

[0080] The superjunction structure is formed in an N-type epitaxial layer 102, and a P-type doped collector region 115 is formed at the bottom of the N-type epitaxial layer 102. The back side of the collector region 115 is connected to a collector electrode composed of a back metal layer.

[0081] In this embodiment of the invention, the P-type pillar 109 is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in the N-type epitaxial layer 102, and the N-type pillar is composed of the N-type epitaxial layer 102 between the P-type pillars 109.

[0082] The N-type epitaxial layer 102 is formed on the surface of the semiconductor substrate 101. Please refer to [reference needed] for the semiconductor substrate 101. Figure 3A As shown, the semiconductor substrate 101 is removed during the back-side thinning process, therefore... Figure 2 It is not displayed.

[0083] The bottom of the P-shaped column 109 and the top surface of the current collection area 115 are spaced apart.

[0084] In the device unit region 101a, a device unit structure of an IGBT device is formed in the top region of each of the superjunction units, and the IGBT device is formed by multiple device unit structures connected in parallel.

[0085] The device unit structure includes:

[0086] P-type doped body region 106, which is formed in the surface regions of the N-type pillar and the P-type pillar 109.

[0087] The trench gate is composed of a gate dielectric layer 104 and a gate conductive material layer 105 filled in a gate trench 103, wherein the gate trench 103 is located in the top region of the N-type pillar and passes through the body region 106.

[0088] The channel region is composed of the body region 106 covered by the side of the trench gate, and the drift region is composed of the N-type epitaxial layer 102 at the bottom of the body region 106.

[0089] In this embodiment of the invention, the gate dielectric layer 104 includes a gate oxide layer; the gate conductive material layer 105 includes a polysilicon gate.

[0090] An emission region 107 composed of N+ regions is formed on the surface of the body region 106 on the side of the trench gate.

[0091] A first contact hole 111 is formed on the top of the emission region 107. The bottom of the first contact hole 111 contacts both the emission region 107 and the body region 106. The top of the first contact hole 111 is connected to the emitter composed of the front metal layer 112.

[0092] A grooved isolation structure 108 is formed in the N-type post between the first contact hole 111 and the adjacent P-type post 109. The grooved isolation structure 108 consists of a first medium layer filled in the isolation groove. The isolation groove passes through the body region 106 and divides the body region 106 into a first body region portion 106a and a second body region portion 106b.

[0093] The first body region portion 106a is located between the isolation trench and the trench grid, and the second body region portion 106b is located between the isolation trench and the P-type post 109. The first body region portion 106a is connected to the emitter through the first contact hole 111.

[0094] In this embodiment of the invention, a body lead-out region composed of P+ regions is also formed on the surface of the first body region portion 106a, so that an ohmic contact can be formed between the first body region portion 106a and the first contact hole 111, thereby reducing the contact resistance.

[0095] The trench isolation structure 108 cuts off the conduction path from the second body region portion 106b and the P-shaped post 109 to the first body region 106.

[0096] An N-type doped field-stopping layer 114 is formed in the N-type epitaxial layer 102 on the front side of the collector region 115. The doping concentration of the field-stopping layer 114 is greater than that of the N-type epitaxial layer 102, and there is a gap between the top surface of the field-stopping layer 114 and the bottom surface of the P-type pillar 109. In other embodiments, the collector region 115 can also be directly disposed on the back side of the N-type epitaxial layer 102, thus eliminating the need for the field-stopping layer 114.

[0097] In this embodiment of the invention, the trench gate further extends into the gate lead-out region 101b, in which a second contact hole (not shown) is formed on the top of the gate conductive material layer 105, and the top of the second contact hole is connected to the gate composed of the front metal layer 112.

[0098] A passivation layer 213 is also formed on the surface of the front metal layer 112.

[0099] Both the first contact hole 111 and the second contact hole pass through the interlayer membrane 110.

[0100] In some embodiments, the semiconductor substrate 101 is P-type doped, and the collector region 115 is composed of the semiconductor substrate 101 after back-side thinning. In some embodiments, the collector region 115 may also be composed of a P-type doped back-side ion implantation region formed at the bottom of the N-type epitaxial layer 102 after back-side thinning of the semiconductor substrate 101.

[0101] In some embodiments, an N-type electrode region for a fast recovery diode is also formed at the bottom of the N-type epitaxial layer 102; the back side of the N-type electrode region is also in contact with the collector, and the collector simultaneously serves as the cathode of the fast recovery diode. When the N-type electrode region is provided, the IGBT device is a reverse-conducting IGBT (RC-IGBT) device.

[0102] In this embodiment of the invention, a trench isolation structure 108 is introduced, dividing the body region 106 of the device unit structure into a first body region portion 106a and a second body region portion 106b. The first body region portion 106a is connected to the emitter through a first contact hole 111, while the second body region portion 106b is in contact with the P-type post 109. However, the conduction path from the second body region 106 and the P-type post 109 to the first body region portion 106a is cut off by the trench isolation structure 108. Therefore, holes cannot be transmitted from the P-type post 109 to the first body region portion 106a and finally to the emitter. In other words, this embodiment of the invention can prevent the formation of a hole conduction path from the P-type post 109 to the P-type body region 106, thereby enhancing the conductance modulation of the drift region and ultimately increasing the current density of the device and reducing the on-state voltage drop of the device.

[0103] The trench isolation structure 108 of this invention is formed by trench etching and filling process, which is simple in structure and easy to manufacture. For example, it is easy to insert into multiple process steps in the entire device manufacturing process, which is very beneficial for adjusting the device process and ultimately improving the device performance.

[0104] like Figures 3A to 3F The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the trench gate superjunction IGBT device according to an embodiment of the present invention. The manufacturing method of the trench gate superjunction IGBT device according to an embodiment of the present invention includes the following steps:

[0105] Step 1, such as Figure 3A As shown, a semiconductor substrate 101 is provided, and an N-type epitaxial layer 102 is formed on the surface of the semiconductor substrate 101; a trench gate is formed in a selected region of the N-type epitaxial layer 102 located in the device cell region 101a, including:

[0106] Gate trench 103 is formed.

[0107] A gate dielectric layer 104 is formed on the inner surface of the gate trench 103. In some embodiments, the gate dielectric layer 104 includes a gate oxide layer;

[0108] like Figure 3B As shown, a gate conductive material layer 105 is filled in the gate trench 103. The trench gate consists of a gate dielectric layer 104 and a gate conductive material layer 105 filled in the gate trench 103. In some embodiments, the gate conductive material layer 105 comprises a polysilicon gate. The polysilicon gate is completely filled in the gate trench 103 by a polysilicon deposition followed by a chemical mechanical polishing (CMP) process, making the top surface of the polysilicon gate flush with the top surface of the gate trench 103.

[0109] In the method of this embodiment of the invention, the trench gate further extends into the gate lead-out region 101b;

[0110] Step Two, as follows Figure 3C As shown, a P-type doped body region 106 is formed in the surface region of the N-type epitaxial layer 102 located in the device cell region 101a; the junction depth of the body region 106 is less than the depth of the gate trench 103, and the gate trench 103 passes through the body region 106.

[0111] Step 3, as follows Figure 3D As shown, an emission region 107 composed of N+ regions is formed on the surface of the body region 106 on the side of the trench gate.

[0112] Step 4, as follows Figure 3EAs shown, an isolation trench is formed in a selected area of ​​the N-type epitaxial layer 102, and a first dielectric layer is filled in the isolation trench to form a trench isolation structure 108.

[0113] In the device unit structure of the IGBT device, the isolation trench passes through the body region 106 and divides the body region 106 into a first body region portion 106a and a second body region portion 106b, wherein the first body region portion 106a is located between the isolation trench and the trench gate.

[0114] Step 5, as follows Figure 3F As shown, a superjunction structure is formed, including:

[0115] A superjunction trench is formed in a selected region of the N-type epitaxial layer 102, and a P-type epitaxial layer is filled in the superjunction trench to form a P-type pillar 109. The N-type pillar is composed of the N-type epitaxial layer 102 between the P-type pillars 109. The superjunction structure is formed by the alternating arrangement of the N-type pillars and the P-type pillars 109. One N-type pillar and one adjacent P-type pillar 109 form a corresponding superjunction unit.

[0116] In the device unit region 101a, each of the device unit structures is located in the top region of the corresponding superjunction unit, and the IGBT device is formed by multiple device unit structures connected in parallel.

[0117] The gate trench 103 is located in the top region of the N-type pillar.

[0118] The second body region portion 106b is located between the isolation trench and the P-shaped post 109; the trench isolation structure 108 cuts off the conduction path from the second body region portion 106b and the P-shaped post 109 to the first body region 106.

[0119] Step Six, as Figure 2 As shown, the metal interconnect process includes: forming an interlayer film 110, contact holes and a front metal layer 112, and patterning the front metal layer 112 to form the source and gate.

[0120] The contact hole passes through the interlayer membrane 110.

[0121] The contact hole includes a first contact hole 111 located at the top of the emission region 107; the bottom of the first contact hole 111 contacts both the emission region 107 and the body region 106, and the top of the first contact hole 111 is connected to the emitter electrode.

[0122] In the method of this embodiment of the invention, the contact hole further includes a second contact hole located on top of the gate conductive material layer 105 extending into the gate lead-out region 101b, and the top of the second contact hole is connected to the gate.

[0123] In some embodiments, after the opening of the first contact hole 111 is formed and before metal filling, the method further includes: performing P+ ion implantation to form a body lead-out region on the surface of the first body region portion 106a.

[0124] In some embodiments, the method also includes the step of forming a passivation layer 113.

[0125] Step 7: Perform the back-side processing, including:

[0126] The semiconductor substrate 101 is thinned on the back side, and after the back side thinning process is completed, a P-type doped collector region 115 is formed at the bottom of the N-type epitaxial layer 102.

[0127] A back metal layer (not shown) is formed, which contacts the back side of the current collector region 115 and forms a current collector.

[0128] In the method of this embodiment, step seven, the back-side process further includes: performing N-type back-side ion implantation to form an electric field cessation layer 114, wherein the electric field cessation layer 114 is located in the N-type epitaxial layer 102 on the front side of the collector region 115, the doping concentration of the electric field cessation layer 114 is greater than the doping concentration of the N-type epitaxial layer 102, and there is a gap between the top surface of the electric field cessation layer 114 and the bottom surface of the P-type pillar 109.

[0129] In some embodiments, step seven of the back-side process further includes:

[0130] N-type backside ion implantation is performed to form the N-type electrode region of the fast recovery diode.

[0131] After the collector is formed, the back side of the N-type electrode region also contacts the collector, and the collector simultaneously serves as the cathode of the fast recovery diode. The IGBT formed in this way is an RC-IGBT.

[0132] In the method of this embodiment, a gate-first superjunction (SJ) process is used. In other embodiments, a pillar-first superjunction (SJ) process can also be used, in which case the following process sequence is included: step five is placed before step one.

[0133] In other embodiments, the following modifications can also be made, including: adopting the following process sequence: step four is placed before step one; or, step four is placed after step one and before step two; or, step four is placed after step two and before step three; or step four is placed after step five.

[0134] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A trench gate superjunction IGBT device, characterized in that, include: A superjunction structure, wherein the superjunction structure is composed of multiple N-type pillars and P-type pillars arranged alternately, and one N-type pillar and one adjacent P-type pillar form a corresponding superjunction unit; The superjunction structure is formed in an N-type epitaxial layer, and a P-type doped collector region is formed at the bottom of the N-type epitaxial layer. The back side of the collector region is connected to a collector electrode composed of a back metal layer. The bottom of the P-shaped column and the top surface of the current collection area are spaced apart; In the device unit region, a device unit structure of an IGBT device is formed in the top region of each superjunction unit, and the IGBT device is formed by multiple device unit structures connected in parallel; The device unit structure includes: P-type doped body region, the body region being formed in the surface regions of the N-type pillar and the P-type pillar; A trench gate is composed of a gate dielectric layer and a gate conductive material layer filled in a gate trench, wherein the gate trench is located in the top region of the N-type pillar and the gate trench passes through the body region; An emission region composed of N+ regions is formed on the surface of the body region on the side of the trench gate; A first contact hole is formed at the top of the emission region, the bottom of the first contact hole contacts both the emission region and the body region, and the top of the first contact hole is connected to the emitter composed of a front metal layer. A trench isolation structure is formed in the N-type post between the first contact hole and the adjacent P-type post. The trench isolation structure consists of a first dielectric layer filled in the isolation trench. The isolation trench passes through the body region and divides the body region into a first body region portion and a second body region portion. The first body region is located between the isolation trench and the trench grid, and the second body region is located between the isolation trench and the P-type post. The first body region is connected to the emitter through the first contact hole. The trench isolation structure cuts off the second body region portion and the conduction path from the P-shaped column to the first body region.

2. The trench gate superjunction IGBT device as described in claim 1, characterized in that: An N-type doped electric field cessation layer is formed in the N-type epitaxial layer on the front side of the collector region. The doping concentration of the electric field cessation layer is greater than that of the N-type epitaxial layer. There is a gap between the top surface of the electric field cessation layer and the bottom surface of the P-type pillar.

3. The trench gate superjunction IGBT device as described in claim 1, characterized in that: The gate dielectric layer includes a gate oxide layer; the gate conductive material layer includes a polysilicon gate.

4. The trench gate superjunction IGBT device as described in claim 1, characterized in that: A body lead-out region composed of P+ regions is also formed on the surface of the first body region.

5. The trench gate superjunction IGBT device as described in claim 1 or 2, characterized in that: An N-type electrode region for a fast recovery diode is also formed at the bottom of the N-type epitaxial layer; the back side of the N-type electrode region is also in contact with the collector, and the collector also serves as the cathode of the fast recovery diode.

6. The trench gate superjunction IGBT device as described in claim 1, characterized in that: The trench gate also extends into the gate lead-out region, in which a second contact hole is formed on top of the gate conductive material layer, and the top of the second contact hole is connected to the gate composed of the front metal layer.

7. The trench gate superjunction IGBT device as described in claim 1, characterized in that: The P-type pillar is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in the N-type epitaxial layer, and the N-type pillar is composed of the N-type epitaxial layer between the P-type pillars.

8. The trench gate superjunction IGBT device as described in claim 1, characterized in that: The N-type epitaxial layer is formed on the surface of the semiconductor substrate; The semiconductor substrate is P-type doped, and the collector region is composed of the semiconductor substrate after back-side thinning; or, the collector region is composed of a P-type doped back-side ion implantation region formed at the bottom of the N-type epitaxial layer after back-side thinning of the semiconductor substrate.

9. A method for manufacturing a trench gate superjunction IGBT device, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate, and form an N-type epitaxial layer on the surface of the semiconductor substrate; form a trench gate in a selected region of the N-type epitaxial layer located in the device cell region; the trench gate consists of a gate dielectric layer and a gate conductive material layer filling the gate trench; Step 2: Form a P-type doped body region in the surface region of the N-type epitaxial layer located in the device cell region; the junction depth of the body region is less than the depth of the gate trench, and the gate trench will pass through the body region; Step 3: Form an emission region composed of N+ regions on the surface of the body region on the side of the trench gate; Step 4: Form an isolation trench in a selected area of ​​the N-type epitaxial layer, fill the isolation trench with a first dielectric layer, and form a trench isolation structure from the first dielectric layer; In the device unit structure of the IGBT device, the isolation trench passes through the body region and divides the body region into a first body region portion and a second body region portion, wherein the first body region portion is located between the isolation trench and the trench gate; Step 5: Forming a superjunction structure, including: forming a superjunction trench in a selected region of the N-type epitaxial layer; filling the superjunction trench with a P-type epitaxial layer to form a P-type pillar; the N-type pillar is composed of the N-type epitaxial layer between the P-type pillars; the superjunction structure is formed by alternating N-type pillars and P-type pillars; one N-type pillar and one adjacent P-type pillar form a corresponding superjunction unit; In the device unit region, each device unit structure is located in the top region of the corresponding superjunction unit, and the IGBT device is composed of multiple device unit structures connected in parallel; The gate trench is located in the top region of the N-type pillar; The second body region is located between the isolation trench and the P-shaped post; the trench isolation structure cuts off the conductive path from the second body region and the P-shaped post to the first body region; Step 6: Perform metal interconnect process, including: forming interlayer film, contact holes and front metal layer, and patterning the front metal layer to form source and gate. The contact hole passes through the interlayer membrane; The contact hole includes a first contact hole located at the top of the emission region; the bottom of the first contact hole contacts both the emission region and the body region, and the top of the first contact hole is connected to the emitter. Step 7: Perform the back-side processing, including: The semiconductor substrate is thinned on the back side, and after the back side thinning process is completed, a P-type doped collector region is formed at the bottom of the N-type epitaxial layer; A back metal layer is formed, which contacts the back side of the current collector region to form a current collector.

10. The method for manufacturing a trench gate superjunction IGBT device as described in claim 9, characterized in that, It also includes the following process sequence: step five is placed before step one.

11. The method for manufacturing a trench gate superjunction IGBT device as described in claim 9, characterized in that, It also includes the following process sequences: step four is placed before step one; or step four is placed after step one and before step two; or step four is placed after step two and before step three; or step four is placed after step five.

12. The method for manufacturing a trench gate superjunction IGBT device as described in claim 9, characterized in that: In step seven, the back-side process further includes: performing N-type back-side ion implantation to form an electric field cessation layer, wherein the electric field cessation layer is located in the N-type epitaxial layer on the front side of the collector region, the doping concentration of the electric field cessation layer is greater than the doping concentration of the N-type epitaxial layer, and there is a gap between the top surface of the electric field cessation layer and the bottom surface of the P-type pillar.

13. The method for manufacturing a trench gate superjunction IGBT device as described in claim 9, characterized in that: In step one, the gate dielectric layer includes a gate oxide layer; the gate conductive material layer includes a polysilicon gate.

14. The method for manufacturing a trench gate superjunction IGBT device as described in claim 9, characterized in that: Step six, after the opening of the first contact hole is formed and before the metal is filled, further includes: performing P+ ion implantation to form a surface extraction area in the first body region portion.

15. The method for manufacturing a trench gate superjunction IGBT device as described in claim 9 or 12, characterized in that: In step seven, the back-side process also includes: N-type backside ion implantation is performed to form the N-type electrode region of the fast recovery diode; After the collector is formed, the back side of the N-type electrode region also contacts the collector, and the collector also serves as the cathode of the fast recovery diode.

16. The method for manufacturing a trench gate superjunction IGBT device as described in claim 9, characterized in that: In step one, the trench gate also extends into the gate lead-out region; In step six, the contact hole further includes a second contact hole located on top of the gate conductive material layer extending into the gate lead-out region, the top of the second contact hole being connected to the gate.

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