A feedback signal transmission circuit for AC-DC converter based on secondary side feedback

Abstract

The present invention discloses an AC-DC converter feedback signal transmission circuit based on secondary-side feedback, which generates a voltage error signal by comparing the sampling of the output voltage with the input voltage reference, and detects the load condition of the system. When overloaded, it adaptively generates a voltage frequency-jittering signal according to the size of the output load, superimposes the voltage error signal and the adaptive frequency-jittering signal, and finally transmits the superimposed signal to the primary-side main control chip through an isolation transmission circuit. The primary-side main control chip adaptively adjusts the switching frequency of the primary-side main power tube according to the size of the error signal to achieve closed-loop control of the output voltage. Compared with traditional optocoupler isolation transmission, the present invention uses capacitor isolation transmission, which optimizes the system EMI performance and obtains a larger system bandwidth and feedback accuracy, while also having smaller dynamic power consumption, and can be fully integrated with the primary-side main control chip, which helps to further improve the system power density.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an AC-DC converter feedback signal transmission circuit based on secondary side feedback. Background Art

[0002] Flyback converters are widely used in small and medium power supply systems, especially in power adapters. Under the general trend of energy conservation and environmental protection, the market has higher and higher requirements for power efficiency and power density. Traditional flyback converters such as quasi-resonant (QR) converters can no longer meet market demand. As a topology of traditional flyback converters, the flyback active clamp converter absorbs the energy stored in the transformer leakage inductance by adding a clamp power tube and a clamp capacitor, and transfers the energy to the secondary side, thereby avoiding the voltage spike when the main power tube is turned on, reducing voltage stress and improving energy conversion efficiency. With the popularization of the third-generation gallium nitride (GaN) power devices, flyback active clamp converters can achieve higher switching frequencies and obtain higher power density. At present, the active clamp topology has been widely used in small and medium power adapters on the market.

[0003] As the switching frequency of the main switch tube gradually increases, the electromagnetic interference generated by the huge instantaneous current change when the main switch tube is turned off becomes more and more serious, and the requirements for the system EMI performance become more and more stringent. In addition, in the AC-DC converter based on secondary feedback, in order to stabilize the output voltage, the error signal between the secondary output voltage and the expected output voltage needs to be transmitted back to the primary control chip. The primary main control chip adaptively adjusts the switching frequency of the primary main switch tube according to the size of the error signal to achieve closed-loop control of the output voltage.

[0004] Since the primary and secondary sides do not share a common ground, in order to avoid safety issues caused by the high voltage on the primary side being transmitted to the secondary side or the switching noise on the primary side being transmitted to the secondary side and affecting the working state of the system, the existing feedback circuit mainly uses optocouplers to isolate the primary and secondary sides while transmitting the error signal generated on the secondary side back to the primary side. Although optocoupler isolators have strong anti-interference capabilities, their transmission rate is relatively low, generally not exceeding 10MHz; optocouplers also have nonlinear transmission characteristics, which reduces the control accuracy of feedback and greatly limits the transient response capability of the system. In addition, optocouplers have high dynamic power consumption and are not compatible with existing CMOS silicon-based processes, so they cannot be integrated, limiting further improvements in system power density.

[0005] For an isolated switching power supply, a Chinese patent application with publication number CN114465461A proposes a feedback circuit and a control method thereof, such as Figure 1As shown in the figure, the three-terminal adjustable voltage regulator TL431 and the optocoupler together form a feedback circuit. The output voltage Vo is divided by resistors R1 and R2 and sent to TL431 for comparison with its internal reference. Since the output voltage of TL431 is inversely proportional to the input, when the load is light, the output current is small and Vo is large, so the output voltage Vm of TL431 will decrease. Vm is applied to both ends of the photodiode D2 and R5, so the current flowing through the photodiode will also decrease; the optocoupler feedback current will have the same change trend as the load current, reducing the loss caused by the optocoupler feedback current when light load or no load. Although this patented technology optimizes the light load power consumption of the whole machine, it requires additional discrete components TL431 and optocoupler circuits, which cannot be integrated with the main control chip, which is not conducive to improving the system power density and also increases the system cost.

[0006] A feedback circuit and its control method are proposed in the literature [Ma C, Wang K, Wang J F. Control Design and Realization of a Fast Transient Response, High-Reliability DC-DC Converter With a Secondary-Side Control Circuit [J]. IEEE Access, 2021, PP (99): 1-1], such as Figure 2 As shown, the main control chip is located on the secondary side and detects the primary excitation current through the auxiliary winding T2. The magnitude of the CS port voltage reflects the magnitude of the excitation current. The secondary output voltage Vo is divided and compared with the reference voltage REF in the error amplifier EA to generate a voltage error signal; the voltage error signal is then sent to the PWM comparator, compared with the superimposed voltage of the slope compensation Vramp and the CS port output voltage, to generate the switch control signal of the primary main switch tube and the synchronous rectifier tube S2. The signal is finally transmitted to the primary side through the magnetic coupling isolator to control the disconnection of the primary main tube S1. The on-chip transformer inside the magnetic coupling isolator allows the signal to be isolated and transmitted to the primary side by electromagnetic induction. Although this method uses one less discrete component TL431 than the feedback method introduced in the above patent technology, and makes it possible to integrate the feedback circuit with the main control chip, the production of the on-chip transformer in the magnetic coupling isolator requires a proprietary integrated circuit manufacturing process, which is expensive. At the same time, its electromagnetic induction signal transmission method is very susceptible to electromagnetic interference. When the system working conditions are relatively bad, the error voltage may not be transmitted correctly. Summary of the invention

[0007] In view of the above, the present invention provides an AC-DC converter feedback signal transmission circuit based on secondary side feedback, which uses a capacitor analog isolator to replace the traditional optocoupler isolator, and combines it with a load adaptive frequency jittering solution. While improving feedback accuracy, system bandwidth and other indicators, it effectively reduces the system's external electromagnetic interference and improves EMI performance. At the same time, it also has lower dynamic power consumption and can be fully integrated with the primary side main control chip, which helps to further improve the system power density.

[0008] An AC-DC converter feedback signal transmission circuit based on secondary side feedback is used to implement an AC-DC converter based on secondary side feedback to isolate and transmit the feedback signal generated by the secondary side to the primary side. The AC-DC converter feedback signal transmission circuit includes four ports and three circuits. The four ports are respectively a secondary side output voltage sampling terminal, an error comparison reference terminal, a mode reference voltage terminal, and a primary side feedback voltage output terminal. The three circuits are respectively:

[0009] The error voltage generating circuit is used to sample the output voltage of the AC-DC converter, divide the output voltage and send it to the internal operational amplifier for comparison with the reference voltage to generate a voltage error signal reflecting the load condition;

[0010] A frequency jittering signal generating circuit generates a frequency jittering signal having a jittering frequency and a jittering amplitude related to the load according to the voltage error signal when the AC-DC converter operates in a heavy load mode;

[0011] The isolated transmission circuit is used for electrical isolation between the primary and secondary sides of the AC-DC converter, and provides a feedback voltage signal to the primary side. The feedback voltage signal is the superposition of the voltage error signal and the frequency jitter signal.

[0012] Furthermore, the error voltage generating circuit includes an operational amplifier AMP1, three resistors R1~R3 ​​and a capacitor C1, wherein one end of R1 is connected to the secondary output voltage sampling end, the other end of R1 is connected to one end of R2 and one end of R3, the other end of R3 is connected to one end of C1 and the positive input end of AMP1, the other end of C1 is connected to the other end of R2 and connected to the secondary ground, the inverting input end of AMP1 is connected to the error comparison reference end, and the output end of AMP1 generates a voltage error signal.

[0013] Furthermore, the frequency-jittering signal generating circuit includes five NMOS tubes MN1-MN5, six PMOS tubes MP1-MP6, four inverters INV1-INV4, three transmission gates TG1-TG3, three current sources I1-I3, a voltage buffer BUF1, a capacitor C2 and a hysteresis comparator SCHMIT1, wherein the source of MP1, the source of MP2, the source of MP3, the source of MP5 and the input ends of the current sources I1-I3 are all connected to the power supply voltage VDD, and the gate of MP1 is connected to the gate of MP2 and the gate of MP5. The drain of MP5 is connected to the source of MP6, the drain of MP3 is connected to the source of MP4, the gate of MP6 is connected to the gate of MP3, the gate of MP4, the drain of MP4 and the drain of MN2, the output end of the current source I3 is connected to the drain of MP6 and a transmission end of TG3, the output end of the current source I2 is connected to the drain of MP2 and a transmission end of TG2, the output end of the current source I1 is connected to the drain of MP1 and a transmission end of TG1, the inverting end of SCHMIT1 is connected to the drain of MP6 and a transmission end of TG2, the output end of the current source I2 is connected to the drain of MP2 and a transmission end of TG2, the output end of the current source I1 is connected to the drain of MP1 and a transmission end of TG1, the inverting end of SCHMIT1 is connected to the drain of MP6 and the source of MP4, the gate of MP6 is connected to the gate of MP3, the gate of MP4, the drain of MP4 and the drain of MN2, the output end of the current source I3 is connected to the drain of MP6 and a transmission end of TG3, the output end of the current source I2 is connected to the drain of MP2 and a transmission end of TG2, the output end of the current source I1 is connected to the drain of MP1 and a transmission end of TG1, the inverting end of SCHMIT1 is connected to the drain of MP6 and the source of MP4, the gate of MP4 is connected to the gate of MP3, the gate of MP4, the drain of MP4 and the drain of MN2, the output end of the current source I3 is connected to the drain of MP6 and a transmission end of TG3, the output end of the current source I2 is connected to the drain of MP2 and a transmission end of TG2, the output end of the current source I1 is connected to the drain of MP1 and a transmission end of TG1, the inverting end of SCHMIT1 is connected to the drain of MP6 and the source The input terminal is connected to the mode reference voltage terminal, the positive phase output terminal of SCHMIT1 is connected to the negative gate terminal of TG1, the negative gate terminal of TG2 and the negative gate terminal of TG3, the inverting output terminal of SCHMIT1 is connected to the positive gate terminal of TG1, the positive gate terminal of TG2 and the positive gate terminal of TG3, the other transmission terminal of TG3 is connected to the drain of MN5, the gate of MN5 is connected to the output terminal of BUF1 and the input terminal of INV4, the source of MN5 is connected to the drain of MN4 and one end of C2 to generate a frequency jittering signal, the other end of C2 is connected to the source of MN3, MN4 and the input terminal of INV4, and the source of MN5 is connected to the drain of MN4 and one end of C2 to generate a frequency jittering signal. The source of MN2 is connected to the source of MN1 and is connected to the secondary ground, the source of MN4 is connected to the drain of MN3, the gate of MN4 is connected to the output end of INV4, the gate of MN3 is connected to the gate of MN2, the gate of MN1, the drain of MN1 and the other transmission end of TG2, the input end of BUF1 is connected to the output end of INV3 and the input end of INV1, the input end of INV3 is connected to the output end of INV2, the input end of INV2 is connected to the output end of INV1, and the power supply ends of INV1 to INV3 are all connected to the other transmission end of TG1.

[0014] Furthermore, the isolated transmission circuit includes eight resistors R4~R11, three capacitors C3~C5, three operational amplifiers AMP2~AMP4, three inverters INV5~INV7, a voltage buffer BUF2, a voltage comparator COMP1 and an isolation capacitor C_ISO, wherein the positive input terminal of AMP2 is connected to the voltage error signal, the inverting input terminal of AMP2 is connected to the output terminal of AMP2 and one end of R7, one end of R4 is connected to one end of C3 and connected to the frequency jitter signal, the other end of R4 is connected to the other end of C3, one end of R5, one end of R6 and the positive input terminal of AMP3, the other end of R5 is connected to the power supply voltage VDD, the other end of R6 is connected to the secondary ground, the inverting input terminal of AMP3 is connected to the other end of R7, one end of C4 and one end of R10, the output end of AMP3 is connected to the other end of C4 and one end of R8 The other end of R8 is connected to one end of R9 and the input end of INV5, the other end of R9 is connected to the input end of INV6 and the output end of INV5, the output end of INV6 is connected to the other end of R10, the input end of INV7 and the input end of BUF2, the output end of INV7 is connected to the positive phase input end of C_ISO, the output end of BUF2 is connected to the negative phase input end of C_ISO, the positive phase output end of C_ISO is connected to the positive phase input end of AMP4, the negative phase output end of C_ISO is connected to the negative phase input end of AMP4, the positive phase output end of AMP4 is connected to the positive phase input end of COMP1, the negative phase output end of AMP4 is connected to the negative phase input end of COMP1, the output end of COMP1 is connected to one end of R11, the other end of R11 is connected to one end of C5 and connected to the primary feedback voltage output end, and the other end of C5 is connected to the primary ground.

[0015] Furthermore, the secondary output voltage sampling terminal is connected to the output voltage of the AC-DC converter through a feedback current limiting resistor, and the error comparison reference terminal is connected to an externally given reference voltage. Adjusting the magnitude of the reference voltage can stabilize the output voltage of the AC-DC converter at different values.

[0016] Furthermore, the mode reference voltage is connected to an externally given mode reference voltage, and the mode reference voltage is used to determine the load condition of the current AC-DC converter. When the voltage error signal is less than the mode reference voltage, it is determined that the AC-DC converter is operating in a heavy load mode.

[0017] Furthermore, the primary side feedback voltage output terminal is used to provide a feedback voltage signal to the primary side, which reflects the current load condition of the AC-DC converter. The primary side main control chip uses the signal to adjust the turn-on time and frequency of the main switch tube in the AC-DC converter, stabilize the output voltage of the AC-DC converter, and realize closed-loop control of the output voltage.

[0018] Furthermore, the AC-DC converter feedback signal transmission circuit may be integrated with a main control chip of the AC-DC converter.

[0019] The AC-DC converter feedback signal transmission circuit of the present invention generates a voltage error signal based on the sampling of the output voltage and compares it with the input voltage reference, and detects the load condition of the system. When overloaded, it adaptively generates a voltage frequency-jittering signal according to the size of the output load, superimposes the voltage error signal and the adaptive frequency-jittering signal, and finally transmits the superimposed signal to the primary side main control chip through the isolation transmission circuit. The primary side main control chip adaptively adjusts the switching frequency of the primary side main power tube according to the size of the error signal to achieve closed-loop control of the output voltage. Compared with traditional optocoupler isolation transmission, the present invention uses capacitor isolation transmission, which optimizes the system EMI performance and obtains a larger system bandwidth and feedback accuracy, while also having smaller dynamic power consumption, and can be fully integrated with the primary side main control chip, which helps to further improve the system power density. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The diagram is a structural diagram of an existing isolated switching power supply feedback circuit.

[0021] Figure 2 It is a structural schematic diagram of another existing isolated switching power supply feedback circuit.

[0022] Figure 3 It is a structural schematic diagram of an AC-DC converter based on secondary-side feedback, its main control chip, and feedback signal transmission circuit.

[0023] Figure 4 It is a schematic diagram of the structure of the feedback signal transmission circuit of the present invention.

[0024] Figure 5 Schematic diagram of the structure of the error voltage generating circuit.

[0025] Figure 6 Schematic diagram of the structure of the frequency jitter signal generating circuit.

[0026] Figure 7 Schematic diagram of waveforms of the voltage error signal V_error, the ring oscillator output voltage signal V_osc, and the frequency jitter signal V_jitter when the system load changes.

[0027] Figure 8 It is a structural schematic diagram of the isolation transmission circuit. DETAILED DESCRIPTION

[0028] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0029] like Figure 3 As shown, the feedback signal transmission circuit of the AC-DC converter of the present invention includes an output voltage sampling Vin terminal, an error comparison reference VREF terminal, a mode reference voltage V_mode terminal, and a primary feedback voltage output FB terminal. The power stage circuit of the AC-DC converter includes an input terminal, an output terminal, an EMI filter circuit, a rectifier circuit, and a transformer T 1 , Main power tube Q L , Clamping tube Q H , Clamping capacitor C C , Excitation current sampling resistor R CS , rectifier diode D 1 , output filter capacitor C 1 , output filter inductor L 1 , output capacitor C O , feedback current limiting resistor R FB .

[0030] like Figure 4 As shown, the feedback signal transmission circuit of the AC-DC converter of the present invention also includes an error voltage generating circuit, a frequency jittering signal generating circuit and an isolation transmission circuit, one input end of the error voltage generating circuit is connected to the secondary side output voltage sampling Vin end, the other input end of the error voltage generating circuit is connected to the error comparison reference VREF end, the output end of the error voltage generating circuit is connected to an input end of the frequency jittering signal generating circuit and an input end of the isolation transmission circuit, the other input end of the frequency jittering signal generating circuit is connected to the mode reference voltage V_mode end, the output end of the frequency jittering signal generating circuit is connected to the other input end of the isolation transmission circuit, and the output end of the isolation transmission circuit is the feedback voltage output FB end.

[0031] like Figure 5 As shown, due to the feedback current limiting resistor R in the power stage circuit FB It is much smaller than the voltage divider resistors R1 and R2 in the error voltage generation circuit. It can be approximately considered that the input Vin of the error voltage generation circuit is equal to the power stage output voltage Vo. After Vin is divided by R1 and R2, it is filtered out by R3 and C1 to form an RC low-pass filter to filter out high-frequency glitches. The voltage at the non-inverting input of the error amplifier AMP1 is approximately When the external input voltage comparison reference VREF is constant, the heavier the AC-DC converter system output load, the higher the V of the error voltage generating circuit. inThe lower the input voltage, the lower the voltage at the in-phase input terminal of the error amplifier AMP1, and the lower the output voltage V_error of the error amplifier AMP1. On the contrary, if the output load of the AC-DC converter is lighter, the output voltage V_error of the error amplifier AMP1 is higher, and the output voltage V_error of the error amplifier AMP1 reflects the severity of the system load. The output voltage of the error amplifier AMP1 is sent to the frequency-jittering signal generating circuit, and the jittering frequency and jittering amplitude of the frequency-jittering signal are controlled by the size of the error voltage V_error and adjusted as the load is adjusted. Since the feedback signal received by the primary main control chip is the superposition of the frequency-jittering signal and the voltage error signal V_error, the primary main power tube Q L The turn-on frequency will also have corresponding frequency jitter to improve the system EMI performance.

[0032] like Figure 6 As shown in FIG. 1 , the channel width-to-length ratio of the P-channel MOS tubes MP1, MP2, and MP5 is 1:5:5. When they work in the saturation region, their source-to-drain current is Except for the MOS channel width-to-length ratio Outside, μ p is the hole mobility, C ox is the gate oxide capacitance per unit area, V THp is the turn-on threshold voltage of the P-channel MOS tube. These parameters are only related to the process.

[0033] When the external input voltage comparison reference VREF is constant, the lighter the output load of the AC-DC converter system, the higher the output voltage V_error of the error amplifier AMP1; on the contrary, if the output load of the AC-DC converter is heavier, the output voltage V_error of the error amplifier AMP1 is lower; therefore, the source and drain currents of MP1, MP2, and MP5 are all regulated by the system load conditions. The heavier the load, the greater the source and drain current. The three identical inverters INV1, INV2, and INV3 form a three-stage ring oscillator. When the transmission gate TG1 is turned on, the oscillation period of the ring oscillator is approximately Where VDD is the power supply voltage, C in is the input capacitance of the inverter, I sd1 is the drain-source current of the P-channel MOS tube MP1. Since the input capacitance of the inverter is only related to the process, the oscillation frequency of the ring oscillator is only regulated by the system load. The heavier the system load, the greater the oscillation frequency. The output of the ring oscillator is shaped by the voltage buffer BUF1. The output of BUF1 and the output of the inverter INV4 serve as a set of complementary switch control signals to control the NMOS switches MN5 and MN4 to be turned on alternately, and the capacitor C2 will be charged and discharged alternately.

[0034] When capacitor C2 is charged and discharged alternately, the waveform at both ends of it, that is, the jitter output V_jitter of the jitter signal generating circuit, will be similar to a triangular wave. When C2 is charged, the amplitude of the voltage rise at both ends is When C2 discharges, the voltage drop across it is Among them I charge ,I discharge are the charging and discharging currents of C2 respectively. The width-to-length ratio of N-channel MOS tubes MN1, MN2, and MN3 is 1:1:1, so I charge =I discharge =I 3 +I sd5 =I 2 +I sd2 , where I sd5 and I sd2 are the drain-source currents of MP5 and MP2 respectively. The voltage rise and fall amplitudes of capacitor C2 are the same when charging and discharging. The oscillation frequency of the ring oscillator increases with the increase of load, and the jitter output V_jitter frequency of the jitter signal generation module will increase with the increase of load. sd5 ,I sd2 are all regulated by the error voltage V_error, and the heavier the load, the greater the I sd5 ,I sd2 The larger the charge and discharge current I of capacitor C2 is, charge ,I discharge The larger the When the load increases, the gate voltage of MP1 decreases, causing I sd1 Increase, T OSC will decrease. However, since the channel width-to-length ratio of MP1, MP2, and MP5 is 1:5:5, when the load increases, T OSC The reduction will be much smaller than I charge ,I discharg e increases, so when the load increases, V up / down That is, the amplitude of the frequency-jittering signal V_jitter will still increase.

[0035] As the load continues to increase, the frequency and amplitude of the frequency-jittering signal will not increase infinitely. When the load increases further, V_error decreases further until MP1, MP2, and MP5 enter the deep linear region. At this time, the drain-source current of the MOS tube will no longer increase with the decrease of V_error, and the behavior of MP1, MP2, and MP5 will be similar to a constant current source, thereby limiting the maximum oscillation frequency and I charge ,I discharge The size of the jitter signal is the maximum jitter frequency and jitter amplitude.

[0036] Since the primary side main control chip uses the feedback signal FB to judge the system load condition and realize the closed-loop control of the system, and the feedback signal FB is the superposition of the voltage error signal and the frequency jitter signal; when the output load of the AC-DC converter is at the junction of heavy load and light load, the frequency jitter signal may affect the primary side main control chip's judgment of the system load condition, and the system works under light load conditions, the primary side excitation current is small, and the main switch tube is disconnected. Much smaller than under heavy load Therefore, in light load mode, the system's external electromagnetic interference is small, and there is no need to use frequency jitter to disperse the electromagnetic interference energy. In order to reduce the impact of frequency jitter on the system state when the primary side main control chip mode is switched and improve the system's working stability, in the feedback signal transmission circuit, the frequency jitter will be turned off before the system enters the light load mode. The specific implementation method is as follows: When the system load decreases, the output V_error of the error signal production circuit will increase. When the value of V_error is greater than the external input mode voltage reference V_mode, the chip will determine that the AC-DC converter system output transitions from heavy load to light load. At this time, the positive output end of the hysteresis comparator SCHMIT1 will output 1, and the negative output end will output 0. The transmission gates TG1, TG2, and TG3 will be turned off at the same time, and the frequency jitter function will not be enabled. Due to the hysteresis characteristics of the hysteresis comparator, when the system load increases again, V_error decreases, and the voltage difference between the external input mode reference voltage V_mode and V_error is the hysteresis window voltage, the output of the hysteresis comparator will flip again to enable the frequency jitter function. Figure 7 shown.

[0037] The voltage error signal output by the error voltage generating circuit and the frequency jitter signal output by the frequency jitter signal generating circuit will be superimposed in the isolation transmission circuit and transmitted to the primary side main control chip as the feedback signal of the AC-DC converter.

[0038] like Figure 8In the isolated transmission circuit shown, the high-voltage isolation capacitor C_ISO is connected across the primary and secondary sides, providing a signal transmission path between the primary and secondary sides while maintaining electrical isolation between the primary and secondary sides. The signal path formed by C_ISO has a high-pass characteristic, and the feedback signal of the secondary side cannot pass directly and needs to be modulated to a high frequency. In the isolated transmission circuit, sigma-delta modulation is used for the signal, the operational amplifier AMP3 and the capacitor C4 form an integrator, the inverter INV6 forms a one-bit quantizer part, the resistor R10 forms a 1-bit DAC, and the resistors R8, R9, and the inverter INV5 form an inverting amplifier structure to amplify the fluctuation of the integrator output formed by AMP3 and C4; at the same time, the inverters INV6, INV5, and INV3 also form a three-stage ring oscillator structure to generate the clock signal required for modulation, so that the continuous signal to discrete signal to sampling and quantization can be completed at the inverter INV6. The above parts constitute the first-order delta-sigma modulator function.

[0039] In order to reduce noise interference and improve voltage driving capability, V_error is not directly fed into the delta-sigma modulation loop, but is fed into the voltage follower formed by the operational amplifier AMP2, and the input of the voltage follower is fed into the modulation loop. At the same time, R5 and R6 (R4>>R5, R6) divide the VDD voltage to obtain the DC value of the integrator reference voltage formed by AMP3 and C4, which is approximately Since the output V_jitter of the frequency jittering generation circuit cannot be directly superimposed with V_error, the output V_jitter of the frequency jittering generation circuit passes through the RC high-pass network composed of R4, R5, R6, and C3 to filter out the DC component to obtain the AC component, which is then superimposed with the voltage division of VDD by R5 and R6. That is, the frequency jittering signal is first superimposed with the integrator reference voltage. In this way, the output of the integrator will contain the information of V_jitter and V_error at the same time, and the superposition of the frequency jittering signal and the voltage error signal is indirectly realized in the modulation loop.

[0040] The output of the inverter INV7 and the output of the voltage buffer BUF2 form a set of differential signals, which are sent to the isolation capacitor C_ISO and transmitted to the primary side through C_ISO. The signal received from the isolation capacitor C_ISO will be greatly attenuated and needs to be restored before demodulation. The operational amplifier AMP4 has sufficient gain to amplify the signal received from C_ISO. The differential output of the operational amplifier AMP4 is sent to the voltage comparator COMP1, and its output is the restored delta-sigma modulated signal; finally, the delta-sigma modulated signal is demodulated through the RC low-pass filter composed of R11 and C5 to obtain the feedback signal FB of the primary side main control chip.

[0041] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments. Improvements and modifications made by those skilled in the art to the present invention based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A feedback signal transmission circuit of an AC-DC converter based on secondary side feedback, used to realize an AC-DC converter based on secondary side feedback to isolate and transmit the feedback signal generated by the secondary side to the primary side, Features: The AC-DC converter feedback signal transmission circuit includes four ports and three circuits. The four ports are a secondary output voltage sampling terminal, an error comparison reference terminal, a mode reference voltage terminal, and a primary feedback voltage output terminal. The three circuits are: The error voltage generating circuit is used to sample the output voltage of the AC-DC converter, divide the output voltage and send it to the internal operational amplifier for comparison with the reference voltage to generate a voltage error signal reflecting the load condition; A frequency jittering signal generating circuit generates a frequency jittering signal having a jittering frequency and a jittering amplitude related to the load according to the voltage error signal when the AC-DC converter operates in a heavy load mode; The isolation transmission circuit is used for electrical isolation between the primary and secondary sides of the AC-DC converter, and provides a feedback voltage signal to the primary side. The feedback voltage signal is a superposition of a voltage error signal and a frequency jitter signal. The frequency-jittering signal generating circuit includes five NMOS transistors MN1-MN5, six PMOS transistors MP1-MP6, four inverters INV1-INV4, three transmission gates TG1-TG3, three current sources I1-I3, a voltage buffer BUF1, a capacitor C2 and a hysteresis comparator SCHMIT1, wherein the source of MP1, the source of MP2, the source of MP3, the source of MP5 and the input ends of the current sources I1-I3 are all connected to the power supply voltage VDD, the gate of MP1 is connected to the gate of MP2, the gate of MP5 and the S The positive input terminal of CHMIT1 is connected to the voltage error signal, the drain of MP5 is connected to the source of MP6, the drain of MP3 is connected to the source of MP4, the gate of MP6 is connected to the gate of MP3, the gate of MP4, the drain of MP4 and the drain of MN2, the output terminal of current source I3 is connected to the drain of MP6 and a transmission terminal of TG3, the output terminal of current source I2 is connected to the drain of MP2 and a transmission terminal of TG2, the output terminal of current source I1 is connected to the drain of MP1 and a transmission terminal of TG1, and the inverting input terminal of SCHMIT1 is connected to the negative input terminal of SCHMIT1. The termination mode reference voltage terminal, the positive phase output terminal of SCHMIT1 is connected to the negative gate terminal of TG1, the negative gate terminal of TG2 and the negative gate terminal of TG3, the inverting output terminal of SCHMIT1 is connected to the positive gate terminal of TG1, the positive gate terminal of TG2 and the positive gate terminal of TG3, the other transmission terminal of TG3 is connected to the drain of MN5, the gate of MN5 is connected to the output terminal of BUF1 and the input terminal of INV4, the source of MN5 is connected to the drain of MN4 and one end of C2 and generates a frequency jittering signal, the other end of C2 is connected to the source of MN3, MN2 The source of MN4 is connected to the drain of MN3, the gate of MN4 is connected to the output end of INV4, the gate of MN3 is connected to the gate of MN2, the gate of MN1, the drain of MN1 and the other transmission end of TG2, the input end of BUF1 is connected to the output end of INV3 and the input end of INV1, the input end of INV3 is connected to the output end of INV2, the input end of INV2 is connected to the output end of INV1, and the power supply ends of INV1 to INV3 are all connected to the other transmission end of TG1.

2. The AC-DC converter feedback signal transmission circuit according to claim 1, Features: The error voltage generating circuit includes an operational amplifier AMP1, three resistors R1 to R3 and a capacitor C1, wherein one end of R1 is connected to the secondary output voltage sampling end, the other end of R1 is connected to one end of R2 and one end of R3, the other end of R3 is connected to one end of C1 and the positive input end of AMP1, the other end of C1 is connected to the other end of R2 and connected to the secondary ground, the inverting input end of AMP1 is connected to the error comparison reference end, and the output end of AMP1 generates a voltage error signal.

3. The AC-DC converter feedback signal transmission circuit according to claim 1, Features: The isolated transmission circuit includes eight resistors R4-R11, three capacitors C3-C5, three operational amplifiers AMP2-AMP4, three inverters INV5-INV7, a voltage buffer BUF2, a voltage comparator COMP1 and an isolation capacitor C_ISO, wherein the positive phase input terminal of AMP2 is connected to the voltage error signal, the negative phase input terminal of AMP2 is connected to the output terminal of AMP2 and one end of R7, one end of R4 is connected to one end of C3 and connected to the frequency jitter signal, the other end of R4 is connected to the other end of C3, one end of R5, one end of R6 and the positive phase input terminal of AMP3, the other end of R5 is connected to the power supply voltage VDD, the other end of R6 is connected to the secondary ground, the negative phase input terminal of AMP3 is connected to the other end of R7, one end of C4 and one end of R10, and the output terminal of AMP3 is connected to the other end of C4 and one end of R8 , the other end of R8 is connected to one end of R9 and the input end of INV5, the other end of R9 is connected to the input end of INV6 and the output end of INV5, the output end of INV6 is connected to the other end of R10, the input end of INV7 and the input end of BUF2, the output end of INV7 is connected to the positive phase input end of C_ISO, the output end of BUF2 is connected to the negative phase input end of C_ISO, the positive phase output end of C_ISO is connected to the positive phase input end of AMP4, the negative phase output end of C_ISO is connected to the negative phase input end of AMP4, the positive phase output end of AMP4 is connected to the positive phase input end of COMP1, the negative phase output end of AMP4 is connected to the negative phase input end of COMP1, the output end of COMP1 is connected to one end of R11, the other end of R11 is connected to one end of C5 and connected to the primary feedback voltage output end, and the other end of C5 is connected to the primary ground.

4. The AC-DC converter feedback signal transmission circuit according to claim 1, Features: The secondary side output voltage sampling terminal is connected to the output voltage of the AC-DC converter through a feedback current limiting resistor, and the error comparison reference terminal is connected to an externally given reference voltage. By adjusting the reference voltage, the output voltage of the AC-DC converter can be stabilized at different values.

5. The AC-DC converter feedback signal transmission circuit according to claim 1, Features: The mode reference voltage is connected to an externally given mode reference voltage, and the mode reference voltage is used to determine the load condition of the current AC-DC converter. When the voltage error signal is less than the mode reference voltage, it is determined that the AC-DC converter is operating in a heavy load mode.

6. The AC-DC converter feedback signal transmission circuit according to claim 1, Features: The primary side feedback voltage output terminal is used to provide a feedback voltage signal to the primary side, which reflects the current load condition of the AC-DC converter. The primary side main control chip uses the signal to adjust the turn-on time and frequency of the main switch tube in the AC-DC converter, stabilize the output voltage of the AC-DC converter, and realize closed-loop control of the output voltage.

7. The AC-DC converter feedback signal transmission circuit according to claim 1, Features: The feedback signal transmission circuit is integrated with the main control chip of the AC-DC converter.

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