Receiver and transmitter for high speed data and low speed command signal transmission

Abstract

A receiver and a transmitter are disclosed. The receiver is configured to receive a serial command signal and a serial data signal from the transmitter and includes a first clock data recovery circuit, a control circuit, and a second clock data recovery circuit. The first clock data recovery circuit is configured to process the serial command signal to generate a clock signal. The control circuit, coupled to the first clock data recovery circuit, is configured to generate a control signal based on the serial command signal and the clock signal from the first clock data recovery circuit. The second clock data recovery circuit, coupled to the control circuit, is configured to process the serial data signal based on the control signal from the control circuit.

Description

[0001] The original application date is March 17, 2021, the original application number is 202110286724.7, and the original application invention name is "Receiver and transmitter for high-speed data and low-speed instruction signal transmission". TECHNICAL FIELD

[0002] The present application relates to a signal transmission system, in particular to a signal transmission system with a receiver and a transmitter and having the ability to transmit high-speed data and low-speed instruction signals. BACKGROUND

[0003] In the conventional signal transmission system on the circuit board, after the power is started, the host device should send an instruction signal to control the slave device to start operation, and then the data signal can be transmitted between the host device and the slave device.

[0004] There are many common signal transmission methods in the signal transmission system. In an example, the instruction signal is transmitted using the same signal rate as the high-speed data rate to achieve high-speed serial transmission, however, the receiver may not be able to complete the setting to normally receive the high-speed instruction signal before the instruction signal is correctly received. In another embodiment, the instruction signal can also be transmitted independently, but it has the disadvantages of more paths and hardware settings. Alternatively, the slave device can be provided with a fixed setting value, but this setting value cannot be flexibly adjusted under different conditions.

[0005] Therefore, it is necessary to propose a new type of signal transmission system which has the ability to transmit low-speed instruction signals and high-speed data signals. SUMMARY

[0006] Therefore, the main purpose of the present application is to provide a signal transmission system with a receiver and a transmitter and having the ability to transmit high-speed data and low-speed instruction signals.

[0007] An embodiment of the present application discloses a receiver for receiving a serial instruction signal and a serial data signal. The receiver comprises a first clock and data recovery (CDR) circuit, a control circuit and a second clock and data recovery circuit. The first clock and data recovery circuit can be used to process the serial instruction signal to generate a clock signal. The control circuit is coupled to the first clock and data recovery circuit and can be used to generate a control signal according to the serial instruction signal and the clock signal from the first clock and data recovery circuit. The second clock and data recovery circuit is coupled to the control circuit and can be used to process the serial data signal according to the control signal from the control circuit.

[0008] Another embodiment of the present invention discloses a transmitter for transmitting a serial command signal and a serial data signal. The transmitter includes a serializer and a multiplexer. The serializer is operable to generate the serial data signal. The multiplexer is coupled to the serializer and is operable to select the serial command signal or the serial data signal for output.

[0009] Another embodiment of the present invention discloses a receiver coupled to a transmitter through a plurality of channels for receiving a serial command signal and a serial data signal from the transmitter. The receiver includes a control circuit and a first clock data recovery circuit. The control circuit is operable to receive the serial command signal through a first channel of the plurality of channels and a clock signal through a second channel of the plurality of channels to generate a first control signal based on the serial command signal and the clock signal. The first clock data recovery circuit is coupled to the control circuit and is operable to process the serial data signal based on the first control signal from the control circuit.

[0010] Another embodiment of the present invention discloses a transmitter coupled to a receiver through a plurality of channels for transmitting a serial command signal and a serial data signal to the receiver. The transmitter includes a serializer and a first multiplexer. The serializer is operable to generate the serial data signal. The first multiplexer is coupled to the serializer and is operable to select the serial command signal or the serial data signal for transmission to a first channel of the plurality of channels. A clock signal corresponding to the serial command signal is transmitted through a second channel of the plurality of channels. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figures 1 to 3 is a schematic diagram of a signal transmission system.

[0012] Figure 4 and Figure 5 is a schematic diagram of a signal transmission system according to an embodiment of the present invention.

[0013] Figure 6 shows several exemplary Manchester coding methods that can be used in a signal transmission system.

[0014] Figure 7 is a schematic diagram of a signal transmission system according to another embodiment of the present invention.

[0015] Figure 8 is a schematic diagram of a signal transmission system according to yet another embodiment of the present invention.

[0016] In the drawings:

[0017] 10, 20, 30, 40, 50, 70, 80 signal transmission system

[0018] 100, 200, 300, 400, 500, 700, 800 transmitter

[0019] 102, 202, 302, 402, 502, 702, 802 serializer

[0020] 104, 204, 214, 304, 404, 504, 704_1, output buffer

[0021] 704_2, 804

[0022] 150, 250, 350, 450, 550, 750, 850 receiver

[0023] 152, 252, 352, 452, 552, 752, 852 termination circuit

[0024] 154, 254, 354, 454, 554, 754, 854 equalizer

[0025] 156, 256, 356, 456_1, 456_2, 556_1, clock data recovery circuit 756, 856

[0026] 158, 258, 358, 458, 558, 758, 858 control circuit

[0027] 160, 260, 360, 460, 560, 760, 860 deserializer

[0028] 162 frequency divider

[0029] CH1, CH2, CHa, CHb channel

[0030] 406, 506, 706, 806 multiplexer

[0031] 508 Manchester encoder

[0032] 510 XOR gate

[0033] 556_2 Manchester decoder

[0034] P1, P2 pair of transceivers DETAILED DESCRIPTION

[0035] Please refer to Figure 1 , Figure 1 is a schematic diagram of a signal transmission system 10. As Figure 1As shown, the signal transmission system 10 includes a transmitter 100 and a receiver 150. The transmitter 100 may be a host device (such as a system processor) located on a circuit board, and it includes a serializer 102 and an output buffer 104. Serial command signals and serial data signals from the digital circuitry in the system processor can be transmitted through the transmitter 100. The serializer 102 can perform parallel-to-serial conversion on the command signals and data signals to generate serialized command signals and data signals. The output buffer 104 is used to output the command signals and data signals to the receiver 150.

[0036] Receiver 150 may be a slave device (such as an integrated circuit, IC) located on a circuit board, comprising a termination circuit 152, an equalizer 154, a clock and data recovery (CDR) circuit 156, a control circuit 158, a deserializer 160, and a frequency divider 162. The termination circuit 152, typically located in a high-speed transmission system, is used for impedance matching and may include terminating resistors or any other similar circuit components that can generate impedance. The equalizer 154 is used to compensate for signal loss occurring on the channel. The clock and data recovery circuit 156 is used to extract the clock signal embedded in the received command and data signals. The clock signal can then be divided by the frequency divider 162 to generate another clock signal with a lower frequency for use by the control circuit 158. The control circuit 158 ​​can be a digital circuit located inside an integrated circuit, which can be used to control the operation of various circuit blocks in the receiver 150. The deserializer 160 can be used to perform serial-to-parallel conversion on the data signal, thereby outputting the data signal to subsequent circuits in parallel form.

[0037] like Figure 1 As shown, transmitter 100 can transmit serial command signals (denoted by C) and serial data signals (denoted by D) to receiver 150. Note that the command signal is transmitted and received before the data signal. The command signal can be used to start or configure circuit blocks in receiver 150, such as termination circuit 152, equalizer 154, and clock data recovery circuit 156. Therefore, when the command signal is successfully received and processed, it means that the circuit blocks in receiver 150 are ready to receive and process high-speed data signals. In this example, the command signal and data signal are transmitted at high speed through the same channel. However, the circuit blocks in receiver 150 need to be started or configured according to the command signal; before initialization is complete, these circuit blocks cannot successfully receive and process the high-speed command signal.

[0038] Referring to Figure 2 , Figure 2 is a schematic diagram of a signal transmission system 20. As shown in Figure 2 , the signal transmission system 20 includes a transmitter 200 and a receiver 250. The transmitter 200 includes a serializer 202 and an output buffer 204, which operate in a manner similar to the serializer 102 and the output buffer 104 of Figure 1 , respectively, and thus are not described in detail herein. The receiver 250 includes a termination circuit 252, an equalizer 254, a clock data recovery circuit 256, a control circuit 258, and a deserializer 260, which also operate in a manner similar to the termination circuit 152, the equalizer 154, the clock data recovery circuit 156, the control circuit 158, and the deserializer 160 of Figure 1 , respectively, and thus are not described in detail herein.

[0039] In the signal transmission system 20, data signals are transmitted through a main channel CHl, and command signals are transmitted through a command channel CH2, which is different from the main channel CHl. The command signals are transmitted at a low speed, so that the control circuit 258 can successfully receive and process the command signals. In this example, the transmitter 200 includes another output buffer 214 for outputting the command signals to the channel CH2. Since the command signals are transmitted at a low speed, they can be directly transmitted to the control circuit 258 without being processed by the termination circuit 252, the equalizer 254, and the clock data recovery circuit 256. In the signal transmission system 20, the command signals and the data signals are transmitted through different channels, and the command signals are transmitted at a low speed, so that the problem of the high-speed command signals being unable to be successfully received or processed in the signal transmission system 10 can be solved. However, the signal transmission system 20 needs to set up an additional channel, which accompanies the problems of cost increase and signal skew.

[0040] Referring to Figure 3 , Figure 3 is a schematic diagram of a signal transmission system 30. As shown in Figure 3 , the signal transmission system 30 includes a transmitter 300 and a receiver 350. The transmitter 300 includes a serializer 302 and an output buffer 304, which operate in a manner similar to the serializer 102 and the output buffer 104 of Figure 1 , respectively, and thus are not described in detail herein. The receiver 350 includes a termination circuit 352, an equalizer 354, a clock data recovery circuit 356, a control circuit 358, and a deserializer 360, which also operate in a manner similar to the termination circuit 152, the equalizer 154, the clock data recovery circuit 156, the control circuit 158, and the deserializer 160 of Figure 1 , respectively, and thus are not described in detail herein.

[0041] In Figure 3 the example, the instruction signal can be transmitted to the control circuit 358 through an input port, which is different from the receiving port of the data signal, thus requiring more port numbers and causing higher circuit cost.

[0042] Please refer to Figure 4 , Figure 4 Fig. 1 is a schematic diagram of a signal transmission system 40 according to an embodiment of the present application. As shown in Fig. 1, the signal transmission system 40 includes a transmitter 400 and a receiver 450. The transmitter 400 includes a serializer 402 and an output buffer 404, which operate in a similar manner to the serializer 102 and the output buffer 104 in Fig. 1, respectively, and thus are not described in detail herein. The receiver 450 includes a termination circuit 452, an equalizer 454, a control circuit 458 and a deserializer 460, which operate in a similar manner to the termination circuit 152, the equalizer 154, the control circuit 158 and the deserializer 160 in Fig. 1, respectively, and thus are not described in detail herein. Figure 4 Figure 1 In this example, the low-speed instruction signal and the high-speed data signal are transmitted through the same channel, and the instruction signal is transmitted and received before the data signal, so that the circuit blocks in the receiver 450 can be initialized by the instruction signal first, and then receive the high-speed data signal after successful initialization. Therefore, the signal transmission system 40 does not need additional ports or channels, and the signal offset problem in the signal transmission system 40 can be avoided. Figure 1

[0043] The transmitter 400 further includes a multiplexer (MUX) 406 coupled between the serializer 402 and the output buffer 404. The multiplexer 406 can be used to select the instruction signal or the data signal to be transmitted to the output buffer 404. In this example, the data signal and the instruction signal are transmitted to the transmitter 400 through different inputs. More specifically, the data signal is serialized by the serializer 402, while the instruction signal is directly transmitted to the multiplexer 406. By the control of the multiplexer 406, the data signal and the instruction signal can be combined and output to the same channel in a serial manner.

[0044]

[0045] ​​​To handle both the low-speed command signal and the high-speed data signal, the receiver 450 includes a high-frequency clock-data recovery circuit 456_1 and a low-frequency clock-data recovery circuit 456_2. The high-frequency clock-data recovery circuit 456_1 is used to process the high-speed data signal, and the low-frequency clock-data recovery circuit 456_2 is used to process the low-speed command signal. Since the command signal is received before the data signal, the low-frequency clock-data recovery circuit 456_2 can start processing the command signal before the data signal is received. According to the received command signal, the low-frequency clock-data recovery circuit 456_2 can generate a clock signal and output the clock signal and the command signal to a control circuit 458. The control circuit 458 can then send control signals to the termination circuit 452, the equalizer 454, and / or the high-frequency clock-data recovery circuit 456_1 to start or set up these circuit blocks. In this way, according to the received control signals, these circuit blocks can be ready to receive and process the high-speed data signal.

[0046] In this example, the serial command signal is a low-speed command signal, and the serial data signal is a high-speed data signal. The command signal and the data signal can be transmitted at any frequency or signal rate. As long as the data rate of the data signal is greater than the signal rate of the command signal, the transmission mechanism used and the associated transmitter and receiver are within the scope of the present application.

[0047] It is noted that, Figure 4 The use of two clock-data recovery circuits in the receiver 450 of FIG. 4 to process signals of different frequencies increases the hardware cost. In an embodiment, a wide-range clock-data recovery circuit can be used to replace the high-frequency clock-data recovery circuit 456_1 and the low-frequency clock-data recovery circuit 456_2. The wide-range clock-data recovery circuit can be used to process signals of a large frequency range. Generally, the data rate of the data signal is several times the signal rate of the command signal, and under a large frequency gap, the complexity and difficulty of the clock-data recovery circuit required also increase substantially.

[0048] To simplify the design of the clock data recovery circuit and reduce the circuit cost of the receiver, in one embodiment, the command signal can be transmitted according to a Manchester-like encoding scheme. Manchester-like encoding schemes include, but are not limited to, GE Thomas Manchester encoding, IEEE 802.3 Manchester encoding, and Differential Manchester encoding. For simplicity, these Manchester-like encodings will be collectively referred to as Manchester encoding below. If the command signal is processed using Manchester encoding, the low-frequency clock data recovery circuit 456_2 can be a Manchester decoder, which is simpler and cheaper than a general clock data recovery circuit.

[0049] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a signal transmission system 50 according to Embodiment 1 of the present invention. Figure 5 As shown, the signal transmission system 50 includes a transmitter 500 and a receiver 550. The transmitter 500 includes a serializer 502, an output buffer 504, and a multiplexer 506, which operate in a manner similar to... Figure 4 The serializer 402, output buffer 404, and multiplexer 406 in the receiver 550 will not be described in detail here. The receiver 550 includes a termination circuit 552, an equalizer 554, a clock data recovery circuit 556_1, a control circuit 558, and a deserializer 560, which operate in a manner similar to those described above. Figure 4 The terminal circuit 452, equalizer 454, high-frequency clock data recovery circuit 456_1, control circuit 458 and deserializer 460 are included in the circuit, so they will not be described in detail here.

[0050] The transmitter 500 also includes a Manchester encoder 508, coupled to the multiplexer 506, which encodes the command signal according to the Manchester encoding method. The Manchester encoding method enables the command signal transmitted to the receiver 550 to carry clock information; correspondingly, the receiver 550 can extract the clock signal without using complex clock data recovery circuitry and additional clock ports, thus reducing the circuit area and power consumption of the receiver 550. In another embodiment, the Manchester encoder 508 and the multiplexer 506 may also be included in the serializer 502, or integrated with it.

[0051] In detail, the Manchester encoder 508 can include a first input to receive the instruction signal, a second input to receive the clock signal, and an output. The clock signal can be set to have the same frequency as the instruction signal so that Manchester encoding becomes possible. After the instruction signal is encoded by the clock signal, the encoded instruction signal can be output through the output. In one embodiment, the Manchester encoder 508 can include an XOR gate 510, as shown in Figure 5 . The XOR gate 510 can perform an XOR operation on the original instruction signal and the clock signal to generate the encoded instruction signal.

[0052] Figure 6 Several exemplary Manchester encoding methods that can be used in the signal transmission system 50 are shown. As shown in Figure 6 , the possible Manchester encoding methods include G.E. Thomas Manchester encoding, IEEE 802.3 Manchester encoding, and differential Manchester encoding. According to the G.E. Thomas Manchester encoding, the rising edge of the clock signal is aligned with the transition time point of the instruction signal, and an XOR operation is applied on the clock signal and the instruction signal to generate the Manchester code. According to the IEEE 802.3 Manchester encoding, the falling edge of the clock signal is aligned with the transition time point of the instruction signal, and an XOR operation is applied on the clock signal and the instruction signal, and then the result of the XOR operation is inverted to generate the Manchester code. According to the differential Manchester encoding and based on the received instruction signal, the output Manchester code includes two states of high-to-low and low-to-high. Wherein, the instruction signal being "1" represents a state change; the instruction signal being "0" represents a state maintaining unchanged.

[0053] Referring back to Figure 5 , according to the Manchester encoding method used, the receiver 550 can further include a Manchester decoder 556_2. The Manchester decoder 556_2 can receive the encoded instruction signal, and then decode the encoded instruction signal to recover the original instruction signal while extracting the clock signal therefrom. In this way, the original instruction signal and the clock signal can be provided to the control circuit 558 so that the control circuit 558 can control the circuit blocks in the receiver 550 to initialize.

[0054] Due to the characteristics of Manchester encoding, original instruction signals and clock signals with the same frequency can be recovered by Manchester decoder 556_2 without receiving additional clock or trigger signals. Manchester decoder 556_2 requires only a simple circuit structure, which may include delay blocks or counters implemented by several logic gates, but is not limited to these. Those skilled in the art will be familiar with the detailed implementation and operation of Manchester decoder 556_2, and will not be elaborated upon here. In another embodiment, Manchester decoder 556_2 may be included in control circuit 558, or integrated with control circuit 558.

[0055] It is worth noting that the purpose of this invention is to provide a novel signal transmission system capable of transmitting both high-speed data and low-speed command signals. Those skilled in the art will be able to make modifications or variations accordingly, and are not limited thereto. For example, the above embodiment uses Manchester encoding to encode the command signal, thus the receiver does not need to use complex clock data recovery circuitry to decode and recover the clock signal and the original command signal. In another embodiment, other similar encoding methods are also feasible. Furthermore, in embodiments of this invention, depending on system requirements, termination circuitry and equalizers can be selectively included or omitted in the receiver, and / or output buffers can be selectively included or omitted in the transmitter. In addition, in the above embodiment, the command signal and clock signal are combined and transmitted through the same channel; however, in another embodiment, if multiple channels are coupled between the transmitter and receiver, the command signal and clock signal can effectively use these channels to be transmitted through different channels.

[0056] Please refer to Figure 7 , Figure 7 This is a schematic diagram of another signal transmission system 70 according to an embodiment of the present invention. Figure 7 As shown, the signal transmission system 70 includes a transmitter 700 and a receiver 750. The transmitter 700 includes a serializer 702 and a multiplexer 706, which operate in a manner similar to... Figure 4 The serializer 402 and multiplexer 406 in the receiver 750 will not be described in detail here. The receiver 750 includes a termination circuit 752, an equalizer 754, a clock data recovery circuit 756, a control circuit 758, and a deserializer 760, which operate in a manner similar to... Figure 4 The terminal circuit 452, equalizer 454, high-frequency clock data recovery circuit 456_1, control circuit 458 and deserializer 460 are included in the circuit, so they will not be described in detail here.

[0057] In this example, the channel connecting transmitter 700 and receiver 750 is a differential channel, which can be used to transmit high-speed differential data signal sequences. Before the differential data signals are transmitted, this channel can be used to transmit low-speed command signal sequences and corresponding clock signals. The differential channel includes two sub-channels CHa and CHb, one of which is used to transmit command signals, and the other is used to transmit clock signals simultaneously with the command signals. In this example, sub-channel CHa is used to transmit command signals and sub-channel CHb is used to transmit clock signals.

[0058] When receiver 750 receives a low-speed command signal, since terminal circuit 752, equalizer 754, and clock data recovery circuit 756 have not yet been configured, the command signal can be directly received by control circuit 758. Control circuit 758 can then initialize these circuit blocks according to the received command signal and its corresponding clock signal. After these circuit blocks are initialized, they are ready to receive and process high-speed data signals.

[0059] Therefore, during a data transmission, the differential channel between the transmitter 700 and the receiver 750 can be used to transmit differential data signals, while during a command transmission prior to the data transmission, the differential channel can be used to transmit command signals and clock signals. The transmitter 700 and the receiver 750 need to be arranged accordingly to implement the above transmission method.

[0060] like Figure 7 As shown, the transmitter 700 also includes two output buffers 704_1 and 704_2 coupled to the multiplexer 706. Specifically, output buffer 704_1 is coupled between the serializer 702 and the multiplexer 706, and is used to output a serial data signal to the multiplexer 706, which is then transmitted to the differential channel. Output buffer 704_1 and the multiplexer 706 are interconnected via two connection lines used to transmit differential data signals. Output buffer 704_2 is coupled to another input of the multiplexer 706, and is used to output a serial command signal and a clock signal to the multiplexer 706, which are then transmitted to the differential channel. Output buffer 704_2 and the multiplexer 706 are interconnected via two connection lines used to transmit two separate signals (i.e., the command signal and the clock signal). Therefore, multiplexer 706 can selectively transmit command / clock signals or data signals to the channels. More specifically, during command transmission, multiplexer 706 can transmit command signals and clock signals to sub-channels CHa and CHb respectively; while during data transmission after command transmission, multiplexer 706 can transmit differential data signals to sub-channels CHa and CHb.

[0061] The circuit structure of receiver 750 is similar to Figure 5 The circuit structure of receiver 550 is shown, except that receiver 750 does not include a Manchester decoder. Therefore, the control circuit 758 of receiver 750 can directly receive command signals and clock signals from transmitter 700 through a differential channel. More specifically, receiver 750 can receive command signals through sub-channel CHa and clock signals through sub-channel CHb.

[0062] Please refer to Figure 8 , Figure 8 This is a schematic diagram of another signal transmission system 80 according to an embodiment of the present invention. Figure 8 As shown, the signal transmission system 80 includes two pairs of transceivers P1 and P2. Each transceiver includes a serializer 802, an output buffer 804, and a multiplexer 806, and their operation is similar to that of... Figure 4 The serializer 402, output buffer 404, and multiplexer 406 in the circuit are not described in detail here; each receiver includes a terminal circuit 852, an equalizer 854, a clock data recovery circuit 856, a control circuit 858, and a deserializer 860, and their operation is similar to that of the serializer 402, output buffer 404, and multiplexer 406 in the circuit. Figure 4 The terminal circuit 452, equalizer 454, high-frequency clock data recovery circuit 456_1, control circuit 458, and deserializer 460 are included in the serializer 802, and will not be described in detail here. In another embodiment, the multiplexer 806 may also be included in the serializer 802, or integrated with the serializer 802.

[0063] In this example, the transceiver is coupled to the transmitter and receiver in P1 via a channel CH1, while the transceiver is coupled to the transmitter and receiver in P2 via a channel CH2. Therefore, if channel CH1 is set to transmit command signals, channel CH2 can be set to transmit the corresponding clock signals simultaneously with the transmission of command signals.

[0064] In detail, during the instruction transmission period, channel CHl can transmit the instruction signal and channel CH2 can transmit the clock signal. During the data transmission period after the instruction transmission period, both channels CHl and CH2 are used to transmit the data signal. Therefore, at the transmitter side, the output buffer 804 and the multiplexer 806 in the transmitter of the transceiver pair Pl are used to output a serial instruction signal and then output a serial data signal; the output buffer 804 and the multiplexer 806 in the transmitter of the transceiver pair P2 are used to output the clock signal and then output another serial data signal. At the receiver side, the receivers of the transceiver pairs Pl and P2 can share the same control circuit 858, which can receive the instruction signal from channel CHl and receive the clock signal from channel CH2, so as to start or set the termination circuit 852, the equalizer 854 and the clock data recovery circuit 856 in the receiver of each transceiver pair Pl and P2.

[0065] The embodiments of the present application can be widely applied to the transmission between different integrated circuits, and the channels can be any inter-chip interface with high-speed data transmission capability, such as Mobile Industry Processor Interface (MIPI) or Inter-Integrated Circuit (I2C) interface.

[0066] In summary, the present application provides a signal transmission system with high-speed data and low-speed instruction signal transmission capability. The low-speed instruction signal can be transmitted through the same channel before the high-speed data signal. According to the instruction signal, the circuit blocks in the receiver can be set to be ready to receive the data signal. The instruction signal can be successfully received by using appropriate clock signal, so the receiver can include high-frequency clock data recovery circuit for processing high-speed data signal, and also include low-frequency clock data recovery circuit or decoder for processing low-speed instruction signal. In an embodiment, the clock information can be embedded in the instruction signal by using Manchester-like encoding, so the decoder can extract the clock information from the received instruction signal. Alternatively, when the instruction signal is transmitted, the clock signal can be transmitted through another available channel at the same time. For example, if a differential channel is provided between the transmitter and the receiver, one sub-channel of the differential channel can be used to transmit the instruction signal and the other sub-channel can be used to transmit the clock signal. In another embodiment, two pairs of transceivers (transmitter plus receiver) can be used to transmit / receive the instruction signal and the clock signal respectively. Therefore, according to the embodiments of the present application, the instruction signal (with corresponding clock signal) can be transmitted through the existing channel without using additional clock port, so as to reduce the circuit area and cost.

[0067] The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A transmitter for transmitting a serial command signal and a serial data signal, the transmitter comprising: a serializer for generating the serial data signal; and a multiplexer coupled to the serializer for selecting the serial command signal or the serial data signal for output; wherein the serial command signal is for initializing a signal processing circuit within a receiver such that the signal processing circuit is able to receive the serial data signal; wherein a data rate of the serial data signal is greater than a signal rate of the serial command signal. The transmitter is for transmitting the serial command signal and the serial data signal over the same channel.

2. The transmitter of claim 1, wherein, The transmitter is for transmitting the serial command signal prior to transmitting the serial data signal.

3. The transmitter of claim 1, wherein, Further comprising:

4. The transmitter of claim 1, wherein, an encoder coupled to the multiplexer for encoding the serial command signal according to a type of Manchester encoding. The encoder comprises:

5. The transmitter of claim 4, wherein, a first input for receiving the serial command signal; a second input for receiving a clock signal; and an output for outputting the serial command signal encoded by the clock signal. Further comprising:

6. The transmitter of claim 1, wherein, an output buffer coupled to the multiplexer for outputting the serial command signal and the serial data signal.

7. A transmitter coupled to a receiver through a plurality of channels for transmitting a serial command signal and a serial data signal to the receiver, the transmitter comprising: a serializer for generating the serial data signal; and a first multiplexer coupled to the serializer for selecting the serial command signal or the serial data signal for transmission to a first channel of the plurality of channels; wherein a clock signal corresponding to the serial command signal is transmitted through a second channel of the plurality of channels; wherein the serial command signal is for initializing a signal processing circuit within the receiver such that the signal processing circuit is able to receive the serial data signal; wherein a data rate of the serial data signal is greater than a signal rate of the serial command signal. The transmitter is for transmitting the serial command signal prior to transmitting the serial data signal. The serial data signal is a differential signal transmitted through a differential channel, the differential channel comprising the first channel and the second channel.

8. The transmitter of claim 7, wherein, Further comprising:

9. The transmitter of claim 7, wherein, a first output buffer coupled to the first multiplexer for outputting the serial command signal through the first channel.

10. The transmitter of claim 7, wherein, The first output buffer is also for outputting the clock signal. Further comprising:

11. The transmitter of claim 10, wherein, a second output buffer coupled to the first multiplexer and the serializer for outputting the serial data signal.

12. The transmitter of claim 10, wherein, Further comprising: a third output buffer for outputting the clock signal to the second channel; and 13. The transmitter of claim 10, wherein, a second multiplexer coupled to the third output buffer for selecting the clock signal or another serial data signal for transmission to the second channel. ​ ​ ​

Images