A circuit architecture for a scrypt algorithm
By dividing the computation process of the Scrypt algorithm into three parallel computation sub-modules and running xor_salsa computation in parallel, the problem of low computational efficiency of the traditional Scrypt algorithm is solved, and high-efficiency computational performance is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI YIJIAXIN INTEGRATED CIRCUIT DESIGN CO LTD
- Filing Date
- 2022-12-09
- Publication Date
- 2026-04-28
AI Technical Summary
The traditional Scrypt algorithm cannot meet the requirements of high-performance computing chips, especially due to the excessively long computation time of the xor_salsa part, resulting in low computational efficiency.
A circuit architecture based on the Scrypt algorithm is adopted, which is divided into three operation sub-modules that run xor_salsa calculations in parallel, including an input module, an operation module, and a memory module. The calculation results are extracted at intervals through a decimation unit to improve the parallelism of the calculation.
By using staged parallel computation, the computational efficiency of the Scrypt algorithm is significantly improved, meeting the requirements of high-performance computing and shortening the total computation time.
Smart Images
Figure CN115883518B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of blockchain technology, and mainly to a circuit architecture for the Scrypt algorithm. Background Technology
[0002] Scrypt is a memory-dependent Proof-of-Work (PoW) algorithm widely used in the blockchain field. The core of the Scrypt algorithm is the salsa algorithm, which operates in two main phases: the first phase determines the set of computational objects; the second phase is the propagation of link relationships, which employs a "random walk model."
[0003] The Scrypt algorithm requires two rounds of 1024-round Xor_salsa calculations for the Xor_salsa part. The Xor_salsa part of the Scrypt algorithm consumes a significant amount of computation time for the salsa8 part. Traditional methods for handling this... Figure 1 As shown, the two 1024-round computation stages are not parallelized, which cannot meet the requirements of high-performance algorithm computing chips. Therefore, it is particularly important to provide an Scrypt algorithm circuit architecture with high computational efficiency that meets the needs of high-performance computing. Summary of the Invention
[0004] This invention provides a circuit architecture for the Scrypt algorithm, which aims to reduce the average computation time of task data and improve computing power.
[0005] To achieve the above objectives, this invention provides a circuit architecture for the Scrypt algorithm, which includes an input module, a computation module, and a memory module. The computation module includes a decimation unit.
[0006] The input module is used to send multiple tasks to be calculated into the calculation module;
[0007] The computing module is used to perform parallel xor_salsa operations on the multiple tasks to be computed;
[0008] The extraction unit is used to extract a preset number of operation result data from the xor_salsa operation results of the multiple tasks to be calculated at a preset interval.
[0009] The memory module is used to provide memory space for the computation result data extracted from the multiple tasks to be computed.
[0010] Furthermore, the computation module includes a first computation submodule.
[0011] The first computing submodule is divided into multiple time slots, with one time slot corresponding to one of the tasks to be computed;
[0012] The first computation submodule has multiple time slots for simultaneously running no more than 1024 xor_salsa operations on the multiple tasks to be computed, and obtaining the first computation result data of the multiple tasks to be computed.
[0013] Furthermore, the first computation submodule uses the data of the task to be computed as the initial value for the first xor_salsa operation of each task to be computed;
[0014] The first operation submodule uses the result of the previous xor_salsa operation of the current task to be calculated as the initial value for each subsequent xor_salsa operation;
[0015] The initial value of the xor_salsa operation is used to input into the first operation submodule to perform the xor_salsa operation and obtain the first operation result data of the multiple tasks to be calculated.
[0016] Furthermore, the extraction unit is located in the first operation submodule, and the extraction unit is used to synchronously extract the first initial value and the result of the first preset interval of xor_salsa operations for each task to be calculated.
[0017] The extraction unit extracts the calculation results as the first calculation result data for each task to be calculated.
[0018] Furthermore, the memory module includes a first memory module.
[0019] The width of the first memory module is 1024 bits;
[0020] The first memory module is used to provide a first preset number of memory addresses for the first calculation result data extracted from each task to be calculated.
[0021] Furthermore, the computation module includes a second computation submodule.
[0022] The second operation submodule is divided into multiple time slots, with one time slot corresponding to one xor_salsa;
[0023] The second operation submodule is used to sequentially perform parallel xor_salsa operations on a single task to be computed in the first memory module in multiple time slots;
[0024] Each time slot is used to perform no more than a first preset interval of xor_salsa operations on the task to be computed, and to obtain the second operation result data of each task to be computed.
[0025] Furthermore, the second operation submodule uses the first operation result data in the first memory module as the initial value for the first xor_salsa operation in each time slot;
[0026] The second operation submodule takes the result of the previous xor_salsa operation in the current time slot as the initial value for each xor_salsa operation after the current time slot;
[0027] The initial value of the xor_salsa operation is used to input into the second operation submodule to perform the xor_salsa operation and obtain the second operation result data of each task to be calculated.
[0028] Furthermore, the extraction unit is located in the second operation submodule. The extraction unit is used to synchronously extract the first initial value and the result of the second preset interval of xor_salsa operations for each task to be calculated.
[0029] The extraction unit extracts the calculation results as the second calculation result data for each task to be calculated.
[0030] Furthermore, the memory module includes a second memory module.
[0031] The second memory module has a width of 1024 bits;
[0032] The second memory module is used to provide a second preset number of memory addresses for the second operation result data extracted from each task to be computed.
[0033] Furthermore, the computation module includes a third computation submodule.
[0034] The third operation submodule is divided into multiple time slots, with one time slot corresponding to one task to be computed.
[0035] The multiple time slots of the third operation submodule are used to simultaneously execute 1024 rounds of parallel xor_salsa operations on multiple tasks to be computed that have completed the second operation submodule, and obtain the third operation result data of each task to be computed as the final output result.
[0036] This invention provides a circuit architecture for the Scrypt algorithm, comprising an input module, a computation module, and a memory module. The computation module includes a scrambling unit. The input module feeds multiple tasks to be computed into the computation module, which then performs parallel Xor_salsa operations on these tasks. The scrambling unit extracts a preset number of computation result data from the Xor_salsa operations of the multiple tasks at preset intervals. The memory module provides memory space for the extracted computation result data. Unlike the traditional method of two 1024-round Xor_salsa calculations, this invention divides the computation process into three sub-modules, performing three 1024-round Xor_salsa calculations. These three sub-modules run the Xor_salsa calculations in parallel, improving the parallelism of the Scrypt algorithm and thus increasing computational efficiency to meet the demands of high-performance computing. Attached Figure Description
[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 A schematic diagram of the traditional Scrypt algorithm calculation process;
[0039] Figure 2 This is a circuit architecture block diagram provided in an embodiment of this application;
[0040] Figure 3 This is a schematic diagram of the calculation process of the second operation submodule provided in an embodiment of this application;
[0041] Figure 4 This is a schematic diagram of the circuit calculation process provided in an embodiment of this application. Detailed Implementation
[0042] To make the objectives, technical solutions, and effects of this invention clearer, specific embodiments of the invention are described below. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0043] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.
[0044] It should be understood that the terminology used in this application specification is for the purpose of describing particular embodiments only and is not intended to limit the application.
[0045] The embodiments of this application provide a circuit architecture for the Scrypt algorithm, the circuit architecture including an input module, a computation module and a memory module, the computation module including an extraction unit;
[0046] The input module is used to send multiple tasks to be calculated into the calculation module;
[0047] The computing module is used to perform parallel xor_salsa operations on the multiple tasks to be computed;
[0048] The extraction unit is used to extract a preset number of operation result data from the xor_salsa operation results of the multiple tasks to be calculated at a preset interval.
[0049] The memory module is used to provide memory space for the computation result data extracted from the multiple tasks to be computed.
[0050] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0051] Please see Figure 2 , Figure 2 This is a circuit architecture block diagram provided in an embodiment of this application. The circuit architecture includes an input module, an arithmetic module, and a memory module, wherein the arithmetic module includes three arithmetic sub-modules, and the memory module includes two memory modules.
[0052] The input module is used to send multiple tasks to be calculated into the calculation module;
[0053] In this embodiment, the input module is responsible for passing the data of the first sha256 part of the Scrypt algorithm, which has already been calculated, as the task to be calculated for the xor_salsa part into the Round1 submodule (i.e., the first operation submodule).
[0054] The computing module is used to perform parallel xor_salsa operations on the multiple tasks to be computed;
[0055] Furthermore, the computing module includes the first computing submodule, which is divided into multiple time slots, with each time slot corresponding to one of the tasks to be computed;
[0056] The first computation submodule has multiple time slots for simultaneously running no more than 1024 xor_salsa operations on the multiple tasks to be computed, and obtaining the first computation result data of the multiple tasks to be computed.
[0057] In this embodiment, the Round1 submodule executes multiple tasks simultaneously and runs the xor_salsa operation in parallel across time slots, with one time slot corresponding to one task. Each time slot (i.e., each task) is allocated N (i.e., the first preset number) memory spaces in memory 1 (i.e., the first memory module). When the Round1 submodule has an idle time slot, the Round1 submodule can start to perform the first stage xor_salsa operation (i.e., the xor_salsa operation in the first operation submodule) on the data passed in from the input module.
[0058] Furthermore, the first computation submodule uses the data of the task to be computed as the initial value for the first xor_salsa operation of each task to be computed;
[0059] The first operation submodule uses the result of the previous xor_salsa operation of the current task to be calculated as the initial value for each subsequent xor_salsa operation;
[0060] The initial value of the xor_salsa operation is used to input into the first operation submodule to perform the xor_salsa operation and obtain the first operation result data of the multiple tasks to be calculated.
[0061] In this embodiment, in order to further obtain the initial value of the xor_salsa operation, the initial value of the first xor_salsa operation is the task data to be calculated transmitted by the transmission module, and the initial value of each subsequent xor_salsa operation is the result of the previous round of xor_salsa operation.
[0062] The extraction unit is used to extract a preset number of operation result data from the xor_salsa operation results of the multiple tasks to be calculated at a preset interval.
[0063] Furthermore, the extraction unit is located in the first operation submodule, and the extraction unit is used to synchronously extract the first initial value and the result of the first preset interval of xor_salsa operations for each task to be calculated.
[0064] The extraction unit extracts the calculation results as the first calculation result data for each task to be calculated.
[0065] The memory module is used to provide memory space for the computation result data extracted from the multiple tasks to be computed.
[0066] Furthermore, the memory module includes a first memory module, the first memory module having a width of 1024 bits;
[0067] The first memory module is used to provide a first preset number of memory addresses for the first calculation result data extracted from each task to be calculated.
[0068] In this embodiment, during the first stage of calculation, N calculation results (a first preset number) are extracted at certain intervals (i.e., a first preset interval) and stored in memory 1. The extraction method is to extract the first initial value and save the xor_salsa calculation results every 1024 / N (i.e., the first preset interval) times to the corresponding time slot space of memory 1. For example, if N is 16, a result data is stored in memory 1 after 64 xor_salsa calculations. The memory depth of memory 1 is N, and the memory data width is 1024 bits.
[0069] Furthermore, the computation module includes a second computation submodule, which is divided into multiple time slots, with each time slot corresponding to one xor_salsa;
[0070] The second operation submodule is used to sequentially perform parallel xor_salsa operations on a single task to be computed in the first memory module in multiple time slots;
[0071] Each time slot is used to perform no more than a first preset interval of xor_salsa operations on the task to be computed, and to obtain the second operation result data of each task to be computed.
[0072] In this embodiment, after the Round1 submodule completes the first stage calculation of the task to be calculated, the task is sequentially executed by the Round2 submodule (i.e. the second operation submodule) for the second stage calculation.
[0073] Tasks in the same batch are queued according to the order in which they completed the first stage of computation, waiting for the Round2 submodule to be computed.
[0074] The Round2 submodule reads N data points from memory 1 sequentially, and then uses these N data points to run xor_salsa operations in parallel across multiple time slots. Each time slot corresponds to one xor_salsa operation, and a maximum of 1024 / N xor_salsa operations are performed.
[0075] Furthermore, the second operation submodule uses the first operation result data in the first memory module as the initial value for the first xor_salsa operation in each time slot;
[0076] The second operation submodule takes the result of the previous xor_salsa operation in the current time slot as the initial value for each xor_salsa operation after the current time slot;
[0077] The initial value of the xor_salsa operation is used to input into the second operation submodule to perform the xor_salsa operation and obtain the second operation result data of each task to be calculated.
[0078] In this embodiment, in order to obtain the initial value of the xor_salsa operation of the task to be calculated, the Round2 submodule finds a task that has been completed in Round1 when it is idle. Then, in each time slot, it reads the corresponding address data stored in memory 1 by the Round1 submodule of this task as the input data of the xor_salsa operation in the Round2 submodule. Finally, multiple time slots execute the second stage xor_salsa operation (i.e., the xor_salsa operation in the second operation submodule) of the same task in parallel.
[0079] Furthermore, the extraction unit is located in the second operation submodule. The extraction unit is used to synchronously extract the first initial value and the result of the second preset interval of xor_salsa operations for each task to be calculated.
[0080] The extraction unit extracts the calculation results as the second calculation result data for each task to be calculated.
[0081] The memory module includes a second memory module, the second memory module having a width of 1024 bits;
[0082] The second memory module is used to provide a second preset number of memory addresses for the second operation result data extracted from each task to be computed.
[0083] In this embodiment, during the second stage of calculation, M calculation results (i.e., the second preset number) are extracted at certain intervals (i.e., the second preset interval) and stored in memory 2 (i.e., the second memory module). The extraction method is to extract the first initial value and the xor_salsa calculation results every 1024 / M (i.e., the second preset interval). For example, if M is 256, the result data is stored in memory 2 after 4 xor_salsa calculations. The memory depth of memory 2 is M, and the memory data width is 1024 bits.
[0084] Furthermore, the computing module includes a third computing submodule, which is divided into multiple time slots, with each time slot corresponding to one of the tasks to be computed;
[0085] The multiple time slots of the third operation submodule are used to simultaneously execute 1024 rounds of parallel xor_salsa operations on multiple tasks to be computed that have completed the second operation submodule, and obtain the third operation result data of each task to be computed as the final output result.
[0086] In this embodiment, after the task to be computed completes the second stage of computation, the Round3 submodule (i.e. the third operation submodule) executes multiple tasks simultaneously on the completed task, running xor_salsa in parallel across time slots, with one time slot corresponding to one task;
[0087] If there is an idle time slot in the Round3 submodule, find a task that has been completed in Round2 and enter the Round3 time slot to perform 1024 rounds of xor_salsa operations. The 1024 rounds of xor_salsa operations are one or more xor_salsa operations to obtain the operation result data of the third stage of the task to be calculated, which is used as the final output result.
[0088] In this embodiment, to further obtain the initial value of the xor_salsa operation, when the task calculates the first round of xor_salsa during the third stage of the xor_salsa operation (i.e., the xor_salsa operation in the third operation submodule), the initial value is obtained by converting the address of the result D1 of the last xor_salsa operation in the second stage to the address of memory 2, and then reading the corresponding data D2 in memory 2 at that address and performing a XOR operation with the result D1. Afterwards, the initial value for each round of xor_salsa calculation is obtained by first addressing the corresponding data in memory 2, reading the data, and then performing a XOR operation with the result of the previous calculation.
[0089] In this embodiment, when a task is executed in each time slot of each Round 3, the xor_salsa process of each round is as follows: Let the result D1[512:521] be called Addr[0:9]. Divide Addr[0:9] by 1024 / M interval and take the integer part to obtain the address of memory 2. If Addr[0:9]Mod(1024 / M) is 0, the corresponding data D2 in memory 2 can be read directly and XORed with D1. Then, the XOR result is used as the initial value to perform an xor_salsa calculation to complete the xor_salsa calculation process of this round. If the value is not 0, then (Addr[0:9]Mod(1024 / M))+1 xor_salsa calculations are performed. First, the data D2 read from memory 2 is used as the initial value to perform (Addr[0:9]Mod(1024 / M)) xor_salsa calculations. Then, the calculation result is XORed with D1, and the XOR result is used as the initial value to perform another xor_salsa calculation, completing this round of xor_salsa calculation. For example, if M is 256 and Addr[0:9] is 35, then the address in memory 2 is: 35 / (1024 / 256) = 8, and the number of xor_salsa calculations in this round is (35mod(1024 / 256))+1 = 4.
[0090] The initial value of the xor_salsa operation is used to input the xor_salsa operation into the third stage. The initial value of the xor_salsa operation is used to input the xor_salsa operation into the third operation submodule to obtain the third operation result data of each task to be calculated.
[0091] Please see Figure 3 , Figure 3 This is a schematic diagram of the calculation process of the second operation submodule provided in an embodiment of this application.
[0092] The computation module includes a second computation submodule, which is used to sequentially perform parallel xor_salsa operations on a single task to be computed in the first memory module in multiple time slots.
[0093] In this embodiment, the Round2 submodule (i.e., the second operation submodule) performs the xor_salsa operation on the task that has completed the operation of the Round1 submodule;
[0094] Once the first stage of the task (the xor_salsa operation of the first operation submodule) is completed, and both memory 2 and the Round2 submodule are free, Round2 can begin the second stage of computation for this task.
[0095] Furthermore, the second operation submodule uses the first operation result data in the first memory module as the initial value for the first xor_salsa operation in each time slot;
[0096] The second operation submodule takes the result of the previous xor_salsa operation in the current time slot as the initial value for each xor_salsa operation after the current time slot;
[0097] The initial value of the xor_salsa operation is used to input into the second operation submodule to perform the xor_salsa operation and obtain the second operation result data of each task to be calculated.
[0098] In this embodiment, in order to further obtain the initial value of the xor_salsa operation, the second stage is run simultaneously in N time slots. Each time slot can run a maximum of 1024 / N xor_salsa calculations. The initial value of the first xor_salsa calculation in each time slot is the N calculation results saved to memory 1 by the corresponding task in the first stage. The initial value of each subsequent xor_salsa calculation is the result after the previous xor_salsa calculation.
[0099] Furthermore, the extraction unit is located in the second operation submodule. The extraction unit is used to synchronously extract the first initial value and the result of the second preset interval of xor_salsa operations for each task to be calculated.
[0100] The extraction unit extracts the calculation results as the second calculation result data for each task to be calculated.
[0101] Furthermore, the memory module includes a second memory module.
[0102] The second memory module has a width of 1024 bits;
[0103] The second memory module is used to provide a second preset number of memory addresses for the second operation result data extracted from each task to be computed.
[0104] In this embodiment, during the Round2 submodule calculation process, the first initial value and the xor_salsa calculation results every 1024 / M intervals need to be saved to the corresponding task space in memory 2. Memory 2 allocates a space with a depth of M and a width of 1024 bits for a single task.
[0105] Furthermore, the second operation submodule is divided into multiple time slots, with one time slot corresponding to one xor_salsa;
[0106] Each time slot is used to perform no more than a first preset interval of xor_salsa operations on the task to be computed, and to obtain the second operation result data of each task to be computed.
[0107] In this embodiment, the same task is executed in N time slots in the Round2 submodule. The maximum computation time occupied by a single task performing the xor_salsa operation in the second stage is 1024 / N.
[0108] In particular, the first time slot data in the Round2 submodule is used to calculate the first to 1024 / Nth xor_salsa calculations of this task, with a calculation count of 1024 / N.
[0109] The second time slot data in the Round2 submodule is used to perform the 1024 / N+1 to 1024 / N*2th xor_salsa calculations for this task, with a total of 1024 / N calculations.
[0110] Similarly, the Nth time slot data in the Round2 submodule is used to calculate the 1024 / N*(N-1)+1 to 1024th rounds of this task, with a calculation count of 1024 / N times.
[0111] The computation time for the second phase of this task is 1024 / N. This represents a significant reduction in computation time compared to the first phase.
[0112] Please see Figure 4 , Figure 4 This is a schematic diagram of the circuit calculation process provided in an embodiment of this application.
[0113] The embodiments of this application also provide a circuit architecture for the Scrypt algorithm, which is divided into three stages: the first stage (Round 1), the second stage (Round 2), and the third stage (Round 3) for performing parallel xor_salsa operations on the computation task.
[0114] In the first stage, the input module sends the first batch of tasks into the Round1 submodule (i.e., the first operation submodule) for the first stage of xor_salsa operation, obtaining the first operation result data of multiple tasks to be calculated.
[0115] The first stage extraction unit extracts N (i.e., the first preset number) of the results of the first stage xor_salsa operation of each task at a certain interval (i.e., the first preset interval) and stores the results in memory module 1 (i.e., the first memory module).
[0116] In the second stage, the Round2 submodule (i.e. the second operation submodule) obtains N data from memory 1 and executes the xor_salsa operation in parallel in multiple time slots according to the order in which the first stage was completed. Multiple time slots execute one task at the same time to obtain the second operation result data of each task to be calculated.
[0117] The extraction unit in the second stage extracts M results (i.e., the second preset number) of the xor_salsa operation results of each task at a certain interval (i.e., the second preset interval) and stores them in memory 2 (i.e., the second memory module).
[0118] In the third stage, the Round3 submodule (i.e. the third operation submodule) performs parallel calculations on the M data in memory 2 in multiple time slots to obtain the third operation result data of each task to be calculated, which is the final output result.
[0119] Furthermore, in the first stage, the input module sends the first batch of tasks into the Round1 submodule (i.e., the first operation submodule) to perform the first stage of xor_salsa operation, and obtains the first operation result data of multiple tasks to be calculated.
[0120] In this implementation case, the Round1 submodule is divided into multiple time slots, with one time slot corresponding to one task. The first batch of tasks is executed simultaneously in multiple time slots, with no more than 1024 xor_salsa operations performed in parallel.
[0121] In this implementation example, in order to further obtain the initial value of the xor_salsa operation,
[0122] The Round1 submodule uses the task data passed in from the input module as the initial value for the first xor_salsa operation of each task;
[0123] The Round1 submodule uses the result of the previous xor_salsa operation for the current task as the initial value for each subsequent xor_salsa operation.
[0124] The initial value of the xor_salsa operation is used as input into the Round1 submodule to perform the xor_salsa operation and obtain the first stage operation result data of each task.
[0125] Furthermore, the extraction unit in the first stage extracts N calculation results from the xor_salsa operation results of the first stage of each task at certain intervals and stores them in memory module 1.
[0126] In this implementation case, during the first stage of computation, the extraction unit extracts the first initial value for each task and saves the xor_salsa calculation results every 1024 / N times to the corresponding time slot space of memory 1. For example, if N is 16, the result data is stored in memory 1 after 64 xor_salsa calculations. The memory depth of memory 1 is N, and the memory data width is 1024 bits.
[0127] Furthermore, in the second stage, the Round2 submodule (i.e. the second operation submodule) obtains N data from memory 1 and executes the xor_salsa operation in parallel in multiple time slots according to the order in which the first stage was completed. Multiple time slots execute one task at the same time to obtain the second operation result data of each task to be calculated.
[0128] In this implementation case, after the Round1 submodule completes the first stage calculation of the first batch of tasks, the second stage calculation of the batch of tasks is performed by the Round2 submodule one by one.
[0129] Tasks in the same batch are queued according to the order in which they completed the first stage of computation, waiting for the Round2 submodule to compute. When the Round2 submodule is idle and there are free resources in memory 2, the Round2 submodule performs parallel xor_salsa operations on a single task in multiple time slots. One time slot corresponds to one xor_salsa operation, and a maximum of 1024 / N xor_salsa operations are performed in one time slot.
[0130] In this embodiment, in order to further obtain the initial value of the xor_salsa operation, each time slot of the second stage reads the corresponding address data of this task stored in memory 1 in the Round1 submodule as the initial value of the xor_salsa operation in the Round2 submodule.
[0131] Furthermore, the extraction unit in the second stage extracts M (i.e., the second preset number) calculation results of the xor_salsa operation results in the second stage of each task at a certain interval (i.e., the second preset interval) and stores them in memory 2 (i.e., the second memory module) in the memory module.
[0132] In this embodiment, during the second stage of calculation, M calculation results (i.e., the second preset number) are extracted at certain intervals (i.e., the second preset interval) and stored in memory 2 (i.e., the second memory module). The extraction method is to extract the first initial value and the xor_salsa calculation results every 1024 / M (i.e., the second preset interval). For example, if M is 256, the result data is stored in memory 2 after 4 xor_salsa calculations. The memory depth of memory 2 is M, and the memory data width is 1024 bits.
[0133] Furthermore, the Round3 submodule (i.e. the third operation submodule) performs parallel calculations on the M data in memory 2 across multiple time slots to obtain the third operation result data for each task to be calculated, which is then used as the final output result.
[0134] In this embodiment, after a task finishes the second stage xor_salsa operation, the third stage Round3 submodule begins to perform xor_salsa operation on the task. The Round3 submodule executes multiple tasks simultaneously and runs xor_salsa operation in parallel across time slots, with one time slot corresponding to one task.
[0135] In this embodiment, to further obtain the initial value of the xor_salsa operation, when the task calculates the first round of xor_salsa in the third stage, the initial value is obtained by converting the address of the result D1 of the last xor_salsa in the second stage to the address of memory 2, and then reading the corresponding data D2 in memory 2 at that address and performing a XOR operation on it with the result D1. Subsequently, the initial value for each xor_salsa calculation is the result of the previous calculation, which is first read from memory 2, and then XORed with the corresponding data.
[0136] In Round 3, when a task is executed in each time slot, the xor_salsa process in each round is as follows: Let the result D1[512:521] be called Addr[0:9]. Divide Addr[0:9] by 1024 / M interval and take the integer part to obtain the address of memory 2. If Addr[0:9]Mod(1024 / M) is 0, first XOR the data D2 read from memory 2 with D1, and then perform an xor_salsa calculation on the XOR result to complete the xor_salsa calculation process of this round. If the value is not 0, then (Addr[0:9]Mod(1024 / M))+1 xor_salsa calculations are performed. First, the data D2 read from memory 2 is subjected to (Addr[0:9]Mod(1024 / M)) xor_salsa calculations. Then, the calculation result is XORed with D1. The XOR result is used as the initial value to perform one xor_salsa calculation, completing this round of xor_salsa calculation. For example, if M is 256 and Addr[0:9] is 35, then the address in memory 2 is: 35 / (1024 / 256) = 8, and the number of xor_salsa calculations in this round is (35mod(1024 / 256))+1 = 4.
[0137] During the execution of Round 1, Round 2, and Round 3, these three stages proceed in parallel. When a task in the first batch begins its second stage calculation, the storage space in Memory 1 occupied by that task, as well as the computing resources from Round 1, can be released and used to calculate the first stage calculation of another task in the second batch. This process continues, with the first stage calculation of the second batch of tasks executing concurrently with the second and third stages of the first batch of tasks. The time consumed by the first stage calculation is not included in the total computation time. Figure 1 The critical path shown is the critical path of the traditional solution. The computation time of the critical path is close to the sum of the computation times of the first stage Round 1 and the third stage Round 3 in this invention. Figure 4 The critical path shown is the sum of the second stage Round 2 and the third stage Round 3, compared to the traditional method. Figure 1 The critical path computation time is reduced as shown.
[0138] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A circuit architecture for the Scrypt algorithm, characterized in that, The circuit architecture includes an input module, an arithmetic module, and a memory module. The arithmetic module includes an extraction unit. The input module is used to send multiple tasks to be calculated into the calculation module; The computing module is used to perform parallel xor_salsa operations on the multiple tasks to be computed; The extraction unit is used to extract a preset number of operation result data from the xor_salsa operation results of the multiple tasks to be calculated at a preset interval. The memory module is used to provide memory space for the computation result data extracted from the multiple tasks to be computed; The memory module includes a first memory module and a second memory module; The computation module includes a first computation submodule, which is divided into multiple time slots, each time slot corresponding to one of the tasks to be computed. The multiple time slots of the first computation submodule are used to simultaneously run no more than 1024 xor_salsa operations on the multiple tasks to be computed. This includes the first computation submodule using the result of the previous xor_salsa operation on the current task to be computed as the initial value for each subsequent xor_salsa operation. This initial value is then input into the first computation submodule to perform the xor_salsa operation, thereby obtaining the first computation result data of the multiple tasks to be computed. The computation module includes a second computation submodule, which is divided into multiple time slots, with each time slot corresponding to one xor_salsa operation. The second computation submodule is used to sequentially perform parallel xor_salsa operations on multiple tasks to be computed in the first memory module in multiple time slots. Each time slot is used to perform xor_salsa operations on the task to be computed no more than a first preset interval to obtain the second computation result data of each task to be computed. The computation module includes a third computation submodule. The third computation submodule divides the data in the second memory module into multiple time slots, with each time slot corresponding to one of the computation tasks to be computed. The multiple time slots of the third computation submodule are used to simultaneously execute 1024 rounds of parallel xor_salsa operations on the multiple computation tasks to be computed by the second computation submodule, and obtain the third computation result data of each computation task as the final output result. The extraction unit is located in the first operation submodule. The extraction unit is used to synchronously extract the first initial value and the result of the first preset interval of xor_salsa operation for each task to be calculated, and store them in the first memory module. The extraction unit is located in the second operation submodule. The extraction unit is used to synchronously extract the first initial value and the result of the second preset interval of xor_salsa operation for each task to be calculated, and store them in the second memory module. The extraction unit extracts the calculation results as the second calculation result data extracted for each task to be calculated; The extraction unit extracts the calculation results as the first calculation result data for each task to be calculated.
2. The circuit architecture as described in claim 1, characterized in that, The width of the first memory module is 1024 bits; The first memory module is used to provide a first preset number of memory addresses for the first calculation result data extracted from each task to be calculated.
3. The circuit architecture as described in claim 2, characterized in that, The second operation submodule uses the first operation result data in the first memory module as the initial value for the first xor_salsa operation in each time slot; The second operation submodule takes the result of the previous xor_salsa operation in the current time slot as the initial value for each xor_salsa operation after the current time slot; The initial value of the xor_salsa operation is used to input into the second operation submodule to perform the xor_salsa operation and obtain the second operation result data of each task to be calculated.
4. The circuit architecture as described in claim 1, characterized in that, The first operation submodule uses the data of the task to be calculated as the initial value for the first xor_salsa operation of each task to be calculated.
5. The circuit architecture as described in claim 1, characterized in that, The second memory module has a width of 1024 bits; The second memory module is used to provide a second preset number of memory addresses for the second operation result data extracted from each task to be computed.
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