Semiconductor device and method of operating same, package structure, system

Abstract

This disclosure provides a semiconductor device, its operation method, packaging structure, and system. The semiconductor device includes a first semiconductor structure and a second semiconductor structure, with a first side of the first and second semiconductor structures bonded together. The first semiconductor structure includes an analog-to-digital converter (ADC). The second semiconductor structure includes a memory array, multiple bit lines, and multiple first connection structures. The memory array is located between the multiple bit lines and the first side of the second semiconductor structure, and the multiple first connection structures are located between the multiple bit lines and the first semiconductor structure. Each bit line is connected to the ADC through a first connection structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor device and its operating method, packaging structure, and system. Background Technology

[0002] In the classic von Neumann computing architecture, the memory device and the processor are separate, and data is transferred between them via a data bus. When executing a command, the processor first reads data from the memory device, processes it, and then writes the updated data back to the memory device. This frequent data movement results in significant power consumption and time overhead. Furthermore, due to the limited bandwidth of the memory device, the processor's processing speed is limited by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a first semiconductor structure and a second semiconductor structure, the first semiconductor structure and the second semiconductor structure being bonded together on a first side; the first semiconductor structure includes an analog-to-digital converter circuit; the second semiconductor structure includes a memory array, a plurality of bit lines, and a plurality of first connection structures, the memory array being located between the plurality of bit lines and the first side of the second semiconductor structure, and the plurality of first connection structures being located between the plurality of bit lines and the first semiconductor structure, wherein each bit line is connected to the analog-to-digital converter circuit through one of the first connection structures.

[0004] In some embodiments, the memory array includes a plurality of sub-memory surfaces, which are spaced apart along the extension direction of the bit line, wherein at least one of the first connection structures is located between two adjacent sub-memory surfaces.

[0005] In some embodiments, the sub-storage surface includes a plurality of first storage blocks, wherein at least one of the first connection structures extends through at least one of the first storage blocks.

[0006] In some embodiments, the second semiconductor structure further includes a second memory block located between two adjacent sub-memory surfaces, wherein the first connection structure located between the two adjacent sub-memory surfaces extends through the second memory block.

[0007] In some embodiments, the semiconductor device further includes a third semiconductor structure bonded to a second side of the second semiconductor structure, the second side of the second semiconductor structure and the first side of the second semiconductor structure being opposite each other along the extension direction of the first connection structure; the third semiconductor structure includes peripheral circuitry; the second semiconductor structure further includes a plurality of second connection structures located between the plurality of bit lines and the third semiconductor structure, wherein each bit line is connected to the peripheral circuitry through one of the second connection structures.

[0008] In some embodiments, the first semiconductor structure further includes a control circuit; the second semiconductor structure further includes a source layer located between the memory array and the first semiconductor structure, wherein the source layer is connected to at least one of the peripheral circuit and the control circuit.

[0009] In some embodiments, the source layer includes a plurality of sub-source layers, which are spaced apart along the extension direction of the bit line, wherein each sub-source layer is connected to a corresponding sub-memory surface; the second semiconductor structure further includes a third connection structure and a fourth connection structure; the third connection structure is located between a first sub-source layer and the third semiconductor structure, wherein the first sub-source layer is connected to the peripheral circuit through the third connection structure; the fourth connection structure is located between a second sub-source layer and the first semiconductor structure, wherein the second sub-source layer is connected to the control circuit through the fourth connection structure.

[0010] In some embodiments, the sub-memory surface connected to the first sub-source layer has a first side and a second side opposite to each other along the arrangement direction of the plurality of bit lines, wherein the third connection structure is located on the first side or the second side of the sub-memory surface connected to the first sub-source layer, and the arrangement direction of the plurality of bit lines intersects with the extension direction of the bit lines.

[0011] In some embodiments, the second semiconductor structure further includes a plurality of conductive layers located between the source layer and the first semiconductor structure and spaced apart along the extension direction of the bit line, wherein the first sub-source layer is connected to the third connection structure through one of the conductive layers, and the second sub-source layer is connected to the fourth connection structure through another of the conductive layers.

[0012] In some embodiments, the second semiconductor structure further includes at least one connection portion located between two adjacent conductive layers, wherein the connection portion is connected to the two adjacent conductive layers at opposite ends along the bit line extension direction.

[0013] In some embodiments, the first semiconductor structure includes a first bonding layer located between the second semiconductor structure and the analog-to-digital conversion circuit; the second semiconductor structure includes a second bonding layer and a third bonding layer, the second bonding layer located between the memory array and the first bonding layer, and the third bonding layer located between the plurality of second connection structures and the third semiconductor structure, wherein the second bonding layer and the first bonding layer are bonded; the third semiconductor structure further includes a fourth bonding layer located between the peripheral circuit and the third bonding layer, wherein the fourth bonding layer and the third bonding layer are bonded.

[0014] In some embodiments, a first end of the first connection structure is connected to the bit line, and a second end of the first connection structure is connected to the second bonding layer, wherein the first end and the second end of the first connection structure are opposite to each other along the extension direction of the first connection structure; a first end of the second connection structure is connected to the bit line, and a second end of the second connection structure is connected to the third bonding layer, wherein the first end and the second end of the second connection structure are opposite to each other along the extension direction of the second connection structure.

[0015] In some embodiments, the cross-sectional dimension of the first end of the first connecting structure is less than or equal to the cross-sectional dimension of the second end of the first connecting structure; the cross-sectional dimension of the first end of the second connecting structure is less than or equal to the cross-sectional dimension of the second end of the second connecting structure.

[0016] In some embodiments, the semiconductor device includes a three-dimensional NAND memory.

[0017] According to a second aspect of the present disclosure, another semiconductor device is provided. The semiconductor device includes: a first semiconductor structure and a second semiconductor structure, the first semiconductor structure and the second semiconductor structure being bonded together on a first side; the first semiconductor structure includes an analog-to-digital converter circuit; the second semiconductor structure includes a plurality of sub-memory surfaces, a plurality of bit lines, and a plurality of first connection structures, the plurality of sub-memory surfaces being located between the plurality of bit lines and the first side of the second semiconductor structure and spaced apart along the extension direction of the bit lines, wherein at least one first connection structure is located between two adjacent sub-memory surfaces and respectively connects the bit lines and the analog-to-digital converter circuit.

[0018] In some embodiments, the sub-storage surface includes a plurality of first storage blocks, wherein at least one of the first connection structures extends through at least one of the first storage blocks.

[0019] In some embodiments, the second semiconductor structure further includes a second memory block located between two adjacent sub-memory surfaces, wherein the first connection structure located between the two adjacent sub-memory surfaces extends through the second memory block.

[0020] In some embodiments, the semiconductor device further includes a third semiconductor structure bonded to a second side of the second semiconductor structure, the second side of the second semiconductor structure and the first side of the second semiconductor structure being opposite each other along the extension direction of the first connection structure; the third semiconductor structure includes peripheral circuitry; the second semiconductor structure further includes a plurality of second connection structures located between the plurality of bit lines and the third semiconductor structure, wherein each bit line is connected to the peripheral circuitry through one of the second connection structures.

[0021] In some embodiments, the first semiconductor structure further includes a control circuit; the second semiconductor structure further includes a source layer located between the plurality of sub-memory surfaces and the first semiconductor structure, wherein the source layer is connected to at least one of the peripheral circuit and the control circuit.

[0022] In some embodiments, the source layer includes a plurality of sub-source layers, which are spaced apart along the extension direction of the bit line, wherein each sub-source layer is connected to a corresponding sub-memory surface; the second semiconductor structure further includes a third connection structure and a fourth connection structure; the third connection structure is located between a first sub-source layer and the third semiconductor structure, wherein the first sub-source layer is connected to the peripheral circuit through the third connection structure; the fourth connection structure is located between a second sub-source layer and the first semiconductor structure, wherein the second sub-source layer is connected to the control circuit through the fourth connection structure.

[0023] In some embodiments, the sub-memory surface connected to the first sub-source layer has a first side and a second side opposite to each other along the arrangement direction of the plurality of bit lines, wherein the third connection structure is located on the first side or the second side of the sub-memory surface connected to the first sub-source layer, and the arrangement direction of the plurality of bit lines intersects with the extension direction of the bit lines.

[0024] In some embodiments, the second semiconductor structure further includes a plurality of conductive layers located between the source layer and the first semiconductor structure and spaced apart along the extension direction of the bit line, wherein the first sub-source layer is connected to the third connection structure through one of the conductive layers, and the second sub-source layer is connected to the fourth connection structure through another of the conductive layers.

[0025] In some embodiments, the second semiconductor structure further includes at least one connection portion located between two adjacent conductive layers, wherein the connection portion is connected to the two adjacent conductive layers at opposite ends along the bit line extension direction.

[0026] In some embodiments, the first semiconductor structure includes a first bonding layer located between the second semiconductor structure and the analog-to-digital conversion circuit; the second semiconductor structure includes a second bonding layer and a third bonding layer, the second bonding layer located between the plurality of sub-memory surfaces and the first bonding layer, and the third bonding layer located between the plurality of second connection structures and the third semiconductor structure, wherein the second bonding layer and the first bonding layer are bonded; the third semiconductor structure further includes a fourth bonding layer located between the peripheral circuit and the third bonding layer, wherein the fourth bonding layer and the third bonding layer are bonded.

[0027] In some embodiments, a first end of the first connection structure is connected to the bit line, and a second end of the first connection structure is connected to the second bonding layer, wherein the first end and the second end of the first connection structure are opposite to each other along the extension direction of the first connection structure; a first end of the second connection structure is connected to the bit line, and a second end of the second connection structure is connected to the third bonding layer, wherein the first end and the second end of the second connection structure are opposite to each other along the extension direction of the second connection structure.

[0028] In some embodiments, the cross-sectional dimension of the first end of the first connecting structure is less than or equal to the cross-sectional dimension of the second end of the first connecting structure; the cross-sectional dimension of the first end of the second connecting structure is less than or equal to the cross-sectional dimension of the second end of the second connecting structure.

[0029] In some embodiments, any one of the plurality of first connection structures is located between two adjacent sub-storage surfaces.

[0030] In some embodiments, a portion of the plurality of first connection structures is located between two adjacent sub-memory surfaces, and another portion of the plurality of first connection structures is located on opposite sides of the plurality of sub-memory surfaces along the bit line extension direction.

[0031] In some embodiments, the semiconductor device includes a three-dimensional NAND memory.

[0032] According to a third aspect of the present disclosure, a method for operating a semiconductor device is provided. The method includes: performing a first operation through a plurality of sub-memory surfaces in a second semiconductor structure to obtain analog computation information; transmitting the analog computation information to an analog-to-digital converter (ADC) circuit in a first semiconductor structure through a plurality of bit lines and a plurality of first connection structures in the second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded together on a first side, and at least one first connection structure is located between two adjacent sub-memory surfaces and respectively connects the bit lines and the ADC circuit; and converting the analog computation information into digital information through the ADC circuit.

[0033] In some embodiments, the operation method further includes: performing a second operation on the digital information through a data processing circuit in the first semiconductor structure, wherein the data processing circuit is connected to the analog-to-digital conversion circuit.

[0034] In some embodiments, the first operation includes a multiply-accumulate-add operation; the second operation includes one or more of the following operations: compensation, activation, shift, or pooling.

[0035] According to a fourth aspect of the present disclosure, a packaging structure is provided. The packaging structure includes: a packaging substrate, a semiconductor device as described in any of the embodiments of the first or second aspect, and a molding compound layer, wherein the semiconductor device is located on one side of the packaging substrate, and the molding compound layer covers the semiconductor device.

[0036] According to a fifth aspect of the present disclosure, a system is provided. The system includes: at least one semiconductor device as described in any embodiment of the first or second aspect; and a controller coupled to the semiconductor device; the controller being configured to: transmit data to the semiconductor device and receive data from the semiconductor device.

[0037] In this embodiment, a first semiconductor structure and a second semiconductor structure are bonded together on their first sides. The first semiconductor structure includes an analog-to-digital converter (ADC) circuit, and the second semiconductor structure includes a memory array, multiple bit lines, and multiple first connection structures. The memory array is located between the multiple bit lines and the first side of the second semiconductor structure, and the multiple first connection structures are located between the multiple bit lines and the first semiconductor structure. Each bit line is connected to the ADC circuit through a first connection structure. Firstly, this enables three-dimensional integration of semiconductor devices, reducing chip size and increasing storage density. Secondly, it allows analog computation information sensed on each bit line to be transmitted to the ADC circuit through the first connection structure connected to that bit line, which is beneficial for improving the parallelism of in-memory computation. Attached Figure Description

[0038] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0039] Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of the present disclosure.

[0040] Figure 2 This is a schematic diagram of a storage surface provided in an embodiment of the present disclosure.

[0041] Figure 3 This is a schematic diagram of a semiconductor device including a memory array and peripheral circuitry, provided for an embodiment of this disclosure.

[0042] Figure 4 This is a schematic cross-sectional view of a storage array including storage strings, provided as an embodiment of the present disclosure.

[0043] Figure 5 This is a schematic diagram of a semiconductor device including peripheral circuitry and a memory array, provided for an embodiment of this disclosure.

[0044] Figure 6 This is a schematic diagram of an input voltage input to a storage array via a top select line, provided as an embodiment of the present disclosure.

[0045] Figure 7 This is a schematic diagram of a plurality of bit-line coupled memory strings provided in an embodiment of the present disclosure.

[0046] Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0047] Figure 9 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this disclosure.

[0048] Figure 10 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this disclosure.

[0049] Figure 11 This is a top view schematic diagram of a channel structure, a dummy channel structure, and a first connecting structure provided in an embodiment of this disclosure.

[0050] Figures 12A to 12D This is a schematic diagram of the first connection structure arrangement provided in an embodiment of this disclosure.

[0051] Figure 13 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure.

[0052] Figure 14 This is a schematic flowchart illustrating an operation method of a semiconductor device provided in an embodiment of this disclosure.

[0053] Figure 15A This is a schematic diagram of a system provided in an embodiment of the present disclosure.

[0054] Figure 15B This is a schematic diagram of another system provided in an embodiment of the present disclosure.

[0055] Figure 16A A schematic diagram of an exemplary memory card with a memory system provided in an embodiment of this disclosure.

[0056] Figure 16B A schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0057] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0058] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0059] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0060] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0061] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0062] In the classic von Neumann computing architecture, the memory device and the processor are separate, and data is transferred between them via a data bus. When executing a command, the processor first reads data from the memory device, processes it, and then writes the updated data back to the memory device. This frequent data movement results in significant power consumption and time overhead. Furthermore, due to the limited bandwidth of the memory device, the processor's processing speed is limited by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottleneck of the von Neumann computing architecture increasingly prominent. To address the bottleneck of the classic von Neumann computing architecture, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within the memory device and directly utilize the memory device for logical calculations. This reduces the amount and distance of data transfer between the memory device and the processor, lowering power consumption while improving computational performance, thus potentially enabling the construction of high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0063] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their electrical conductance, based on their physical properties. Computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices, applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied area of ​​interest in IMC chips. The following section will provide a detailed introduction to NAND flash memory.

[0064] Figure 1 This is a schematic diagram of a semiconductor device provided according to an embodiment of the present disclosure. The semiconductor device includes, but is not limited to, 3D NAND. (Refer to...) Figure 1 As shown, the semiconductor device 100 includes a first semiconductor structure 102 and a second semiconductor structure 104, with first sides 104a of the first semiconductor structure 102 and the second semiconductor structure 104 bonded together. The first semiconductor structure 102 and the second semiconductor structure 104 may be located in different planes, and the first semiconductor structure 102 and the second semiconductor structure 104 may be stacked on top of each other, i.e., the first semiconductor structure 102 and the second semiconductor structure 104 are at different horizontal heights, thus reducing the planar dimensions of the semiconductor device 100. In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 may be formed on different substrates. For example, the first semiconductor structure 102 may be formed on a first substrate and the second semiconductor structure 104 may be formed on a second substrate, and they may be stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding.

[0065] The first semiconductor structure 102 includes an analog-to-digital converter (ADC) 108 configured to convert analog signals into digital signals and transmit them to a data processing circuit 109. As an example, the ADC 108 is configured to convert analog computation information obtained by performing a first operation on the memory array 110 in the second semiconductor structure 104 into digital information and transmit it to the data processing circuit 109; the data processing circuit 109 is configured to perform a second operation on the digital information. The first operation includes multiplication-accumulation-addition operations, and the second operation includes one or more of compensation, activation, shift, or pooling operations.

[0066] It should be noted that, Figure 1In the example shown, both the analog-to-digital converter (ADC) circuit 108 and the data processing circuit 109 are located within the first semiconductor structure 102, meaning the first semiconductor structure 102 includes both the ADC circuit 108 and the data processing circuit 109. However, in other examples, the data processing circuit 109 may be located within other semiconductor structures. For example, the data processing circuit may be formed on another substrate and bonded to the first substrate on which the ADC circuit 108 is formed, thereby achieving the connection between the ADC circuit 108 and the data processing circuit 109.

[0067] The analog-to-digital conversion circuit 108 includes, but is not limited to, an analog-to-digital converter (ADC). The data processing circuit 109 includes a processor, which may include a dedicated processor, including, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a tensor processing unit (TPU), a video processing unit (VPU), a neural processing unit (NPU), a secure processing unit (SPU), a physical processing unit (PPU), and an image signal processor (ISP). In a specific example, the data processing circuit is an NPU. The NPU can perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations. In some embodiments, activation operations can be implemented using activation functions stored in the NPU. These activation functions may include, but are not limited to, step functions, correction functions, sigmoid functions, hyperbolic tangent (tanh) functions, and softplus functions (also known as smoothing correction).

[0068] The second semiconductor structure 104 includes a memory array 110, which can perform a first operation to obtain analog calculation information, which can be transmitted to an analog-to-digital converter circuit 108.

[0069] The second semiconductor structure 104 may also include multiple bit lines and multiple first connection structures, for example, Figures 8 to 10Bit lines BL0 to BL3 and multiple first connection structures 622 are shown. The memory array 110 is located between the multiple bit lines and a first side 104a of the second semiconductor structure 102, and the multiple first connection structures are located between the multiple bit lines and the first semiconductor structure 102. It is understood that the multiple bit lines are located on the side of the memory array 110 opposite to the first semiconductor structure 102, and each bit line is connected to the analog-to-digital converter circuit 108 via a first connection structure. The analog calculation information obtained by the memory array 110 in performing the first operation can be transmitted to the analog-to-digital converter circuit 108 through the corresponding bit lines and the first connection structures.

[0070] In this embodiment, a first semiconductor structure 102 and a second semiconductor structure 104 are bonded together on their first sides 104a. The first semiconductor structure 102 includes an analog-to-digital converter (ADC) circuit 108, and the second semiconductor structure 104 includes a memory array 110, multiple bit lines, and multiple first connection structures. The memory array 110 is located between the multiple bit lines and the first side 104a of the second semiconductor structure 104, and the multiple first connection structures are located between the multiple bit lines and the first semiconductor structure 102. Each bit line is connected to the ADC circuit 108 through a first connection structure. Firstly, this enables three-dimensional integration of the semiconductor device 100, reducing chip size and increasing storage density. Secondly, it allows analog computation information sensed on each bit line to be transmitted to the ADC circuit 108 through the first connection structure connected to that bit line, which is beneficial for improving the parallelism of in-memory computation.

[0071] In some embodiments, refer to Figure 1 As shown, the semiconductor device 100 further includes a third semiconductor structure 106, which is bonded to a second side 104b of the second semiconductor structure 104. The second side 104b of the second semiconductor structure 104 and the first side 104a of the second semiconductor structure 104 are opposite to each other along the extension direction of the first connection structure. As an example, see... Figure 1 As shown, the third semiconductor structure 106, the second semiconductor structure 104, and the first semiconductor structure 102 are stacked sequentially along the extension direction of the first connection structure. That is, the third semiconductor structure 106 and the first semiconductor structure 102 are respectively integrated on opposite sides of the second semiconductor structure 104 along the extension direction of the first connection structure. In this way, the planar size of the semiconductor device 100 can be reduced, the integration density can be increased, and the storage density can be increased. In some embodiments, the third semiconductor structure 106 can be formed on a third substrate and stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding.

[0072] The third semiconductor structure 106 includes peripheral circuitry 112; the second semiconductor structure 104 also includes multiple second connection structures, for example, Figures 8 to 10Multiple second connection structures 624 are shown. These second connection structures are located between multiple bit lines and the third semiconductor structure 106. It is understood that the multiple bit lines are located between the memory array 110 and the third semiconductor structure 106, and each bit line is connected to the peripheral circuit 112 via a second connection structure. The read results obtained by the memory array 110 performing a read operation, the programming verification results obtained by performing a programming verification operation, and the erase verification results obtained by performing an erase verification operation can all be transmitted to the peripheral circuit 112 through the corresponding bit lines and second connection structures.

[0073] In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 can be vertically connected by bonding. As an example, see... Figure 1 As shown, the first semiconductor structure 102 includes a first bonding layer 114, and the second semiconductor structure 104 includes a second bonding layer 116. The second bonding layer 116 and the first bonding layer 114 are bonded together, thereby making the first semiconductor structure 102 and the second semiconductor structure 104 vertically connected. In the bonded first semiconductor structure 102 and second semiconductor structure 104, the first bonding layer 114 is located between the second semiconductor structure 104 and the analog-to-digital converter circuit 108, and the second bonding layer 116 is located between the memory array 110 and the first bonding layer 114.

[0074] In some embodiments, the second semiconductor structure 104 and the third semiconductor structure 106 can be vertically connected by bonding. As an example, see... Figure 1 As shown, the second semiconductor structure 104 includes a third bonding layer 118, and the third semiconductor structure 106 includes a fourth bonding layer 120. The fourth bonding layer 120 and the third bonding layer 118 are bonded together, thereby making the second semiconductor structure 104 and the third semiconductor structure 106 vertically connected. In the bonded second semiconductor structure 104 and third semiconductor structure 106, the third bonding layer 118 is located between the plurality of second connection structures and the third semiconductor structure 106, and the fourth bonding layer 120 is located between the peripheral circuit 112 and the third bonding layer 118.

[0075] It should be noted that the aforementioned bonding connections include hybrid bonding connections (also known as "metal / dielectric hybrid bonding connections"), a direct bonding technique that, for example, forms bonds between surfaces without the use of intermediate layers such as solder or adhesive, and can simultaneously achieve metal-to-metal and dielectric-to-dielectric bonding. It should also be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above.

[0076] In some embodiments, the semiconductor device 100 further includes a first bonding interface between the first bonding layer 114 and the second bonding layer 116, and a second bonding interface between the third bonding layer 118 and the fourth bonding layer 120. Data transmission between the first semiconductor structure 102 and the second semiconductor structure 104 can be achieved through interconnects (e.g., bonding contacts) across the first bonding interface. Data transmission between the second semiconductor structure 104 and the third semiconductor structure 106 can be achieved through interconnects (e.g., bonding contacts) across the second bonding interface.

[0077] In some embodiments, the first bonding layer 114 includes a first bonding contact and a first dielectric layer that isolates the first bonding contact, and the second bonding layer 116 includes a second bonding contact and a second dielectric layer that isolates the second bonding contact, wherein the first bonding contact and the second bonding contact are bonded, and the first dielectric layer and the second dielectric layer are bonded.

[0078] In some embodiments, the third bonding layer 118 includes a third bonding contact and a third dielectric layer that isolates the third bonding contact; the fourth bonding layer 120 includes a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; the third bonding contact and the fourth bonding contact are bonded, and the third dielectric layer and the fourth dielectric layer are bonded.

[0079] In some embodiments, the bonding contacts may include a conductive material, including but not limited to one or more of tungsten, cobalt, copper, aluminum, or polycrystalline silicon. As an example, the bonding contacts of the bonding layer may include copper, and the remaining area of ​​the bonding layer may be formed of a dielectric, including but not limited to one or more of silicon oxide, silicon nitride, silicon oxynitride, or low-k dielectrics. The bonding contacts in the bonding layer and the surrounding dielectric can be used for hybrid bonding, simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding.

[0080] It should be noted that the analog calculation information obtained by the memory array 110 in performing the first operation can be transmitted to the analog-to-digital converter circuit 108 through the corresponding bit lines, the first connection structure, the second bonding layer 116, and the first bonding layer 114. The read results obtained by the memory array 110 in performing the read operation, the programming verification results obtained by performing the programming verification operation, and the erase verification results obtained by performing the erase verification operation can all be transmitted to the peripheral circuit 112 through the corresponding bit lines, the second connection structure, the third bonding layer 118, and the fourth bonding layer 120.

[0081] Figure 2 This is a schematic diagram of a storage plane provided in an embodiment of the present disclosure. The storage array may include multiple storage planes 200, for example, the storage array may include 2, 4, 8, or other numbers of storage planes. Each storage plane 200 may include multiple sub-storage planes, for example, Figure 2The diagram shows sub-storage surface 0 and sub-storage surface 1. Each sub-storage surface can include multiple storage blocks, for example, Figure 2 The diagram shows storage blocks 0 to (N-1), where N is an integer greater than 1. It should be noted that the number of sub-storage surfaces in storage surface 200 and the number of storage blocks in each sub-storage surface are not limited to... Figure 2 As shown, other quantities are also possible. In practical applications, the number of storage surfaces 200, the number of sub-storage surfaces, and the number of storage blocks in the storage array can be configured reasonably according to usage requirements.

[0082] Figure 3 This is a schematic diagram of a semiconductor device including a memory array and peripheral circuitry, provided as an embodiment of the present disclosure. For ease of understanding, the memory array 301 is described as a three-dimensional NAND type memory array, wherein the memory cells 306 are NAND memory cells, and the memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically. In some embodiments, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 can hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0083] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In other embodiments, each memory cell 306 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0084] Reference Figure 3As shown, each memory string 308 may include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. The bottom select gate 310 and top select gate 312 can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the source ends of memory strings 308 within the same memory block 304 can be coupled via a common source line (CSL) 314. In other words, all memory strings 308 within the same memory block 304 have a common source (ACS). According to some implementations, the top select gate 312 of each memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 312) or a deselection voltage (e.g., 0V) to the corresponding top select transistor 312 via one or more top select lines (TSL) 313 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 310) or a deselection voltage (e.g., 0V) to the corresponding bottom select transistor 310 via one or more bottom select lines (BSL) 315.

[0085] Reference Figure 3 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase a memory cell 306 in a selected memory block, an erase voltage bias can be used to couple the common source line 314 to the selected memory block and to any unselected memory block on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0086] Figure 4 This is a schematic cross-sectional view of a storage array including storage strings, provided as an embodiment of this disclosure. (Refer to...) Figure 4As shown, the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked, and a memory string 308 extending through the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array is primarily related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0087] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten, cobalt, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as a top select line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a bottom select line, and the gate layer 411 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0088] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon, silicon germanium, gallium arsenide, germanium, silicon-on-insulator, germanium-on-insulator, or any other suitable material. In other embodiments, the semiconductor device may not include the semiconductor layer.

[0089] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0090] Return to reference Figure 3The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, bottom select line 315, and top select line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, bottom select line 315, and top select line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0091] Figure 5 This is a schematic diagram of a semiconductor device including peripheral circuitry and a memory array, provided for embodiments of this disclosure. The peripheral circuitry 302 may include a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a register 514, and a data bus 518. It should be understood that in some examples, it may also include... Figure 5 Additional peripheral circuitry not shown.

[0092] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0093] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cell 306 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0094] The line decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The line decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the line decoder / word line driver 508 can also select / deselect and drive bottom select line 315 and top select line 313. As described in detail below, the line decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, input voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0095] Combination Figure 1 and Figure 5 When performing the first operation using the second semiconductor structure, control logic 512 can receive input data sent by an external device (e.g., a host). The digital-to-analog converter (DAC) converts the input data into a voltage signal that needs to be applied to the word line or bit line. The voltage generator 510 generates the corresponding voltage that needs to be applied to the word line or bit line. The row decoder / word line driver 508 is configured to drive the selected word line using the word line voltage generated from the voltage generator 510, or the column decoder / bit line driver 506 is configured to drive the selected bit line using the bit line voltage generated from the voltage generator 510. The analog calculation information obtained after performing the first operation is transmitted to the analog-to-digital converter (ADC) through the corresponding bit line, the first connection structure, the second bonding layer, and the first bonding layer. The ADC converts the analog calculation information into digital information and transmits the final digital information to the data processing circuit, which then performs the second operation on the digital information. It should be noted that the ADC can be located within the third semiconductor structure and form part of the peripheral circuit; or, the ADC can be located within the first semiconductor structure.

[0096] In some embodiments, for in-memory computing chips, it is necessary to perform a first operation between input data and a weight matrix. The input data can be an input vector or an input matrix composed of multiple elements, and the weight matrix is ​​composed of multiple weights. Each element in the input data needs to be multiplied and added with the multiple weights in the weight matrix to obtain the corresponding element in the output data.

[0097] To achieve the aforementioned computational functions, the storage array 301 can be configured to store a weight matrix. Specifically, the weights in the weight matrix can be written into the storage array 301 according to a certain mapping rule, and each storage cell 306 in the storage array 301 can be configured to store one weight. During the computation phase, the second semiconductor structure can receive input data from an external device. The input data can be an input vector or an input matrix composed of multiple elements. Each element in the input data can be converted into an input voltage by a digital-to-analog converter circuit and input to the storage array 301 via bit line 316 or word line 318.

[0098] In this embodiment of the disclosure, analog computation information can be output via bit lines or via the source terminal. That is, the bit lines in the second semiconductor structure are analog information output terminals, or the source terminal is an analog information output terminal. For ease of understanding, the following description will use bit lines as an example of analog information output terminals.

[0099] Figure 6 This is a schematic diagram illustrating an embodiment of the present disclosure where the input voltage is input to the storage array via a top select line. Figure 7 This is a schematic diagram of multiple memory strings coupled to bit lines, provided as an embodiment of this disclosure. It should be noted that... Figure 6 and Figure 7 The number of bit lines, the number of memory strings coupled to each bit line, and the number of memory cells in each memory string shown are merely examples, and this disclosure does not limit the specific numbers for each structure. The following will combine... Figure 6 and Figure 7 Taking the bit line as an analog information output terminal as an example, the specific process of the first operation will be illustrated by way of example.

[0100] Reference Figure 6 As shown, the input voltage corresponding to an element in the input data can be input via multiple top select lines. During the first operation phase using the memory array, the peripheral circuitry is configured to apply a first read voltage V to the target word line WLn coupled to the target memory block. rd Appropriate input voltages are applied to the multiple top select lines coupled to the target memory block. For example, input voltages V can be applied to the top select lines TSL0, TSL1, and TSL2 coupled to the target memory block. in0 V in1 V in2 A first on-state voltage is applied to a non-target word line coupled to the target memory block. For example, a first on-state voltage V can be applied to word line WLn+1. pass1 A second on-state voltage is applied to the bottom select line coupled to the target memory block; for example, a second on-state voltage V can be applied to the bottom select line BSL. pass2Analog calculation information can be obtained by sensing the current on the bit line coupled to the target memory block. For example, by sensing the current I0 on bit line BL0 and converting the current I0, information related to the input voltage V can be obtained. in0 Corresponding elements and weights w 00 The product of the input voltage V in1 Corresponding elements and weights w 10 The product of the input voltage V in2 Corresponding elements and weights w 20 The sum of these three products. In some embodiments, the first operation includes a multiplication-accumulation operation.

[0101] In some embodiments, the peripheral circuitry is configured to apply a corresponding programming voltage to a target word line coupled to a target memory block to program the memory cell coupled to the target word line before performing a first operation using the memory array.

[0102] In a specific example, a memory cell in the target memory block is configured to store one bit of data. Multiple memory cells in the target memory block have a first memory state and a second memory state. The threshold voltage of a memory cell having the first memory state is less than the threshold voltage of a memory cell having the second memory state. The first read voltage V... rd The threshold voltage is greater than that of the memory cell with the first memory state and less than that of the memory cell with the second memory state. Here, the memory cell in the target memory block can be a single-level cell (SLC) storing one bit of data, the first memory state can be an erase state (E), and the second memory state can be a programmable state (P). The peripheral circuit can be configured to perform a programming operation on the memory cell coupled to the target word line before performing the first operation, writing weights to the memory cell according to a certain mapping rule. For a single-level cell, the weight writing process includes applying a corresponding programming voltage to adjust the threshold voltage of a portion of the memory cells coupled to the target word line to the range of the threshold voltage distribution corresponding to the second memory state.

[0103] In some embodiments, refer to Figure 7As shown, taking a target memory block comprising eight memory strings coupled to bit line BL0 as an example, four memory cells coupled to the target word line WLn are in the first memory state (erase state E), and the other four memory cells are in the second memory state (programming state P). Input data can be input from the eight top select lines TSL0 to TSL7. Specifically, the input data can be an input vector comprising eight elements, which can include five "1"s and three "0"s. The digital-to-analog converter circuit can convert each element of the input vector into a corresponding voltage signal, and the voltage signal is converted into an input voltage to be applied to the top select line by a voltage generator. The input voltage is then transmitted to the top select line by a driver coupled to the top select line. Specifically, the eight input voltages can be applied to the eight top select lines simultaneously. Among them, the input voltage corresponding to "1" includes V in0 V in1 V in4 V in5 and V in6 This allows the top selection transistors TSG0, TSG1, TSG4, TSG5, and TSG6, respectively coupled to the top selection lines TSL0, TSL1, TSL4, TSL5, and TSL6, to be turned on. The input voltages corresponding to "0" include V. in2 V in3 V in7 This can turn off the top select transistors TSG2, TSG3, and TSG7, which are coupled to the top select lines TSL2, TSL3, and TSL7, respectively.

[0104] In a specific example, refer to Figure 7 As shown, the current I0 on bit line BL0 is the sum of the output currents of the eight memory strings coupled to bit line BL0. The input voltage on the top select line coupled to memory strings Str0, Str4 and Str5 causes the top select transistors TSG0, TSG4 and TSG5 to be in the on state. The memory cells in memory strings Str0, Str4 and Str5 coupled to the target word line WLn have the first memory state (erasure state E). Therefore, memory strings Str0, Str4 and Str5 are turned on and can generate a current greater than or equal to the preset current. The current I0 on bit line BL0 is basically equal to the sum of the output currents of memory strings Str0, Str4 and Str5. The multiple of current I0 relative to the current generated by any memory string in memory strings Str0, Str4 and Str5 is approximately 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory strings coupled to the bit line BL0 can be equivalent to: 1×1+1×0+0×1+0×0+1×1+1×1+1×0+0×0=3.

[0105] Based on the specific example above, when there are Y+1 memory strings coupled to bit lines BLx in the target memory block, the Y+1 elements corresponding to the input voltages input by the top selection lines of the Y+1 strings are α0, α1...α... Y The Y+1 memory cells coupled to the target word line WLn store weights w0, w1, ..., w1, respectively. Y Then, the analog calculation information equivalent to the current on bit line BLx relative to the multiple of the output current greater than or equal to the preset current can be α. 0* w0+α 1* w1+……+α Y* w Y .

[0106] In this embodiment of the present disclosure, when multiple sub-memory planes are required to perform the first operation, a first conduction voltage can be applied to the non-target word lines in the multiple sub-memory planes simultaneously. Thus, the voltage establishment phases of the first conduction voltage applied to the non-target word lines coupled to different sub-memory planes can overlap. Compared with the method of applying the first conduction voltage to the non-target word lines coupled to different sub-memory planes separately in different operation phases, the overall operation time can be shortened and the operation efficiency of performing the first operation using multiple sub-memory planes can be improved.

[0107] Furthermore, for each sub-memory plane, multiple memory blocks within that sub-memory plane can be used simultaneously for the first operation. The peripheral circuitry can be configured to: apply a first read voltage to the target word lines coupled to each of the multiple memory blocks in the sub-memory plane; apply corresponding input voltages to the multiple top select lines coupled to each of the multiple memory blocks in the sub-memory plane; and sense the current on the bit lines coupled to the multiple memory blocks in the sub-memory plane. Specifically, the first read voltage V can be applied simultaneously to the target word lines coupled to memory blocks 0 to (N-1) in sub-memory plane 0. rd Simultaneously, a corresponding input voltage V is applied to the multiple top select lines coupled to memory blocks 0 to (N-1) in memory plane 0. in The system senses the current on the bit lines coupled to memory blocks 0 to (N-1) in memory plane 0. The current on the bit lines represents the analog computation information after all memory strings coupled to that bit line have performed the first operation. Thus, multiple memory blocks can perform the first operation in parallel, thereby further improving the computational efficiency and power of the semiconductor device.

[0108] Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. The semiconductor device 600 includes, but is not limited to, a three-dimensional NAND memory. It should be noted that... Figure 8The number of sub-memory surfaces, bit lines, first connection structures 622, and second connection structures 624 shown are merely examples, and this disclosure does not limit the specific number of each structure.

[0109] Reference Figure 8 As shown, the second semiconductor structure 604 includes a memory array, multiple bit lines, and multiple first connection structures 622. For example, four bit lines BL0 to BL3 are located on the side of the memory array away from the first semiconductor structure 602, and each of the four bit lines BL0 to BL3 is connected to the analog-to-digital converter circuit in the first semiconductor structure 602 through four first connection structures 622. In a specific example, the first connection structure 622 is a through silicon contact (TSC). The first end of the first connection structure 622 is connected to the bit line, and the second end of the first connection structure 622 is connected to the second bonding layer 616. The first end and the second end of the first connection structure 622 are opposite each other along the extension direction of the first connection structure 622. Figure 8 The Z direction is represented in the diagram. Therefore, the bit line can pass through the first connection structure 622, the second bonding layer 616, and the first bonding layer (…). Figure 8 (Not shown) is connected to the analog-to-digital converter circuit, thereby transmitting analog calculation information to the analog-to-digital converter circuit. For details regarding the first bonding layer and the second bonding layer 616, please refer to [reference needed]. Figure 1 The relevant descriptions of the first bonding layer 114 and the second bonding layer 116 in the process.

[0110] In some embodiments, the memory array includes a plurality of sub-memory surfaces, which are spaced apart along the extension direction of the bit lines, wherein at least one first connection structure is located between two adjacent sub-memory surfaces. For example, sub-memory surfaces 0 and 1 are spaced apart along the Y direction, and the two first connection structures 622 connecting bit lines BL2 and BL3 are both located between sub-memory surfaces 0 and 1. The first connection structure 622 connecting bit line BL0 is located between sub-memory surface 0 and other sub-memory surfaces adjacent to the left of sub-memory surface 0; or, the first connection structure 622 connecting bit line BL0 is located at the leftmost of the plurality of sub-memory surfaces, i.e., there are no other sub-memory surfaces to the left of sub-memory surface 0. The first connection structure 622 connecting bit line BL1 is located between sub-memory surface 1 and other sub-memory surfaces adjacent to the right of sub-memory surface 1; or, the first connection structure 622 connecting bit line BL1 is located at the rightmost of the plurality of sub-memory surfaces, i.e., there are no other sub-memory surfaces to the right of sub-memory surface 1.

[0111] Understandable Figure 8The diagram shows a portion of the first connection structure 622 located between two adjacent sub-memory surfaces, and another portion located on opposite sides of multiple sub-memory surfaces along the Y direction. This allows at least a portion of the bit lines to be routed to the first semiconductor structure 602 using the space between adjacent sub-memory surfaces, thereby optimizing space utilization, the arrangement of the multiple first connection structures 622, and reducing the area occupied by the multiple first connection structures 622. Of course, in other examples, the multiple first connection structures 622 can be located between any two adjacent sub-memory surfaces.

[0112] Reference Figure 8 As shown, the second semiconductor structure 604 also includes a plurality of second connection structures 624. For example, four bit lines BL0 to BL3 are respectively connected to the peripheral circuits in the third semiconductor structure 606 through four second connection structures 624. Figure 8 (Not shown in the image). In a specific example, the second connection structure 624 is a TSC, the first end of the second connection structure 624 is connected to a bit line, and the second end of the second connection structure 624 is connected to a third bonding layer, wherein the first end and the second end of the second connection structure 624 are opposite to each other along the extension direction of the second connection structure 624. The extension direction of the second connection structure 624 is in... Figure 8 The Z direction is represented in the diagram. Therefore, the bit line can be connected to the peripheral circuitry via the second connection structure 624, the third bonding layer, and the fourth bonding layer, thereby transmitting information such as read results, programming verification results, or erase verification results to the peripheral circuitry. For details on the third and fourth bonding layers, please refer to [reference needed]. Figure 1 The relevant descriptions of the third bonding layer 118 and the fourth bonding layer 120 in the process.

[0113] In some embodiments, the cross-sectional dimension of the first end of the first connection structure 622 is less than or equal to the cross-sectional dimension of the second end of the first connection structure 622; the cross-sectional dimension of the first end of the second connection structure 624 is less than or equal to the cross-sectional dimension of the second end of the second connection structure 624. In actual fabrication, after forming structures such as the memory array and bit lines on the front side of the second substrate, a second connection hole is etched along the direction towards the front side of the second substrate to form the first surface exposing the bit lines. Conductive material is then filled into the second connection hole to form the second connection structure 624. Due to the significant challenges of deep hole etching, the bottom cross-sectional dimension of the formed second connection hole is typically less than or equal to the top cross-sectional dimension, thereby making the cross-sectional dimension of the first end of the second connection structure 624 less than or equal to the cross-sectional dimension of the second end of the second connection structure 624.

[0114] After bonding the second semiconductor structure 604 and the third semiconductor structure 606, the back side of the second substrate can be thinned. A first connection hole is formed by etching along the direction towards the thinned back side of the second substrate, exposing the second surface of the bit line. Conductive material is filled into the first connection hole to form the first connection structure 622, with the first and second surfaces of the bit line facing each other along the Z direction. Similarly, due to the greater challenge of deep hole etching, the cross-sectional dimension of the bottom of the first connection hole is usually smaller than or equal to the cross-sectional dimension of the top of the first connection hole, so that the cross-sectional dimension of the first end of the first connection structure 622 is smaller than or equal to the cross-sectional dimension of the second end of the first connection structure 622.

[0115] In some embodiments, a sub-memory plane includes a plurality of first memory blocks, wherein at least one first connection structure 622 extends through at least one first memory block. For example, a portion of the first memory blocks in the sub-memory plane are configured to store data, while another portion of the first memory blocks in the sub-memory plane are configured as dummy memory blocks. At least one first connection structure 622 can extend through the first memory blocks in the sub-memory plane configured as dummy memory blocks. In this way, bit lines can be led out using the space occupied by the first memory blocks in the sub-memory plane configured as dummy memory blocks, that is, bit lines can be led out using the space already occupied by the first memory blocks without increasing the planar dimensions of the semiconductor device 600. It should be noted that the structure of the dummy memory block can be substantially the same as the structure of the memory block, but the dummy memory block is not used for storing data. The dummy memory block usually serves to provide support, balance stress, etc.

[0116] In some embodiments, the second semiconductor structure 604 further includes a second memory block located between two adjacent sub-memory surfaces, wherein a first connection structure 622 located between the two adjacent sub-memory surfaces extends through the second memory block. For example, the second memory block can be configured as a dummy memory block, and at least one first connection structure 622 can extend through the dummy memory block between the two adjacent sub-memory surfaces. Thus, the space occupied by the second memory block between the two adjacent sub-memory surfaces can be used to bring out bit lines, i.e., the space already occupied by the second memory block can be used to bring out bit lines without increasing the planar dimensions of the semiconductor device 600. It should be noted that the structure of the second memory block and the first memory block can be substantially the same, and the second memory block can be used to physically separate two adjacent sub-memory surfaces. Of course, in other examples, two adjacent sub-memory surfaces can be physically isolated by a dielectric layer, and at least one first connection structure 622 can extend through the dielectric layer between the two adjacent sub-memory surfaces.

[0117] In some embodiments, the first semiconductor structure 602 further includes a control circuit (not shown in the figure), which can be configured to control the operation of the semiconductor device 600. That is, the control circuit can act as a memory controller managing data storage and transmission in the bonded second semiconductor structure 604 and third semiconductor structure 606 (hereinafter referred to as the bonded semiconductor structure), and an arithmetic controller managing data processing and transmission in the first semiconductor structure. It should be noted that the process node corresponding to the first semiconductor structure can be smaller than the process node corresponding to the third semiconductor structure. In this embodiment, by integrating the control circuit into the first semiconductor structure 602 with a smaller process node and bonding it to the bonded semiconductor structure, not only can the planar size of the semiconductor device be reduced and the integration density improved, but the data transmission rate can also be increased.

[0118] In some embodiments, control circuitry is coupled to the bonding semiconductor structure and an external device (e.g., a host computer). It is configured to control the bonding semiconductor structure. The control circuitry can manage data stored in the bonding semiconductor structure and communicate with the external device. For example, the control circuitry is also configured to control data transmission between the first semiconductor structure 602 and the bonding semiconductor structure. As another example, the control circuitry is also configured to receive input data sent by the external device and send the input data to the bonding semiconductor structure. Of course, in other embodiments, part or all of the host computer may be integrated into the first semiconductor structure; for example, a host processor may be integrated into the first semiconductor structure.

[0119] In some embodiments, the control circuitry may also be configured to manage various functions relating to data stored or to be stored in the bonded semiconductor structure, including but not limited to bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, the control circuitry is also configured to process error correction codes (ECCs) relating to data read from or written to the bonded semiconductor structure. In some embodiments, the control circuitry may also perform any other suitable function, such as formatting the bonded semiconductor structure.

[0120] In some embodiments, the first semiconductor structure 602 further includes a first interface circuit (not shown), wherein the first interface circuit is configured to receive and transmit data between the semiconductor device 600 and an external device. Specifically, the first interface circuit is configured to output the result of a second operation performed by the data processing circuit to the external device. An interface protocol can be used as the first interface circuit between the control circuit and the external device, so that the control circuit can communicate with the external device through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), Firewire, etc. This first interface circuit can also be referred to as a front-end interface. In some embodiments, the control circuit interacts with the bonding semiconductor structure via multiple configured channels for command / data exchange. These channels are also referred to as back-end interfaces.

[0121] In some embodiments, the third semiconductor structure 606 further includes a second interface circuit (not shown in the figure); the third semiconductor structure 606 can be connected to the first semiconductor structure through the second interface circuit. That is, the second interface circuit here is the interface coupled to the back-end interface of the aforementioned control circuit; in other words, the second interface circuit can also be the interface for communication between the third semiconductor structure and the first semiconductor structure. The second interface circuit can be coupled to... Figure 5 The control logic 512 in the middle acts as a control buffer to buffer control commands received from the host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay it to the host. The second interface circuit can also be transmitted via... Figure 5 The data bus 518 in the middle is coupled to Figure 5 The column decoder / bit line driver 506 in the memory array acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory array.

[0122] In some embodiments, the second semiconductor structure 604 further includes a source layer (not shown) located between the memory array and the first semiconductor structure 602, wherein the source layer connects to at least one of the peripheral circuitry and the control circuitry. For example, combined with Figure 8As shown, the source layer can be located between the memory array and the conductive layer 626. The conductive layer 626 is located between the source layer and the second bonding layer 616, that is, the source layer is located on the side of the memory array closer to the first semiconductor structure 602. The source end of the memory string mentioned above can be connected to the source layer, and the drain end of the memory string can be connected to the bit line. In one example, the source layer can be connected to the peripheral circuit through the third connection structure 628, the third bonding layer, and the fourth bonding layer mentioned below. In another example, the source layer can be connected to the control circuit through the conductive layer 626, the fourth connection structure 630 mentioned below, the second bonding layer 616, and the first bonding layer. The source layer can include one or more layers. For example, the source layer includes a conductive layer and a semiconductor layer. In one example, the material of the source layer is a semiconductor material, including but not limited to intrinsic polysilicon, doped polysilicon (e.g., N-type doped silicon, P-type doped silicon), etc. In some embodiments, the source layer can extend laterally as the array common source ACS. That is, multiple memory strings in the same memory block are coupled together. However, when the source layer is divided into multiple sub-source layers (described below), the sub-source layers can constitute part of a sub-memory plane. 。

[0123] Figure 9 This is a schematic diagram of another semiconductor device provided in an embodiment of this disclosure. It should be noted that... Figure 9 The embodiments shown here use the same reference numerals for the same structures as those in the above embodiments, and the same structures can be referred to the relevant descriptions in the above embodiments, which will not be described in detail again. This embodiment only describes the different structures in detail. For ease of illustration, Figure 9 An exemplary location of the analog-to-digital converter circuit 608 in the first semiconductor structure 602 is shown; however, it should be understood that in an actual memory device, the analog-to-digital converter circuit 608 is integrated within the first semiconductor structure 602.

[0124] In some embodiments, the source layer includes multiple sub-source layers, which are spaced apart along the extension direction of the bit line, wherein each sub-source layer is connected to a corresponding sub-memory plane. For example, the source layer includes two sub-source layers spaced apart along the Y direction, with the source end of the memory string of sub-memory plane 0 connected to one sub-source layer, and the source end of the memory string of sub-memory plane 1 connected to the other sub-source layer. In practical applications, the number of sub-source layers is not limited to... Figure 9 As shown, the number of sub-source pole layers can be reasonably set according to the number of sub-storage surfaces.

[0125] In some embodiments, the second semiconductor structure 604 further includes a third connection structure 628 and a fourth connection structure 630; the third connection structure 628 is located between a first sub-source layer and the third semiconductor structure 606 in a plurality of sub-source layers, wherein the first sub-source layer is connected to a peripheral circuit through the third connection structure 628; the fourth connection structure 630 is located between a second sub-source layer and the first semiconductor structure 602 in a plurality of sub-source layers, wherein the second sub-source layer is connected to a control circuit through the fourth connection structure 630. For example, Figure 9 The sub-source pole layer connected to the source pole of the storage string at neutron storage plane 0 can be the first sub-source pole layer. Figure 9 The sub-source pole layer of the storage string of neutron storage plane 1 can be a second sub-source pole layer.

[0126] In this embodiment, the peripheral circuit can be coupled to sub-memory plane 0 through a first sub-source layer, and the control circuit can be coupled to sub-memory plane 1 through a second sub-source layer. For example, if the second sub-source layer is an analog signal output terminal, the control circuit can control the second sub-source layer to transmit the analog calculation information obtained from the first operation on sub-memory plane 1 to the analog-to-digital conversion circuit 608, thereby reducing the signal transmission distance. It is understood that the sub-source layer connected to the peripheral circuit among the multiple sub-source layers is the first sub-source layer, and the sub-source layer connected to the control circuit among the multiple sub-source layers is the second sub-source layer. Of course, in other embodiments, the multiple sub-source layers can be connected to the peripheral circuit through multiple third connection structures 628 respectively.

[0127] In some embodiments, the sub-memory surface connected to the first sub-source layer has a first side and a second side opposite to each other along the arrangement direction of multiple bit lines, wherein the third connection structure 628 is located on the first side or the second side of the sub-memory surface connected to the first sub-source layer, and the arrangement direction of the multiple bit lines intersects with the extension direction of the bit lines. Figure 9 The diagram shows that the third connection structure 628 is located on one side opposite to the four bit lines BL0 to BL3 along the X direction. That is, the third connection structure 628 is located on one side opposite to the multiple bit lines along the X direction, which avoids overly dense arrangement of connection structures on both sides opposite to the bit lines along the Y direction, thus optimizing the arrangement of connection structures in the semiconductor device 600. The arrangement direction of the multiple bit lines is... Figure 9 The direction of the bit line is represented by the X direction, and the extension direction of the bit line is in... Figure 9 The Y direction is represented in the figure. It should be noted that... Figure 9 The third connection structure 628 shown is for illustrative purposes only. The third connection structure 628 may also have other shapes, and the third connection structure 628 may also be a TSC.

[0128] In some embodiments, the second semiconductor structure 604 further includes a plurality of conductive layers 626, which are located between the source layer and the first semiconductor structure 602 and are spaced apart along the extension direction of the bit lines. A first sub-source layer is connected to a third connection structure 628 via one conductive layer 626, and a second sub-source layer is connected to a fourth connection structure 630 via another conductive layer 626. For example... Figure 9 Two conductive layers 626 are shown arranged at intervals along the Y direction. A first sub-source layer is connected to one conductive layer 626, which is connected to a third bonding layer via a third connection structure 628. A second sub-source layer is connected to the other conductive layer 626, which is connected to a second bonding layer 616 via a fourth connection structure 630. In practical applications, the number of conductive layers 626 is not limited to... Figure 9 As shown, the number of conductive layers 626 can be reasonably set according to the number of sub-source layers.

[0129] Figure 10 This is a schematic diagram of the structure of another semiconductor device 600 provided in an embodiment of this disclosure. It should be noted that... Figure 10 The embodiments shown here use the same reference numerals for the same structures as those in the above embodiments, and the same structures can be referred to the relevant descriptions in the above embodiments, which will not be described in detail again. This embodiment only provides a detailed description of the different structures.

[0130] In some embodiments, the second semiconductor structure 604 further includes at least one connection portion 632 located between two adjacent conductive layers 626, wherein the opposite ends of the connection portion 632 along the bit line extension direction are respectively connected to the two adjacent conductive layers 626. For example, Figure 10 Two first connection portions 632 are shown, which allows two adjacent conductive layers 626 to be connected using the space between two adjacent sub-memory surfaces. It should be noted that the number of first connection portions 632 is not limited to this. Figure 10 As shown, the first connection structure 622 and the connection portion 632 located between two adjacent sub-storage surfaces are isolated from each other.

[0131] Figure 11 This is a top view schematic diagram of a channel structure, a dummy channel structure, and a first connecting structure 622 provided for embodiments of this disclosure. (Refer to...) Figure 11As shown, the channel structures located on opposite sides of the first connection structure 622 along the Y direction belong to two sub-memory surfaces. The dummy channel structure located between the first connection structure 622 and the channel structure belongs to either the first memory block configured as a dummy memory block or the second memory block. By forming the first connection structure 622 in the space occupied by the dummy memory block in the semiconductor device 600, space can be rationally utilized, the arrangement of multiple first connection structures 622 can be optimized, and the area occupied by multiple first connection structures 622 can be reduced. It should be noted that the structure of the dummy channel structure can be basically the same as the structure of the channel structure, but the dummy memory cells corresponding to the dummy channel structure are not used for storing data. The dummy channel structure usually plays a role in support and stress balancing. For more information on the channel structure, please refer to... Figure 4 Related descriptions.

[0132] Figures 12A to 12D This is a schematic diagram showing the arrangement of the first connection structure 622 provided in an embodiment of this disclosure. For ease of understanding, Figures 12A to 12D The diagram shows m sub-memory planes, n bit lines, and n first connection structures 622, where m and n are both integers greater than 1.

[0133] In some embodiments, a portion of the plurality of first connection structures 622 are located between two adjacent sub-memory surfaces, and another portion of the plurality of first connection structures 622 are located on opposite sides of the plurality of sub-memory surfaces along the bit line extension direction. For example, Figure 12A and Figure 12B The diagram shows that the first connection structure 622-0 connecting bit line BL0 and the first connection structure 622-(n-1) connecting bit line BLn-1 are located on opposite sides of sub-memory plane 0 to sub-memory plane (m-1) along the bit line extension direction. Figure 12A The first connection structure 622-1 of the intermediate connection bit line BL1 is located between sub-memory surface 0 and sub-memory surface 1, and the first connection structure 622-(n-2) of the connection bit line BLn-2 is located between sub-memory surface 1 and sub-memory surface (m-1). Figure 12B The first connection structure 622-1 of the intermediate connection bit line BL1 and the first connection structure 622-(n-2) of the connection bit line BLn-2 are both located between sub-memory plane 0 and sub-memory plane 1.

[0134] In some embodiments, any one of the plurality of first connection structures 622 is located between two adjacent sub-storage surfaces. For example, Figure 12CThe diagram shows that the first connection structure 622-0 of bit line BL0 and the first connection structure 622-(n-2) of bit line BLn-2 are both located between sub-memory plane 0 and sub-memory plane 1, and the first connection structure 622-1 of bit line BL1 and the first connection structure 622-(n-1) of bit line BLn-1 are both located between sub-memory plane 1 and sub-memory plane (m-1). For example, Figure 12D The first connection structure 622-0 of the bit line BL0, the first connection structure 622-1 of the bit line BL1, the first connection structure 622-(n-1) of the bit line BLn-1, and the first connection structure 622-(n-2) of the bit line BLn-2 are all located between sub-memory plane 0 and sub-memory plane 1.

[0135] It should be noted that, Figures 12A to 12D Several examples of the arrangement of the multiple first connection structures 622 are shown; however, the arrangement of the multiple first connection structures 622 is not limited to these examples. Figures 12A to 12D As shown. In practical applications, the feature size of the first connection structure 622, the distance between two adjacent sub-memory surfaces, and the distance between two adjacent bit lines should be comprehensively considered to reasonably arrange multiple first connection structures 622, so as to reduce problems such as short circuits or large parasitic capacitances caused by the close proximity of two adjacent first connection structures 622.

[0136] Figure 13 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. (Refer to...) Figure 13 As shown, the semiconductor device 100 includes a core region A, a connection region B, and a peripheral region C. The semiconductor device 100 includes a first semiconductor structure 702, a second semiconductor structure 704, and a third semiconductor structure 706. The first semiconductor structure 702 and the second semiconductor structure 704 are bonded together on their first sides, and the third semiconductor structure 706 is bonded together on the second side of the second semiconductor structure 704. The first side of the second semiconductor structure 704 and the second side of the second semiconductor structure 704 are opposite sides of the second semiconductor structure 704 along the Z direction.

[0137] The first semiconductor structure 702 includes an analog-to-digital converter circuit 708 and a data processing circuit 709. For details on the analog-to-digital converter circuit 708 and the data processing circuit 709, please refer to... Figure 1 Description of the analog-to-digital converter circuit 108 and the data processing circuit 109.

[0138] The second semiconductor structure 704 includes a stacked structure 710 and a memory string extending through the stacked structure 710, wherein the source end of the memory string is connected to a semiconductor material layer 734, and the drain end of the memory string is connected to a bit line. For more information on the stacked structure 710, please refer to [reference needed]. Figure 4For a description of the 410 mid-layer stack-up structure, please refer to the documentation on storage strings. Figure 3 and Figure 4 Description of the storage string 308.

[0139] The third semiconductor structure 706 includes peripheral circuitry 712, which can be found in [reference]. Figure 1 peripheral circuit 112 and Figure 5 Related descriptions.

[0140] In some embodiments, the first semiconductor structure 702 and the second semiconductor structure 704 can be vertically connected by bonding. As an example, see [reference needed]. Figure 13 As shown, the first semiconductor structure 702 includes a first bonding layer 714, and the second semiconductor structure 704 includes a second bonding layer 716. The second bonding layer 716 and the first bonding layer 714 are bonded together, thereby making the first semiconductor structure 702 and the second semiconductor structure 704 vertically connected. For details on the first bonding layer 714 and the second bonding layer 716, please refer to... Figure 1 Descriptions of the first bonding layer 114 and the second bonding layer 116.

[0141] In some embodiments, the second semiconductor structure 704 and the third semiconductor structure 706 can be vertically connected by bonding. As an example, see [reference needed]. Figure 13 As shown, the second semiconductor structure 704 includes a third bonding layer 718, and the third semiconductor structure 706 includes a fourth bonding layer 720. The fourth bonding layer 720 and the third bonding layer 718 are bonded together, thereby making the second semiconductor structure 704 and the third semiconductor structure 706 vertically connected. For details on the third bonding layer 718 and the fourth bonding layer 720, please refer to... Figure 1 Description of the third bonding layer 118 and the fourth bonding layer 120.

[0142] In some embodiments, the second semiconductor structure 704 further includes a conductive layer 726, which is located between the semiconductor material layer 734 and the second bonding layer 716 and coupled to the semiconductor material layer 734. The semiconductor material layer 734 can be connected to the peripheral circuit 712 or the control circuit in the first semiconductor structure 702 through the conductive layer 726. For example, the semiconductor material layer 734 can be connected to the conductive layer 726 and the conductive structure 722 (see also [reference]). Figure 9 The third connection structure 628, the third bonding layer 718, and the fourth bonding layer 720 are connected to the peripheral circuit 712. For example, the semiconductor material layer 734 can be connected to the conductive layer 726, the conductive structure 724 (or, for example, refer to...), through the conductive layer 726, the conductive structure 724 (or, for example, refer to...). Figure 9 The fourth connection structure 630, the second bonding layer 716, and the first bonding layer 714 are connected to the control circuit.

[0143] This disclosure also provides a semiconductor device. The semiconductor device includes: a first semiconductor structure and a second semiconductor structure, with a first side of the first semiconductor structure and the second semiconductor structure bonded together; the first semiconductor structure includes an analog-to-digital converter circuit; the second semiconductor structure includes a plurality of sub-memory surfaces, a plurality of bit lines, and a plurality of first connection structures, the plurality of sub-memory surfaces being located between the plurality of bit lines and the first side of the second semiconductor structure and arranged at intervals along the extension direction of the bit lines, wherein at least one first connection structure is located between two adjacent sub-memory surfaces and respectively connects the bit lines and the analog-to-digital converter circuit.

[0144] In some embodiments, a sub-storage plane includes a plurality of first storage blocks, wherein at least one first connection structure extends through at least one first storage block.

[0145] In some embodiments, the second semiconductor structure further includes a second memory block located between two adjacent sub-memory surfaces, wherein a first connection structure located between the two adjacent sub-memory surfaces extends through the second memory block.

[0146] In some embodiments, the semiconductor device further includes a third semiconductor structure, the third semiconductor structure and the second semiconductor structure are bonded together on a second side, the second side of the second semiconductor structure and the first side of the second semiconductor structure are opposite to each other along the extension direction of the first connection structure; the third semiconductor structure includes peripheral circuitry; the second semiconductor structure further includes a plurality of second connection structures, the plurality of second connection structures being located between a plurality of bit lines and the third semiconductor structure, wherein each bit line is connected to the peripheral circuitry through a second connection structure.

[0147] In some embodiments, the first semiconductor structure further includes a control circuit; the second semiconductor structure further includes a source layer located between the plurality of sub-memory surfaces and the first semiconductor structure, wherein the source layer is connected to at least one of the peripheral circuits and the control circuit.

[0148] In some embodiments, the source layer includes a plurality of sub-source layers, which are spaced apart along the extension direction of the bit line, wherein each sub-source layer is connected to a corresponding sub-memory surface; the second semiconductor structure further includes a third connection structure and a fourth connection structure; the third connection structure is located between the first sub-source layer and the third semiconductor structure among the plurality of sub-source layers, wherein the first sub-source layer is connected to a peripheral circuit through the third connection structure; the fourth connection structure is located between the second sub-source layer and the first semiconductor structure among the plurality of sub-source layers, wherein the second sub-source layer is connected to a control circuit through the fourth connection structure.

[0149] In some embodiments, the sub-memory surface connected to the first sub-source layer has a first side and a second side opposite to each other along the arrangement direction of multiple bit lines, wherein the third connection structure is located on the first side or the second side of the sub-memory surface connected to the first sub-source layer, and the arrangement direction of the multiple bit lines intersects with the extension direction of the bit lines.

[0150] In some embodiments, the second semiconductor structure further includes a plurality of conductive layers, which are located between the source layer and the first semiconductor structure and are spaced apart along the extension direction of the bit line, wherein the first sub-source layer is connected to the third connection structure through a conductive layer, and the second sub-source layer is connected to the fourth connection structure through another conductive layer.

[0151] In some embodiments, the second semiconductor structure further includes at least one connection portion located between two adjacent conductive layers, wherein the two opposite ends of the connection portion along the bit line extension direction are respectively connected to the two adjacent conductive layers.

[0152] In some embodiments, the first semiconductor structure includes a first bonding layer located between the second semiconductor structure and the analog-to-digital conversion circuit; the second semiconductor structure includes a second bonding layer and a third bonding layer, the second bonding layer being located between a plurality of sub-memory surfaces and the first bonding layer, and the third bonding layer being located between a plurality of second interconnect structures and the third semiconductor structure, wherein the second bonding layer and the first bonding layer are bonded; the third semiconductor structure further includes a fourth bonding layer located between the peripheral circuit and the third bonding layer, wherein the fourth bonding layer and the third bonding layer are bonded.

[0153] In some embodiments, a first end of the first connection structure is connected to a bit line, and a second end of the first connection structure is connected to a second bonding layer, wherein the first end and the second end of the first connection structure are opposite to each other along the extension direction of the first connection structure; a first end of the second connection structure is connected to a bit line, and a second end of the second connection structure is connected to a third bonding layer, wherein the first end and the second end of the second connection structure are opposite to each other along the extension direction of the second connection structure.

[0154] In some embodiments, the cross-sectional dimension of the first end of the first connecting structure is less than or equal to the cross-sectional dimension of the second end of the first connecting structure; the cross-sectional dimension of the first end of the second connecting structure is less than or equal to the cross-sectional dimension of the second end of the second connecting structure.

[0155] In some embodiments, any one of the plurality of first connection structures is located between two adjacent sub-storage surfaces.

[0156] In some embodiments, a portion of the plurality of first connection structures is located between two adjacent sub-memory surfaces, and another portion of the plurality of first connection structures is located on opposite sides of the plurality of sub-memory surfaces along the bit line extension direction.

[0157] In some embodiments, the semiconductor device includes a three-dimensional NAND memory.

[0158] The specific structures and other details of the first, second, and third semiconductor structures are similar to those in the aforementioned semiconductor devices, and will not be repeated here for the sake of brevity.

[0159] Based on the above-described semiconductor device, this disclosure provides an operation method for the semiconductor device. Figure 14 This is a flowchart illustrating an operation method of a semiconductor device provided in an embodiment of this disclosure, as shown below. Figure 14 As shown, the operation method of the semiconductor device includes at least the following steps S10 and S20.

[0160] Step S10: Perform the first operation through multiple sub-memory surfaces in the second semiconductor structure to obtain analog calculation information.

[0161] Step S20: The analog computing information is transmitted to the analog-to-digital conversion circuit in the first semiconductor structure through multiple bit lines and multiple first connection structures in the second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded together on their first sides, and at least one first connection structure is located between two adjacent sub-memory surfaces and is respectively connected to the bit lines and the analog-to-digital conversion circuit; the analog computing information is converted into digital information through the analog-to-digital conversion circuit.

[0162] In some embodiments, the above-described operation method further includes: performing a second operation on digital information through a data processing circuit in a first semiconductor structure, wherein the data processing circuit is connected to an analog-to-digital conversion circuit.

[0163] In some embodiments, the first operation includes a multiplication-accumulation-addition operation; the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0164] Based on the aforementioned semiconductor device, this disclosure provides a packaging structure. The packaging structure includes: a packaging substrate, a semiconductor device according to any of the above embodiments, and a molding compound layer, wherein the semiconductor device is located on one side of the packaging substrate, and the molding compound layer covers the semiconductor device.

[0165] In some embodiments, the packaging substrate includes a substrate and an interposer formed on the substrate, wherein interconnection circuitry is formed within the interposer, and semiconductor devices are located on the side of the interposer away from the substrate.

[0166] Based on the aforementioned semiconductor devices, this disclosure provides a system. The system includes: at least one semiconductor device according to any of the above embodiments; and a controller coupled to the semiconductor device; the controller is configured to: send data to the semiconductor device and receive data from the semiconductor device.

[0167] Here, the specific structure of the semiconductor device is described in the above embodiments. Since this system adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0168] In some embodiments, the system described above may be as follows: Figure 15A The memory system 802 shown includes a memory controller 806 and a semiconductor device 804 coupled to the memory controller 806. The semiconductor device 804 may include the semiconductor device 100 or the semiconductor device 600 in the above embodiments. The processor in the memory controller 806 can control the semiconductor device 804 to perform parallel computing.

[0169] According to some implementation methods, such as Figure 15A As shown, the memory controller 806 is coupled to the semiconductor device 804 and the host 808, and is configured to control the operation of the semiconductor device 804, such as read, erase, program, and compute operations. The memory controller 806 can manage the data stored in the semiconductor device 804 and communicate with the host 808.

[0170] In other embodiments, the system described in the above embodiments can be as follows: Figure 15B The system shown includes a host 808 and a semiconductor device 804 coupled to the host 808. The host 808 may include a GPU, and the semiconductor device 804 may include the semiconductor device 100 or semiconductor device 600 in the above embodiments. The GPU in the host 808 can control the semiconductor device 804 to perform parallel computing.

[0171] In such Figure 16AIn one example shown, the system can be integrated into a memory card 902. The semiconductor device in the system can be semiconductor device 804 within the memory card 902, and the controller in the system can be memory controller 806 within the memory card 902. The memory card 902 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 902 may also include a memory card connector 904 that couples the memory card 902 to a host computer. Figure 16B In another example shown, the system can be integrated into a solid-state drive (SSD) 906. The semiconductor device in the system can be semiconductor device 804 within the SSD 906, and the controller in the system can be memory controller 806 within the SSD 906. The SSD 906 may also include a solid-state drive connector 908 that couples the SSD 906 to a host device. In some embodiments, the storage capacity and / or operating speed of the SSD 906 is greater than the storage capacity and / or operating speed of the memory card 902.

[0172] In other embodiments, the system can be integrated into the terminal device, and the controller can be the central processing unit (CPU) of the terminal device. Here, the terminal device can be, but is not limited to, any terminal device or portable terminal device such as mobile phone, smart TV, smart speaker, wearable device, tablet computer, desktop computer, all-in-one computer, handheld computer, laptop computer, server, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), laptop computer, mobile computer, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, etc.

[0173] In some embodiments, the system can be used to implement various complex algorithms and data processing tasks. In one specific embodiment, the system can be used in the field of artificial intelligence, such as machine learning, deep learning, neural networks, convolutional neural networks, etc.

[0174] Based on the above-described semiconductor devices and their operating methods, this disclosure provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the operating methods as described in any of the above embodiments.

[0175] Here, implementing all or part of the processes in the operation methods of the above embodiments can be accomplished by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc or a compact disc read-only memory (CD-ROM), etc.; the storage medium can also include combinations of the above types of memory.

[0176] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0177] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0178] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0179] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0180] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure are bonded together on a first side; The first semiconductor structure includes an analog-to-digital converter circuit; The second semiconductor structure includes a memory array, multiple bit lines, and multiple first connection structures. The memory array is located between the multiple bit lines and a first side of the second semiconductor structure, and the multiple first connection structures are located between the multiple bit lines and the first semiconductor structure. Each bit line is connected to the analog-to-digital conversion circuit through one of the first connection structures.

2. The semiconductor device according to claim 1, characterized in that, The memory array includes multiple sub-memory surfaces, which are spaced apart along the extension direction of the bit line, wherein at least one of the first connection structures is located between two adjacent sub-memory surfaces.

3. The semiconductor device according to claim 2, characterized in that, The sub-storage surface includes a plurality of first storage blocks, wherein at least one of the first connection structures extends through at least one of the first storage blocks.

4. The semiconductor device according to claim 2, characterized in that, The second semiconductor structure further includes a second memory block located between two adjacent sub-memory surfaces, wherein the first connection structure located between the two adjacent sub-memory surfaces extends through the second memory block.

5. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a third semiconductor structure, which is bonded to a second side of the second semiconductor structure, and the second side of the second semiconductor structure and the first side of the second semiconductor structure are opposite to each other along the extension direction of the first connection structure. The third semiconductor structure includes peripheral circuitry; The second semiconductor structure further includes a plurality of second connection structures located between the plurality of bit lines and the third semiconductor structure, wherein each bit line is connected to the peripheral circuit through a second connection structure.

6. The semiconductor device according to claim 5, characterized in that, The first semiconductor structure further includes a control circuit; the second semiconductor structure further includes a source layer located between the memory array and the first semiconductor structure, wherein the source layer is connected to at least one of the peripheral circuit and the control circuit.

7. The semiconductor device according to claim 6, characterized in that, The source layer includes a plurality of sub-source layers, which are spaced apart along the extension direction of the bit line, wherein each sub-source layer is connected to a corresponding sub-memory surface; The second semiconductor structure also includes a third connection structure and a fourth connection structure; The third connection structure is located between the first sub-source layer and the third semiconductor structure in the plurality of sub-source layers, wherein the first sub-source layer is connected to the peripheral circuit through the third connection structure; The fourth connection structure is located between the second sub-source layer and the first semiconductor structure in the plurality of sub-source layers, wherein the second sub-source layer is connected to the control circuit through the fourth connection structure.

8. The semiconductor device according to claim 7, characterized in that, The sub-memory surface connected to the first sub-source layer has a first side and a second side opposite to each other along the arrangement direction of the plurality of bit lines, wherein the third connection structure is located on the first side or the second side of the sub-memory surface connected to the first sub-source layer, and the arrangement direction of the plurality of bit lines intersects with the extension direction of the bit lines.

9. The semiconductor device according to claim 7, characterized in that, The second semiconductor structure further includes a plurality of conductive layers, which are located between the source layer and the first semiconductor structure and are spaced apart along the extension direction of the bit line. The first sub-source layer is connected to the third connection structure through one of the conductive layers, and the second sub-source layer is connected to the fourth connection structure through another conductive layer.

10. The semiconductor device according to claim 9, characterized in that, The second semiconductor structure further includes at least one connection portion located between two adjacent conductive layers, wherein the two opposite ends of the connection portion along the bit line extension direction are respectively connected to the two adjacent conductive layers.

11. The semiconductor device according to claim 5, characterized in that, The first semiconductor structure includes a first bonding layer, which is located between the second semiconductor structure and the analog-to-digital conversion circuit; The second semiconductor structure includes a second bonding layer and a third bonding layer, the second bonding layer being located between the memory array and the first bonding layer, and the third bonding layer being located between the plurality of second connection structures and the third semiconductor structure, wherein the second bonding layer and the first bonding layer are bonded; The third semiconductor structure further includes a fourth bonding layer, which is located between the peripheral circuit and the third bonding layer, wherein the fourth bonding layer and the third bonding layer are bonded.

12. The semiconductor device according to claim 11, characterized in that, The first end of the first connection structure is connected to the bit line, and the second end of the first connection structure is connected to the second bonding layer, wherein the first end and the second end of the first connection structure are opposite to each other along the extension direction of the first connection structure; The first end of the second connection structure is connected to the bit line, and the second end of the second connection structure is connected to the third bonding layer, wherein the first end and the second end of the second connection structure are opposite to each other along the extension direction of the second connection structure.

13. The semiconductor device according to claim 12, characterized in that, The cross-sectional dimension of the first end of the first connecting structure is less than or equal to the cross-sectional dimension of the second end of the first connecting structure; the cross-sectional dimension of the first end of the second connecting structure is less than or equal to the cross-sectional dimension of the second end of the second connecting structure.

14. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a three-dimensional NAND memory.

15. A semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure are bonded together on a first side; The first semiconductor structure includes an analog-to-digital converter circuit; The second semiconductor structure includes multiple sub-memory surfaces, multiple bit lines, and multiple first connection structures. The multiple sub-memory surfaces are located between the multiple bit lines and a first side of the second semiconductor structure and are spaced apart along the extension direction of the bit lines. At least one of the first connection structures is located between two adjacent sub-memory surfaces and connects the bit lines and the analog-to-digital conversion circuit, respectively.

16. The semiconductor device according to claim 15, characterized in that, The sub-storage surface includes a plurality of first storage blocks, wherein at least one of the first connection structures extends through at least one of the first storage blocks.

17. The semiconductor device according to claim 15, characterized in that, The second semiconductor structure further includes a second memory block located between two adjacent sub-memory surfaces, wherein the first connection structure located between the two adjacent sub-memory surfaces extends through the second memory block.

18. The semiconductor device according to claim 15, characterized in that, The semiconductor device further includes a third semiconductor structure, which is bonded to a second side of the second semiconductor structure, and the second side of the second semiconductor structure and the first side of the second semiconductor structure are opposite to each other along the extension direction of the first connection structure. The third semiconductor structure includes peripheral circuitry; The second semiconductor structure further includes a plurality of second connection structures located between the plurality of bit lines and the third semiconductor structure, wherein each bit line is connected to the peripheral circuit through a second connection structure.

19. The semiconductor device according to claim 18, characterized in that, The first semiconductor structure further includes a control circuit; the second semiconductor structure further includes a source layer located between the plurality of sub-memory surfaces and the first semiconductor structure, wherein the source layer is connected to at least one of the peripheral circuit and the control circuit.

20. The semiconductor device according to claim 19, characterized in that, The source layer includes a plurality of sub-source layers, which are spaced apart along the extension direction of the bit line, wherein each sub-source layer is connected to a corresponding sub-memory surface; The second semiconductor structure also includes a third connection structure and a fourth connection structure; The third connection structure is located between the first sub-source layer and the third semiconductor structure in the plurality of sub-source layers, wherein the first sub-source layer is connected to the peripheral circuit through the third connection structure; The fourth connection structure is located between the second sub-source layer and the first semiconductor structure in the plurality of sub-source layers, wherein the second sub-source layer is connected to the control circuit through the fourth connection structure.

21. The semiconductor device according to claim 20, characterized in that, The sub-memory surface connected to the first sub-source layer has a first side and a second side opposite to each other along the arrangement direction of the plurality of bit lines, wherein the third connection structure is located on the first side or the second side of the sub-memory surface connected to the first sub-source layer, and the arrangement direction of the plurality of bit lines intersects with the extension direction of the bit lines.

22. The semiconductor device according to claim 20, characterized in that, The second semiconductor structure further includes a plurality of conductive layers, which are located between the source layer and the first semiconductor structure and are spaced apart along the extension direction of the bit line. The first sub-source layer is connected to the third connection structure through one of the conductive layers, and the second sub-source layer is connected to the fourth connection structure through another conductive layer.

23. The semiconductor device according to claim 22, characterized in that, The second semiconductor structure further includes at least one connection portion located between two adjacent conductive layers, wherein the two opposite ends of the connection portion along the bit line extension direction are respectively connected to the two adjacent conductive layers.

24. The semiconductor device according to claim 18, characterized in that, The first semiconductor structure includes a first bonding layer, which is located between the second semiconductor structure and the analog-to-digital conversion circuit; The second semiconductor structure includes a second bonding layer and a third bonding layer. The second bonding layer is located between the plurality of sub-memory surfaces and the first bonding layer, and the third bonding layer is located between the plurality of second interconnect structures and the third semiconductor structure. The second bonding layer is bonded to the first bonding layer. The third semiconductor structure further includes a fourth bonding layer, which is located between the peripheral circuit and the third bonding layer, wherein the fourth bonding layer and the third bonding layer are bonded.

25. The semiconductor device according to claim 24, characterized in that, The first end of the first connection structure is connected to the bit line, and the second end of the first connection structure is connected to the second bonding layer, wherein the first end and the second end of the first connection structure are opposite to each other along the extension direction of the first connection structure; The first end of the second connection structure is connected to the bit line, and the second end of the second connection structure is connected to the third bonding layer, wherein the first end and the second end of the second connection structure are opposite to each other along the extension direction of the second connection structure.

26. The semiconductor device according to claim 25, characterized in that, The cross-sectional dimension of the first end of the first connecting structure is less than or equal to the cross-sectional dimension of the second end of the first connecting structure; the cross-sectional dimension of the first end of the second connecting structure is less than or equal to the cross-sectional dimension of the second end of the second connecting structure.

27. The semiconductor device according to claim 15, characterized in that, Any one of the plurality of first connection structures is located between two adjacent sub-storage surfaces.

28. The semiconductor device according to claim 15, characterized in that, A portion of the plurality of first connection structures is located between two adjacent sub-memory surfaces, and another portion of the plurality of first connection structures is located on opposite sides of the plurality of sub-memory surfaces along the bit line extension direction.

29. The semiconductor device according to claim 15, characterized in that, The semiconductor device includes a three-dimensional NAND memory.

30. A method of operating a semiconductor device, characterized in that, include: The first operation is performed through multiple sub-memory surfaces in the second semiconductor structure to obtain analog computation information; The analog computing information is transmitted to the analog-to-digital conversion circuit in the first semiconductor structure through multiple bit lines and multiple first connection structures in the second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded together on the first side, and at least one first connection structure is located between two adjacent sub-memory surfaces and is respectively connected to the bit lines and the analog-to-digital conversion circuit. The analog-to-digital converter circuit converts the analog calculation information into digital information.

31. The operating method according to claim 30, characterized in that, The operation method further includes: The digital information is subjected to a second operation by the data processing circuit in the first semiconductor structure, wherein the data processing circuit is connected to the analog-to-digital conversion circuit.

32. The operating method according to claim 31, characterized in that, The first operation includes multiplication-accumulation-addition operations; the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

33. A packaging structure, characterized in that, include: The package substrate, the semiconductor device as described in any one of claims 1 to 14 or 15 to 29, and the molding compound, wherein the semiconductor device is located on one side of the package substrate and the molding compound covers the semiconductor device.

34. A system, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 14 or claims 15 to 29; and a controller, the controller being coupled to the semiconductor device; The controller is configured to send data to the semiconductor device and receive data from the semiconductor device.

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