QR-operated switching converter current driver

Abstract

Various embodiments of the present disclosure relate to a switching converter current driver for QR operation. In one embodiment, a control circuit includes: an output terminal configured to be coupled to a control terminal of a transistor coupled to an inductor; a logic circuit configured to control the transistor using a first signal; a zero-crossing detection circuit configured to generate a freewheeling signal indicating demagnetization of the inductor; a comparator having a first input configured to receive a sense voltage indicating current flowing through the transistor and a second input configured to receive a reference voltage, and an output configured to cause the logic circuit to deassert the first signal; a reference generator configured to generate a reference voltage and including: a current generator; a capacitor; and a resistor coupled to the output of the reference generator; and a switch coupled in series with the resistor and configured to be controlled based on the first signal and the freewheeling signal.

Description

Technical Field

[0001] The present disclosure relates generally to electronic systems and methods, and in particular embodiments to a quasi-resonant (QR) operated switching converter current driver. Background Art

[0002] A light emitting diode (LED) driver is configured to provide sufficient current to illuminate the LED. A switching voltage regulator can be used to drive the LED.

[0003] The intensity of light produced by an LED is related to the average current flowing through the LED. Generally, the higher the average current flowing through the LED, the higher the intensity of light produced by the LED. Therefore, it is generally desirable to use a current driver to drive the LED in order to accurately control the average current flowing through the LED.

[0004] By controlling the average current flowing through the LED, the LED can be dimmed. For example, reducing the light intensity produced by the LED can be achieved by reducing the average current flowing through the LED.

[0005] Fluctuations in the average current flowing through the LED may result in fluctuations in the light emitted by the LED.Therefore, a switching converter current driver may be used to properly drive the LED by switching at a frequency above the flicker fusion threshold.

[0006] LED lamp drivers are typically specified for a rated output current (sometimes user programmable within a range) and an output voltage range to power different types / lengths of LED strings. It is important to note that the rated output current is usually specified with very tight accuracy, typically less than 5% overall.

[0007] It is also common for LED lamp drivers to provide dimming capabilities, that is, the ability to reduce the LED current from the rated value to a low value (sometimes less than 1%) to enable the user to reduce the intensity of the light output of the LED string. It is usually desired that the LED current reduction and the resulting light modulation be seamless and flicker-free. Summary of the Invention

[0008] According to an embodiment, a control circuit includes: an output terminal configured to be coupled to a control terminal of a first transistor, the first transistor having a current path coupled to an inductor; a first logic circuit having an output coupled to the output terminal and configured to control the first transistor using a first signal; a zero-crossing detection circuit having a demagnetization sensing input and a first output, the demagnetization sensing input being configured to be coupled to the inductor, the first output of the zero-crossing detection circuit being coupled to a first input of the first logic circuit, wherein the zero-crossing detection circuit is configured to: generate a freewheeling signal indicating demagnetization of the inductor based on the demagnetization sensing input, and utilize the first output of the zero-crossing detection circuit to cause the first logic circuit to assert the first signal based on the demagnetization sensing input to turn on the first transistor; and a first comparator having a first input, a second input, and an output, the first input of the first comparator being configured to receive a first signal. a first comparator configured to receive a sense voltage indicative of a current flowing through a current path of the first transistor, a second input of the first comparator configured to receive a first reference voltage, an output of the first comparator coupled to a second input of the first logic circuit, and the first comparator configured to cause the first logic circuit to deassert a first signal to turn off the first transistor when the sense voltage becomes higher than the first reference voltage; and a reference generator having an output coupled to the second input of the first comparator and configured to generate the first reference voltage at the output of the reference generator, the reference generator comprising: a first current generator configured to generate a first current; a first capacitor coupled to the output of the reference generator and the first current generator; a first resistor coupled to the output of the reference generator; and a first switch coupled in series with the first resistor, the first switch configured to be controlled based on the first signal and a freewheeling signal.

[0009] According to an embodiment, a method for regulating an average output current flowing through an inductor includes: generating a demagnetization signal using an interface circuit, the interface circuit having an input coupled to a first intermediate node, the first intermediate node being coupled between a current path of a power transistor and the inductor; generating a freewheeling signal indicating demagnetization of the inductor based on the demagnetization signal; generating a first signal based on the demagnetization signal; turning on the power transistor at a valley of the demagnetization signal that occurs after the freewheeling signal is deasserted using the first signal; receiving a sense voltage indicating a current flowing through the current path of the power transistor; generating a first reference voltage at a second intermediate node by the following operations: generating a first current using a first current generator coupled to a second intermediate node, the second intermediate node being coupled to a first capacitor and a first resistor; closing a first switch coupled in series with the first resistor when the first signal or the freewheeling signal is asserted, and opening the first switch when the first signal and the freewheeling signal are deasserted; and turning off the power transistor when the sense voltage becomes higher than the first reference voltage, wherein regulating the average output current includes regulating the average output current based on the first current.

[0010] According to an embodiment, a switching converter includes: a first power terminal configured to receive a first voltage; a second power terminal configured to receive a second voltage lower than the first voltage; a power transistor having a current path coupled between the first power terminal and the second power terminal; a sense resistor coupled between the current path of the power transistor and the second power terminal; an inductor coupled between the current path of the power transistor and the first power terminal; a freewheeling diode coupled between the inductor and the first power terminal; a driver having an output coupled to a control terminal of the power transistor; a trigger having a first output coupled to an input of the driver, wherein the trigger is configured to generate a first signal at the first output of the trigger; a zero-crossing detection circuit having a demagnetization sensing input coupled to the current path of the power transistor and the inductor, wherein the zero-crossing detection circuit is configured to: generate a freewheeling signal based on demagnetization of the inductor, and to cause the trigger to a trigger asserting a first signal based on a demagnetization sense input to turn on the power transistor; a first comparator having a first input, a second input, and an output, the first input of the first comparator being configured to receive a sense voltage indicating a current flowing through a current path of the power transistor, the second input of the first comparator being configured to receive a first reference voltage, the output of the first comparator being configured to cause the trigger to deassert the first signal to turn off the power transistor when the sense voltage becomes higher than the first reference voltage; and a reference generator being configured to generate the first reference voltage, the reference generator comprising: a first current generator configured to generate a first current; a first capacitor coupled to the output of the reference generator and the first current generator; a first resistor coupled to the output of the reference generator; and a first switch coupled in series with the first resistor, the first switch being configured to be controlled based on the first signal and a freewheeling signal, wherein an average output current flowing through the inductor is proportional to the first current. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 An LED lamp driver according to an embodiment of the present invention is shown;

[0013] Figure 2 shows a schematic diagram of a buck converter according to an embodiment of the present invention;

[0014] Figure 3 and Figure 4 The diagrams respectively show the operation in the QR mode with or without valley jump according to an embodiment of the present invention. Figure 2 The waveforms associated with the buck converter;

[0015] Figure 5 and Figure 6 The embodiment according to the present invention is shown Figure 2 Schematic diagram of the interface circuit (I / F);

[0016] Figure 7 1. A schematic diagram of a ZCD circuit with valley jump according to an embodiment of the present invention is shown;

[0017] Figure 8 shows a schematic diagram of a buck converter according to an embodiment of the present invention;

[0018] Figure 9 and Figure 10 1 and 2 are respectively coupled to the Figure 5 and Figure 6 a schematic diagram of a portion of a control circuit of an interface circuit; and

[0019] Figure 11 and Figure 12 The embodiment according to the present invention is shown Figure 8 Simulation results associated with a buck converter.

[0020] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0021] The making and using of the disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

[0022] The following description illustrates various specific details to provide an in-depth understanding of several example embodiments according to the description. These embodiments can be obtained without one or more of the specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail to avoid confusing different aspects of the embodiments. References to "embodiments" in this description indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment" that may appear at different points in this description do not necessarily refer to the same embodiment in their entirety. In addition, specific formations, structures, or features may be combined in any appropriate manner in one or more embodiments.

[0023] Embodiments of the present invention will be described in the specific context of a QR-operated buck switching LED driver (constant current source), for example, for solid-state lighting (SSL), such as for driving one or more LEDs as a load. In some embodiments, the load may not include LEDs. Some embodiments can be implemented in applications other than SSL, such as industrial, consumer, ICT, white goods, etc., "as is" or with minor adaptations. Some embodiments can be used in topologies other than buck converters, such as boost or buck-boost converters, for example, with minor adaptations.

[0024] In embodiments of the present invention, the average inductor current of a QR-operated buck converter is regulated by sensing only the current flowing through the power transistor, where the regulated current is independent of the buck converter's switching frequency. Some embodiments utilize a peak current mode control core. In some embodiments, a valley trip circuit limits the buck converter's maximum switching frequency using a nominally constant control scheme, resulting in good average output current regulation accuracy during analog dimming. In some embodiments, a voltage feedforward circuit compensates for propagation delays, making the regulated output current less sensitive to input and output voltage variations.

[0025] Figure 1 An LED lamp driver 100 according to an embodiment of the present invention is shown. The LED lamp driver 100 includes a switching mode power supply (SMPS) 102 and an SMPS 104 for driving an LED string 106. The switching converter 102 provides a regulated DC output voltage V across a storage capacitor 108 that supplies power to the cascade converter 104. 102 The converter 104 provides a regulated output current that powers the LED string 106 .

[0026] In some embodiments, the switching converter 102 can be implemented as a power factor corrector (PFC) front-end converter that can draw a sinusoidal line voltage V mains In-phase sinusoidal current I mains (e.g. 60Hz, 110V rms ;50Hz, 220V rms ) can be used. Using a PFC front-end converter can advantageously achieve high power factor and low distortion of the input current. In some embodiments, using a switching converter 102 with PFC can advantageously help maintain low harmonic emissions, which can advantageously help comply with standards such as IEC61000-3-2, which sets Class C harmonic emission limits for applications such as LED lamp drivers. In some embodiments, implementing a converter 102 with PFC can advantageously help maintain input current I mains Low total harmonic distortion (THD).

[0027] The AC / DC switching converter 102 can output a current I 102 For example, the current I 102 The ripple may exhibit a high-frequency component at the switching frequency of the converter 102 (typically above 50 kHz), and a low-frequency component at twice the frequency of the AC power line (due to the pulsating nature of the power converter 102 drawing from the power line and delivering to its output). If provided to the LED string 106, the low-frequency ripple may result in a given peak average LED current I LED The low frequency ripple may decrease and may cause the operating temperature of the LEDs of the LED string 106 to increase, which may shorten the life of the LEDs of the LED string 106. This low frequency ripple may also cause light fluctuations (flickering and shimmering), which may be undesirable if perceptible and has been reported to cause health problems even when not perceptible.

[0028] PFC output voltage V 102 may be affected by the output current I 102 The converter 102 typically regulates the output voltage V by using a low-bandwidth control loop. 102 The DC value of the input current can be adjusted to achieve high power factor and low distortion of the input current, but low frequency output ripple may not be suppressed.

[0029] In some embodiments, it is advantageous to use a Figure 1 The two-stage power conversion shown, in which the front-end PFC converter 102 supplies power to the capacitor 108 and the cascaded post-regulator converter 104 supplies a regulated current to the LED string 106, helps prevent the LED string 106 from being exposed to ripple at the output of the PFC converter 102. For example, in some embodiments, the converter 104 provides a DC constant current I LED , regulated by a wideband control loop capable of suppressing low-frequency input voltage ripple, which advantageously optimizes the use of the LED string 106 and provides flicker-free operation of the LED string 106.

[0030] In some embodiments, converter 102 may be implemented as a boost converter, and converter 104 may be implemented as a buck converter. For example, in some embodiments, to deliver less than 100W of power to LED string 106, voltage V 102 The voltage V may be between 100 V and 400 V, for example, and the converter 104 provides the voltage V at a level suitable for the LED string 106. LED , such as between 30 V and 60 V. In some embodiments, implementing converter 102 as a step-up converter and converter 104 as a step-down converter can advantageously maintain a low current I 102(and associated low frequency ripple), and can advantageously allow capacitor 108 to be implemented without using bulky, high-capacity energy storage capacitors. Implementing converters 102 and 104 as step-up and step-down converters, respectively, can also advantageously help comply with the requirement that V LED Limited to 60V Safety Extra Low Voltage (SELV) requirements.

[0031] In some embodiments, converter 102 may be implemented as a flyback converter, which may advantageously provide isolation from the mains. Isolation from the mains may advantageously help comply with electrical safety standards such as, for example, IEC 60950, IEC 62368, IEC 61347-1.

[0032] Figure 2 1 is a schematic diagram of a buck converter 200 according to an embodiment of the present invention. Buck converter 200 includes a power transistor 202, an interface (I / F) circuit 210, a sense resistor 208, an inductor 204, a diode 206, capacitors 232 and 234, and a control circuit 220. Control circuit 220 includes a zero current detection (ZCD) circuit 212, a gate driver 218, a trigger 216, a valley trip circuit 214, a comparator 224, and a reference generator 226. Reference generator 226 includes capacitor 230, switches 218 and 228, a resistor 222, an OR gate 238, and a current generator 236. SMPS 104 can be implemented as a buck converter 200 (e.g., where node N1 receives a voltage V 102 As V in ).

[0033] Although LED string 106 is shown as the load driven by buck converter 200, in some embodiments, other loads may be driven by buck converter 200 instead of or in addition to the LED string. For example, in some embodiments, load 106 may be a rechargeable battery.

[0034] like Figure 2 As shown, in some embodiments, power transistor 202 has its source terminal connected to ground, freewheeling diode 206 is connected to node N1, and load 106 is attached to node N1 in series with inductor 204. This configuration can advantageously allow transistor 202 to be driven more easily than driving a floating power switch, and allows control circuit 220 to be referred to ground, which can advantageously allow for simplified interfacing with lamp controls (such as remote on / off, dimming circuits, etc.).

[0035] In some embodiments, the converter 202 can operate in QR mode without valley jumping (the power transistor 202 is turned on at the first valley ringing of the drain of the power transistor 202). In QR mode, the converter 202 synchronizes the turn-on moment of the power transistor 202 with the demagnetization of the inductor 204. The delay T D is introduced so that the turn-on of the power transistor 202 coincides with the minimum drain-source voltage (valley switching), which can advantageously minimize power losses (e.g., associated with the capacitance of the drain of the power transistor 202) and EMI. By operating the converter 202 in QR mode, some embodiments advantageously avoid experiencing any reverse recovery of the freewheeling diode 206 (because no current flows through the inductor 204 or the diode 206 during the turn-on period of the power transistor 202), and therefore, the diode 206 can be implemented with a conventional ultrafast pn diode. Because some embodiments avoid experiencing any reverse recovery of the freewheeling diode 206, some embodiments are advantageously suitable for high voltage applications (e.g., input voltage V in above 200V).

[0036] In some embodiments, the converter 202 can operate in QR mode with valley jumping (the power transistor 202 is turned on when the kth valley of the drain of the power transistor 202 rings, where k is an integer greater than 1). D is increased so that one or more valleys are skipped and the skip delay time T D After the valley occurs during this period, valley switching is still used to turn on power transistor 202. By operating converter 202 using valley skipping, some embodiments advantageously prevent the switching frequency from becoming too high (and thus avoiding the consequent reduction in efficiency) while still maintaining the benefits of valley switching.

[0037] Figure 3 Waveforms 300 associated with the buck converter 200 operating in QR mode without valley skipping are shown in accordance with an embodiment of the present invention. Figure 4 Waveforms 400 associated with the buck converter 200 operating in QR mode with valley skipping are shown in accordance with an embodiment of the present invention. Figures 2 to 4 can be understood together.

[0038] During normal operation, the average current I delivered to the LED string 106 is LED is the inductor current I L The average value of (t) is independent of the operation mode. S When the flip-flop 216 is set, the power transistor 202 is turned on. When the flip-flop 216 is reset by the comparator 224, the power transistor 202 is turned off. CSEqual to voltage V CSref When tripping.

[0039] like Figure 2 As shown, the voltage V CS corresponds to the voltage across the resistor 208 and therefore to the inductor current I flowing through the power transistor 202. L Since the current flows through the power transistor 202 only when the power transistor 202 is off, and since the voltage V CS Equal to voltage V CSref The power transistor 202 is turned off when , so the turn-off condition of the power transistor 202 can be expressed as:

[0040] V CSref =V CS (T ON )=Rs·Isw(T oN )=Rs·I Lpk (1)

[0041] Where T ON represents the time when the power transistor 202 is turned off, Rs represents the resistance of the resistor 208, the current Isw represents the current flowing through the current path of the power transistor 202, and I Lpk Indicates the inductor current I L peak value.

[0042] By using the current I ch The capacitor 230 is charged and discharged through the resistor 222 via the switch 218. The reference generator 226 generates a reference voltage V CSref The switch 218 is configured (via signal V 218 ) remains closed, and the inductor current I L Greater than zero (in the interval T ON +T FW period), and in the remainder of the switching cycle T D Therefore, the switching cycle T S It can be obtained from the following

[0043] T s =T oN +T FW -+T D (2)

[0044] Where T FW represents the current from the power transistor 202 being turned off to the current I L Demagnetization time to reach 0mA, and T D represents the delay between the current IL reaching zero and the power transistor 202 being turned on.

[0045] In some embodiments, the time constant R associated with resistor 222 and capacitor 230 is t ·C t Much longer than the switching period T S (e.g., 10 times greater or more). In some such embodiments (e.g., Figure 3 and Figure 4 As shown), the voltage V generated on the capacitor 230 CSref It is essentially constant (DC voltage) and has a small ripple superimposed on it (for example, the superimposed ripple can be a voltage V CSref 5% or less of the average value of ). Apply the charge balance in the switching cycle to C t , voltage V Csref It can be obtained from the following

[0046]

[0047] Among them I ch represents the current generated by the current generator 236, and R t represents the resistance of the resistor 222 .

[0048] Due to geometric reasons, the average inductor current I LED It can be obtained from the following

[0049]

[0050] Since the peak inductor current I is inferred from Equation 1 Lpk It can be obtained from the following

[0051]

[0052] Then, given Equation 4, the average inductor current I LED It can be obtained from the following

[0053]

[0054] Given Formula 3, it can be obtained as follows

[0055]

[0056] In some embodiments, as seen in Equation 7, the average current I LED It may depend only on the resistor Rs (which may be user selectable) and internal fixed parameters such as I ch and R t ), and does not depend on the voltage V LED or V in Or the inductance L or the switching period T S Or the delay time T DThus, some embodiments may operate in QR mode with valley jumps (e.g., with a delay of T D Duration and time T S Compared to the possible large Figure 4 shown) or without valley jump (where the delay time T D May be relatively small, such as Figure 3 As shown), the same principle (e.g., Equation 7) is used to control the average current I LED .

[0057] In some embodiments, the current I ch Based on R t The matching resistors (not shown) generate the average current I LED High-accuracy control.

[0058] Advantages of some embodiments include allowing accurate control of the output current I in QR mode with or without valley skipping LED , while only monitoring the current Isw flowing through the power transistor 202. Therefore, some embodiments advantageously achieve accurate control of the output current I in a low-cost, low-complexity manner. LED , and does not consume excessive energy. For example, some embodiments advantageously avoid using a resistor in series with the inductor to measure the inductor current I L In some embodiments, avoiding the use of a series resistor to measure inductor current can advantageously reduce power consumption, avoid the use of differential sensing with large common-mode dynamics, and / or avoid the use of a level shifter.

[0059] Additional advantages of some embodiments include achieving high output current (I LED ) accuracy, inductance L, operation mode (QR mode with or without valley switching), switching period T S 、Input voltage V in and LED string voltage V LED Some embodiments advantageously allow adaptation to different V LED Setup requires no external calibration or correction components.

[0060] Some embodiments can advantageously limit the operating frequency range of the converter 202 by using valley skipping without affecting the average current I delivered to the load (eg, 106). LED For example, in some embodiments, the switching frequency F SW (in ) can be varied (e.g. between 130kHz and 230kHz) without causing the average current I LED significant changes in the target average current value (e.g., less than 1% change in the target average current value).

[0061] In some embodiments, control circuit 220 is implemented in the same (e.g., monolithic) integrated circuit, while elements 202, 204, 206, 208, 210, 232, 234, and 106 are implemented outside the integrated circuit (e.g., such that the integrated circuit may include a circuit for receiving voltage V ZCD Demagnetization sensing input, such as Figure 2 Thus, some embodiments advantageously allow the user to accurately control the current I by changing the resistance value Rs of the external component (208). LED In some embodiments, components 206 and 210 are integrated in the same package external to an integrated circuit that includes control circuit 220. In some embodiments, components 202 and / or 204 may be integrated in the same package external to an integrated circuit that includes control circuit 220.

[0062] In some embodiments, the circuitry of buck converter 200 can be integrated in different ways. For example, in some embodiments, interface circuit 210 can be implemented within an integrated circuit that includes control circuit 220. For example, in some embodiments, components 202, 204, and / or 210 can be integrated into the same package as components 212, 214, 216, 218, 222, 224, 228, 230, 236, and 238. In some embodiments, each of components 106, 202, 204, 206, 208, 210, 212, 214, 216, 218, 222, 223, 228, 230, 236, and 238 can be implemented in a discrete manner. Other implementations are also possible.

[0063] In some embodiments, capacitor 234 may be the output capacitor of a previous power stage. For example, in some embodiments, capacitor 108 is connected to node N1 and capacitor 234 may be omitted.

[0064] The power transistor 202 may be implemented as a metal oxide semiconductor field effect transistor (MOSFET). The power transistor 202 may also be implemented in other ways. For example, in some embodiments, the power transistor 202 may be implemented as a gallium nitride (GaN) transistor or as an insulated gate bipolar transistor (IGBT).

[0065] The interface circuit 210 is configured to determine the current I flowing through the inductor 204 based on the current I L Generated voltage V ZCD Voltage V ZCD It can be used to sense the demagnetization moment of the inductor 204 (eg, via the ZCD circuit 212 ).

[0066] In some embodiments, ZCD 212 is configured to sense the current I L The start of voltage ringing at the floating terminal of the inductor 204 (the drain terminal of the power transistor 202) occurs when 0 mA is reached, and a current indicating the demagnetization time T FW The signal V FW For example, in some embodiments, the ZCD circuit 212 includes a circuit for receiving a voltage V ZCD The demagnetization sense input, and based on the voltage V ZCD Generate signal V FW , so that the signal V FW High during the demagnetization period of the inductor 204. In some embodiments, the ZCD 212 can be implemented in a conventional manner. In some embodiments, the ZCD circuit 212 advantageously enables QR operation.

[0067] In some embodiments, the valley skipping circuit 214 is configured to be based on the signal V FW and V ZCD For example, in some embodiments, the valley trip circuit 214 is configured to deliver a pulse to set the flip-flop 216a at the first valley (e.g., as determined by monitoring V ZCD detected), the valley occurs when the inductor current I L After a period of time after zeroing (for example, by monitoring the signal V FW In some embodiments, the valley jump circuit is configured to deliver a pulse to set the trigger 216, which is connected to the delay time T D In some embodiments, the valley skipping circuit 214 advantageously allows the use of a nominally constant control scheme (eg, as illustrated in Equation 7) to limit the maximum switching frequency F SW .

[0068] Figure 5 Schematic diagram of an interface circuit 500 according to an embodiment of the present invention is shown. Interface circuit 210 may be implemented as interface circuit 500. Interface circuit 500 includes a secondary winding 504 of inductor 204 and resistors 506 and 508 forming a voltage divider.

[0069] In some embodiments, the secondary winding 504 tracks the voltage of the drain terminal of the power transistor 202 and has a configuration such that when the power transistor 202 is turned off (at T ON During this period, the voltage has a negative polarity.

[0070] like Figure 5 As shown, the interface circuit 500 is based on the current I flowing through the inductor 204 L Generated voltage V ZCD Voltage VZCD It can be used to sense the demagnetization moment of the inductor 204 (eg, via the ZCD circuit 212 ).

[0071] Figure 6 FIG2 shows a schematic diagram of an interface circuit 600 according to an embodiment of the present invention. The interface circuit 210 may be implemented as the interface circuit 600. The interface circuit 600 includes a DC blocking capacitor 604 (e.g., connected to the drain terminal of the power transistor 202) and resistors 606 and 608 forming a voltage divider. Similar to the interface circuit 500, the voltage V ZCD It can be used to sense the demagnetization moment of the inductor 204 (eg, via the ZCD circuit 212 ).

[0072] Figure 7 Shown is a schematic diagram of a ZCD circuit 700 with a valley jump according to an embodiment of the present invention. ZCD circuit 212 and valley jump circuit 214 can be implemented as ZCD circuit 700 together. ZCD circuit 700 includes a trigger 704, a comparator 702 and 722, an OR gate 706, a delay circuit 724, a single shot circuit 726 and 728m, and a low pass filter 712 including a resistor 710 and a capacitor 708. Low pass filter 712 and comparator 702 form a negative derivative detector.

[0073] In some embodiments, the ZCD circuit 700 can be used to determine the current I L Demagnetization time T to reach 0mA FW For example, Figure 7 As shown, the ZCD circuit 500 monitors the voltage V ZCD (eg, generated by interface circuit 500 or 600) to sense the start of voltage ringing at the floating terminal (drain) of power transistor 202, which occurs when the inductor current I L Therefore, in some embodiments, the voltage V FW At the current I L is reset (e.g., reset to logic low) when it reaches zero, and is turned on when the power transistor 202 is turned on (e.g., according to the signal V S ) is set (e.g., to logic high). For example, in some embodiments (e.g., Figure 7 As shown), since the inverting input of the comparator 702 receives the voltage V ZCD , and the non-inverting input receives the offset V filtered by the low pass filter 712 and shifted downward th The voltage V ZCD , when V ZCD When experiencing a negative edge, the output of the low-pass filter 712 lags behind, and when the difference between them exceeds V th, comparator 702 triggers, thereby resetting flip-flop 704. In some embodiments, offset V th The offset voltage may be constant, such as 25 mV. Other voltages (eg, higher than 25 mV, such as 30 mV or higher, or lower than 25 mV, such as 20 mV or lower) may also be used.

[0074] like Figure 7 As shown, the signal V of the trigger 216 is set S is generated based on the output of the comparator 722 and based on the masking time. Figure 7 As shown, the output of the comparator 722 increases with the voltage V ZCD Below the predetermined threshold V dem After a delay inserted by delay circuit 724 (which may be tuned to match the expected quarter cycle of the ringing at the drain terminal of power transistor 202 ), one-shot circuit 726 generates a pulse intended to set flip-flop 216 .

[0075] When the power transistor 202 is turned off, the signal is asserted, which causes the one-shot circuit 728 to generate a negative pulse whose duration (masking time) is equal to the minimum off-time T of the power transistor 202. OFF Related (and therefore related to the switching period T S The minimum duration of the switching frequency F SW related).

[0076] As in Figure 7 As can be seen in the figure, AND gate 730 makes the signal V S asserts (and sets flip-flop 216) during the first pulse generated by single shot 726 after the masking time. Thus, before power transistor 202 is set, signal V ZCD Can ring multiple times and voltage V ZCD The threshold V can be crossed multiple times dem , which leads to valley jumping.

[0077] In some embodiments, the one-shot circuit 726 is configured to generate a pulse of a predetermined duration (e.g., 20 ns) when the output of the delay circuit 724 transitions from high to low. Pulses of different durations (e.g., greater than 20 ns, such as 25 ns, 30 ns, or longer, or less than 20 ns, such as 18 ns, 15 ns, or shorter) may also be used. The one-shot circuit 726 may be implemented in any manner known in the art.

[0078] In some embodiments, the one-shot circuit 728 is configured to When the signal transitions from high to low (or when the signal VQ The one-shot circuit 728 may be implemented in any manner known in the art.

[0079] In some embodiments, delay circuit 724 produces at its output a delayed version of the signal received at its input, where the introduced delay is a predetermined delay.Delay circuit 724 may be implemented in any manner known in the art.

[0080] Some embodiments allow the current I to be varied in a continuous manner. LED In some embodiments, analog dimming is achieved by reducing the current I ch For example, Figure 8 Schematic diagram of a buck converter 800 according to an embodiment of the present invention is shown. Buck converter 800 includes power transistor 202, interface (I / F) circuit 210, sense resistor 208, inductor 204, diode 206, capacitors 232 and 234, and control circuit 820. Control circuit 820 includes zero current detection (ZCD) circuit 212, gate driver 218, trigger 216, valley trip circuit 214, comparator 224, and reference generator 826. Reference generator 826 includes capacitor 230, switches 218 and 228, resistor 222, OR gate 238, and current generator 236 and d802. SMPS 104 can be implemented as buck converter 200 (e.g., where node N1 receives voltage V 102 As V in ). The control circuit 220 may be implemented as the control circuit 820. The reference generator 226 may be implemented as the reference generator 826.

[0081] Buck converter 800 operates in a similar manner to buck converter 200. However, buck converter 800 includes a current generator 802 configured to sink current from node N2 to reduce the magnitude of the current charging capacitor 230 by I dim Therefore, in some embodiments, the average current I LED It can be obtained from the following

[0082]

[0083] Among them I dim represents the current generated by the current generator 802. As shown in Formula 8, the current I LED can be reduced to zero (by making I dim Equal to I ch In some embodiments, dimming can be achieved by changing the current I ch And omit the current I dim to achieve.

[0084] In some embodiments, the current source 802 may be a voltage-controlled current source based on the voltage V dim Generated current I dim , and the voltage V dim For example, it is received from an input terminal of a control circuit (eg, 820 ).

[0085] review Figure 2 , from the voltage V CS Equal to V CSref The propagation delay ΔT from the time when the power transistor 202 is turned off may not be negligible. Delaying the turning off of the power transistor 202 by ΔT may cause the current I LED is greater than predicted by, for example, Equation 7 or 8. The additional inductor current I L (generated as a result of the additional time ΔT that the power transistor 202 is off) may depend on the applied V in -V LED Therefore, the V in and V LED For example, the propagation delay ΔT has a significant effect on the peak inductor current I Lpk The influence of can be obtained from the following

[0086]

[0087] And I LED It can be obtained from the following

[0088]

[0089] Among them I LED0 represents the average current I determined by, for example, Equation 7 LED .

[0090] In some embodiments, voltage feed-forward is used to compensate for the propagation delay ΔT. For example, in some embodiments, the voltage feed-forward circuit can be based on the voltage V received from the interface circuit 210. ZCD Injection current I FF , to be added to the current Isw. For example, Figure 9 A schematic diagram of a portion of a control circuit 900 coupled to the interface circuit 500 according to an embodiment of the present invention is shown. The control circuit 900 includes a diode 902, a current mirror 904, a current source 906, a resistor 908, and a comparator 224. The control circuit 220 or 820 may be implemented as the control circuit 900.

[0091] The control circuit 900 operates in a similar manner to the control circuit 200. However, the control circuit 900 converts the current I FF is injected into the inverting terminal of the comparator 224 .

[0092] During the on-time T of the power transistor 202 ON During this period, the voltage V across the secondary winding 504 504 It can be obtained from the following

[0093]

[0094] Where n represents the turns ratio between the number of turns of the inductor 204 and the number of turns of the secondary winding 504 .

[0095] Current I ZCD It can be obtained from the following

[0096]

[0097] where R 506 represents the resistance of the resistor 506 .

[0098] As shown by elements 904 and 906, the current I ZCD is mirrored to generate the current I FF , which results in a shift in V 908 It can be obtained from the following

[0099] V 908 =R 908 I FF (13)

[0100] where R 1308 represents the resistance of resistor 908. Therefore, the inductor peak current I Lpk It can be obtained from the following

[0101]

[0102] In some embodiments, R 506 Selected as

[0103]

[0104] So that the voltage V FF From the following

[0105]

[0106] Therefore, it helps to offset the effect of propagation delay ΔT on the peak inductor current I Lpk Contribution, and make I LED =I LED0 .

[0107] like Figure 9 As shown, the interface circuit 210 can be implemented as an interface circuit 500. Other implementations are also possible. For example, Figure 10A schematic diagram is shown of a portion of a control circuit 900 coupled to an interface circuit 600 according to an embodiment of the present invention.

[0108] During the on-time T of the power transistor 202 ON During this period, the voltage V across the DC blocking capacitor 604 604 It can be obtained from the following

[0109] V 6o4 =-(V in -V LED ) (17)

[0110] And the current I LED It can be obtained from the following

[0111]

[0112] where R 606 represents the resistance of the resistor 606 .

[0113] Equations 13 and 14 apply similarly to Figure 10 In some embodiments, R 606 Selected as

[0114]

[0115] So that the voltage V FF From formula 16, we get

[0116] To make I LED Equal to I LED0 , thus, helps to offset the effect of propagation delay ΔT on the peak inductor current I Lpk Contribution, and make I LED =I LED0 .

[0117] Advantages of some embodiments include enabling lighting engineers to design LED lamp drivers that meet market and regulatory requirements with less effort and lower cost.

[0118] Figure 11 and Figure 12 FIG. 2 shows simulation results associated with a buck converter 800 according to an embodiment of the present invention. Figure 9 The voltage feed-forward circuit shown is implemented. The simulated buck converter 200 is designed to receive a V between 108V and 132V. in , generating a voltage V between 30V and 90V LED , generating an output current of 1A I LED, and the dimming range is between 5% and 100%, wherein the inductance L of the inductor 204 is 50 μH, wherein the capacitance of the output capacitor 232 is 22 μF, and wherein the sensing resistance Rs of the resistor 208 is 0.2Ω. Other parameters of the simulated buck converter 800 include a current I ch 4MΩ resistor R t , 50pF C t capacitor and a dimming gain of 1 / 100 A / A. Other implementations are also possible.

[0119] Figure 11 FIG1 illustrates an embodiment of the present invention. LED The 5% to 100% range is given by Equation 8 for the minimum V LED (30V) nominal V LED (60V) and maximum V LED (90V) captured measurement relationship. Figure 12 FIG1 illustrates an embodiment of the present invention. LED Within the range of 5% to 100% of V LED The minimum to maximum change of I LED Deviation. Figure 11 and Figure 12 As shown, I LED and I dim The relationship between is very linear, and I LED V LED The sensitivity of the current regulator is low (approximately 1% of the rated current), which may be advantageous in some embodiments.

[0120] Other advantages of some embodiments include using valley hopping with a QR pattern while avoiding the associated I LED The ability to detect discrete steps in value and corresponding step changes in luminescence.

[0121] Example embodiments of the present invention are summarized herein. Other embodiments are also contemplated from the entirety of this specification and the claims filed herein.

[0122] Example 1. A control circuit comprising: an output terminal configured to be coupled to a control terminal of a first transistor, the first transistor having a current path coupled to an inductor; a first logic circuit having an output coupled to the output terminal and configured to control the first transistor using a first signal; a zero-crossing detection circuit having a demagnetization sensing input and a first output, the demagnetization sensing input being configured to be coupled to the inductor, the first output of the zero-crossing detection circuit being coupled to a first input of the first logic circuit, wherein the zero-crossing detection circuit is configured to: generate a freewheeling signal indicating demagnetization of the inductor based on the demagnetization sensing input, and utilize the first output of the zero-crossing detection circuit to cause the first logic circuit to assert the first signal based on the demagnetization sensing input to turn on the first transistor; a first comparator having a first input, a second input, and an output, the first input of the first comparator being configured to receive the first signal. a first comparator configured to receive a sense voltage indicative of a current flowing through a current path of the first transistor, a second input of the first comparator configured to receive a first reference voltage, an output of the first comparator coupled to a second input of the first logic circuit, and the first comparator configured to cause the first logic circuit to deassert a first signal to turn off the first transistor when the sense voltage becomes higher than the first reference voltage; and a reference generator having an output coupled to the second input of the first comparator and configured to generate the first reference voltage at the output of the reference generator, the reference generator comprising: a first current generator configured to generate a first current; a first capacitor coupled to the output of the reference generator and the first current generator; a first resistor coupled to the output of the reference generator; and a first switch coupled in series with the first resistor, the first switch configured to be controlled based on the first signal and a freewheeling signal.

[0123] Example 2. The control circuit of Example 1, wherein the reference generator further comprises a second switch coupled between the first current generator and an output of the reference generator, wherein the second switch is configured to be controlled based on the first signal.

[0124] Example 3. The control circuit of one of Examples 1 or 2, wherein the first input of the first comparator is configured to be coupled to a sense resistor coupled in series with the current path of the first transistor.

[0125] Example 4. The control circuit according to one of Examples 1 to 3, wherein the control circuit is configured to control the current flowing through the inductor by the following formula

[0126] Example 5. The control circuit of one of Examples 1 to 4, wherein the control circuit is configured to change the magnitude of the first current to change the magnitude of the current flowing through the inductor.

[0127] Example 6. The control circuit of one of Examples 1 to 5, wherein the reference generator further comprises a second current generator configured to subtract the second current from the first current to change the magnitude of the current flowing through the inductor.

[0128] Example 7. The control circuit according to one of Examples 1 to 6 further includes an OR gate having a first input, a second input, and an output, the first input of the OR gate being configured to receive a first signal, the second input of the OR gate being configured to receive a freewheeling signal, and the output of the OR gate being coupled to the control terminal of the first switch.

[0129] Example 8. A control circuit according to one of Examples 1 to 7, wherein the zero-crossing detection circuit includes: a second comparator having a first input and a second input, the first input of the second comparator being coupled to the demagnetization sensing input, the second input of the second comparator being coupled to the demagnetization sensing input via a low-pass filter; and a trigger having a first input and an output, the first input of the trigger being coupled to the output of the second comparator, and the output of the trigger being configured to deliver a freewheeling signal.

[0130] Example 9. The control circuit of one of Examples 1 to 8, wherein the zero-crossing detection circuit includes: a second comparator having a first input and a second input, the first input of the second comparator having a first input coupled to a demagnetization sense input, the second input of the second comparator being configured to receive a second reference voltage; a first one-shot circuit having an input coupled to an output of the second comparator; a delay circuit coupled between the output of the second comparator and the input of the first one-shot circuit; a second one-shot circuit having an input configured to receive a second signal, the second signal being an inverted version of the first signal; and a second logic circuit having a first input, a second input, and an output, the first input of the second logic circuit being coupled to the output of the first one-shot circuit, the second input of the second logic circuit being coupled to the output of the second one-shot circuit, and the output of the second logic circuit being coupled to the first output of the zero-crossing detection circuit.

[0131] Example 10. The control circuit of one of Examples 1 to 9, wherein the zero-crossing detection circuit is configured to cause the first logic circuit to assert the first signal at a kth valley occurring after the freewheeling signal is de-asserted, where k is a positive integer greater than 1.

[0132] Example 11. A control circuit according to one of Examples 1 to 10, wherein the first logic circuit includes a flip-flop having a set input, a reset input, and an output, the set input being coupled to the first output of the zero-crossing detection circuit, the reset input being coupled to the output of the first comparator, and the output of the flip-flop being coupled to the output terminal, wherein the flip-flop is configured to generate a first signal at the output of the flip-flop.

[0133] Example 12. The control circuit of one of Examples 1 to 11 further includes a current mirror configured to be coupled to the first current path terminal of the first transistor via the interface circuit, wherein the current mirror is configured to inject a first current into the first input of the first comparator based on a current flowing through the interface circuit.

[0134] Example 13. The control circuit of one of Examples 1 to 12, further comprising a sense resistor coupled between the first input of the first comparator and ground.

[0135] Example 14. The control circuit of one of Examples 1 to 13, wherein the control circuit is integrated into a single integrated circuit.

[0136] Example 15. The control circuit of one of Examples 1 to 14 further includes a first transistor and a gate driver having an input coupled to the output of the first logic circuit, wherein the first transistor is a power metal oxide semiconductor field effect transistor (MOSFET) having a gate coupled to the output of the gate driver.

[0137] Example 16. A method for regulating an average output current flowing through an inductor, the method comprising: generating a demagnetization signal using an interface circuit, the interface circuit having an input coupled to a first intermediate node, the first intermediate node being coupled between a current path of a power transistor and the inductor; generating a freewheeling signal indicating demagnetization of the inductor based on the demagnetization signal; generating a first signal based on the demagnetization signal; turning on the power transistor at a valley of the demagnetization signal that occurs after the freewheeling signal is deasserted using the first signal; receiving a sense voltage indicating a current flowing through the current path of the power transistor; generating a first reference voltage at a second intermediate node by: generating a first current using a first current generator coupled to a second intermediate node, the second intermediate node being coupled to a first capacitor and a first resistor; closing a first switch coupled in series with the first resistor when the first signal or the freewheeling signal is asserted, and opening the first switch when the first signal and the freewheeling signal are deasserted; and turning off the power transistor when the sense voltage becomes higher than the first reference voltage, wherein regulating the average output current comprises regulating the average output current based on the first current.

[0138] Example 17. The method of Example 16, wherein generating the first reference voltage further comprises: subtracting the second current from the first current to change the magnitude of the current flowing through the inductor.

[0139] Example 18. The method of one of Examples 16 or 17, wherein the average output current is proportional to the first current.

[0140] Example 19. A switching converter comprising: a first power terminal configured to receive a first voltage; a second power terminal configured to receive a second voltage lower than the first voltage; a power transistor having a current path coupled between the first power terminal and the second power terminal; a sense resistor coupled between the current path of the power transistor and the second power terminal; an inductor coupled between the current path of the power transistor and the first power terminal; a freewheeling diode coupled between the inductor and the first power terminal; a driver having an output coupled to a control terminal of the power transistor; a trigger having a first output coupled to an input of the driver, wherein the trigger is configured to generate a first signal at the first output of the trigger; a zero-crossing detection circuit having a demagnetization sensing input coupled to the current path of the power transistor and the inductor, wherein the zero-crossing detection circuit is configured to: generate a freewheeling signal based on demagnetization of the inductor, and cause the trigger to a trigger asserting a first signal based on a demagnetization sense input to turn on the power transistor; a first comparator having a first input, a second input, and an output, the first input of the first comparator being configured to receive a sense voltage indicating a current flowing through a current path of the power transistor, the second input of the first comparator being configured to receive a first reference voltage, the output of the first comparator being configured to cause the trigger to deassert the first signal to turn off the power transistor when the sense voltage becomes higher than the first reference voltage; and a reference generator being configured to generate the first reference voltage, the reference generator comprising: a first current generator configured to generate a first current; a first capacitor coupled to the output of the reference generator and the first current generator; a first resistor coupled to the output of the reference generator; and a first switch coupled in series with the first resistor, the first switch being configured to be controlled based on the first signal and a freewheeling signal, wherein an average output current flowing through the inductor is proportional to the first current.

[0141] Example 20. The switching converter of Example 19, further comprising a light emitting diode (LED) string coupled between the inductor and the first power terminal.

[0142] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the description. Accordingly, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A control circuit comprising: an output terminal configured to be coupled to a control terminal of a first transistor having a current path coupled to an inductor; a first logic circuit having an output coupled to the output terminal and configured to control the first transistor using a first signal; a zero-crossing detection circuit having a demagnetization sensing input and a first output, wherein the demagnetization sensing input is configured to be coupled to the inductor, the first output of the zero-crossing detection circuit is coupled to the first input of the first logic circuit, wherein the zero-crossing detection circuit is configured to: generating a freewheeling signal indicative of demagnetization of the inductor based on the demagnetization sense input, and utilizing the first output of the zero-crossing detection circuit to cause the first logic circuit to assert the first signal based on the demagnetization sensing input to turn on the first transistor; a first comparator having a first input, a second input, and an output, the first input of the first comparator being configured to receive a sense voltage indicative of a current flowing through the current path of the first transistor, the second input of the first comparator being configured to receive a first reference voltage, the output of the first comparator being coupled to the second input of the first logic circuit, and the first comparator being configured to cause the first logic circuit to deassert the first signal to turn off the first transistor when the sense voltage becomes higher than the first reference voltage; as well as a reference generator having an output coupled to the second input of the first comparator and configured to generate the first reference voltage at the output of the reference generator, the reference generator comprising: a first current generator configured to generate a first current, a first capacitor coupled to the output of the reference generator and the first current generator, a first resistor coupled to the output of the reference generator, and A first switch is coupled in series with the first resistor, and the first switch is configured to be controlled based on the first signal and the freewheeling signal.

2. The control circuit of claim 1 , wherein the reference generator further comprises a second switch coupled between the first current generator and the output of the reference generator, wherein the second switch is configured to be controlled based on the first signal. 3 . The control circuit of claim 1 , wherein the first input of the first comparator is configured to be coupled to a sense resistor coupled in series with the current path of the first transistor.

4. The control circuit according to claim 3 , wherein the control circuit is configured to control the current flowing through the inductor by the following formula: Among them I LED represents the current flowing through the inductor, Rs represents the resistance of the sensing resistor, and I ch represents the first current, and R t represents the resistance of the first resistor. 5 . The control circuit of claim 4 , wherein the control circuit is configured to change the magnitude of the first current to change the magnitude of the current flowing through the inductor. 6 . The control circuit of claim 1 , wherein the reference generator further comprises a second current generator configured to subtract a second current from the first current to change the magnitude of the current flowing through the inductor.

7. The control circuit according to claim 1 further includes an OR gate having a first input, a second input, and an output, the first input of the OR gate being configured to receive the first signal, the second input of the OR gate being configured to receive the freewheeling signal, and the output of the OR gate being coupled to the control terminal of the first switch.

8. The control circuit according to claim 1 , wherein the zero-crossing detection circuit comprises: a second comparator having a first input and a second input, wherein the first input of the second comparator is coupled to the demagnetization sensing input, and the second input of the second comparator is coupled to the demagnetization sensing input via a low-pass filter; as well as A flip-flop has a first input and an output, the first input of the flip-flop being coupled to the output of the second comparator, the output of the flip-flop being configured to deliver the freewheeling signal.

9. The control circuit according to claim 1 , wherein the zero-crossing detection circuit comprises: a second comparator having a first input and a second input, the first input of the second comparator being coupled to the demagnetization sense input, the second input of the second comparator being configured to receive a second reference voltage; a first one-shot circuit having an input coupled to the output of the second comparator; a delay circuit coupled between the output of the second comparator and the input of the first one-shot circuit; a second one-shot circuit having an input configured to receive a second signal, the second signal being an inverted version of the first signal; as well as a second logic circuit having a first input, a second input, and an output, wherein the first input of the second logic circuit is coupled to the output of the first one-shot circuit, the second input of the second logic circuit is coupled to the output of the second one-shot circuit, and the output of the second logic circuit is coupled to the first output of the zero-crossing detection circuit. 10 . The control circuit of claim 1 , wherein the zero-crossing detection circuit is configured to cause the first logic circuit to assert the first signal at a k-th valley occurring after the freewheeling signal is de-asserted, wherein k is a positive integer greater than 1.

11. The control circuit of claim 1 , wherein the first logic circuit comprises a flip-flop having a set input, a reset input, and an output, the set input being coupled to the first output of the zero-crossing detection circuit, the reset input being coupled to the output of the first comparator, the output of the flip-flop being coupled to the output terminal, wherein the flip-flop is configured to generate the first signal at the output of the flip-flop.

12. The control circuit of claim 1 , further comprising a current mirror configured to be coupled to the first current path terminal of the first transistor via an interface circuit, wherein the current mirror is configured to inject a first current into the first input of the first comparator based on a current flowing through the interface circuit.

13. The control circuit of claim 1, further comprising a sense resistor coupled between the first input of the first comparator and ground.

14. The control circuit of claim 1, wherein the control circuit is integrated into a single integrated circuit.

15. The control circuit of claim 1 , further comprising the first transistor and a gate driver having an input coupled to the output of the first logic circuit, wherein the first transistor is a power metal oxide semiconductor field effect transistor (MOSFET) having a gate coupled to an output of the gate driver.

16. A method for regulating an average output current flowing through an inductor, the method comprising: generating a demagnetization signal using an interface circuit, the interface circuit having an input coupled to a first intermediate node, the first intermediate node coupled between a current path of the power transistor and the inductor; generating a freewheeling signal indicating demagnetization of the inductor based on the demagnetization signal; generating a first signal based on the demagnetization signal; turning on the power transistor at a valley of the demagnetization signal that occurs after the freewheeling signal is de-asserted by using the first signal; receiving a sense voltage indicative of a current flowing through the current path of the power transistor; The first reference voltage is generated at the second intermediate node by: generating a first current using a first current generator coupled to the second intermediate node, the second intermediate node being coupled to a first capacitor and a first resistor; When the first signal or the freewheeling signal is asserted, closing a first switch coupled in series with the first resistor, and opening the first switch when the first signal and the freewheeling signal are de-asserted; as well as When the sense voltage becomes higher than the first reference voltage, the power transistor is turned off, wherein adjusting the average output current includes adjusting the average output current based on the first current.

17. The method according to claim 16, wherein generating the first reference voltage further comprises: A second current is subtracted from the first current to change the magnitude of the current flowing through the inductor. The method of claim 16 , wherein the average output current is proportional to the first current.

19. A switching converter comprising: a first power terminal configured to receive a first voltage; a second power terminal configured to receive a second voltage lower than the first voltage; a power transistor having a current path coupled between the first power terminal and the second power terminal; a sense resistor coupled between the current path of the power transistor and the second power terminal; an inductor coupled between the current path of the power transistor and the first power terminal; a freewheeling diode coupled between the inductor and the first power terminal; a driver having an output coupled to a control terminal of the power transistor; a flip-flop having a first output coupled to an input of the driver, wherein the flip-flop is configured to generate a first signal at the first output of the flip-flop; a zero-crossing detection circuit having a demagnetization sensing input coupled to the current path of the power transistor and the inductor, wherein the zero-crossing detection circuit is configured to: generating a freewheeling signal based on demagnetization of the inductor, and causing the trigger to assert the first signal based on the demagnetization sense input to turn on the power transistor; a first comparator having a first input, a second input, and an output, the first input of the first comparator being configured to receive a sense voltage indicative of a current flowing through the current path of the power transistor, the second input of the first comparator being configured to receive a first reference voltage, the output of the first comparator being configured to cause the flip-flop to deassert the first signal to turn off the power transistor when the sense voltage becomes higher than the first reference voltage; as well as a reference generator configured to generate the first reference voltage, the reference generator comprising: a first current generator configured to generate a first current, a first capacitor coupled to the output of the reference generator and the first current generator, a first resistor coupled to the output of the reference generator, and A first switch is coupled in series with the first resistor, the first switch being configured to be controlled based on the first signal and the freewheeling signal, wherein an average output current flowing through the inductor is proportional to the first current. 20 . The switching converter of claim 19 , further comprising a light emitting diode (LED) string coupled between the inductor and the first power terminal.

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