A display substrate and a display device

Abstract

The application provides a display substrate and a display device, relates to the technical field of display, and can improve the problem of green screen caused by static charge and improve the display effect. The display substrate comprises a display area and a non-display area connected with the display area, the non-display area comprises an edge area and a first dam area, and the first dam area is located between the display area and the edge area. The display substrate further comprises a substrate, an anti-static layer arranged on the substrate, the anti-static layer is located at least in the edge area, a driving unit and a touch unit arranged on the substrate, the driving unit is located in the display area, the touch unit is located in the display area and the non-display area and covers the driving unit, the anti-static layer and the touch unit are arranged in the same layer, or the anti-static layer is arranged on the side of the touch unit away from the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] When a user's finger continuously slides on an OLED (Organic Light-Emitting Diode) touch screen for a period of time, a large amount of static charges will be generated on the screen surface in contact with the finger. The OLED touch screen includes an insulating layer; the insulating layer contains a large number of organic polymer molecules, so that the static charges are aggregated and a polarization reaction is generated, and then part of the charges are conducted into a driving backplane, finally causing the characteristics of thin film transistors (TFTs) in the driving backplane to deviate, and a green phenomenon appears at the edge of the screen, thereby reducing the display effect. SUMMARY

[0003] Embodiments of the present application provide a display substrate and a display device, which can improve the problem of screen green caused by static charges, and thereby improve the display effect.

[0004] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0005] In one aspect, a display substrate is provided, comprising: a display area and a non-display area connected with the display area, the non-display area comprising an edge area and a first dam area, the first dam area being located between the display area and the edge area.

[0006] The display substrate further comprises:

[0007] a substrate;

[0008] an anti-static layer disposed on the substrate; the anti-static layer is located at least in the edge area;

[0009] a driving unit and a touch control unit disposed on the substrate; wherein the driving unit is located in the display area, and the touch control unit is located in the display area and the non-display area and covers the driving unit;

[0010] wherein the anti-static layer and the touch control unit are disposed in the same layer, or the anti-static layer is disposed on a side of the touch control unit away from the substrate.

[0011] Optionally, the touch control unit comprises a first touch control layer, a first insulating layer, a second touch control layer and a second insulating layer which are sequentially stacked on the driving unit; the first touch control layer and the second touch control layer are both located in the display area, and the first insulating layer and the second insulating layer are located in the display area and the non-display area.

[0012] The first touch control layer and the second touch control layer are a metal grid electrode layer and a bridge metal layer.

[0013] Optionally, the anti-static layer is arranged in the same layer as the first touch control layer.

[0014] Optionally, the anti-static layer is arranged in the same layer as the second touch control layer.

[0015] Optionally, the second insulating layer covers the first insulating layer, and a boundary of the second insulating layer is farther away from the first dam area than a boundary of the first insulating layer.

[0016] The second insulating layer located in the non-display area is arranged on a side of the anti-static layer away from the substrate.

[0017] Optionally, a projection of the anti-static layer on the substrate partially overlaps a projection of the second insulating layer on the substrate.

[0018] Optionally, a projection of the anti-static layer on the substrate is located within a projection of the second insulating layer on the substrate.

[0019] Optionally, when the anti-static layer is arranged on a side of the touch control unit away from the substrate, the second insulating layer located in the non-display area is arranged on a side of the anti-static layer close to the substrate.

[0020] Optionally, the first dam area is arranged around the display area, and the edge area is arranged around the first dam area.

[0021] Optionally, the edge area includes a cutting transition area, a crack dam area, and a driving circuit area; the crack dam area is arranged around the first dam area and is disconnected in the driving circuit area; and the cutting transition area is arranged around the crack dam area and the driving circuit area.

[0022] The crack dam area includes at least one groove, the groove is arranged around the first dam area and is disconnected in the driving circuit area; and the anti-static layer covers at least part of the groove.

[0023] Optionally, the display substrate further includes: a buffer layer, a gate insulating layer, and an interlayer dielectric layer arranged in sequence; the interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the display area, the first dam area, and the crack dam area.

[0024] The groove at least penetrates part of the interlayer dielectric layer located in the crack dam area.

[0025] Optionally, the display substrate further comprises a first flat portion and a first protrusion, the first flat portion is located in the cutting transition area and the crack dam area; the first protrusion is located in the crack dam area, is arranged around the first dam area, and is disconnected in the driving circuit area;

[0026] The first flat portion covers all the grooves, the first protrusion is arranged on the side of the first flat portion away from the substrate, and the anti-static layer covers the first protrusion.

[0027] Optionally, edges of the whole formed by the interlayer dielectric layer, the gate insulating layer and the buffer layer close to the cutting transition area have at least one step; the first flat portion covers all the steps.

[0028] Optionally, the edge area further comprises a crack detection area, the crack detection area is located between the first dam area and the crack dam area.

[0029] The crack detection area comprises a plurality of crack detection lines, and the anti-static layer covers all the crack detection lines and all the grooves.

[0030] Optionally, the anti-static layer is also located in the first dam area.

[0031] The non-display area further comprises a wiring area, the wiring area is located between the first dam area and the display area.

[0032] The display substrate further comprises a power signal line, the power signal line is located in the wiring area and the first dam area; the power signal line and the anti-static layer partially overlap in a direction perpendicular to the substrate.

[0033] Optionally, the interlayer dielectric layer, the gate insulating layer and the buffer layer are all located in the wiring area and the crack detection area.

[0034] The first dam area comprises at least one first dam, the first dam is arranged on the side of the interlayer dielectric layer away from the substrate; the first dam comprises a second protrusion, a second flat portion and a third flat portion arranged in sequence; the second flat portion covers the second protrusion, and the third flat portion covers the second flat portion.

[0035] The second protrusion and the first flat portion are arranged in the same layer, and the second flat portion and the first protrusion are arranged in the same layer.

[0036] Optionally, the first dam region further comprises a jumper and a third protrusion, the third protrusion is arranged on the side of the first dam closest to the cutting transition region and close to the crack dam region, the jumper is arranged on the side of the interlayer dielectric layer away from the substrate, and the third protrusion covers the jumper, and the third protrusion, the second protrusion and the first flat portion are arranged in the same layer.

[0037] Optionally, the power signal line comprises at least a first power line, the first power line is arranged on the side of the interlayer dielectric layer away from the substrate; and the first dam is arranged on the side of the first power line away from the substrate.

[0038] The first power line and the jumper are arranged in the same layer and disconnected with each other, and the third protrusion further covers the edge of the first power line close to the cutting transition region.

[0039] The first power line and the anti-static layer partially overlap in the direction perpendicular to the substrate.

[0040] Optionally, the power signal line further comprises a second power line and a third power line; the third power line is arranged on the side of the second power line away from the substrate.

[0041] The edge of the second power line close to the cutting transition region is arranged between the second protrusion and the second flat portion in the first dam closest to the cutting transition region, and the edge of the third power line close to the cutting transition region is arranged between the second flat portion and the third flat portion in the first dam closest to the cutting transition region.

[0042] Optionally, the display substrate further comprises a plurality of light emitting units arranged in an array; the light emitting units are located in the display region and arranged between the driving units and the touch units.

[0043] The light emitting unit comprises a first electrode, a light emitting functional layer and a second electrode; the second electrode is arranged on the side of the light emitting functional layer away from the driving unit.

[0044] The driving unit comprises a plurality of transistors arranged in an array, a first flat film, a plurality of transfer electrodes and a second flat film, wherein the first flat film covers the transistors, the transfer electrodes are arranged between the first flat film and the second flat film and electrically connected with the transistors; the first electrode is arranged on the side of the second flat film away from the substrate and electrically connected with the transfer electrodes.

[0045] The first power supply line is arranged in the same layer as the source / drain electrode of the transistor, the second power supply line is arranged in the same layer as the transfer electrode, and the third power supply line is arranged in the same layer as the first electrode.

[0046] Optionally, the edge region comprises an opening region and a transition region; the transition region is arranged around the opening region, and the first dam region is arranged around the transition region.

[0047] The anti-static layer is located at least in the transition region.

[0048] Optionally, the transition region comprises at least one second dam, the second dam is arranged on the side of the anti-static layer close to the substrate and at least partially overlaps the anti-static layer in the direction perpendicular to the substrate.

[0049] Optionally, the first dam region comprises at least one third dam, the third dam is arranged in the same layer as the second dam.

[0050] The anti-static layer does not overlap the third dam in the direction perpendicular to the substrate.

[0051] Optionally, the transition region further comprises a barrier wall, the barrier wall is located between the second dam and the third dam and is arranged around the second dam.

[0052] Optionally, the non-display region further comprises an isolation region, the isolation region is located between the first dam region and the display region and is arranged around the first dam region.

[0053] The isolation region comprises an isolation column, and the isolation column is arranged around the first dam region.

[0054] Optionally, the non-display region further comprises a wiring region, the wiring region is located between the isolation region and the display region and is arranged around the isolation region.

[0055] The wiring region comprises a plurality of wirings, and the wirings of the wiring region are electrically connected to the corresponding wirings of the display region.

[0056] Optionally, the display substrate further comprises: a buffer layer, a gate insulating layer and an interlayer dielectric layer arranged in sequence; the interlayer dielectric layer, the gate insulating layer and the buffer layer are all located in the display region, the wiring region, the isolation region, the first dam region and the transition region.

[0057] The second dam, the third dam and the isolation column are all arranged on the side of the interlayer dielectric layer away from the substrate.

[0058] Optionally, the display substrate further comprises a packaging unit and a plurality of light-emitting units arranged in an array; the packaging unit covers the light-emitting units and is arranged between the light-emitting units and the touch unit; the packaging unit is located in the non-display area and the display area, and the light-emitting units are located in the display area.

[0059] The packaging layer comprises a first inorganic packaging layer, an organic packaging layer and a second inorganic packaging layer arranged in sequence; the first inorganic packaging layer and the second inorganic packaging layer are configured to package the first dam area and the light-emitting unit; and the organic packaging layer is configured to package the light-emitting unit and is disconnected at the first dam area.

[0060] In another aspect, the embodiments of the present application also provide a display device comprising the display substrate described above.

[0061] Optionally, the display device further comprises a packaging substrate, and the packaging substrate and the display substrate are fixed together through an adhesive layer.

[0062] In the display substrate provided by the embodiments of the present application, the electrostatic charge generated by the friction of a finger on the surface of the screen is blocked and released by the anti-static layer, so that the charge conducted through the non-display area to the driving unit is greatly reduced, the probability of characteristic shift of the transistor of the driving unit is greatly reduced, the problem of green light in the edge area is finally improved, and the display effect is improved.

[0063] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0065] Figure 1 The structure schematic diagram of a display device provided by the embodiments of the present application is shown in the figure;

[0066] Figure 2a And Figure 2b The top view of two display substrates provided by the embodiments of the present application is shown in the figure;

[0067] Figure 3 AndFigure 4 Two cross-sectional views along the EE direction Figure 2b Two cross-sectional views along the EE direction

[0068] Figure 5 Two cross-sectional views along the EE direction Figure 6 Two cross-sectional views along the EE direction

[0069] Figure 7 Two cross-sectional views along the EE direction

[0070] Figures 8-12 Two cross-sectional views along the EE direction

[0071] Figure 13a Two cross-sectional views along the EE direction Figures 14-16 Two cross-sectional views along the EE direction Figure 2a Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0072] Two cross-sectional views along the EE direction Figure 13b Two cross-sectional views along the EE direction Figure 13a Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0073] Two cross-sectional views along the EE direction Figure 17 Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0074] Two cross-sectional views along the EE direction Figure 18 Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0075] Two cross-sectional views along the EE direction Figure 19 Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0076] Two cross-sectional views along the EE direction Figure 20 Two cross-sectional views along the EE direction Figure 21 Two cross-sectional views along the EE direction Figure 2a Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0077] Two cross-sectional views along the EE direction Figures 22-25 Two cross-sectional views along the EE direction Figure 2a Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0078] Two cross-sectional views along the EE direction Figure 26 Two cross-sectional views along the EE direction Two cross-sectional views along the EE direction

[0079] Two cross-sectional views along the EE direction Figure 27 Two cross-sectional views along the EE direction DETAILED DESCRIPTION

[0080] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0081] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", etc., only for clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0082] In the embodiments of the present application, the meaning of "multiple" is two or more than two, and the meaning of "at least one" is one or more than one, unless otherwise explicitly and specifically limited.

[0083] In the embodiments of the present application, the positions or location relationships indicated by the terms "upper", "lower", etc. are based on the positions or location relationships shown in the drawings, only for the convenience of describing the present application and simplifying the description, and are not indicative or implied that the indicated devices or elements must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application.

[0084] Reference Figure 1 As shown, when a user's finger continuously slides on the OLED touch screen for a period of time, a large amount of static charges 11 will be generated on the screen surface in contact with the finger. Since the glass cover plate 12, the OCA (Optically Clear Adhesive) layer 13 and the POL (Polarize) layer 14 contain a large number of organic polymer molecules, the static charges are aggregated and polarized, and then the charges are conducted along Figure 1 the direction (indicated by a dashed line with an arrow) shown in the figure, through the touch layer 15, the second CVD layer 16, the IJP (Ink Jet Printing) layer 17, the first CVD layer 18, and then to the driving back plate 11. When the charges 11 are conducted along the direction shown in the figure to the CTD layer 19, a part of the charges are released through the CTD layer; another part of the charges are conducted from the edge of the CTD layer 19 to the driving back plate 10, and finally cause the characteristics of the TFT (Thin Film Transistor) 20 of the driving back plate 10 to deviate, and a green phenomenon appears at the edge of the screen, thereby reducing the display effect. Figure 1 When the charges 11 are conducted along the direction shown in the figure to the CTD layer 19, a part of the charges are released through the CTD layer; another part of the charges are conducted from the edge of the CTD layer 19 to the driving back plate 10, and finally cause the characteristics of the TFT (Thin Film Transistor) 20 of the driving back plate 10 to deviate, and a green phenomenon appears at the edge of the screen, thereby reducing the display effect. Figure 1 In the figure, the organic light-emitting layer (EL) layer is marked as 21.

[0085] Based on the above, the embodiment of the present application provides a display substrate, comprising: a display area and a non-display area connected with the display area, the non-display area comprising an edge area and a first dam area, the first dam area being located between the display area and the edge area.

[0086] The display area refers to an area for realizing display, and the non-display area is generally used for arranging driving wires and driving circuits, such as a GOA (Gate Driver on Array, array substrate row driving) driving circuit or for arranging an in-screen camera, an earpiece or a loudspeaker and the like. The non-display area can only include one area. For example, the non-display area can only include an A0 area as shown in Figure 2a The A0 area comprises an edge area A3 area and a first dam area A2 area, the first dam area A2 area surrounds the display area A1, and the edge area A3 area surrounds the first dam area A2. Alternatively, the non-display area can also only include a B0 area as shown in Figure 2a The B0 area comprises an edge area B6 area and a first dam area B2 area, the edge area B6 area comprises an opening area B1 area and a transition area B3 area, the transition area B3 area surrounds the opening area B1 area, and the first dam area B2 area surrounds the transition area B3 area. Of course, the non-display area can also simultaneously include two independent areas. For example, the non-display area can simultaneously include A0 and B0 areas as shown in Figure 2a The present application does not make any limitation on this. It should be noted that, for the sake of subsequent clear description, the A0 area can be referred to as a first non-display area, and the B0 area can be referred to as a second non-display area.

[0087] The first dam area can comprise at least one dam (also referred to as DAM), which is used to solve the problem of water and oxygen invasion caused by ink overflow when an organic encapsulation layer is formed by inkjet printing. The number of the dam is not limited. Figure 2a For example, the first dam area A2 area in the first non-display area A0 area comprises two dams (38a and 38) as shown in Figure 2a The dam can be arranged around the display area in one circle as shown in Figure 2a The dam can comprise one layer or multiple layers of structures, which are not limited herein.

[0088] In combination with Figure 2b , Figure 3 and Figure 4 The display substrate further comprises:

[0089] A substrate 101; the material of the substrate is not limited, for example, it can be a rigid material such as glass, or a flexible material such as PI (polyimide).

[0090] The anti-static layer 1 is arranged on the substrate 101; the anti-static layer 1 is at least located in the edge area A3 of the first non-display area A0. Figure 3 And Figure 4 the A3 area in the first non-display area A0.

[0091] The driving unit 3 and the touch unit 2 are arranged on the substrate 101; the driving unit 3 is located in the display area A1, the touch unit 2 is located in the display area A1 and the non-display area (the first non-display area A0 in Figure 3 And Figure 4 the first non-display area A0), and covers the driving unit 3.

[0092] As shown in Figure 4 , the anti-static layer 1 and the touch unit 2 are arranged in the same layer, or as shown in Figure 3 , the anti-static layer 1 is arranged on the side of the touch unit 2 away from the substrate 101.

[0093] It should be noted that Figure 3 And Figure 4 the anti-static layer 1 is arranged in the edge area A3 of the first non-display area A0. The anti-static layer 1 can be a ring-shaped metal layer as shown in Figure 2b , and the ring shape can be a circular ring, a rectangular ring, or an irregular ring, which is not limited here. The material of the anti-static layer can include metal or metal oxide. For example, the material of the anti-static layer can include silver, molybdenum, aluminum, or titanium, or can also include ITO (Indium Tin Oxide, Indium Tin Oxide) and other metal oxides.

[0094] As shown in Figure 3 And Figure 4 , the display substrate can further include a plurality of light emitting units 1d arranged in an array; the light emitting unit 1d is located in the display area A1 and is arranged between the driving unit 3 and the touch unit 2. The above-mentioned driving unit can include a plurality of driving circuits, and each driving circuit is used to provide a driving current to the corresponding light emitting unit to make the light emitting unit emit light. As shown in Figure 3 And Figure 4 , the driving circuit can include at least one transistor 22, which can be a polysilicon transistor, such as an LTPS (Low Temperature Poly-silicon, Low Temperature Poly-silicon) transistor, or an oxide transistor, such as an IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) transistor, which is not limited here.

[0095] The structure of the above-mentioned touch unit is not limited, for example, the touch unit can adopt a mutual capacitance touch structure or a self-capacitance touch structure. The mutual capacitance touch structure or the self-capacitance touch structure can be obtained according to related technologies, which will not be described in detail here.

[0096] The aforementioned single-layer setup refers to a process using a single patterning process. A single patterning process refers to the process of forming the required layer structure through a single exposure. A single patterning process includes processes such as masking, exposure, development, etching, and stripping.

[0097] The aforementioned antistatic layer can be disposed on the same layer as the touch unit. In this way, the antistatic layer can be formed at the same time as the touch unit, which can reduce the number of patterning processes and reduce costs. Alternatively, the antistatic layer can also be disposed on the side of the touch unit away from the substrate. That is, the touch unit can be formed first and then the antistatic layer can be formed. This can prevent the edge film layer of the touch unit from bulging, thereby preventing it from peeling and improving the performance of the display substrate.

[0098] In the display substrate provided in this application embodiment, an anti-static layer is provided to block and release the electrostatic charge generated by friction between fingers and the screen surface, thereby significantly reducing the charge conducted to the driving unit through the non-display area. This significantly reduces the probability of transistor characteristic shift in the driving unit, ultimately improving the green tint problem at the edges and enhancing the display effect. Figure 3 and Figure 4 The structure shown is used as an example for detailed explanation. (Refer to...) Figure 3 and Figure 4 As shown, when the static charge 11 generated by the friction of the finger on the screen surface is conducted to the antistatic layer 1, the antistatic layer 1 can block and release the charge, thereby greatly reducing the charge conducted to the driving unit through the non-display area, and thus greatly reducing the probability of the transistor of the driving unit experiencing characteristic deviation, ultimately improving the display effect.

[0099] In one or more embodiments, reference is made to Figure 5 and Figure 6 As shown, the touch unit 2 includes a first touch layer 25, a first insulating layer 26, a second touch layer 27, and a second insulating layer 28 stacked sequentially on the driving unit; the first touch layer 25 and the second touch layer 27 are both located in the display area, and the first insulating layer 26 and the second insulating layer 28 are located in the display area and the non-display area; wherein, one of the first touch layer and the second touch layer is a metal mesh electrode layer, and the other is a bridging metal layer.

[0100] The first touch layer can be a metal mesh electrode layer, and the second touch layer can be a bridging metal layer; alternatively, the first touch layer can be a bridging metal layer, and the second touch layer can be a metal mesh electrode layer. The latter is preferable to achieve better touch performance.

[0101] refer to Figure 7As shown, the metal mesh electrode layer 24 can include driving electrodes (TX electrodes) 241 and sensing electrodes (RX electrodes) 242, each column of driving electrodes 241 is directly connected and electrically connected with the touch driving unit 23 through a TX line; each row of sensing electrodes 242 is electrically connected with the bridge metal layer through a via hole penetrating the first insulating layer, and is electrically connected with the touch driving unit 23 through an RX line. Wherein, the metal mesh electrode layer 24 can be located in the display area, and the TX line, the RX line and the touch driving unit can be located in the non-display area. The structure of the touch unit belongs to FMLOC (Flexible Multi-Layer On Cell, flexible multi-layer structure) touch structure, which can reduce the thickness of the screen, thereby facilitating folding; at the same time, there is no fitting tolerance, which can reduce the width of the frame; in addition, it can also reduce the risk of crack.

[0102] The material of the first insulating layer and the second insulating layer can be any one of silicon nitride, silicon oxide or silicon oxynitride.

[0103] In order to better form the first touch layer, the touch unit can further include an isolation layer 29 as shown in Figure 5 and Figure 6 , which is arranged on the side of the first touch layer 25 away from the first insulating layer 26.

[0104] Optionally, in order to simplify the process and reduce the difficulty of manufacturing, when the anti-static layer and the touch unit are arranged in the same layer, referring to Figure 6 , the anti-static layer 1 and the first touch layer 25 are arranged in the same layer, that is, the anti-static layer and the first touch layer can be formed at the same time through one patterning process.

[0105] Alternatively, when the anti-static layer and the touch unit are arranged in the same layer, referring to Figure 5 , the anti-static layer 1 and the second touch layer 27 are arranged in the same layer, that is, the anti-static layer and the second touch layer can be formed at the same time through one patterning process.

[0106] Further optionally, referring to Figures 8-11 , the second insulating layer 28 covers the first insulating layer 27, and the boundary of the second insulating layer 28 is farther away from the first dam area than the boundary of the first insulating layer 27; the second insulating layer 28 located in the non-display area is arranged on the side of the anti-static layer 1 away from the substrate 101.

[0107] Optionally, referring to Figure 8 , Figure 9 , Figure 11 , the orthographic projection S1 of the anti-static layer 1 on the substrate 101 partially overlaps with the orthographic projection S2 of the second insulating layer 28 on the substrate 101; or, referring to Figure 10As shown, the orthographic projection S1 of the antistatic layer 1 on the substrate 101 is located within the orthographic projection S2 of the second insulating layer 28 on the substrate 101.

[0108] The distance between the edge of the antistatic layer furthest from the display area and the edge of the edge area furthest from the display area is not limited. For example, see reference. Figure 8 , Figure 10 , Figure 11 As shown, a certain distance D can exist between the edge of the antistatic layer away from the display area and the edge of the edge area away from the display area. The size of this distance is not limited, for example: Figure 8 and Figure 11 D in the figure can be 50 μm. Figure 10 D in the figure can be 80 μm; or, refer to Figure 9 As shown, the edge of the antistatic layer away from the display area roughly coincides with the edge of the edge area away from the display area. "Roughly coincident" here includes both actual coincidence and coincidence within the range of manufacturing tolerances.

[0109] Figure 9 In the structure shown, the antistatic layer has a large area, which allows it to absorb and release static charge more quickly and effectively.

[0110] Optionally, if the antistatic layer is disposed on the side of the touch unit away from the substrate, refer to Figure 12 As shown, the second insulating layer 28 located in the non-display area is disposed on the side of the antistatic layer 1 near the substrate 101.

[0111] It should be noted that, Figures 7-12 Only the positional relationship between the first insulating layer, the second insulating layer, and the antistatic layer is shown; other structures are not shown.

[0112] The structure when the anti-static layer is set in the first non-display area A0 is described in detail below.

[0113] In one or more embodiments, reference is made to Figure 2a As shown, within the first non-display area A0, the first dam area A2 surrounds the display area A1, and the edge area A3 surrounds the first dam area A2.

[0114] refer to Figure 2a As shown, within the first non-display area A0, the edge area A3 includes a cutting transition area A4, a crack dam area A5, and a driving circuit area A6; the crack dam area A5 surrounds the first dam area A2 and is disconnected in the driving circuit area A6; the cutting transition area A4 surrounds the crack dam area A5 and the driving circuit area A6.

[0115] Combination Figure 2a and Figure 13a , Figures 14-16The cracked dam area A5 includes at least one groove 33, which is arranged around the first dam area A2 and disconnected in the drive circuit area A6; the antistatic layer 1 covers at least part of the groove.

[0116] The number of the aforementioned grooves is not limited. Figure 13a , Figures 14-16 The illustration uses five consecutively spaced grooves as an example. These grooves reduce and disperse the stress generated during cutting, thereby lowering the risk of cracks. Therefore, these grooves can also be called crack dams. The depth of these grooves perpendicular to the substrate is not limited and can be determined based on the specific circumstances.

[0117] It should be noted that if the driving circuit area A6 adopts a pad bending structure (that is, bending the pad area to the non-display surface of the substrate), the break position of the groove corresponds to the lead area (fanout area) on the bending area; if the driving circuit area A6 adopts a non-pad bending structure, the break position of the groove corresponds to the pad area (bonding area).

[0118] Optional, see reference Figure 13a , Figures 14-16 As shown, the display substrate also includes: a buffer layer 102, a gate insulating layer 100 and an interlayer dielectric layer 103 stacked sequentially; the interlayer dielectric layer 103, the gate insulating layer 100 and the buffer layer 102 are all located in the display area, the first dam area and the crack dam area; the groove 33 at least penetrates the portion of the interlayer dielectric layer 103 located in the crack dam area A5.

[0119] It should be noted that groove 33 can be as follows: Figure 13a , Figures 14-16 The groove can be shown to penetrate only the portion of the interlayer dielectric layer 103 located in the crack dam region A5; or, the groove can also penetrate the portions of both the interlayer dielectric layer and the grid insulation layer located in the crack dam region; or, the groove can also penetrate the portions of the interlayer dielectric layer, the grid insulation layer, and the buffer layer located in the crack dam region, which is not limited here.

[0120] In addition, the display substrate may also include: an isolation layer located between the substrate and the buffer layer, the isolation layer being located in the display area, the first dam area and the crack dam area; the aforementioned groove may also penetrate the portions of the interlayer dielectric layer, the gate insulating layer, the buffer layer and the isolation layer located in the crack dam area.

[0121] Optional, see reference Figure 13a , Figures 14-16 As shown, the display substrate further includes: a first flat portion 41 and a first protrusion 34, wherein the first flat portion 41 is located in the cutting transition region A4 and the crack dam region A5; Reference Figure 2aAs shown, the first protrusion 34 is located in the cracked dam area A5, is arranged around the first dam area A2, and is disconnected in the drive circuit area A6.

[0122] refer to Figure 13a , Figures 14-16 As shown, the first flat portion 41 covers all the grooves 33, the first protrusion 34 is disposed on the side of the first flat portion 41 away from the substrate 101, and the antistatic layer 1 covers the first protrusion 34.

[0123] It should be noted that if the driving circuit area A6 adopts a pad bending structure (that is, bending the pad area to the non-display surface of the substrate), the break position of the first protrusion corresponds to the lead area (fanout area) on the bending area; if the driving circuit area A6 adopts a non-pad bending structure, the break position of the first protrusion corresponds to the pad area (bonding area).

[0124] The aforementioned first flat portion covers and fills all the grooves, which can further reduce the risk of cracks generated during cutting, and at the same time facilitate the deposition of the antistatic layer.

[0125] refer to Figure 13a , Figures 14-16 As shown, the integral formed by the interlayer dielectric layer 103, the gate insulating layer 100, and the buffer layer 102 has at least one step 35 near the edge of the cutting transition region A4; the first flat portion 41 covers all steps 35.

[0126] The aforementioned interlayer dielectric layer, grid insulating layer, and buffer layer are mostly made of inorganic materials. When patterned using a dry engraving process, residues are easily generated, forming the aforementioned steps. The aforementioned first flat portion covers all steps, which can provide better protection.

[0127] Optional, see reference Figure 13a , Figures 14-16 As shown, the edge region also includes crack detection zone A7, which is located between the first dam zone A2 and the cracked dam zone A5; Reference Figure 13a , Figures 14-15 As shown, the crack detection area A7 includes multiple crack detection lines 36, and the antistatic layer 1 covers all crack detection lines 36 and all grooves 33.

[0128] The number of crack detection lines mentioned above is not limited. Figure 13a , Figures 14-16 The illustration is based on four examples.

[0129] The aforementioned crack detection area is mainly used for crack detection to improve product yield and reduce production costs.

[0130] It should be noted that the reference Figure 16As shown, the anti-static layer 1 can also only cover part of the groove 33 and does not cover the crack detection line 36.

[0131] Optionally, as shown in Figure 13a , Figures 14-15 As shown, the anti-static layer 1 is also located in the first dam area A2 area; as shown in Figure 2a The non-display area further includes a wiring area A8 area located between the first dam area A2 area and the display area A1 area.

[0132] As shown in Figure 13a , Figures 14-15 The display substrate further includes: a power signal line 37, the power signal line 37 is located in the wiring area A8 area and the first dam area A2 area; as shown in Figure 13a , Figures 14-15 The power signal line 37 and the anti-static layer 1 partially overlap in the direction perpendicular to the substrate 101; then, the static electricity generated by the friction of the fingers on the screen surface can be absorbed and released by the power signal line and the anti-static layer respectively, and the power signal line and the anti-static layer partially overlap in the direction perpendicular to the substrate, which can further ensure the effect of absorbing and releasing static electricity.

[0133] It should be noted that, as shown in Figure 16 If the anti-static layer 1 is only located in the cutting transition area A4 area and the crack dam area A5 area, the anti-static layer 1 and the power signal line 37 do not overlap in the direction perpendicular to the substrate 101.

[0134] The above-mentioned wiring area A8 area can be used to set signal lines such as power signal line ELVSS. The display substrate can adopt a 7T1C driving circuit as shown in Figure 17 The driving principle of the circuit can be obtained by referring to related technologies, which will not be described here), which includes a total of 7 thin film transistors T1-T7, a capacitor C1 and an oled light emitting diode; Except for the driving transistor T3, the rest of the tubes are controlled by different driving signals, such as: ELVSS power signal, Vdata signal, gate signal, EM signal, Vinit signal, ELVDD signal, reset signal; And these driving signals are provided by the corresponding driving signal lines. The ELVSS power signal line, the Vinit signal line and the like can be set as shown in Figure 18 The ELVSS power signal line can be electrically connected to the cathode located in the display area through a via, and the cathode in the display area is generally set in a whole layer. Here, the number of layers included by the ELVSS power signal line is not limited, for example, it can include two layers (belonging to single SD structure); Or three layers (belonging to double SD structure), for example Figure 13a , Figures 14-15The first power line 371, the second power line 372, and the third power line 373 shown are provided in the following ways: the third power line 373 can be disposed on the same layer as the first electrode (used as an anode) located in the display area to prevent the circuit below from being interfered with by light or electrostatic discharge; the first power line 371 can be disposed on the same layer as the source and drain of the transistor located in the display area; and the second power line 372 can be disposed on the same layer as the transition electrode located in the display area.

[0135] Optional, see reference Figure 13a , Figures 14-16 As shown, the interlayer dielectric layer 103, the gate insulating layer 100, and the buffer layer 102 are all located in the wiring area. Figure 13a , Figures 14-16 (Not shown) and crack detection area A7.

[0136] The first dam area A2 includes at least one first dam 38, which is disposed on the side of the interlayer dielectric layer 103 away from the substrate 101. The first dam 38 includes a second protrusion 381, a second flat portion 382 and a third flat portion 383 arranged sequentially. The second flat portion 382 covers the second protrusion 381 and the third flat portion 383 covers the second flat portion 382.

[0137] The second protrusion 381 and the first flat portion 41 are disposed on the same layer, and the second flat portion 382 and the first protrusion 34 are disposed on the same layer.

[0138] There is no limit to the number of first-level dikes here. For example, to improve ink spill prevention, two first-level dikes can be used. The structure of two first-level dikes can be referenced. Figure 19 As shown, the substrate includes two first dams, labeled 38a and 38, respectively. The height of the first dam 38a near the wiring area A8 in a direction perpendicular to the substrate 101 is lower than the height of the first dam 38 away from the wiring area A8 in a direction perpendicular to the substrate 101. The first dam 38a near the wiring area A8 blocks the organic encapsulation layer 118b.

[0139] Optional, see reference Figure 13a , Figures 14-16 As shown, the first dam area A7 also includes a jumper 39 and a third protrusion 40. The third protrusion 40 is disposed on the side of the first dam 38 closest to the cut transition area A4, near the crack dam area A5. The jumper 39 is disposed on the side of the interlayer dielectric layer 103 away from the substrate 101. The third protrusion 40 covers the jumper 39. The third protrusion 40, the second protrusion 381, and the first flat portion 41 are disposed in the same layer.

[0140] The jumpers mentioned above can discharge static electricity and reduce its impact on the signal lines.

[0141] Optional, see reference Figure 13a ,Figures 14-16 As shown, the power signal line 37 includes at least a first power line 371, which is disposed on the side of the interlayer dielectric layer 103 away from the substrate 101; a first dam 38 is disposed on the side of the first power line 371 away from the substrate 101. The first power line 371 and the jumper 39 are disposed in the same layer and disconnected from each other, and the third protrusion 40 also covers the edge of the first power line 371 near the cutting transition region A4.

[0142] refer to Figure 13a , Figure 13b , Figure 14 , Figure 15 As shown, the first power line 371 and the antistatic layer 1 partially overlap in a direction perpendicular to the substrate 101. Figure 13b Cutting along the cutting line can form Figure 13a The structure shown. Figure 13b This is a top view of the substrate. (Reference) Figure 13b As shown, the antistatic layer 1 extends 50 μm beyond the cutting line along the C1C2 direction. Therefore, after cutting, the antistatic layer roughly coincides with the edge of the edge region. The width of the cut antistatic layer along the C1C2 direction is 335 μm, and the width of the portion where the first power line 371 overlaps with the antistatic layer 1 in a direction perpendicular to the substrate is 5 μm. Of course, the width of the antistatic layer along the C1C2 direction and the width of the overlapping portion of the antistatic layer and the first power line along the C1C2 direction can be selected according to the actual design. Here, only the above width values ​​are used as an example for explanation. Figure 13a The relative positional relationship between the first power line and the antistatic layer is explained in the corresponding uncut structure. Figures 14-16 The situation is similar, so I won't go into details here.

[0143] The aforementioned first power line can be disposed on the same layer as the source and drain terminals of the transistor located in the display area. The aforementioned first power line and the anti-static layer can simultaneously absorb and release static charges, further mitigating the adverse effects of static charges.

[0144] Optional, see reference Figure 13a , Figure 13b , Figures 14-16 As shown, the power signal line 37 also includes a second power line 372 and a third power line 373; the third power line 373 is disposed on the side of the second power line 372 away from the substrate 101.

[0145] The second power line 372 is positioned between the second protrusion 381 and the second flat portion 382 in the first dam 38 closest to the cutting transition zone A4, and the third power line 373 is positioned between the second flat portion 382 and the third flat portion 383 in the first dam 38 closest to the cutting transition zone A4, near the edge of the cutting transition zone A4.

[0146] Figure 13a , Figures 14-16 In this configuration, the power signal line 37 includes a first power line 371, a second power line 372, and a third power line 373, forming a dual SD structure. The third power line 373 can be disposed on the same layer as the first electrode (used as the anode) located in the display area to prevent interference from light or electrostatic discharge to the circuitry below. The first power line 371 can be disposed on the same layer as the source and drain electrodes of the transistor located in the display area. The second power line 372 can be disposed on the same layer as the transition electrode located in the display area. The power signal line can be electrically connected to the cathode located in the display area via a via.

[0147] In one or more embodiments, reference is made to Figure 3 and Figure 4 As shown, the display substrate may also include multiple light-emitting units 1d arranged in an array; the light-emitting units 1d are located in the display area A1 and are disposed between the driving unit 3 and the touch unit 2.

[0148] refer to Figure 20 and Figure 21 As shown, the light-emitting unit 1d includes a first electrode 112, a light-emitting functional layer 114a, and a second electrode 115; the second electrode 115 is disposed on the side of the light-emitting functional layer 114a away from the driving unit.

[0149] refer to Figure 21 As shown, the driving unit includes multiple transistors T arranged in an array, multiple transition electrodes 133, and a planarization layer 116. The planarization layer 116 includes a first planarization film 116a and a second planarization film 116b. The first planarization film 116a covers the transistors T. The transition electrodes 133 are disposed between the first planarization film 116a and the second planarization film 116b and are electrically connected to the transistors T. The first electrode 112 is disposed on the side of the second planarization film 116b away from the substrate 101 and is electrically connected to the transition electrodes 133.

[0150] In this configuration, the first power line is disposed on the same layer as the source and drain of the transistor; the second power line is disposed on the same layer as the transition electrode; the third power line is disposed on the same layer as the first electrode; the first planarization film, the first planar portion, the second protrusion, and the third protrusion are disposed on the same layer; and the second planarization film, the second planar portion, and the first protrusion are disposed on the same layer.

[0151] Figure 20 and Figure 21In the embodiment, the transistor T includes a first electrode 110, a second electrode 111, a control electrode 106, and an active layer 104, wherein either of the first electrode 110 and the second electrode 111 is used as a source electrode, and the other is used as a drain electrode, and the control electrode 106 can be used as a gate electrode. Here, the type of the transistor is not limited, and can be a top-gate thin film transistor or a bottom-gate thin film transistor. The transistor can be classified into two types according to the positional relationship of the three electrodes. One type is that the gate electrode is located below the source electrode and the drain electrode, and this type is referred to as a bottom-gate transistor. The other type is that the gate electrode is located above the source electrode and the drain electrode, and this type is referred to as a top-gate transistor. Figure 20 and Figure 21 The top-gate type is taken as an example for illustration. Here, the material of the active layer is not limited, and can be an oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide), and the like. The material of the active layer can also be LTPS (Low Temperature Poly-silicon), or a single crystal silicon material.

[0152] Referring to FIG. 1, the substrate can further include a first gate insulating sub-layer 105, a second gate insulating sub-layer 108, an interlayer dielectric layer 103, a passivation layer 134, and a capacitor unit. Figure 20 and Figure 21 The capacitor unit can include a first electrode plate 130 and a second electrode plate 131. The first electrode plate 130 is arranged in the same layer as the gate electrode 106. The second electrode plate 131 is arranged between the second gate insulating layer 108 and the interlayer dielectric layer 103, and is arranged opposite to the first electrode plate 130.

[0153] It should be noted that if the capacitor unit is not arranged, only one gate insulating sub-layer needs to be arranged. The first gate insulating sub-layer and the second gate insulating sub-layer can also be arranged in a non-display area to form a gate insulating layer.

[0154] The materials of the gate electrode and the first electrode plate and the second electrode plate can include a metal material or an alloy material, such as molybdenum, aluminum, titanium, or the like. The materials of the first electrode and the second electrode can include a metal material or an alloy material, such as a single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, or the like. For example, the multi-layer structure is a multi-metal layer stack, such as a three-layer metal stack of titanium, aluminum, and titanium (Al / Ti / Al), or the like. The planarization layer is usually made of an organic material, such as a photoresist, an acrylic-based polymer, a silicon-based polymer, or the like.

[0155] The first electrode described above can be used as the anode, which can be made of materials such as ITO (indium tin oxide), indium zinc oxide (IZO), or zinc oxide (ZnO); (See reference) Figure 20 and Figure 21 As shown, the substrate also includes a pixel defining portion 113, which is disposed on the side of the planarization layer 116 away from the substrate 101. The pixel defining portion 113 can be made of organic materials, such as photoresist, and the portion of the pixel defining portion 113 located in the display area A1 has a pixel opening that exposes the first electrode 112. The light-emitting functional layer 114a is located in the pixel opening and formed on the first electrode 112. The light-emitting functional layer can include small molecule organic materials or polymer molecule organic materials, or it can also be a fluorescent light-emitting material or a phosphorescent light-emitting material, which can emit red light, green light, or blue light, etc. In addition, depending on the actual needs, in different examples, the light-emitting functional layer can further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. The second electrode covers the light-emitting functional layer. This second electrode 115 can be used as a cathode, and its material can be a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), or silver (Ag).

[0156] It should be noted that, as Figure 20 and Figure 21 As shown, the first electrode 112, the light-emitting functional layer 114a, and the second electrode 115 can constitute a light-emitting unit 1d. The portion of this substrate located in the display area may include multiple light-emitting units arranged in an array. Furthermore, it should be noted that the first electrode of each light-emitting unit is independent, while the second electrode of each light-emitting unit is an integral structure and can be disposed as a single layer.

[0157] In one or more embodiments, reference is made to Figure 20 and Figure 21 As shown, a support portion 132 may also be provided on the side of the pixel defining portion 113 away from the substrate 101. This support portion 132 can support the protective film layer. Figure 20 and Figure 21 The protective film (not shown) serves to prevent the first electrode 112 or other traces from coming into contact with each other, thus avoiding potential damage to the first electrode 112 or other traces. It should be noted that this protective film is primarily used during the transfer of semi-finished products to prevent damage during this process. Specifically, a protective film can be applied during the transfer of the substrate with the support portion 132 to the evaporation line. This protective film is removed when the luminescent material needs to be deposited.

[0158] For example, the material of the support portion 132 can be the same as the material of the pixel defining portion 113, and the support portion 132 and the pixel defining portion 113 can be formed by the same patterning process, but are not limited thereto. The material of the support portion 132 can also be different from the material of the pixel defining portion 113, and the support portion 132 and the pixel defining portion 113 can also be formed by different patterning processes.

[0159] In one or more embodiments, referring to Figure 20 As shown, the first electrode 112 can be directly electrically connected with the second electrode 111 through a via of the planar layer 116. Figure 3 The structure shown belongs to a single SD structure. At this time, the power signal line located in the non-display area can include a two-layer structure. For example, the power signal line can include two power lines. One power line is arranged in the same layer as the first electrode and the second electrode (i.e., the source / drain electrode) of the transistor. The other power line is arranged in the same layer as the first electrode.

[0160] In one or more embodiments, referring to Figure 21 As shown, the first electrode 112 can also be electrically connected with the second electrode 111 through the transfer electrode 133. When the first electrode 112 is electrically connected with the second electrode 111 through the transfer electrode 133, the planar layer 116 can be a double-layer structure, which can specifically include a first planar film 116a and a second planar film 116b formed in sequence. In addition, a passivation layer 134 can be formed between the first planar film layer 116a and the interlayer dielectric layer 103. The passivation layer 134 can be formed of silicon oxide, silicon nitride, or silicon oxynitride, etc. The passivation layer 134 covers the first electrode 110 and the second electrode 111. It should be noted that when the planar layer 116 is a single layer, a passivation layer 134 can also be formed between the planar layer 116 and the interlayer dielectric layer 103. The transfer electrode 133 is formed between the first planar film 116a and the second planar film 116b and is electrically connected with the second electrode 111 in sequence through a via (e.g., a metal via) on the first planar film 116a and the passivation layer 134. The first electrode 112 can be electrically connected with the transfer electrode 133 through a via (e.g., a metal via) on the second planar film 116b, as shown in Figure 4 However, the transfer electrode 133 can also be formed between the first planar film 116a and the passivation layer 134.

[0161] Figure 21 The structure shown belongs to a double SD structure. At this time, the power signal line located in the non-display area can include a three-layer structure. For example, the power signal line can include a first power line 371, a second power line 372, and a third power line 373, as shown in Figure 13a Figures 14-15 The first power line is arranged in the same layer as the first electrode and the second electrode (i.e., the source / drain electrode) of the transistor. The second power line is arranged in the same layer as the transfer electrode. The third power line is arranged in the same layer as the first electrode.​Figure 21 and Figure 13a 、 Figures 14-16 The first flat film 116a, the first flat portion 41, the second protrusion 381 and the third protrusion 40 are arranged in the same layer; the second flat film 116b, the second flat portion 382 and the first protrusion 34 are arranged in the same layer, so that the number of patterning processes can be reduced and the manufacturing cost can be reduced.

[0162] In one or more embodiments, referring to Figure 3 and Figure 4 , the display substrate further includes an encapsulation unit 118 and a plurality of light emitting units 1d arranged in an array; the encapsulation unit 118 covers the light emitting units 1d and is arranged between the light emitting units 1d and the touch units 2; the encapsulation unit 118 is located in the non-display area and the display area, and the light emitting units are located in the display area.

[0163] Referring to Figure 20 and Figure 21 , the encapsulation layer 118 includes a first inorganic encapsulation layer 118a, an organic encapsulation layer 118b and a second inorganic encapsulation layer 118c arranged in sequence; in combination with Figure 20 、 Figure 21 and Figure 19 , the first inorganic encapsulation layer 118a and the second inorganic encapsulation layer 118c are configured to encapsulate the first dam area A2 area and the light emitting units 1d; the organic encapsulation layer 118b is configured to encapsulate the light emitting units 1d and is disconnected in the first dam area A2 area.

[0164] The first inorganic encapsulation layer and the second inorganic encapsulation layer described above can be formed by a chemical vapor deposition process, but are not limited thereto, or can also be formed by a physical vapor deposition process, etc. The organic encapsulation layer can be formed by an inkjet printing process, but is not limited thereto, or can also be formed by a spraying process, etc. In the process of forming the organic encapsulation layer, since the organic encapsulation material has a certain flowability, it is necessary to set a dam in the first dam area to block the overflow of the organic encapsulation material, so as to avoid the problem of encapsulation failure.

[0165] The structure of the anti-static layer arranged in the second non-display area B0 area will be described in detail below.

[0166] In one or more embodiments, referring to Figure 2a , in the non-display area B0 area, the edge area B6 includes an opening area B1 area and a transition area B3 area; the transition area B3 area is arranged around the opening area B1 area, and the first dam area B2 area is arranged around the transition area B3 area; referring to Figures 22-25 , the anti-static layer 1 is located at least in the transition area B3 area.

[0167] It should be noted that the opening area B1 of the display substrate of the present application is subjected to the opening processing, and is used for assembling devices such as camera, sensor, HOME key, earpiece or loudspeaker. For the display substrate of the present application, the opening area B1 can be subjected to the opening processing before assembling the devices such as camera, as shown in Figure 22 and Figure 24 Alternatively, the opening area B1 can be subjected to the opening processing after assembling the devices such as camera, as shown in Figure 23 and Figure 25 In this case, the display substrate can be directly subjected to subsequent assembly.

[0168] The shape of the opening area is not limited herein, and can be a racetrack hole or a circular hole, etc. After the opening processing, the obtained opening can include but is not limited to the following forms: through hole, groove, opening, etc. In addition, the number of the opening areas is not limited, and the display substrate can be provided with a single hole or double holes, Figure 2a for example, a single hole is shown.

[0169] The anti-static layer located at least in the transition area includes: the anti-static layer is located only in the transition area; or the anti-static layer is located in the transition area and the first dam area; or the anti-static layer is located in the transition area and the opening area; or the anti-static layer is located in the transition area, the opening area and the first dam area, etc., which is not limited herein. Figures 22-25 For example, the anti-static layer is located in part of the first dam area and all of the transition area and the opening area.

[0170] The anti-static layer can block and release static charges, thereby greatly reducing the charge conduction through the transition area, further reducing the probability of characteristic shift of the transistor of the driving unit, and finally improving the display effect.

[0171] Optionally, as shown in Figure 24 and Figure 25 The transition area B3 includes at least one second dam 1c, which is located on the side of the anti-static layer 1 close to the substrate 101 and at least partially overlaps the anti-static layer 1 in the direction perpendicular to the substrate 101.

[0172] The second dam at least partially overlaps the anti-static layer in the direction perpendicular to the substrate includes: the second dam partially overlaps the anti-static layer in the direction perpendicular to the substrate, at this time, the orthographic projection of the second dam on the substrate partially overlaps the orthographic projection of the anti-static layer on the substrate. Alternatively, the second dam fully overlaps the anti-static layer in the direction perpendicular to the substrate, at this time, the orthographic projection of the second dam on the substrate is located within the orthographic projection of the anti-static layer on the substrate. Figure 24 and Figure 25 In the anti-static layer 1 is located in all areas of the transition area B3, and the second dam 1c fully overlaps the anti-static layer 1 in the direction perpendicular to the substrate 101.

[0173] The specific number of the second dam is not limited here, Figures 24-25 A second dam is taken as an example for illustration.

[0174] Reference Figures 24-25 As shown, the second dam 1c can include a first protective portion 140, a first barrier portion 141, and a first spacer portion 142 arranged in sequence.

[0175] In one or more embodiments, in combination Figure 21 and Figure 24 As shown, the first protective portion 140 can be arranged in the same layer as the first electrode 112 of the display area. Since the first conductive thin film covers the interlayer dielectric layer 103 in the transition area B3, the interlayer dielectric layer 103 in the transition area B3 will not be cleaned by the etching liquid in the process of patterning the first electrode 112, reducing the number of times the interlayer dielectric layer 103 in the transition area B3 is cleaned by the etching liquid, thereby improving the adhesion of the interlayer dielectric layer 103 in the transition area B3. In addition, the first protective portion 140 can also be formed at the same time as the first electrode 112 is formed, so that the first protective portion 140 can continue to protect the interlayer dielectric layer 103 in the transition area B3 from being cleaned by the etching liquid in subsequent patterning processes. Since the first protective portion 140 and the first electrode 112 are formed by one patterning process, the number of processing steps and the use of masks can also be reduced, thereby reducing costs.

[0176] In one or more embodiments, in combination Figure 21 and Figure 24 As shown, the first protective portion 140 can be arranged in the same layer as the planarization layer 116. Since the planarization thin film covers the interlayer dielectric layer 103 in the transition area B3, the interlayer dielectric layer 103 in the transition area B3 will not be cleaned by the etching liquid in the process of patterning the planarization layer 116, reducing the number of times the interlayer dielectric layer 103 in the transition area B3 is cleaned by the etching liquid, thereby improving the adhesion of the interlayer dielectric layer 103 in the transition area B3. Since the first protective portion 140 is formed at the same time as the planarization layer 116 is formed, the first protective portion 140 can also continue to protect the interlayer dielectric layer 103 in the transition area B3 from being cleaned by the etching liquid in subsequent patterning processes. Since the first protective portion 140 and the planarization layer 116 are formed by one patterning process, the number of processing steps and the use of masks can also be reduced, thereby reducing costs.

[0177] In one or more embodiments, in combination Figure 21 andFigure 24 As shown, the first barrier portion 141 can be arranged in the same layer as the pixel defining portion 113 in the display area. Therefore, the first barrier portion 141 has the same material as the pixel defining portion 113, which is also an organic material. In this embodiment, the first protective portion 140 is arranged in the same layer as the planarization layer 116, so that the material of the first protective portion 140 is the same as that of the planarization layer 116, which is also an organic material. The material of the first protective portion 140 can be the same as that of the first barrier portion 141. This design can improve the bonding force between the first protective portion 140 and the first barrier portion 141, ensure the structural stability of the second encapsulation dam 1c, avoid the first barrier portion 141 from falling off the first protective portion 140, further reduce the risk of packaging failure, improve the packaging yield, and ensure the display effect and product service life.

[0178] The first spacer portion can be arranged in the same layer as the support portion 132 in the display area, which can increase the thickness of the second dam 1c in the direction perpendicular to the substrate. The first spacer portion can block the flow of the organic encapsulation material in the encapsulation unit 118 to the opening area B1, further improve the restriction of the flow of the organic encapsulation material in the encapsulation unit, and further improve the reliability of the display substrate packaging.

[0179] Of course, the second dam can also include a two-layer structure, which is not limited here. The actual situation can be determined.

[0180] In this application, the second dam can further improve the blocking effect, so that the transition area can be fully separated from the opening area and the display area, preventing impurities such as water and oxygen from entering the display area from the opening area, and preventing cracks that may be formed in the opening area from extending to the display area.

[0181] It should be noted that, in one or more embodiments, in order to save space, reference Figures 22-23 As shown, no second dam is arranged in the transition area B3, and the first dam area can rely on the dam of the first dam area to achieve the blocking of the organic encapsulation material.

[0182] In one or more embodiments, reference Figures 22-25 As shown, the first dam area B2 includes at least one third dam, and the third dam is arranged in the same layer as the second dam. The anti-static layer 1 and the third dam do not overlap in the direction perpendicular to the substrate.

[0183] The number of the third dam is not limited, Figures 22-25 For example, the first dam area B2 includes two third dams, which are marked as 1b and 1a respectively.

[0184] Reference Figures 22-25As shown, the structures of the third dam 1b close to the second dam 1c and the third dam 1a away from the second dam 1c are the same as that of the second dam 1c and are arranged in the same layer, and the beneficial effects of the corresponding structures are similar, which will not be described here. Specifically, the third dam 1b close to the second dam 1c includes the second protection part 120, the second barrier part 121 and the second spacer part 123 arranged in sequence in layers; and the third dam 1a away from the second dam 1c includes the third protection part 119, the third barrier part 117 and the third spacer part 122 arranged in sequence in layers.

[0185] The first protection part, the second protection part and the third protection part are arranged in the same layer; the first barrier part, the second barrier part and the third barrier part are arranged in the same layer; and the first spacer part, the second spacer part and the third spacer part are arranged in the same layer.

[0186] The thickness of the third dam 1b close to the second dam 1c along the direction perpendicular to the substrate can be greater than the thickness of the third dam 1a away from the second dam 1c along the direction perpendicular to the substrate, so as to better achieve the barrier effect. For example, the thickness of the second protection part along the direction perpendicular to the substrate can be greater than the thickness of the third protection part along the direction perpendicular to the substrate, the thickness of the second barrier part along the direction perpendicular to the substrate is the same as that of the third barrier part, and the thickness of the second spacer part along the direction perpendicular to the substrate is the same as that of the third spacer part, so as to achieve that the thickness of the third dam 1b close to the second dam 1c along the direction perpendicular to the substrate is greater than the thickness of the third dam 1a away from the second dam 1c along the direction perpendicular to the substrate. Of course, the heights of the two dams can also be made different in other ways.

[0187] The third dam can effectively play a role in blocking the organic packaging material, thereby improving the packaging effect and display effect.

[0188] In one or more embodiments, reference is made to Figure 24 and Figure 25 As shown, the transition area B3 further includes a barrier wall 135, which is arranged between the second dam 1c and the third dam 1b and surrounds the second dam 1c.

[0189] The barrier wall is arranged on the side of the anti-static layer close to the substrate; and the barrier wall and the anti-static layer at least partially overlap or do not overlap along the direction perpendicular to the substrate, which can be selected as needed. Figure 24 and Figure 25 For example, the barrier wall and the anti-static layer completely overlap along the direction perpendicular to the substrate, at which time the orthographic projection of the barrier wall on the substrate is located within the orthographic projection of the anti-static layer on the substrate.

[0190] In combination with Figure 21 and Figure 26The barrier wall can include a first film layer 136 arranged in the same layer as the control electrode 106 and the first electrode plate 130, a second film layer 137 arranged in the same layer as the second electrode plate 131, a third film layer 138 arranged in the same layer as the first electrode 110 and the second electrode 111, a second gate insulating sub-layer 108 between the first film layer 136 and the second film layer 137, and an interlayer dielectric layer 103 between the third film layer 138 and the second film layer 137. That is, the first film layer 136, the control electrode 106, and the first electrode plate 130 have the same structure and include the same material, and can be manufactured by one patterning process; the second film layer 137 and the second electrode plate 131 have the same structure and include the same material, and can be manufactured by one patterning process; and the third film layer 138, the first electrode 110, and the second electrode 111 have the same structure and include the same material, and can be manufactured by one patterning process.

[0191] In one or more embodiments, referring to Figure 24 and Figure 25 As shown, the transition region B2 can further include an organic insulating encapsulation portion 139 between the second dam 1c and the third dam 1b and covering the barrier wall 135. The organic insulating encapsulation portion 139 has the same material as the organic encapsulation layer 118b of the encapsulation unit 118, and both can be formed by the same inkjet printing process.

[0192] In this application, by providing the second encapsulation dam 1c, the barrier wall 135, and the organic insulating encapsulation portion 139, a further barrier effect is provided, so that the transition region B3 can be sufficiently separated from the opening region B1 and the display region A1, preventing impurities such as water and oxygen from entering the display region A1 from the opening region B1, and preventing cracks that can be formed when the opening region B1 is formed from extending to the display region A1.

[0193] In addition, referring to Figure 24 and Figure 25 As shown, when the transition region B3 includes the second dam 1c, the barrier wall 135, and the organic insulating encapsulation portion 139, the first inorganic encapsulation layer 118a mentioned above further covers the second dam 1c and the barrier wall 135; the organic encapsulation layer 118b and the organic insulating encapsulation portion 139 are formed by the inkjet printing process; and the second inorganic encapsulation layer 118c further covers the second dam 1c, the barrier wall 135, and the organic insulating encapsulation portion 139. As shown in Figure 24 and Figure 25 As shown, when the first dam region B2 includes the third dams 1b and 1a, the first inorganic encapsulation layer 118a and the second inorganic encapsulation layer 118c further cover the third dams 1b and 1a, and the organic encapsulation layer 118b is blocked by the third dams 1b and 1a.

[0194] It should be noted that in this application, as Figure 2aAs shown, when the aperture area B1 is circular, the orthographic projection of the second dam 1c, the third encapsulation dams 1b and 1a, and the barrier wall 135 on the substrate can also be an annulus; when the aperture area B1 is rectangular, the orthographic projection of the second dam 1c, the third encapsulation dams 1b and 1a, and the barrier wall 135 on the substrate can also be a rectangular annulus; but not limited to this, the aperture area B1 can also be other regular or irregular shapes, and the second dam 1c, the third encapsulation dams 1b and 1a, and the barrier wall 135 can be adapted to them.

[0195] In one or more implementations, refer to Figures 22-25 As shown, the non-display area also includes the isolation area B4 area, which is located between the first dam area B2 area and the display area A1 area, and is set around the first dam area B2 area.

[0196] refer to Figures 22-25 As shown, isolation zone B4 includes isolation pillars 124, which are arranged around the first dam zone B2; (Reference) Figure 27 As shown, the side wall of the isolation column 124 is provided with a partition groove 124a.

[0197] The number of the aforementioned isolation columns is not limited to one, or there may be multiple columns.

[0198] In one or more embodiments, the isolation pillar can be disposed in the same layer as the first electrode 110 and the second electrode 111 of the thin-film transistor. If the first electrode 110 and the second electrode 111 are a three-layer metal structure, then the isolation pillar can also be a three-layer metal structure. For example, Figure 27 As shown, the isolation pillar 124 may include a first metal layer 124b, a second metal layer 124c, and a third metal layer 124d stacked sequentially. The outer boundary of the orthogonal projection of the second metal layer 124c onto the substrate is located within the outer boundaries of the orthogonal projections of the first metal layer 124b and the third metal layer 124d onto the substrate, so as to form a partition groove 124a on the sidewall of the isolation pillar 124, making the longitudinal section of the isolation pillar 124 have an "I" shaped structure. In this way, when evaporating the light-emitting material or the cathode material, the light-emitting material layer 114 and the cathode (i.e., the second electrode 115) are interrupted at this partition groove 124a, thereby blocking the path of water and oxygen in the opening area B1 to erode the display area A1, thereby further preventing the display area A1 from being eroded, improving the display effect of the display substrate and extending the product life.

[0199] In one or more implementations, refer to Figures 22-25As shown, the isolation region B4 includes a first slot 125 and a second slot 126; the first slot 125 is located on the side of the isolation column 124 close to the third dam 1a, and the first slot 125 is arranged around the third dam 1a; the second slot 126 is located on the side of the isolation column 124 close to the display region A1, and the second slot 126 is arranged around the first slot 125. In this way, the probability of the light emitting material being disconnected on the side of the isolation column 124 can be increased.

[0200] Figures 22-25 In some embodiments, the first slot and the second slot can be formed by removing the portions of the interlayer dielectric layer 103, the second gate insulating sub-layer 108, and the first gate insulating sub-layer 105 that are located in the region of the isolation region B4 where the isolation column 124 is not arranged. Of course, other methods can also be used, which will not be described here.

[0201] In this application, the first slot and the second slot are arranged to further increase the probability of the light emitting material or the cathode material being disconnected on the side of the isolation column. In addition, when the display substrate is flexible and is bent, the design can also relieve part of the stress and ensure the reliability.

[0202] It should be noted that, in this application, Figure 2a As shown, when the opening region B1 is circular, the orthogonal projection of the isolation column, the first slot, and the second slot on the substrate can also be a circular ring; when the opening region B1 is rectangular, the orthogonal projection of the isolation column, the first slot, and the second slot on the substrate can also be a rectangular ring; but it is not limited to this, the opening region B1 can also be other regular or irregular shapes, and the isolation column, the first slot, and the second slot can be adapted thereto.

[0203] In one or more embodiments, referring to Figures 22-25 As shown, the non-display region further includes a wiring region B5, which is located between the isolation region B4 and the display region A1 and is arranged around the isolation region B4.

[0204] The wiring region B5 includes a plurality of wires, and the wires of the wiring region are electrically connected to the corresponding wires of the display region.

[0205] Referring to Figures 22-25 As shown, the wiring region B5 can include a first wire 129a, a second wire 129b, and a third wire 129c,

[0206] The first wire can include a data signal line, but it is not limited to this, and in this case, the first wire can be electrically connected to the data signal line in the display region; the second wire can include a gate line, but it is not limited to this, and in this case, the second wire can be electrically connected to the gate line in the display region; the third wire can include a reset signal line or an initialization line, but it is not limited to this, and in this case, the third wire can be electrically connected to the reset signal line or the initialization line in the display region.

[0207] Alternatively, the first trace described above can include a gate line, but is not limited thereto, and in this case, the first trace can be electrically connected to the gate line in the display area; the second trace can include a data signal line, but is not limited thereto, and in this case, the second trace can be electrically connected to the data signal line in the display area; and the third trace can include a reset signal line or an initialization line, but is not limited thereto, and in this case, the third trace can be electrically connected to the reset signal line or the initialization line in the display area. Of course, other cases are also possible, which will not be described here.

[0208] Reference is made to Figures 24-25 As shown in FIG. 1, the display substrate further includes: a buffer layer 102, a gate insulating layer (including a second gate insulating sublayer 108 and a first gate insulating sublayer 105), and an interlayer dielectric layer 103, which are sequentially stacked; the interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the display area, the trace area, the isolation area, the first dam area, and the transition area; the second dam 1c, the third dams 1b and 1a, and the isolation column 124 are all disposed on the side of the interlayer dielectric layer 103 away from the substrate 101.

[0209] It should be noted that the structure of the gate insulating layer in the display area is the same as that of the gate insulating layer in the non-display area. For example, if the gate insulating layer in the display area includes two layers of the first gate insulating sublayer and the second gate insulating sublayer, the gate insulating layer in the non-display area also includes two layers of the first gate insulating sublayer and the second gate insulating sublayer.

[0210] In one or more embodiments, reference is made to Figure 3 and Figure 4 As shown in FIG. 1, the display substrate further includes: a polarizing layer 54, which is disposed on the side of the touch unit 1 away from the packaging unit 2.

[0211] It should be noted that the display substrate can also include other structures, and only the structures related to the invention points are introduced here. The remaining structures can be obtained by referring to related technologies, which will not be described here.

[0212] The display device provided by the embodiments of the present application includes the display substrate described above.

[0213] The display device can be a flexible display device (also known as a flexible screen), or can also be a rigid display device (i.e., a display device that cannot be bent), which is not limited here.

[0214] The display device can be an OLED (Organic Light-Emitting Diode) display device, and can also be a Micro LED display device or a Mini LED display device, as well as a television, a digital camera, a mobile phone, a tablet computer, or any product or component having a display function. The display device can greatly improve the problem of green light at the edge of the screen, has good display effect, and provides good user experience.

[0215] Optionally, referring to Figure 3 and Figure 4 As shown in the figure, the display device further comprises a packaging substrate 52, and the packaging substrate 52 and the display substrate 50 are fixed together through an adhesive layer 53.

[0216] The packaging substrate can comprise a glass substrate, and the adhesive layer can comprise an OCA (Optically Clear Adhesive).

[0217] It should be noted that, in order to enable the display device to have a photographing function, the display device can further integrate an optical unit, which can be arranged on the side of the substrate of the display substrate away from the driving unit (i.e., the back of the substrate); in order to better arrange the optical unit, an isolation layer can be further arranged between the substrate and the optical unit. Of course, the display device can further comprise other structures, which can be obtained according to related technologies, and will not be described here.

[0218] As used herein, the term “one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

[0219] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0220] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not limit the technical solutions of the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A display substrate, characterized in that, include: A display area and a non-display area connected to the display area, the non-display area including an edge area and a first dam area, the first dam area being located between the display area and the edge area; The display substrate further includes: Substrate; An antistatic layer is disposed on the substrate; the antistatic layer is located at least in the edge region; A driving unit and a touch unit are disposed on the substrate; wherein, the driving unit is located in the display area, and the touch unit is located in the display area and the non-display area, and covers the driving unit; The antistatic layer and the touch unit are disposed on the same layer, or the antistatic layer is disposed on the side of the touch unit away from the substrate; The edge region includes a cutting transition region, a crack dam region, and a drive circuit region; the crack dam region is arranged around the first dam region and is disconnected in the drive circuit region; the cutting transition region is arranged around the crack dam region and the drive circuit region. The cracked dam area includes at least one groove, which is disposed around the first dam area and disconnected in the drive circuit area; the antistatic layer at least covers a portion of the groove; The display substrate further includes: a buffer layer, a gate insulating layer, and an interlayer dielectric layer stacked sequentially; The first dam area also includes a jumper wire and a third protrusion. The third protrusion is disposed on the side of the first dam area closest to the cut transition area, near the crack dam area. The jumper wire is disposed on the side of the interlayer dielectric layer away from the substrate. The third protrusion covers the jumper wire. The integral formed by the interlayer dielectric layer, the gate insulating layer, and the buffer layer has at least one step near the edge of the cut transition region.

2. The display substrate according to claim 1, characterized in that, The touch unit includes a first touch layer, a first insulating layer, a second touch layer, and a second insulating layer stacked sequentially on the driving unit; the first touch layer and the second touch layer are both located in the display area, and the first insulating layer and the second insulating layer are located in the display area and the non-display area, respectively. In this design, one of the first touch layer and the second touch layer is a metal mesh electrode layer, and the other is a bridging metal layer.

3. The display substrate according to claim 2, characterized in that, When the antistatic layer and the touch unit are disposed on the same layer, the antistatic layer and the first touch layer are disposed on the same layer; Alternatively, if the antistatic layer and the touch unit are disposed on the same layer, the antistatic layer and the second touch layer are disposed on the same layer.

4. The display substrate according to claim 3, characterized in that, The second insulating layer covers the first insulating layer, and the boundary of the second insulating layer is farther away from the boundary of the first insulating layer from the first dam area; The second insulating layer located in the non-display area is disposed on the side of the antistatic layer away from the substrate.

5. The display substrate according to claim 4, characterized in that, The orthographic projection of the antistatic layer on the substrate overlaps with the orthographic projection of the second insulating layer on the substrate; Alternatively, the orthographic projection of the antistatic layer on the substrate lies within the orthographic projection of the second insulating layer on the substrate.

6. The display substrate according to claim 2, characterized in that, When the antistatic layer is disposed on the side of the touch unit away from the substrate, the second insulating layer located in the non-display area is disposed on the side of the antistatic layer closer to the substrate.

7. The display substrate according to any one of claims 1-6, characterized in that, The first dam area is arranged around the display area, and the edge area is arranged around the first dam area.

8. The display substrate according to claim 7, characterized in that, The interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the display area, the first dam area, and the crack dam area; The groove at least penetrates the portion of the interlayer medium layer located in the cracked dam area.

9. The display substrate according to claim 8, characterized in that, The display substrate further includes: a first flat portion and a first protrusion, wherein the first flat portion is located in the cutting transition area and the crack dam area; the first protrusion is located in the crack dam area, is disposed around the first dam area, and is disconnected in the driving circuit area; The first flat portion covers all the grooves, the first protrusion is disposed on the side of the first flat portion away from the substrate, and the antistatic layer covers the first protrusion.

10. The display substrate according to claim 9, characterized in that, The first flat portion covers all of the steps.

11. The display substrate according to claim 9, characterized in that, The edge region also includes a crack detection region, which is located between the first dam region and the cracked dam region; The crack detection area includes multiple crack detection lines, and the antistatic layer covers all the crack detection lines and all the grooves.

12. The display substrate according to claim 11, characterized in that, The antistatic layer is also located in the first dam area; The non-display area also includes a wiring area, which is located between the first dam area and the display area; The display substrate further includes: a power signal line located in the wiring area and the first dam area; the power signal line partially overlaps with the antistatic layer in a direction perpendicular to the substrate.

13. The display substrate according to claim 12, characterized in that, The interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the wiring area and the crack detection area; The first dam area includes at least one first dam, which is disposed on the side of the interlayer dielectric layer away from the substrate; the first dam includes a second protrusion, a second flat portion, and a third flat portion disposed sequentially; the second flat portion covers the second protrusion, and the third flat portion covers the second flat portion; The second protrusion and the first flat portion are disposed in the same layer, and the second flat portion and the first protrusion are disposed in the same layer.

14. The display substrate according to claim 13, characterized in that, The third protrusion, the second protrusion, and the first flat portion are arranged in the same layer.

15. The display substrate according to claim 14, characterized in that, The power signal line includes at least a first power line, which is disposed on the side of the interlayer dielectric layer away from the substrate; the first dam is disposed on the side of the first power line away from the substrate. The first power line and the jumper are arranged in the same layer and disconnected from each other, and the third protrusion also covers the edge of the first power line near the cutting transition area; The first power line and the antistatic layer partially overlap in a direction perpendicular to the substrate.

16. The display substrate according to claim 14, characterized in that, The power signal line further includes a second power line and a third power line; the third power line is disposed on the side of the second power line away from the substrate; The second power line is positioned near the edge of the cutting transition zone between the second protrusion and the second flat portion in the first dam closest to the cutting transition zone, and the third power line is positioned near the edge of the cutting transition zone between the second flat portion and the third flat portion in the first dam closest to the cutting transition zone.

17. The display substrate according to claim 16, characterized in that, The display substrate further includes a plurality of light-emitting units arranged in an array; the light-emitting units are located in the display area and are disposed between the driving unit and the touch unit; The light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode; the second electrode is disposed on the side of the light-emitting functional layer away from the driving unit. The driving unit includes an array of transistors, a first flat film, a plurality of transition electrodes, and a second flat film. The first flat film covers the transistors, and the transition electrodes are disposed between the first flat film and the second flat film and are electrically connected to the transistors. The first electrode is disposed on the side of the second flat film away from the substrate and is electrically connected to the transition electrode. The first power line is disposed on the same layer as the source and drain of the transistor; the second power line is disposed on the same layer as the transition electrode; the third power line is disposed on the same layer as the first electrode; the first flat film, the first flat portion, the second protrusion and the third protrusion are disposed on the same layer; the second flat film, the second flat portion and the first protrusion are disposed on the same layer.

18. The display substrate according to any one of claims 1-6, characterized in that, The edge region includes an opening region and a transition region; the transition region is arranged around the opening region, and the first dam region is arranged around the transition region; The antistatic layer is located at least in the transition zone.

19. The display substrate according to claim 18, characterized in that, The transition zone includes at least one second dam, which is disposed on the side of the antistatic layer near the substrate and at least partially overlaps the antistatic layer in a direction perpendicular to the substrate.

20. The display substrate according to claim 19, characterized in that, The first dam area includes at least one third dam, which is arranged in the same layer as the second dam; The antistatic layer and the third dam do not overlap in a direction perpendicular to the substrate.

21. The display substrate according to claim 20, characterized in that, The transition zone also includes a barrier wall located between the second dam and the third dam, and surrounding the second dam.

22. The display substrate according to claim 21, characterized in that, The non-display area also includes an isolation area, which is located between the first dam area and the display area and is arranged around the first dam area; The isolation zone includes isolation columns, which are arranged around the first dam area.

23. The display substrate according to claim 22, characterized in that, The non-display area also includes a wiring area, which is located between the isolation area and the display area and surrounds the isolation area; The wiring area includes multiple wirings, and the wirings in the wiring area are electrically connected to the wirings corresponding to the display area.

24. The display substrate according to claim 23, characterized in that, The display substrate further includes: a buffer layer, a gate insulating layer, and an interlayer dielectric layer stacked sequentially; the interlayer dielectric layer, the gate insulating layer, and the buffer layer are all located in the display area, the wiring area, the isolation area, the first dam area, and the transition area; The second dam, the third dam, and the isolation column are all located on the side of the interlayer dielectric layer away from the substrate.

25. The display substrate according to claim 1, characterized in that, The display substrate further includes an encapsulation unit and a plurality of light-emitting units arranged in an array; the encapsulation unit covers the light-emitting units and is disposed between the light-emitting units and the touch unit; the encapsulation unit is located in the non-display area and the display area, and the light-emitting units are located in the display area; the encapsulation unit includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked sequentially; the first inorganic encapsulation layer and the second inorganic encapsulation layer are configured to encapsulate the first dam area and the light-emitting units; the organic encapsulation layer is configured to encapsulate the light-emitting units and is disconnected in the first dam area.

26. A display device, characterized in that, Includes the display substrate as described in any one of claims 1-25.

Images