Adaptive Hysteresis Control Circuit System and Related Methods for Power Converters

Abstract

An apparatus (500) includes: a first control circuit (508) having an output and including a first comparator (524); and a second control circuit (510) coupled to the output of the first control circuit (508). The second control circuit (510) includes a second comparator (514) configured to: compare a first value with a reference frequency value, the first value indicating the frequency of a signal at the output of the first control circuit; and provide an adjustment value to change the hysteresis window of the first comparator (524).

Description

Technical Field

[0001] This invention generally relates to power converters, and more specifically, to adaptive hysteresis control for power converters. Background Technology

[0002] Power converters (also referred to as converters herein) (e.g., AC-DC or DC-DC converters) can be used in systems such as power supplies to power loads. Loads may include motors, computers, etc. Some power converters include switching circuitry that switches the power converter on and off to provide a regulated DC signal (e.g., regulated voltage and / or current). Output signal regulation can be achieved using closed-loop feedback control, which compares a signal based on, for example, a small portion of the regulated output signal with a reference signal. The result of this comparison is used to control the switching circuitry of the power converter. Despite the inclusion of closed-loop feedback control, the regulated output signal may have "ripple." "Ripple," characterized by its amplitude and frequency, is a variation relative to a target output signal. The amplitude reflects the amount or level of deviation from the target output value, and the frequency reflects the frequency of said deviation. In systems containing power converters, one or both of the amplitude and frequency of the regulated output signal can be degraded by transients in the load current. Appropriate control of both amplitude and frequency reduces potential negative impacts on other circuitry within the system. Summary of the Invention

[0003] In one example, a device includes: a first control circuit having an output and including a first comparator; and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value with a reference frequency value, the first value indicating the frequency of a signal at the output of the first control circuit; and provide an adjustment value to change the hysteresis window of the first comparator.

[0004] In another example, a device includes a first circuit comprising: a power converter having a control input and a converter output; and a first control circuit having a feedback input and a control output coupled to the control input. The device further includes a second control circuit and a third control circuit. The second control circuit has an input and a feedback output, wherein the input of the second control circuit is coupled to the converter output, and the feedback output is coupled to the feedback input. The second control circuit includes a first comparator. The third control circuit is coupled to the feedback output and includes a second comparator. The comparators are configured to: compare a first value with a reference frequency value, the first value indicating the frequency of the signal at the feedback output; and provide an adjustment value to change the hysteresis window of the first comparator.

[0005] In another example, a method includes: receiving an output signal; and comparing the output signal with a hysteresis window and responsively generating a feedback signal having a frequency. The method further includes comparing the first value indicating the frequency with a reference frequency value and responsively generating an adjustment value. The method further includes adjusting the hysteresis window based on the adjustment value. Attached Figure Description

[0006] Figure 1 It is a block diagram depicting an example circuit system containing adaptive hysteresis control for a power converter.

[0007] Figure 2 This is a block diagram and schematic diagram depicting an example circuit system containing adaptive hysteresis control for a quasi-resonant DC-DC converter.

[0008] Figure 3 It is a description Figure 2 The diagram and schematic representation of the system shown are simplified representations of the system.

[0009] Figure 4 Plot multiple curves; their descriptions can be found in... Figure 2 and 3 The corresponding hysteresis value used during the operation of the circuit system in the circuit is used to maintain the ripple frequency of the regulated DC output signal within the target range.

[0010] Figure 5 This is a block diagram and schematic diagram depicting another example system containing adaptive hysteresis control for a power converter.

[0011] Figure 6 Describing for operation Figure 5 The digital timing diagram of the system is shown in the image.

[0012] Figure 7 Depicting Figure 5 The example simulation results of the system load scan shown in the figure illustrate the ripple frequency maintained within the target range.

[0013] Figure 8 Depicting Figure 5 The example simulation results of the system shown in the figure illustrate the ripple amplitude plotted for multiple decoupling capacitor values ​​relative to the percentage of load current.

[0014] Figure 9 Depicting Figure 5 The example simulation results of the system shown in the figure illustrate the ripple frequency plotted for multiple decoupling capacitor values ​​relative to the percentage of load current.

[0015] Figure 10 This is a block diagram and schematic diagram depicting another example system containing adaptive hysteresis control for a power converter.

[0016] Figure 11 This is a flowchart depicting a method for adaptive hysteresis control for a power converter.

[0017] In the diagram, the same reference number refers to all the same element, and various features are not necessarily drawn to scale. Detailed Implementation

[0018] Some closed-loop feedback control methods effectively control either the ripple amplitude or the ripple frequency of the regulated output signal of a power converter, rather than both. For example, pulse width modulation (PWM) feedback control effectively controls the ripple frequency. However, a drawback of this method is the large overshoot and undershoot (e.g., greater than 200 mV) of the target DC output signal during load transients. Such voltage spikes can damage some loads. Increasing the decoupling capacitor at the converter output can reduce the ripple amplitude, but at the cost of increased system cost. Another disadvantage is the slow transient response of the regulated output signal due to the limited loop bandwidth used to stabilize the system. For example, the loop bandwidth may be 30 kHz compared to a 625 kHz PWM frequency.

[0019] In contrast, hysteresis feedback control benefits from: a fast transient response (e.g., 200 ns) to the regulated output signal; and effective control of ripple amplitude, for example, down to 10 mV. However, compared to PWM feedback control, some hysteresis feedback control methods suffer from degraded control due to ripple frequency (due to increased input and output voltages), especially when using a fixed hysteresis window. Lack of ripple frequency control can generate electromagnetic interference, such as interfering with electromagnetic emissions from other nearby circuit systems.

[0020] Several hysteresis feedback control methods have been proposed to work with buck converters using hysteresis windows adapted or adjusted based on the input and output voltages of the converter, in order to reduce ripple frequency variations. These adaptive hysteresis feedback control methods use open-loop correction and include a differentiator that determines the adjustment of the hysteresis window to regulate the ripple frequency. Using these proposed topologies, effective ripple frequency control can be maintained even as the input voltage increases. However, ripple frequency control degrades as the output voltage increases. Furthermore, the differentiator introduces cost and complexity to the system, and load transients further reduce the effectiveness of the open-loop correction.

[0021] The described examples include circuits and methods for adaptive hysteresis feedback control (or simply adaptive hysteresis control) of power converters based on ripple frequency. The benefits of the adaptive hysteresis control examples described include: maintaining the ripple amplitude within a target range using the fast transient response of the regulated output signal; controlling the ripple frequency within a target value or range using a closed-loop circuit system when load transients are present; and improving the ripple amplitude with a larger decoupling capacitor. Furthermore, some examples control the ripple frequency for nonlinear load changes. Additionally, some examples can be applied to control the ripple frequency in isolated DC-DC converters or other converter types (e.g., other DC-DC converter types).

[0022] Based on the first example, Figure 1 This illustration depicts a block diagram of system 100, which includes an example circuit system for an adaptive hysteresis control power converter based on ripple frequency. Specifically, system 100 includes a power converter (or simply converter) 102, a power control circuit system (or simply control circuit system) 104, a hysteresis output regulator 106, and pins and / or pads 112 to 118. For simplicity, elements 112 to 118 are referred to as pins. The hysteresis output regulator 106 includes a hysteresis control circuit system 108 and a frequency-based hysteresis window control circuit system (or simply hysteresis window control circuit system) 110. Circuit systems 104, 108, and 110 (and their embodiments in other figures) are referred to herein as control circuitry.

[0023] Although not all are individually labeled in the figures (e.g., 1, 2, 3, 5, and 10), the components or elements of the systems and circuits illustrated therein have one or more conductors or terminals that allow signals to enter or exit the component or element. Conductors or terminals (or portions thereof) may be referred to herein as pins, pads, terminals (including, for example, input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects. Furthermore, system 100 may be a single integrated circuit (IC) or IC package built on a monolithic silicon substrate and having pins 112 to 118. Alternatively, system 100 may be integrated into multiple ICs and / or multiple IC packages (each package having one or more ICs), wherein the multiple ICs or IC packages are coupled to or mounted on a printed circuit board (PCB) having pads 112 to 118.

[0024] As shown in the figure, the voltage input of converter 102 is coupled to pin 112 at node 101. The output of converter 102 is coupled to pin 116 and the voltage input of hysteresis control circuitry system 108 at node 107. The control input of converter 102 is coupled to the control output of control circuitry system 104 at node 103. The first reference (e.g., ground) terminal of converter 102 is coupled to pin 114 at node 105, and the second reference (e.g., ground) terminal of converter 102 is coupled to pin 118 at node 111. The feedback output of hysteresis control circuitry system 108 is coupled to the feedback input of hysteresis window control circuitry system 110 and the feedback input of control circuitry system 104 at node 109. The reference input of hysteresis control circuitry system 108 is coupled to a reference voltage V. ref The circuit system (not shown). The (reference) input of the hysteresis window control circuit system 110 is coupled to provide a reference frequency f. ref The circuit system (not shown) and the (hysteresis) output of the hysteresis window control circuit system 110 is coupled to the (hysteresis) input of the hysteresis control circuit system 108 at node 113.

[0025] As further shown, pin 112 receives a voltage, such as an AC or DC voltage V, provided to the voltage input of converter 102. CC1 Pin 114 is coupled to a first common reference voltage, such as first electrical ground (or simply ground) GND1. Pin 116 provides a voltage from the output of converter 102, such as a regulated DC voltage V. OUT Pin 118 is coupled to a second common reference voltage, such as a second ground GND2. In this example, pins 114 and 118 are shown coupled to different grounds to, for example, promote electrical isolation between different voltage domains. However, in another example, pins 114 and 118 are coupled to the same ground.

[0026] In one embodiment, converter 102 is a "switching" converter that includes a switching circuitry (not shown) that operates using a switching mode to switch the frequency of converter 102 on or off (e.g., on or conducting state and off or non-conducting state) to provide a regulated DC output signal, in this case V. OUT A switching circuit system may contain one or more switches, such as one or more transistors used as switches, such as field-effect transistors. Example switching converter types include (but are not limited to) buck, boost, buck-boost, and flyback converters. Example switching converter topologies that include multi-transistor switching circuit systems are push-pull, half-bridge, and full-bridge converters, which can provide one or more regulated output signals.

[0027] The power control circuit system 104 provides signals to control the switching circuit system to switch the frequency on and off the converter 102 to generate V. OUT The load (not shown) can be coupled to pin 118 to receive V. OUT When receiving V OUT At that time, the load draws current I LOAD I LOAD It may be transient or variable, such as instantaneous or near-instantaneous changes, for example, during the energization and / or de-energization of the load.

[0028] Hysteresis output regulator 106 is configured to, for example, respond to I LOAD Adjusting V in the transient state OUT The ripple amplitude and ripple frequency. More specifically, the hysteresis control circuit system 108 is configured to, for example, base on the output voltage V. OUT A small portion is used to monitor the voltage and determine whether the amplitude (which indicates the ripple amplitude) is within a hysteresis window defined or characterized by an upper and lower voltage threshold. In this example, the hysteresis control circuit system 108 is relative to V ref The upper and lower threshold values ​​of the hysteresis window are set. Based on whether the voltage is within or outside the hysteresis window, the hysteresis control circuitry 108 provides and / or adjusts the feedback signal FB. The control circuitry 104 uses FB to adjust the duty cycle of the switching circuitry to regulate (including control) V. OUT The ripple amplitude. Furthermore, the hysteresis window control circuit system 110 is configured to control the adjustment of the hysteresis window to thereby control V. OUT The ripple frequency. That is, the hysteresis window control circuit system 110 is configured to monitor the frequency of FB (FB). freq (It indicates the ripple frequency) and compares the frequency of FB (or a small portion thereof) with f. ref To determine whether to adjust or control the hysteresis window (e.g., using an adjustment signal and / or the value HYST_VAL) to maintain the ripple frequency within a target value or target range. An example implementation of System 100 is described in... Figure 2 , 3 Explanation in sections 5 and 10.

[0029] More specifically, Figure 2This is a block diagram depicting a system 200 comprising an example circuit system for an adaptive hysteresis-controlled quasi-resonant DC-DC converter based on ripple frequency. System 200 includes a quasi-resonant DC-DC converter 202, a power control circuit system 204, a hysteresis output regulator 206, a feedback (FB) channel receive (RX) circuit system 226, an FB channel transmit (TX) circuit system 228, isolation capacitors C2 and C3 (each having corresponding first and second (capacitor) terminals coupled to corresponding first and second plates), and pins and / or pads 212 to 218. For simplicity, components 212 to 218 are referred to as pins.

[0030] In one example, system 200 is located within or included in a power supply system, which may also include other circuits, components, and / or subsystems (not shown). In another example, control circuit system 204 is... Figure 1 The implementation scheme of the control circuit system 104. The converter 202 is... Figure 1 The implementation of converter 102, and the hysteresis output regulator 206 is Figure 1 An implementation of the hysteresis output regulator 106. Furthermore, the system 200 can be integrated into a single IC or IC package built on a monolithic silicon chip and having pins 212 to 218. Alternatively, the system 200 can be integrated into multiple ICs and / or multiple IC packages (each package having one or more ICs), wherein the multiple ICs or IC packages are coupled to or mounted on a PCB having pads 212 to 218. In another example, one or more of the passive components in the system 200 (e.g., capacitors and resistors) are discrete components.

[0031] As shown in the figure, converter 202 includes transformer 250 (including primary winding 232 and secondary winding 236), capacitor C1 having first and second (capacitor) terminals coupled to corresponding first and second plates, transformer driver circuit (or simply transformer driver) 234, and rectifier circuit (or simply rectifier) ​​238. Control circuit system 204 includes oscillator circuit (or simply oscillator) 222 and power controller 220.

[0032] As also shown in the figure, the voltage input of transformer driver 234 is coupled to pin 212 at node 201. The output of rectifier 238 is coupled to pin 216 at node 207. The control input of transformer driver 234 is coupled to the control output of control circuit system 204 at node 203. The reference (e.g., ground) terminal of transformer driver 234 is coupled to pin 214 at node 205, and the reference (e.g., ground) terminal of rectifier 238 is coupled to pin 218 at node 211. Additionally, the terminals of primary winding 232 of transformer 250 are coupled to the output of transformer driver 234. The terminals of secondary winding 236 of transformer 250 are coupled to the input of rectifier 238 and the terminal of capacitor C1, respectively, such that secondary winding 236 and capacitor C1 are coupled in parallel across the input of rectifier 238. Furthermore, the frequency output of oscillator 222 is coupled to the frequency input of power controller 220.

[0033] The transformer driver 234 includes a switching circuitry (not shown), such as one or more transistors acting as switches. The transistors switch on and off at a frequency using signals provided to corresponding control terminals. This on / off switching allows power from an input signal supplied at pin 212 to be supplied to the primary winding 232, transferred to the secondary winding 236, and rectified by rectifier 238 to produce a regulated output signal at the output of rectifier 238, which is then supplied to pin 216. In an example, rectifier 238 includes diodes arranged in a half-bridge or full-bridge topology. The power controller 220 may include one or more amplifiers, comparators, and other circuitry and / or logic that operate at least partially under the control of the hysteresis output regulator 206 to regulate the output signal.

[0034] As further shown, transformer 250 is an "isolation" transformer, wherein windings 232 and 236 are separated by a current isolation (or insulation) barrier 240. For example, an IC containing transformer 250 may include an insulating material (e.g., one or more layers of dielectric material, such as a thin-film polymer) between windings 232 and 236 to create isolation barrier 240. Isolation barrier 240 allows for electrical isolation between two systems to prevent current and voltage in one system from negatively impacting the other system, for example, by damaging or interfering with the operation of one or more components of the other system.

[0035] For example, during operation, the output signal generated by converter 202 (in this case, the DC output voltage V) ISO ) and the input signal (in this case, the DC input signal V) CC1 Electrical isolation. Therefore, the two systems can be powered by different power sources (e.g., V). CC1 and V ISOPower is supplied separately from a common ground connection, as illustrated by separate ground connections GND1 at pin 214 and GND2 at pin 218. A load (not shown) can be coupled to pin 218 to receive V. ISO When receiving V ISO At that time, the load draws current I LOAD .

[0036] In a specific instance, transformer 250 is a laminated transformer with an inductance of approximately 0.6 to 0.7 kJ, less than 100 nanohenries (nH), and a turns ratio of less than 1.5. Furthermore, V CC1 It is 3 to 5.5 volts (V), and V ISO A 3.3 V or 5 V pin configuration is available. Therefore, in this example, converter 202 operates in buck-boost mode. Furthermore, converter 202 features a resonant topology, where transformer 250 is driven by oscillator 222 at a fixed frequency (e.g., 25 MHz) to optimize efficiency. Additionally, a parallel LC resonance from secondary winding 236 and capacitor C1 provides a Q-boost voltage to rectifier 238, which generates a resonant peak depending on the fixed frequency.

[0037] As further shown, the hysteresis output regulator 206 includes a hysteresis control circuit system 208, a hysteresis window control circuit system 210 (also referred to herein as a hysteresis controller 210), and an oscillator circuit (or simply oscillator) 230. The hysteresis control circuit system 208 includes a hysteresis controller 224 (e.g., a comparator with hysteresis, also referred to herein as comparator 224) and resistors R1, R2, and R3 (each having corresponding first and second (resistor) terminals), wherein resistor R2 has an adjustable resistance and is therefore referred to as an adjustable resistor. Furthermore, in this example, comparator 224 is implemented as an inverting comparator. However, in an alternative example, comparator 224 is implemented as a non-inverting comparator.

[0038] As shown in the figure, resistors R1, R2, and R3 are coupled in series between nodes 207 and 211. Specifically, the first terminal of resistor R1 is coupled to node 207. The second terminal of resistor R1 is coupled to the first terminal of resistor R2 at node 215. The second terminal of resistor R2 is coupled to the first terminal of resistor R3 at node 217, and the second terminal of resistor R3 is coupled to node 211. Furthermore, the inverting input of comparator 224 is coupled to nodes 215 and 217, for example, through corresponding switches (not shown). The non-inverting input of comparator 224 is coupled to a reference voltage V. ref The circuit system (not shown). The output of comparator 224 is coupled at node 209 to the input of the FB channel TX circuit system 228 and the (frequency) input of the hysteresis controller 210. The (reference) input of the hysteresis controller 210 is coupled to provide a reference frequency f.ref The oscillator 230 has a (reference) output. The output of the hysteresis controller 210 is coupled to resistor R2 at node 213. The output of the FB channel TX circuit system 228 is coupled to the first terminal of capacitor C3. The second terminal of capacitor C3 is coupled to the first terminal of capacitor C2. The second terminal of capacitor C2 is coupled to the input of the FB channel RX circuit system 226. The output of the FB channel RX circuit system 226 is coupled to the feedback input of the power controller 220.

[0039] In this example, the FB channel TX circuit system 228 and the FB channel RX circuit system 226 include circuitry for transmitting digital signals (in this case, FB (also known as FB data)) across a communication channel containing capacitors C2 and C3 and an isolation barrier 240. In a particular example, the communication channel is a dedicated channel for FB data. Furthermore, in this example, the FB channel TX circuit system 238 and the FB channel RX circuit system 226 include circuitry employing an on-off keying (OOK) modulation scheme to transmit FB data across the communication channel. For example, the FB channel TX circuit system 238 transmits a high-frequency (e.g., 35 MHz) carrier wave across the communication channel to indicate one state and does not transmit a signal to indicate another state. The speed of the communication channel enables a fast transient response of system 200. The FB channel RX circuit system 226 demodulates the signal after signal conditioning and generates an output to power controller 220 via a buffer stage. Example FB channel TX circuit system 228 includes an electrostatic discharge (ESD) / buffer amplifier, an oscillator, logic for facilitating OOK modulation, and TX signal conditioning circuitry. Correspondingly, the example FB channel RX circuit system 226 includes an RX signal conditioning circuit, an envelope detector that may include rectifier circuitry and comparator circuitry, and an ESD / buffer amplifier.

[0040] Figure 3 It is a description Figure 2 The simplified block diagram and schematic diagram of system 200 shown in the figure will be used to explain the regulation of V by system 200. ISO The operation of ripple amplitude and ripple frequency. That is, the power path of converter 202 in Figure 3 The representation in the middle is a voltage-dependent current source I. SRC 300, which has a finite impedance R4 connected in parallel with it between nodes 207 and 211. Furthermore, current source I... SRC Its conduction (or on / off state) is controlled by switch SW1 coupled between nodes 201 and 205, wherein switch SW1 opens and closes at a switching frequency. For example, the switching frequency is approximately 50 kHz.

[0041] Hysteresis control circuit system 208 provides V ISOClosed-loop control of the ripple amplitude. More specifically, comparator 224 provides a signal FB, used by power controller 220 to control SW1, thereby adjusting the ripple amplitude. That is, comparator 224 receives V... ISO Compare V at node 215 ISO A small portion of the voltage is compared with the upper and lower threshold values ​​of the hysteresis window to generate the FB. The FB (or its representation, such as FB data) is transmitted over the communication channel (as previously described). The power controller 220 uses the FB to adjust the duty cycle of SW1 to regulate the ripple amplitude relative to the upper and lower threshold values ​​of the hysteresis window. As shown, the upper and lower threshold values ​​are set by a series resistor ladder network including resistors R1, R2, and R3.

[0042] In this example, FB is a digital signal that switches or transitions between logic high and low signal levels (e.g., between logic level 1 and logic level 0) at a switching frequency. In this example, FB transitions from logic high to logic low when the voltage at node 215 exceeds the upper voltage threshold. In response, corresponding to the disconnection of converter 202, power controller 220 turns switch SW1 to the off state to stop current source I. SRC In this way, V ISO Pull low. Conversely, when the voltage at node 215 falls below the lower limit voltage threshold, FB transitions from logic low to logic high. In response, corresponding to converter 202 being turned on, power controller 220 turns switch SW1 to the on state to provide current source I. SRC In this way, V ISO Push it up.

[0043] Hysteresis controller 210 provides V by adjusting the hysteresis window of comparator 224. ISO Closed-loop control of the ripple frequency. In this example, the hysteresis controller 210 adjusts the hysteresis window by adjusting the value of resistor R2. More specifically, the hysteresis controller 210: monitors or detects the frequency of FB (referred to as FB). freq ), its indicator V ISO Ripple frequency; compare FB freq (or a small part thereof) with f ref The comparator 224 provides an adjustment signal and / or value HYST_VAL based on the comparison. In one example, HYST_VAL is a digital signal or code indicating or transmitting a discrete value. Alternatively, HYST_VAL is an analog signal or value. HYST_VAL is used to change the value of resistor R2. Therefore, comparator 224 can be considered as a voltage-to-frequency converter of hysteresis output regulator 206. Correspondingly, hysteresis controller 210 can be considered as a frequency-to-voltage converter of hysteresis output regulator 206.

[0044] In the example, when FBfreq (or a small portion thereof) exceeds f ref At this time, the hysteresis controller 210 provides an adjustment signal HYST_VAL to change the value of resistor R2 relative to V. ref Expanding the hysteresis window. Expanding the hysteresis window leads to a decrease in ripple frequency. However, when FB... freq (or a small portion thereof) fell below f ref At this time, the hysteresis controller 210 provides an adjustment signal HYST_VAL to change the value of resistor R2 relative to V. ref Shrink or tighten the hysteresis window. Shrinking the hysteresis window increases the ripple frequency.

[0045] Figure 4 Plot multiple curves; their descriptions can be found in... Figure 2 and 3 The circuitry in the diagram uses a specific hysteresis value during operation to maintain the ripple frequency of the regulated DC output signal within a target level or range. Seven curves, labeled HYST_1 to HYST_7, are shown. Each curve corresponds to a different HYST_VAL (in this case, a numeric code) and illustrates the relationship between the ripple frequency and %I for different hysteresis window steps. LOAD / I SRC The graph shows the hysteresis window size. In this example, the hysteresis window size increases with the HYST_VAL numeric code. Therefore, HYST_1 corresponds to the smallest hysteresis window that produces the highest ripple frequency, and HYST_7 corresponds to the largest hysteresis window that produces the minimum ripple frequency.

[0046] In this example, and as shown in the figure, the hysteresis controller 210 can change HYST_VAL between digital codes HYST_1 and HYST_7 to maintain the ripple frequency (labeled as curve 400) between the upper frequency threshold f1 (labeled as 402) and the lower frequency threshold f2 (labeled as 404). As shown in the figure, the hysteresis controller 210 can use a hysteresis window (relative to f) ref To operate to minimize or prevent f ref The frequency hysteresis window provides some stability to the hysteresis output regulator 206 due to multiple transitions (or oscillations). Alternatively, a single frequency threshold can be used, at which the hysteresis controller 210 maintains a constant or substantially constant ripple frequency.

[0047] In another example, to improve system stability, the hysteresis output regulator 206 is implemented as a unipolar system. In one example of a unipolar system, the voltage-to-frequency conversion (performed by comparator 224) is slower than the frequency-to-voltage conversion (performed by the hysteresis controller 210). Alternatively, in a unipolar system, the frequency-to-voltage conversion is slower than the voltage-to-frequency conversion.

[0048] In one example of a single-pole system, the hysteresis controller 210 is configured to have a "weak" pole relative to the comparator 224, wherein the hysteresis controller 210 slowly adjusts the hysteresis window relative to the frequency of the FB signal. For example, the hysteresis controller 210 adjusts the hysteresis window every four to five cycles (e.g., on / off cycles) of the FB signal. In another example, the hysteresis controller 210 has low gain, wherein the hysteresis controller 210 changes only one code value of HYST_VAL at a time, i.e., changes to the next highest code value or the next lowest code value.

[0049] Figure 5 This is a block diagram and schematic diagram depicting an example system 500 including a circuit system for adaptive hysteresis control of a power converter. System 500 includes a power converter and control circuit system 502, a digital communication circuit system 504, a hysteresis output regulator 506, and decoupling capacitors C having first and second (capacitor) terminals coupled to corresponding first and second plates. DE-CAP and a load 534 having first and second terminals. The load 534 is in Figure 5 Described as a variable current source I L This represents the current drawn by load 534. System 500 can be integrated into a single IC or IC package built on a monolithic silicon substrate. Alternatively, system 500 can be integrated into multiple ICs and / or multiple IC packages (each package having one or more ICs), wherein the multiple ICs or IC packages are coupled to or mounted on a PCB. In another instance, one or more of the passive components in system 500 (e.g., capacitors and resistors) are discrete components.

[0050] In this example, the power converter and control circuit system 502 is implemented in the same or similar manner. Figure 2 and 3 The quasi-resonant DC-DC isolated converter 202 (including isolation barrier 540) and control circuit system 204 described above are explained in the text. Therefore, the power path of the power converter and control circuit system 502 can be represented as a voltage-dependent current source I with finite impedance (not shown). SRC 536, where current source I SRC Its conduction (or on / off state) is controlled by a switch (not shown) at a switching frequency (e.g., 50 kHz). Current source I coupled to node 511. SRC The first terminal represents the ground terminal of the power converter and control circuit system 502, wherein the ground terminal is coupled to electrical ground. Current source I is coupled to node 507. SRC The second terminal indicates that it provides an regulated DC output voltage V. ISOOUTThe output of the power converter and control circuit system 502. Furthermore, in this example, the digital communication circuit system 504 is implemented in the same or similar manner. Figure 2 and 3 The circuit system comprising the FB channel RX circuit system 226, the FB channel TX circuit system 228, and the isolation capacitors C2 and C3 as described above.

[0051] In one example, the hysteresis output regulator 506 is Figure 2 and 3 An embodiment of the hysteresis output regulator 206 includes a hysteresis control circuit system 508, a hysteresis controller 510, and an oscillator circuit (or simply oscillator) 530. The hysteresis control circuit system 508 includes: a comparator 524 with hysteresis; resistors R5, R6, and R7, each having corresponding first and second (resistor) terminals, wherein resistor R6 has an adjustable resistance (and is therefore called an adjustable resistor); and a voltage source 526 providing a reference voltage V. ref The system includes an interference filter 520 and switches SW2 and SW3, each having a corresponding control terminal and corresponding first and second (switch) terminals. In this example, comparator 524 is implemented as an inverting comparator. However, in an alternative example, comparator 524 is implemented as a non-inverting comparator. Furthermore, switches SW2 and SW3 may be implemented as transistors used as switches. Additionally, in this example, the hysteresis controller 510 is implemented as digital circuitry, including a feedback (FB) divider circuit 512 (also referred to herein as FB divider circuit 512) and digital synchronization and logic 514. Digital synchronization and logic 514 includes circuitry serving at least as an edge detector, a counter, and a digital comparator. Although not shown, the digital comparator includes a first (comparator) input coupled to the FB divider 512, a second (comparator) input coupled to the oscillator 530, and a (comparator) output coupled to resistor R6.

[0052] As shown in the figure, the first terminal of load 534 is coupled to node 507 to receive V. ISOOUT The second terminal of load 534 is coupled to electrical ground at node 511. When receiving V ISOOUT At that time, load 534 draws current I L Capacitor C DE-CAP The first terminal is coupled to node 507, and capacitor C DE-CAPThe second terminal of resistor R5 is coupled to node 511. Resistors R5, R6, and R7 are coupled in series between nodes 507 and 511. That is, the first terminal of resistor R5 is coupled to node 507. The second terminal of resistor R5 is coupled to the first terminal of resistor R6 at node 515. The second terminal of resistor R6 is coupled to the first terminal of resistor R7 at node 517, and the second terminal of resistor R7 is coupled to node 511.

[0053] Furthermore, the first terminal of switch SW2 is coupled to node 515, and the first terminal of switch SW3 is coupled to node 517. The corresponding second terminals of switches SW2 and SW3 are coupled at node 501 to the inverting input of comparator 524. The non-inverting input of comparator 524 is coupled to the output of voltage source 526. The input of voltage source 526 is coupled to node 507. The output of comparator 524 is coupled at node 503 to the input of interference filter 520. The output of interference filter 520 is coupled at node 509 to the input of digital communication circuit system 504, the input of FB divider 512, and the corresponding control terminals of switches SW2 and SW3. The output of digital communication circuit system 504 is coupled to the input of power converter and control circuit system 502. The output of FB divider 512 is coupled at node 505 to the (frequency) input of digital synchronization and logic 514. The (reference) input of digital synchronization and logic 514 is coupled to the reference frequency f provided therein. ref The (reference) output of oscillator 530 is shown. In this example, oscillator 530 is a 2.5 MHz oscillator. Finally, the output of digital synchronization and logic 514 is coupled to resistor R6 at node 513.

[0054] Reference Figure 6 Describe the operation of system 500. Figure 6 The diagrams depict the signals V respectively. ISOOUT FB, FB_DIV2 (where FB is the frequency of FB) freq Divide by 2), FB_DIV4 (which is FB) freq Divide by 4), HYST_VAL and V ISOOUT The digital timing diagrams for the ripple frequency are shown in Figures 602 to 612. Some of these signals are in... Figure 5 The instruction is in the middle. In this example, HYST_VAL can have Figure 4 The numerical value indicated in the text.

[0055] Hysteresis control circuit system 508 provides V ISOOUT Closed-loop control of the ripple amplitude. More specifically, comparator 524 compares V at node 515. ISOA small portion of the voltage is compared with the upper or lower threshold of the hysteresis window (depending on whether switch SW1 or SW2 is closed) to generate a signal based on comparison. The upper and lower threshold voltages are set by a series resistor ladder network including resistors R5, R6, and R7 and provided to comparator 524 based on the states of switches SW2 and SW3. That is, when switch SW2 is closed and switch SW3 is open, the lower threshold voltage is provided at the non-inverting input of comparator 524. Therefore, comparator 524 compares the voltage at node 515 with the lower threshold. Conversely, when switch SW2 is open and switch SW3 is closed, the upper threshold voltage is provided at the non-inverting input of comparator 524. Therefore, comparator 524 compares the voltage at node 517 with the upper threshold.

[0056] The signal output from comparator 524 is provided to interference filter 520. Interference filter 520 filters "short" pulses from the output signal of comparator 524, which have a pulse width less than the minimum acceptable pulse width. This filtering removes pulses that can reduce the efficiency of the power converter and control circuitry system 502. In this example, signal FB is the filtered signal from the output of interference filter 520. In another example, system 500 does not include interference filter 520. In this example, signal FB comes directly from the output of comparator 524. FB (or its representation, such as FB data) is transmitted via the communication channel (not shown) of digital communication circuitry system 504. FB is used to adjust the duty cycle of the switching circuitry system (not shown) power converter and control circuitry system 502 to regulate the ripple amplitude relative to the upper and lower voltage thresholds of the hysteresis window.

[0057] In this example, FB is a digital signal that switches or transitions between logic high and low signal levels (e.g., between logic level 1 and logic level 0) at a switching frequency. In this example, FB transitions from logic high to logic low when the voltage at node 517 exceeds the upper voltage threshold. In response, the power converter (not shown) of the power converter and control circuitry system 502 disconnects to stop the current source I. SRC In this way, V ISOOUT Pull low. Conversely, when the voltage at node 515 falls below the lower limit voltage threshold, FB transitions from logic low to logic high. In response, the power converter turns on to provide current source I. SRC In this way, V ISOOUT Pushing up. Additionally, FB provides corresponding control terminals to switches SW2 and SW3. When FB is logic low, switch SW3 is closed and switch SW2 is open to provide an upper limit voltage threshold at node 501. Conversely, when FB is logic high, switch SW3 is open and switch SW2 is closed to provide a lower limit voltage threshold at node 501.

[0058] Hysteresis controller 510 provides V by adjusting the hysteresis window of comparator 524. ISOOUT Closed-loop control of the ripple frequency. In this example, the hysteresis controller 510 adjusts the hysteresis window by digitally adjusting the value of resistor R6. More specifically, the FB divider 512 makes the frequency of FB (referred to as FB)... freq And its indicator V ISOOUT The ripple frequency is divided by 4 to generate the signal FB_DIV4. This frequency division provides stability to the hysteresis output regulator 506 by giving the hysteresis controller 510 a weaker polarity relative to the comparator 524. Although in this example, the FB divider 512 makes FB... freq Divide by 4, but instead, the FB divider 512 makes FB... freq Divide by another integer value (e.g., 2), as illustrated by curve 606 depicting the FB_DIV2 signal.

[0059] The digital synchronous and logic circuit system 514 includes a digital comparator that compares FB_DIV4 with f ref And it provides an adjustment signal and / or value HYST_VAL based on comparison. In this example, HYST_VAL is, for example, from... Figure 4 The code described herein selects a digital signal or code that indicates or transmits a corresponding discrete value to resistor R6. In a specific instance, at each rising edge of the FB_DIV4 signal (e.g., as indicated by...), Figure 6 At point 614 (not shown), the counter (not shown) counts the number of clock pulses from oscillator 530 within the high pulse of FB_DIV4 and compares said number with the number based on f ref The upper and lower frequency thresholds. For example, for 2.5 MHz f ref The upper and lower frequency thresholds are 26 and 24, respectively. A higher counter value indicates a lower ripple frequency value, and a lower counter value indicates a higher ripple frequency value. Based on the comparison results, the digital synchronization and logic circuit system 514 determines the ripple frequency value at the falling edge of the high pulse of FB_DIV4 (e.g., as indicated by...). Figure 6 The HYST_VAL signal is then supplied to resistor R6 after the 616 indicator in the code. Therefore, in this example, the hysteresis window is updated every four FB signals.

[0060] In this example, when FB_DIV4 drops below 24, the digital synchronization and logic circuit system 514 decreases HYST_VAL to change the value of resistor R6 relative to V. ref Shrinking the hysteresis window. Shrinking the hysteresis window leads to an increase in ripple frequency. However, when FB_DIV4 rises above 26, the digital synchronization and logic circuitry system 514 increases HYST_VAL to change the value of resistor R6 relative to V. refExpanding the hysteresis window increases the ripple frequency. In this example, frequency hysteresis is used to minimize the ripple frequency around f. ref The oscillation. Alternatively, a single reference frequency value is used to maintain or substantially maintain the ripple frequency at a constant frequency.

[0061] like Figure 6 The text further explains that at time 0 microseconds (µsec), HYST_VAL has an initial value of 7 to produce the maximum or widest hysteresis window. However, HYST_VAL can have any suitable initial value. The counter value of the first FB_DIV4 high pulse is 54, which is greater than the upper frequency threshold 26. Therefore, after the falling edge of this high pulse, the digital synchronization and logic circuitry system 514 reduces HYST_VAL to 6, which tightens the hysteresis window and increases the ripple frequency, as indicated by curve 612. During the shown period, the counter value continues to exceed the upper frequency threshold, except that the counter value of the last FB_DIV4 high pulse shown is 26. Therefore, the digital synchronization and logic circuitry system 514 reduces HYST_VAL to a minimum value and maintains it at that value until the counter value drops below the lower frequency threshold 24 (not shown), where the digital synchronization and logic circuitry system 514 will begin to increase HYST_VAL. Furthermore, during the shown period, the ripple amplitude (as indicated by V...) ISOOUT Curve 602 indicates that the voltage stabilized from about 56 millivolts (mV) at power-up to about 29 mV, and the ripple frequency stabilized from about 100 kHz at startup to about 200 kHz.

[0062] Figure 7 Depicting Figure 5 The example simulation result 700 of the system 500 over time shows the load sweep of the system 500, illustrating the ripple frequency maintained within the target range. Curve 702 indicates the plot of % load current. Vertical line 714 indicates 20% I... L / I SRC (or 20% load current), and the vertical line 716 indicates 80% I. L / I SRC (or 80% load current). Curve 704 indicates V. ISOOUT The ripple frequency. Graph 718 indicates the counter value determined by the digital synchronization and logic circuitry system 514, and graph 720 indicates HYST_VAL determined by the digital synchronization and logic circuitry system 514. In this example, the upper frequency threshold is 26 and the lower frequency threshold is 24.

[0063] As indicated by the curves and graphs, HYST_VAL is 1 at 1 millisecond (ms), corresponding to the tightest hysteresis window. At 1 ms, the counter value is 63, which exceeds the upper frequency threshold. Therefore, the digital synchronization and logic circuitry system 514 keeps HYST_VAL 1 for a period of time to allow FB. freq The ripple frequency continues to increase. Between 20% and 80% of the load current, the digital synchronization and logic circuitry system 514 operates to limit the ripple frequency to approximately 220 kHz to 260 kHz by adjusting HYST_VAL accordingly. The ellipses labeled 706, 708, 710, and 712 indicate the time during which the digital synchronization and logic circuitry system 514 changes HYST_VAL to adjust the ripple frequency. Subsequently, after 80% load current, the ripple frequency decreases again, even at lower HYST_VAL and corresponding tightest hysteresis window. Figure 7 The performance indicated in this model contrasts with systems that lack frequency-based adaptive hysteresis, such as those using PWM for output signal conditioning. For example, in a PWM system, the ripple frequency can steadily increase until it reaches its maximum value at 50% load, after which the ripple frequency then steadily decreases.

[0064] Figure 8 Describing for Figure 5 The example simulation results of system 500 shown in the figure 800 illustrate the application of multiple decoupling capacitors C. DE-CAP The value is plotted as a percentage of the load current (up to 50%), representing the ripple amplitude. In curve 802, C... DE-CAP It is 10 microfarads (µF). In curve 804, C DE-CAP It is 20 µF. In curve 806, C DE-CAP It is 40 µF. In curve 808, C DE-CAP The value is 100µF. These curves illustrate that the ripple amplitude in system 500 is proportional to the load current, similar to a system using hysteresis control with a fixed hysteresis window for output signal conditioning. That is, as the percentage of load current increases, even at the indicated maximum C... DE-CAP At this value, the ripple amplitude was also controlled within 30 mV. Furthermore, at lower C values... DE-CAP At this value, very good ripple amplitude is achieved, for example, within 20 mV.

[0065] Figure 9 Describing for Figure 5 The simulation results of System 500 shown in the figure illustrate the application of multiple decoupling capacitors C. DE-CAP The ripple frequency is plotted as a percentage of the load current. In curve 902, C... DE-CAP It is 10 microfarads (µF). In curve 904, C DE-CAPIt is 20 µF. In curve 906, C DE-CAP It is 40 µF. In curve 908, C DE-CAP The value is 100 µF. These curves illustrate that, unlike using a fixed hysteresis control window for output signal conditioning, System 500 also provides multiple C... DE-CAP This value provides tighter control over the ripple frequency. In certain circuit implementations of System 500, a minimum load is required to achieve the desired frequency range. However, this is application-specific and at least partially dependent on one or more parameters, such as the selected frequency, C... DE-CAP Values, etc.

[0066] Figure 10 This is a block diagram and schematic representation of an example system 1000 containing a circuit system for adaptive hysteresis control of a power converter. System 1000 may be integrated into a single IC or IC package built on a monolithic silicon substrate. Alternatively, system 1000 may be integrated into multiple ICs and / or multiple IC packages (each package having one or more ICs), wherein the multiple ICs or IC packages are coupled to or mounted on a PCB. In another example, one or more of the passive components in system 500 (e.g., capacitors and resistors) are discrete components.

[0067] System 1000 includes a power converter and control circuit system 502, a digital communication circuit system 504, a hysteresis output regulator 1006, and decoupling capacitors C having first and second (capacitor) terminals coupled to the respective first and second plates. DE-CAP and a load 534 having first and second terminals. The hysteresis output regulator 1006 includes a hysteresis control circuit system 508 and a hysteresis controller 1010. As indicated by the same reference digit, the power converter and control circuit system 502, the digital communication circuit system 504, the hysteresis control circuit system 508, and the decoupling capacitor C... DE-CAP and load 534 is coupled within system 1000 and as referenced Figure 5 The implementation is as described. However, in this example, the hysteresis controller 1010 has a simulated implementation.

[0068] That is, the hysteresis controller 1010 includes a low-pass filter 1012 and an analog comparator 1014. In this example, the low-pass filter 1012 is an RC low-pass filter including one or more resistors and one or more capacitors. As shown, the input of the low-pass filter 1012 is coupled to node 509, and the output of the low-pass filter 1012 is coupled to the inverting input of the comparator 1014 at node 1001. The non-inverting input of the comparator 1014 is coupled to the non-inverting input of the comparator 524 and the output of the voltage source 526. The output of the comparator 1014 is coupled to resistor R6 at node 513. Furthermore, in this example, the comparator 1014 is implemented as an inverting comparator. However, in an alternative example, the comparator 1014 is implemented as a non-inverting comparator. In addition, in one example, the comparator 1014 may include hysteresis.

[0069] During operation, the RC low-pass filter 1012 acts as a frequency-to-voltage converter, at least in part dependent on the RC time constant set for the filter. In this example, higher frequencies of the FB signal decrease the output voltage of the RC low-pass filter 1012, while lower frequencies of the FB signal increase the output voltage of the RC low-pass filter 1012. Therefore, when the frequency of the FB signal is higher than a reference frequency value, the output voltage of the RC low-pass filter 1012 will be lower than V. ref This causes comparator 1014 to provide an adjustment value, which changes resistor R6 to increase the hysteresis window and reduce the ripple frequency. Conversely, when the frequency of the FB signal is lower than the reference frequency, the output voltage of the RC low-pass filter 1012 will be higher than V. ref This causes comparator 1014 to provide an adjustment value, which changes resistor R6 to reduce the hysteresis window and increase the ripple frequency.

[0070] Figure 11 This is a flowchart depicting a method 1100 for adaptive hysteresis control of a power converter. For example, method 1100 is performed by one or more of the systems 100, 200, 300, 500, or 1000 described above. Method 1100 includes the functionality shown in blocks 1102 through 1110, but may include additional functionality not described herein, but consistent with one or more of the systems described herein or with additional systems consistent with the example systems described herein.

[0071] As shown in the figure, according to method 1100, the system (in block 1102) receives an output signal. For example, the output signal is or is based on the signal at the output of the power converter. For example, a voltage ladder circuit provides the output signal to a first comparator. The output signal is a small portion of the signal at the output of the power converter. The first comparator (in block 1104) compares the output signal with a hysteresis window and responsively generates a feedback signal with a frequency. In one example, the feedback signal appears at the output of the first comparator. In another example, the signal at the output of the first comparator is filtered by an interference filter, and the feedback signal appears at the output of the interference filter.

[0072] The second comparator (digital or analog comparator) (in box 1106) compares a first value indicating the frequency with a reference frequency value and responds by generating an adjustment value. In one example, the first value is contained in the signal at the output of the frequency divider. In another example, the first value is contained in the signal at the output of the low-pass filter. In yet another example, the first value is the frequency of the feedback signal. Furthermore, in this example, the second comparator has hysteresis. Therefore, the reference frequency value is a first threshold of the frequency hysteresis window, which also contains a second threshold.

[0073] The system (in block 1108) adjusts the hysteresis window based on an adjustment value to maintain the frequency of the signal at the output of the power converter within one or more threshold frequency values. For example, adjusting the hysteresis window includes adjusting the resistance of an adjustable resistor based on the adjustment value. Furthermore, the system (in block 1110) provides a feedback signal to a control circuit coupled to the control input of the power converter circuit to regulate the signal at the output of the power converter so that the amplitude of the signal is maintained within the hysteresis window.

[0074] In the detailed description and claims, unless otherwise stated, the terms "comprising" and "having," and variations thereof, are intended to be inclusive in a manner similar to the term "comprising." Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the value. In another instance, "about," "approximately," or "substantially" preceding a value means + / - 5% of the value. In yet another instance, "about," "approximately," or "substantially" preceding a value means + / - 1% of the value.

[0075] As used herein, the terms “coupled,” “coupling,” and variations thereof may cover a connection, communication, or signal path that achieves a functional relationship consistent with this specific embodiment. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B; or in a second instance, if intermediate component C substantially does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C, such that device B is controlled by the control signal generated by device A. Furthermore, the terms “coupled,” “coupling,” and variations thereof include indirect or direct electrical or mechanical connections.

[0076] A device "configured" to perform a task or function may be configured by the manufacturer at the time of manufacture (e.g., programming and / or hardwiring) to perform the function, and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0077] As used herein, a “terminal” for a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component refers to a conductor, such as a wire, trace, pin, pad, or other connector or interconnect that enables the component, device, system, etc., to be electrically and / or mechanically connected to another component, device, system, etc. For example, terminals may be used to receive or provide analog or digital electrical signals (or simply signals) or to be electrically connected to a common or ground reference. Thus, an input terminal or input is used to receive signals from another component, device, system, etc. An output terminal or output is used to provide signals to another component, device, system, etc. Other terminals may be used to connect to a common, ground, or voltage reference, such as a reference terminal or ground terminal. Terminals on an IC or PCB may also be referred to as pins (vertical conductors) or pads (planar conductors). A node refers to a connection point or interconnect of two or more terminals. The number of instances of terminals and nodes is shown. However, depending on the specific circuit or system topology, there may be more or fewer terminals and nodes. The terms “terminal,” “node,” “interconnect,” “pad,” and “pin” are used interchangeably.

[0078] Within the scope of the claims, the described instances may be modified, and other instances are also possible.

Claims

1. A circuit system comprising: A first control circuit, having an output and including: A resistor having adjustable resistance, a control input, and a first terminal and a second terminal; A first comparator having a hysteresis window that is adjustable in response to changes in the resistance of the resistor, the first comparator having an input; A first switch having a control terminal coupled to the output of the first control circuit, wherein the first switch is coupled between the first terminal of the resistor and the input of the first comparator; and A second switch having a control terminal coupled to the output of the first control circuit, wherein the second switch is coupled between the second terminal of the resistor and the input of the first comparator; and A second control circuit, coupled to the output of the first control circuit, includes a second comparator having an output coupled to the control input of the resistor, and the second comparator is configured to: Compare a first value with a reference value, where the first value indicates the frequency of the signal at the output of the first control circuit; and An adjustment value is provided to adjust the resistance of the resistor.

2. The circuit system of claim 1, wherein the resistor is a first resistor, and the first control circuit further comprises: A second resistor having a terminal coupled to the first terminal of the first resistor; and A third resistor has a terminal coupled to the second terminal of the first resistor.

3. The circuit system of claim 2, wherein the first comparator has an output, and the first control circuit further includes a filter circuit having an input and an output, the input of the filter circuit being coupled to the output of the first comparator, and the output of the filter circuit being coupled to the second control circuit.

4. The circuit system of claim 2, wherein the input of the first comparator is a first input, the first comparator has a second input, and the first control circuit further includes a voltage reference source coupled to the second input of the first comparator.

5. The circuit system of claim 1, wherein the second comparator is a digital comparator.

6. The circuit system of claim 5, wherein the digital comparator has an input, and the second control circuit further includes a frequency divider circuit coupled between the output of the first control circuit and the input of the digital comparator.

7. The circuit system of claim 6, wherein the input of the digital comparator is a first input, the digital comparator has a second input, and the circuit system further includes an oscillator circuit coupled to the second input of the digital comparator.

8. The circuit system of claim 1, wherein the input of the first comparator is a first input, the first comparator has a second input, the second comparator is an analog comparator having a first input and a second input, the second input of the first comparator and the first input of the second comparator are coupled together, and the second control circuit further comprises: A low-pass filter is coupled between the output of the first control circuit and the second input of the second comparator.

9. A circuit system comprising: The first circuit includes: A power converter having a control input, a ground input, and a converter output; and A first control circuit has a feedback input and a control output, wherein the control output is coupled to the control input; A second control circuit having a feedback output coupled to the feedback input, the second control circuit comprising: A first resistor having a first terminal and a second terminal, the second terminal being coupled to the output of the converter; The second resistor has an adjustable resistance, has a first terminal coupled to the first terminal of the first resistor, has a second terminal and a control input; A third resistor has a second terminal coupled to the second terminal of the second resistor and a first terminal coupled to the ground input; A first comparator having a hysteresis window that is adjustable in response to changes in the resistance of the second resistor; and A third control circuit, coupled to the feedback output, includes a second comparator having an output coupled to the control input of the second resistor, the second comparator being configured to: Compare a first value with a reference value, where the first value indicates the frequency of the signal at the feedback output; and An adjustment value is provided to adjust the resistance of the second resistor.

10. The circuit system of claim 9, wherein the first comparator has an input, and the second control circuitry further comprises: A first switch is coupled between the first terminal of the second resistor and the input of the first comparator; and A second switch is coupled between the second terminal of the second resistor and the input of the first comparator.

11. The circuit system of claim 9, wherein the second control circuit further comprises a filter circuit having an input and an output, the input of the filter circuit being coupled to the output of the first comparator, and the output of the filter circuit being coupled to the third control circuit.

12. The circuit system of claim 9, wherein the second comparator is a digital comparator.

13. The circuit system of claim 12, wherein the third control circuit further comprises a frequency divider circuit coupled between the feedback output and the input of the digital comparator.

14. The circuit system of claim 9, wherein the input of the first comparator is a first input, the first comparator has a second input, the second comparator is an analog comparator having the first and second inputs, the second input of the first comparator and the second input of the second comparator are coupled together, and the third control circuit further comprises: A low-pass filter is coupled between the feedback output and the first input of the second comparator.

15. A method for operating the circuit system of claim 1, the method comprising: Receive output signals; The output signal is compared with the hysteresis window and a feedback signal is generated responsively, the feedback signal having a frequency. The system compares a first value indicating the frequency with a reference frequency value and generates an adjustment value in response. The hysteresis window is adjusted based on the adjustment value.

16. The method of claim 15, wherein the reference frequency value is a first threshold that further includes a frequency hysteresis window containing a second threshold.

17. The method of claim 15, wherein the first value is included in the signal at the output of the frequency divider.

18. The method of claim 15, wherein the first value is included in the signal at the output of the low-pass filter.

19. The method of claim 15, wherein the output signal is based on a signal at the output of the power converter circuit, and the method further comprises providing the feedback signal to a control circuit coupled to a control input of the power converter circuit.

20. The method of claim 15, wherein adjusting the hysteresis window comprises adjusting the resistance of the adjustable resistor based on the adjustment value.

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