Method for manufacturing an image display device and image display device

Abstract

The manufacturing method of the image display device according to the embodiment includes: a step of preparing a second substrate on which a semiconductor layer is formed on a first substrate; a step of bonding the semiconductor layer to the third substrate; a step of removing the first substrate; a step of etching the semiconductor layer to form a light-emitting element including a light-emitting surface facing the bottom surface on the third substrate; a step of forming a first insulating film covering the third substrate and the light-emitting element; a step of forming circuit elements on the first insulating film; a step of forming a second insulating film covering the circuit elements and the first insulating film; a step of removing a part of the first insulating film and the second insulating film to expose the surface including the light-emitting surface; a step of forming vias penetrating the first and second insulating films; and a step of forming a wiring layer on the second insulating film.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Art

[0002] There is a need for a thin image display device with low power consumption, high brightness, wide viewing angle, and high contrast. In response to such market requirements, the development of display devices using self-luminous elements is being promoted.

[0003] As a self-luminous element, the appearance of a display device using a fine light-emitting element, i.e., a micro LED, is expected. As a method for manufacturing a display device using a micro LED, a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced. However, as the image quality becomes full high definition or 4K, 8K, etc., if the number of micro LED elements increases, a large amount of time is required for the transfer process when a large number of micro LEDs are individually formed and sequentially transferred to a substrate on which a drive circuit or the like is formed. In addition, poor contact between the micro LED and the drive circuit or the like may occur, resulting in a decrease in the yield.

[0004] There is known a technique of growing a semiconductor layer including a light-emitting layer on a Si substrate, forming electrodes on the semiconductor layer, and then bonding the semiconductor layer to a circuit substrate on which a drive circuit is formed (for example, refer to Patent Document 1).

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent Laid-Open No. 2002-141492 Summary of the Invention

[0008] Technical Problem to be Solved by the Invention

[0009] One embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer process of light-emitting elements and improves the yield.

[0010] Technical Solution for Solving the Technical Problem

[0011] A manufacturing method of an image display device according to an embodiment of the present invention includes: a step of preparing a second substrate having a semiconductor layer including a light-emitting layer formed on a first substrate; a step of forming a first metal layer on a third substrate; a step of bonding the semiconductor layer to the first metal layer; a step of removing the first substrate; a step of etching the semiconductor layer to form a light-emitting element including a bottom surface on the first metal layer and a light-emitting surface disposed opposite to the bottom surface; a step of forming a first insulating film covering the third substrate and the light-emitting element; a step of forming circuit elements on the first insulating film; a step of forming a second insulating film covering the circuit elements and the first insulating film; a step of removing a part of the first insulating film and a part of the second insulating film to expose the surface including the light-emitting surface; a step of forming a wiring layer on the second insulating film.

[0012] A manufacturing method of an image display device according to an embodiment of the present invention includes: a step of preparing a second substrate having a semiconductor layer including a light-emitting layer formed on a first substrate; a step of forming a second metal layer on the second substrate; a step of bonding the semiconductor layer to a third substrate via the second metal layer; a step of removing the first substrate; a step of etching the semiconductor layer to form a light-emitting element including a bottom surface on the second metal layer and a light-emitting surface disposed opposite to the bottom surface; a step of forming a first insulating film covering the third substrate and the light-emitting element; a step of forming circuit elements on the first insulating film; a step of forming a second insulating film covering the circuit elements and the first insulating film; a step of removing a part of the first insulating film and a part of the second insulating film to expose the surface including the light-emitting surface; a step of forming a wiring layer formed on the second insulating film.

[0013] An image display device according to an embodiment of the present invention includes: a substrate having a first surface; a conductive layer provided on the first surface; a light-emitting element having a bottom surface on the conductive layer and including a surface opposite to the bottom surface, i.e., a light-emitting surface; a first insulating film covering the side surface of the light-emitting element and the conductive layer; circuit elements provided on the first insulating film; a second insulating film covering the circuit elements and the first insulating film; a wiring layer provided on the second insulating film.

[0014] An image display device according to an embodiment of the present invention includes: a substrate having a first surface; a conductive layer provided on the first surface; a semiconductor layer having a bottom surface on the conductive layer and including a plurality of light-emitting surfaces on a surface opposite to the bottom surface; a first insulating film covering the side surfaces of the semiconductor layer and the conductive layer; a plurality of transistors provided on the first insulating film; a second insulating film covering the plurality of transistors and the first insulating film; and a wiring layer provided on the second insulating film.

[0015] Advantageous Effects of the Invention

[0016] According to an embodiment of the present invention, a method for manufacturing an image display device that shortens the transfer process of light-emitting elements and improves the yield is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. is a schematic cross-sectional view showing a part of the image display device according to the first embodiment.

[0018] Figure 2 FIG. is a cross-sectional view schematically showing a part of a modified example of the image display device according to the first embodiment.

[0019] Figure 3 FIG. is a schematic block diagram illustrating the image display device according to the first embodiment.

[0020] Figure 4 FIG. is a schematic plan view illustrating a part of the image display device according to the first embodiment.

[0021] Figure 5A FIG. is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the first embodiment.

[0022] Figure 5B FIG. is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the first embodiment.

[0023] Figure 6 FIG. is a schematic perspective view illustrating the manufacturing method of the image display device according to the first embodiment.

[0024] Figure 7A FIG. is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the first embodiment.

[0025] Figure 7B FIG. is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the first embodiment.

[0026] Figure 8A FIG. is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the first embodiment.

[0027] Figure 8BIt is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0028] Figure 8C It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0029] Figure 9A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0030] Figure 9B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0031] Figure 10A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0032] Figure 10B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0033] Figure 11A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0034] Figure 11B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0035] Figure 12A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the first embodiment.

[0036] Figure 12B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the first embodiment.

[0037] Figure 13 It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0038] Figure 14A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0039] Figure 14B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0040] Figure 14C It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0041] Figure 14D It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0042] Figure 15 It is a schematic perspective view illustrating the image display device of the first embodiment.

[0043] Figure 16 It is a schematic cross-sectional view illustrating a part of the image display device of the second embodiment.

[0044] Figure 17 It is a schematic block diagram illustrating the image display device of the second embodiment.

[0045] Figure 18A It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0046] Figure 18B It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0047] Figure 18C It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0048] Figure 19A It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0049] Figure 19B It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0050] Figure 20A It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0051] Figure 20B It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0052] Figure 21A It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0053] Figure 21B It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the second embodiment.

[0054] Figure 22 It is a schematic cross-sectional view illustrating a part of the image display device of the third embodiment.

[0055] Figure 23A It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the third embodiment.

[0056] Figure 23B It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of the third embodiment.

[0057] Figure 24AIt is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the third embodiment.

[0058] Figure 24B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the third embodiment.

[0059] Figure 25A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the third embodiment.

[0060] Figure 25B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the third embodiment.

[0061] Figure 26 It is a schematic cross-sectional view illustrating a part of an image display device according to the fourth embodiment.

[0062] Figure 27A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the fourth embodiment.

[0063] Figure 27B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the fourth embodiment.

[0064] Figure 28 It is a schematic cross-sectional view illustrating a part of an image display device according to the fifth embodiment.

[0065] Figure 29A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the fifth embodiment.

[0066] Figure 29B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the fifth embodiment.

[0067] Figure 30 It is a schematic cross-sectional view illustrating a part of an image display device according to the sixth embodiment.

[0068] Figure 31A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the sixth embodiment.

[0069] Figure 31B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the sixth embodiment.

[0070] Figure 32A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the sixth embodiment.

[0071] Figure 32B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the sixth embodiment.

[0072] Figure 33AIt is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a sixth embodiment.

[0073] Figure 33B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a sixth embodiment.

[0074] Figure 34 It is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the sixth embodiment.

[0075] Figure 35A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the sixth embodiment.

[0076] Figure 35B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the sixth embodiment.

[0077] Figure 35C It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the sixth embodiment.

[0078] Figure 36A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the sixth embodiment.

[0079] Figure 36B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the sixth embodiment.

[0080] Figure 37 It is a chart illustrating the characteristics of a pixel LED element.

[0081] Figure 38 It is a block diagram illustrating an image display device according to a seventh embodiment.

[0082] Figure 39 It is a block diagram illustrating an image display device according to a modified example of the seventh embodiment. Detailed Embodiments

[0083] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0084] It should be noted that the drawings are schematic or conceptual, and the relationships between the thicknesses and widths of the respective parts, and the size ratios between the parts are not necessarily the same as those of the actual objects. In addition, when representing the same parts, there are cases where the dimensions or ratios are illustrated differently in the drawings.

[0085] It should be noted that in the specification of the present application and each drawing, the same elements as those described in the previous drawings are denoted by the same reference numerals and detailed descriptions are appropriately omitted.

[0086] (First Embodiment)

[0087] Figure 1 It is a schematic cross-sectional view showing a part of the image display device of the present embodiment.

[0088] In Figure 1 the structure of the sub-pixel 20 of the image display device of the present embodiment is schematically shown. A pixel constituting an image displayed on the image display device is composed of a plurality of sub-pixels 20.

[0089] Hereinafter, the description will sometimes be made using a three-dimensional coordinate system of XYZ. The sub-pixels 20 are arranged in a two-dimensional planar shape as described later in Figure 15 The two-dimensional plane in which the sub-pixels 20 are arranged is the XY plane. The sub-pixels 20 are arranged along the X-axis direction and the Y-axis direction. Figure 1 represents a sectional view in the direction of view of the AA' line described later in Figure 4 and is a cross-sectional view connecting cross-sections in a plurality of planes perpendicular to the XY plane with one plane. In other figures, as in Figure 1 shown, in the cross-sectional views in a plurality of planes perpendicular to the XY plane, the X-axis and the Y-axis are not shown, and only the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z-axis is the XY plane. It should be noted that, for convenience, the positive direction of the Z-axis is sometimes referred to as "up" or "above", and the negative direction of the Z-axis is referred to as "down" or "below", but the direction along the Z-axis is not necessarily the direction in which gravity is applied. In addition, the length in the direction along the Z-axis is sometimes referred to as the height.

[0090] The sub-pixel 20 has a light-emitting surface 151S substantially parallel to the XY plane. The light-emitting surface 151S is mainly a surface that emits light toward the positive direction of the Z-axis orthogonal to the XY plane.

[0091] As Figure 1 shown, the sub-pixel 20 of the image display device includes a substrate 102, a conductive layer 130, a light-emitting element 150, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, and a wiring layer 110.

[0092] In the present embodiment, the substrate 102 on which the light-emitting element 150 is formed is a light-transmissive substrate, such as a glass substrate. The substrate 102 has a first surface 102a. The first surface 102a is a surface substantially parallel to the XY plane. The light-emitting element 150 is formed on the first surface 102a. The light-emitting element 150 is driven by a transistor 103 provided via the first interlayer insulating film 156. The transistor 103 is a thin film transistor (Thin Film Transistor, TFT) and is formed on the first interlayer insulating film 156. Regarding the process of forming circuit elements including TFTs on a large glass substrate, it has been established for the manufacture of liquid crystal panels or organic EL panels, etc., and has the advantage of being able to use existing equipment.

[0093] The sub-pixel 20 further includes a color filter 180. The color filter 180 (wavelength conversion component) is disposed on the surface resin layer 170 via a transparent film bonding layer 188. The surface resin layer 170 is disposed on the second interlayer insulating film 108 and the wiring layer 110.

[0094] Hereinafter, the structure of the sub-pixel 20 will be described in detail.

[0095] The conductive layer 130 is disposed on the first surface 102a. The conductive layer 130 includes a connection plate 130a (first part). The light-emitting element 150 is disposed on the connection plate 130a. The connection plate 130a is a conductive member having a film shape, a layer shape, or a plate shape that is square, an arbitrary polygon, an ellipse, a circle, etc. when viewed in the XY plane. The connection plate 130a is electrically connected to the bottom surface 153B of the light-emitting element 150.

[0096] The conductive layer 130 and the connection plate 130a are formed of, for example, Al or an alloy of Al, a laminated film of Al and Ti, etc. For example, in a laminated film of Al and Ti, Ti is laminated on the upper layer of the Al film, and then Ti is laminated on the Al. Therefore, the connection plate 130a has light reflectivity. The light reflectivity can be further improved by providing a metal material with high light reflectivity such as Ag on a metal layer such as Al or Ti.

[0097] The light-emitting element 150 is disposed on the connection plate 130a. Preferably, a connection plate 130a is provided for each light-emitting element 150.

[0098] The light-emitting element 150 includes a bottom surface 153B and a light-emitting surface 151S. The light-emitting element 150 is a prismatic or cylindrical element having a bottom surface 153B on the connection plate 130a. The bottom surface 153B is disposed on the connection plate 130a and is electrically connected to the connection plate 130a. The light-emitting surface 151S is a surface opposite to the bottom surface 153B of the light-emitting element 150.

[0099] Preferably, the outer periphery of the connection plate 130a is set to include the outer periphery of the light-emitting element when the light-emitting element 150 is projected in the XY plane when viewed. The connection plate 130a has light reflectivity, thereby reflecting the scattered light toward the lower side of the light-emitting element 150 toward the light-emitting surface 151S side, thereby substantially improving the light-emitting efficiency.

[0100] Preferably, the outer periphery of the connection plate 130a is set not to include the outer periphery of the transistor 103 when the transistor 103 described later is projected onto the XY plane including the connection plate 130a. It is difficult for the transistor 103 to receive the reflected light from the connection plate 130a, thereby being able to sufficiently reduce the probability of generating malfunction, etc. The outer periphery of the transistor refers to the outer periphery of the TFT channel 104.

[0101] The light-emitting element 150 includes a p-type semiconductor layer 153, a light-emitting layer 152, and an n-type semiconductor layer 151. The p-type semiconductor layer 153, the light-emitting layer 152, and the n-type semiconductor layer 151 are stacked in this order from the bottom surface 153B toward the light-emitting surface 151S. Accordingly, the p-type semiconductor layer 153 is electrically connected to the connection plate 130a.

[0102] In the case where the light-emitting element 150 has a prismatic shape, the shape of the light-emitting element 150 when viewed in the XY plane is, for example, a substantially square or rectangular shape. In the case where the shape of the light-emitting element 150 when viewed in the XY plane is a polygon including a square shape, the corners of the light-emitting element 150 may be rounded. In the case where the shape of the light-emitting element 150 when viewed in the XY plane is a cylindrical shape, the shape of the light-emitting element 150 when viewed in the XY plane is not limited to a circular shape and may be, for example, an elliptical shape. By appropriately selecting the shape or arrangement of the light-emitting element when viewed from above, the degree of layout freedom is improved.

[0103] The light-emitting element 150 preferably uses, for example, a gallium nitride-based compound semiconductor for the light-emitting layer such as In X Al Y Ga 1-X-Y N (0 ≦ X, 0 ≦ Y, X + Y < 1), etc. Hereinafter, the above-mentioned gallium nitride-based compound semiconductor may be sometimes simply referred to as gallium nitride (GaN). The light-emitting element 150 in one embodiment of the present invention is a so-called light-emitting diode. The wavelength of the light emitted by the light-emitting element 150 may be a wavelength in the range from the near-ultraviolet region to the visible light region, for example, about 467 nm ± 20 nm. The wavelength of the light emitted by the light-emitting element 150 may be blue-violet light of about 410 nm ± 20 nm. The wavelength of the light emitted by the light-emitting element 150 is not limited to the above values and may be an appropriate value.

[0104] The area of the light-emitting layer 152 when viewed in the XY plane is set according to the emission color of the red, green, and blue sub-pixels. Hereinafter, the area when viewed in the XY plane may be sometimes simply referred to as the area. The area of the light-emitting layer 152 is appropriately set by the visual brightness or the conversion efficiency of the color conversion unit 182 of the color filter 180 described later. That is, the areas of the light-emitting layers 152 of the sub-pixels 20 of each emission color may be the same or may be different depending on the emission color. It should be noted that the area of the light-emitting layer 152 is the area of the outer peripheral surrounding region of the light-emitting layer 152 projected onto the XY plane.

[0105] The first interlayer insulating film (first insulating film) 156 covers the first surface 102a and the conductive layer 130. The first interlayer insulating film 156 covers the side surfaces of the light-emitting elements 150. The first interlayer insulating film 156 does not cover the light-emitting surface 151S. The first interlayer insulating film 156 insulates between the light-emitting elements 150. The first interlayer insulating film 156 insulates the light-emitting elements 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming circuit elements such as the transistor 103. The first interlayer insulating film 156 covers the light-emitting elements 150, thereby protecting the light-emitting elements 150 from thermal stress and the like when forming the transistor 103 and the like.

[0106] The first interlayer insulating film 156 is formed of a dielectric such as an organic insulating material. The organic insulating material for the first interlayer insulating film 156 is preferably a white resin. The white resin reflects the lateral emitted light of the light-emitting element 150 or the return light caused by the interface of the color filter 180 or the like. Therefore, making the first interlayer insulating film 156 a white resin helps to substantially improve the luminous efficiency of the light-emitting element 150.

[0107] The white resin is formed by dispersing scattering fine particles having a Mie scattering effect in a transparent resin such as a silicon-based resin such as SOG (Spin On Glass) or a phenolic phenol resin. The scattering fine particles are colorless or white and have a diameter of about 1 / 10 to several times the wavelength of the light emitted from the light-emitting element 150. The preferably used scattering fine particles have a diameter of about 1 / 2 of the light wavelength. For example, as such scattering fine particles, there are TiO2, Al2SO3, ZnO, etc.

[0108] Alternatively, the white resin can also be formed by using a large number of fine pores or the like dispersed in the transparent resin. When whitening the first interlayer insulating film 156, an SiO2 film or the like formed by ALD (Atomic-Layer-Deposition) or CVD (Chemical Vapor Deposition) can be used, for example, overlapping with SOG or the like.

[0109] The first interlayer insulating film 156 can also be a black resin. By making the first interlayer insulating film 156 a black resin, the scattering of light within the sub-pixel 20 is suppressed, and stray light is further effectively suppressed. An image display device with suppressed stray light can display a clearer image.

[0110] On the first interlayer insulating film 156, a TFT lower layer film 106 is formed over the entire area. The TFT lower layer film 106 is provided for the following purposes: to ensure flatness during the formation of the transistor 103 and to protect the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is an insulating film such as SiO2, for example.

[0111] The transistor 103 is formed on the TFT lower layer film 106. On the TFT lower layer film 106, in addition to the transistor 103, other circuit elements such as other transistors or capacitors are also formed, and a circuit 101 is constituted by wirings and the like. For example, in the following Figure 3 the transistor 103 corresponds to the driving transistor 26. In addition, in Figure 3 the selection transistor 24 or the capacitor 28 or the like is a circuit element. The circuit 101 includes the TFT channel 104, the insulating layer 105, the second interlayer insulating film 108, the vias 111s, 111d, and the wiring layer 110.

[0112] The transistor 103 is an n-channel thin film transistor (TFT) in this example. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature poly-silicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating a region of amorphous Si formed on the TFT lower layer film 106. For example, laser annealing is used for the polycrystallization and activation of the region of amorphous Si. The TFT formed by the LTPS process has a sufficiently high mobility.

[0113] The TFT channel 104 includes regions 104s, 104i, 104d. The regions 104s, 104i, 104d are all provided on the TFT lower layer film 106. The region 104i is provided between the region 104s and the region 104d. In the regions 104s, 104d, an n-type impurity such as phosphorus (P) is doped and ohmic contact is made with the vias 111s, 111d.

[0114] The gate 107 is provided on the TFT channel 104 via the insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 and the gate 107 and to insulate from other adjacent circuit elements. When a potential higher than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, and the current flowing between the regions 104s, 104d can be controlled.

[0115] The insulating layer 105 is, for example, SiO2. The insulating layer 105 may also be a multi-layer insulating layer including SiO2 or Si3N4 or the like depending on the covered region.

[0116] The gate electrode 107 may be formed of, for example, polycrystalline Si, or may be formed of a high melting point metal such as W or Mo. The polycrystalline Si film of the gate electrode 107 is formed by, for example, CVD.

[0117] The second interlayer insulating film 108 is provided on the gate electrode 107 and the insulating layer 105. The second interlayer insulating film 108 is formed of, for example, the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of a white resin or an inorganic film such as SiO2. The second interlayer insulating film 108 also has a function as a flat film for forming the wiring layer 110.

[0118] The first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 are configured as described above, and therefore are not provided on the upper portion of the light emitting surface 151S. That is, the light emitting surface 151S is exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 through the opening 158. As described later, the opening 158 is filled with the surface resin layer 170.

[0119] The vias 111s and 111d are provided to penetrate the second interlayer insulating film 108 and the insulating layer 105. The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes a plurality of wirings that can have different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110a.

[0120] A portion of the wiring 110s is provided above the region 104s. The wiring 110s is connected to, for example, Figure 3 The wiring 110a is connected to the ground line 4 shown. A portion of the wiring 110d is provided above the region 104d. Another portion of the wiring 110d is provided near the light emitting surface 151S but is not connected to the light emitting surface 151S. A portion of the wiring 110a is provided above the connecting plate 130a. The wiring 110a is connected to, for example, Figure 3 The power cord 3 is shown connected.

[0121] exist Figure 1 In each of the following cross-sectional views, a reference numeral for a wiring layer is indicated at a position next to one wiring included in the wiring layer unless otherwise specified.

[0122] The light-transmitting electrode 159d is provided over the wiring 110d. The light-transmitting electrode 159d is provided over the light-emitting surface 151S. The light-transmitting electrode 159d is also provided between the wiring 110d and the light-emitting surface 151S, and electrically connects the wiring 110d and the light-emitting surface 151S.

[0123] The translucent electrode 159s is disposed throughout on the wiring 110s. Together with the wiring 110s, the translucent electrode 159s is connected to the ground wire 4 of a circuit such as Figure 3 The translucent electrode 159a is disposed throughout on the wiring 110a. Together with the wiring 110a, the translucent electrode 159a is connected to the power supply line 3 of a circuit such as Figure 3 The translucent electrodes 159d, 159s, and 159a are formed of a translucent conductive film. The translucent electrodes 159d, 159s, 159a are preferably made of an ITO film or a ZnO film or the like.

[0124] The light emitting surface 151S is preferably roughened as in this example. When the light emitting surface 151S of the light emitting element 150 is a rough surface, the light extraction efficiency can be improved.

[0125] By providing the translucent electrode 159d on the light emitting surface 151S, the connection area between the translucent electrode 159d and the n-type semiconductor layer 151 can be increased, the area of the light emitting surface 151S can be substantially increased, and the connection resistance can be reduced. In addition, since the area of the light emitting surface 151S can be substantially increased, the light emitting efficiency can be improved. Since the light emitting surface 151S is a rough surface, by increasing the connection area between the light emitting surface 151S and the translucent electrode 159d, the contact resistance can be reduced, and thus the light emitting efficiency can be further improved.

[0126] The via hole 111s is provided between the wiring 110s and the region 104s and electrically connects the wiring 110s and the region 104s. The via hole 111d is provided between the wiring 110d and the region 104d and electrically connects the wiring 110d and the region 104d.

[0127] The wiring 110s is connected to the region 104s via the via hole 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to the ground wire 4 via the via hole 111s and the wiring 110s.

[0128] The wiring 110d and the translucent electrode 159d are connected to the region 104d via the via hole 111d. The region 104d is the drain region of the transistor 103. Therefore, the drain region of the transistor 103 is electrically connected to the n-type semiconductor layer 151 via the via hole 111d, the wiring 110d, and the translucent electrode 159d.

[0129] Via 161a is provided to penetrate through the second interlayer insulating film 108, insulating layer 105, TFT lower layer film 106, and first interlayer insulating film 156. Via 161a is provided between wiring 110a and connection plate 130a and electrically connects wiring 110a and connection plate 130a. Therefore, the p-type semiconductor layer 153 is electrically connected to the power supply line 3 of the circuit such as Figure 3 through connection plate 130a, via 161a, wiring 110a, and light-transmissive electrode 159a.

[0130] The wiring layer 110 and vias 111s, 111d, 161a are formed of, for example, Al or an alloy of Al, a stacked film of Al and Ti, etc. For example, in the stacked film of Al and Ti, Al is stacked on the thin film of Ti, and then Ti is stacked on Al.

[0131] The surface resin layer 170 covers the second interlayer insulating film 108, wiring layer 110, and light-transmissive electrodes 159s, 159d, 159a. The surface resin layer 170 also fills the opening 158. The surface resin layer 170 is provided on the light-emitting surface 151S via the light-transmissive electrode 159d. The surface resin layer 170 filled in the opening 158 is provided on the light-transmissive electrode 159d, and the light-transmissive electrode 159d is provided to cover the side surfaces of each of the first interlayer insulating film 156, TFT lower layer film 106, insulating layer 105, and second interlayer insulating film 108. The surface resin layer 170 is a transparent resin, protects the interlayer insulating film 156 and wiring layer 110, and provides a flat surface for bonding the color filter 180.

[0132] The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided directly above the light-emitting surface 153S of the light-emitting element 150 according to the shape of the light-emitting surface 153S. In the color filter 180, the portion other than the color conversion portion 182 is the light-shielding portion 181. The light-shielding portion 181 is a so-called black matrix, which can reduce the penetration caused by color mixing of light emitted from adjacent color conversion portions 182, etc., and thus can display a clear image.

[0133] The color conversion portion 182 is one layer or two or more layers. In Figure 1 the case where the color conversion portion 182 is two layers is shown. Whether the color conversion portion 182 is one layer or two layers is determined by the color, i.e., wavelength, of the light emitted from the sub-pixel 20. When the light-emitting color of the sub-pixel 20 is red, it is preferable that the color conversion portion 182 is two layers of a color conversion layer 183 and a filter layer 184 that allows red light to pass through. When the light-emitting color of the sub-pixel 20 is green, it is preferable that the color conversion portion 182 is two layers of a color conversion layer 183 and a filter layer 184 that allows green light to pass through. When the light-emitting color of the sub-pixel 20 is blue, it is preferably one layer.

[0134] When the color conversion section 182 has two layers, the first layer is the color conversion layer 183 and the second layer is the light filtering layer 184. The color conversion layer 183 of the first layer is disposed closer to the light emitting element 150. The light filtering layer 184 is stacked on the color conversion layer 183.

[0135] The color conversion layer 183 converts the wavelength of the light emitted from the light emitting element 150 into a desired wavelength. In the case of the sub-pixel 20 that emits red, the light with a wavelength of 467 nm ± 20 nm from the light emitting element 150 is converted into light with a wavelength of, for example, about 630 nm ± 20 nm. In the case of the sub-pixel 20 that emits green, the light with a wavelength of 467 nm ± 20 nm from the light emitting element 150 is converted into light with a wavelength of, for example, about 532 nm ± 20 nm.

[0136] The light filtering layer 184 blocks the wavelength component of the blue light emission that remains without being color-converted by the color conversion layer 183.

[0137] In the case where the color of the light emitted from the sub-pixel 20 is blue, the sub-pixel 20 can output light via the color conversion layer 183 or can directly output light without passing through the color conversion layer 183. In the case where the wavelength of the light emitted from the light emitting element 150 is about 467 nm ± 20 nm, the sub-pixel 20 can output light without passing through the color conversion layer 183. In the case where the wavelength of the light emitted from the light emitting element 150 is set to 410 nm ± 20 nm, in order to convert the wavelength of the output light to about 467 nm ± 20 nm, it is preferable to provide one layer of the color conversion layer 183.

[0138] Even in the case of the blue sub-pixel 20, the sub-pixel 20 can have the light filtering layer 184. By providing the light filtering layer 184 that transmits blue light in the blue sub-pixel 20, minute external light reflection other than the blue light generated on the surface of the light emitting element 150 is suppressed.

[0139] Figure 2 It is a cross-sectional view schematically showing a part of an image display device according to a modified example of the present embodiment.

[0140] In the case of Figure 2 In the sub-pixel 20a, the connection method between the light emitting element 150a and the wiring 110d1 is different from that in the case of the first embodiment above. In this modified example, it is also different from the case of the first embodiment in that a light-transmissive electrode is not provided on the wirings 110s, 110d1, and 110a. In other respects, this modified example is the same as the case of the first embodiment, and for the same components, the same reference numerals are used and the detailed description is appropriately omitted. Note that in Figure 2This also represents the structure of the upper part of the surface resin layer 170. These upper structures are also the same as those in the first embodiment.

[0141] As Figure 2 shown, the sub-pixel 20a includes a light-emitting element 150a and a wiring 110d1. A part of the wiring 110d1 is disposed above the region 104d. Another part of the wiring 110d1 is arranged to extend to the light-emitting surface 151S, and its front end is connected to the surface including the light-emitting surface 151S. The surface including the light-emitting surface 151S is a surface in the same plane as the light-emitting surface 151S. The front end of the wiring 110d1 is connected to a surface other than the light-emitting surface 151S on this surface. In this example, the light-emitting surface 151S is not roughened, but it may also be roughened. In the case of not being roughened, the process for roughening can be omitted.

[0142] In the present embodiment, it is possible to include any one of the structures of the sub-pixels 20 and 20a shown above.

[0143] Figure 3 is a schematic block diagram illustrating the image display device of the present embodiment.

[0144] As Figure 3 shown, the image display device 1 of the present embodiment includes a display region 2. Sub-pixels 20 are arranged in the display region 2. The sub-pixels 20 are arranged, for example, in a grid pattern. For example, n sub-pixels 20 are arranged along the X-axis, and m sub-pixels 20 are arranged along the Y-axis.

[0145] The pixel 10 includes a plurality of sub-pixels 20 that emit light of different colors. The sub-pixel 20R emits red light. The sub-pixel 20G emits green light. The sub-pixel 20B emits blue light. By the three sub-pixels 20R, 20G, and 20B emitting light with a desired luminance, the emission color and luminance of one pixel 10 are determined.

[0146] One pixel 10 includes three sub-pixels 20R, 20G, and 20B. The sub-pixels 20R, 20G, and 20B are linearly arranged on the X-axis as shown in, for example, Figure 3 shown. In each pixel 10, sub-pixels of the same color may be arranged in the same column, as in this example, or sub-pixels of different colors may be arranged in each column.

[0147] The image display device 1 further includes a power supply line 3 and a ground line 4. The power supply line 3 and the ground line 4 are arranged in a grid pattern along the arrangement of the sub-pixels 20. The power supply line 3 and the ground line 4 are electrically connected to each sub-pixel 20, and power is supplied to each sub-pixel 20 from a DC power supply connected between the power supply terminal 3a and the GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are respectively provided at the ends of the power supply line 3 and the ground line 4, and are connected to a DC power supply circuit provided outside the display area 2. The power supply terminal 3a is supplied with a positive voltage with respect to the GND terminal 4a.

[0148] The image display device 1 further includes a scanning line 6 and a signal line 8. The scanning line 6 is arranged in a direction parallel to the X-axis. That is, the scanning line 6 is arranged along the row direction of the sub-pixels 20. The signal line 8 is arranged in a direction parallel to the Y-axis. That is, the signal line 8 is arranged along the column direction of the sub-pixels 20.

[0149] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via the scanning line 6, and supplies a selection signal to each sub-pixel 20.

[0150] The signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 of each row via the signal line 8, and supplies a signal voltage to each sub-pixel 20.

[0151] The sub-pixel 20 includes a light-emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. In Figure 3 and those described later Figure 4 the selection transistor 24 is denoted as T1, the driving transistor 26 is denoted as T2, and the capacitor 28 is denoted as Cm.

[0152] The light-emitting element 22 is connected in series with the driving transistor 26. In the present embodiment, the driving transistor 26 is an n-channel TFT, and the cathode of the light-emitting element 22 is connected to the drain of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain and the source. The anode of the light-emitting element 22 is connected to a p-type semiconductor layer. The cathode of the light-emitting element 22 is connected to an n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to the transistor 103 in Figure 1 and the light-emitting element 22 corresponds to Figure 1corresponds to the light-emitting element 150 therein. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and the source of the driving transistor 26, and the light-emitting element 22 emits light with a luminance corresponding to the flowing current.

[0153] The selection transistor 24 is connected between the gate electrode of the driving transistor 26 and the signal line 8 via the main electrode. The gate electrode of the selection transistor 24 is connected to the scanning line 6. A capacitor 28 is connected between the gate electrode of the driving transistor 26 and the ground line 4.

[0154] The row selection circuit 5 selects one row from the arrangement of the sub-pixels 20 in the m rows and supplies the selection signal to the scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each of the sub-pixels 20 in the selected row. A signal voltage is applied between the gate and the source of the driving transistor 26 in the sub-pixel 20 in the selected row. The signal voltage is held by the capacitor 28. The driving transistor 26 causes a current corresponding to the signal voltage to flow through the light-emitting element 22. The light-emitting element 22 emits light with a luminance corresponding to the current flowing through the light-emitting element 22.

[0155] The row selection circuit 5 sequentially switches the rows to which the selection signal is supplied. That is, the row selection circuit 5 scans the rows in which the sub-pixels 20 are arranged. Currents corresponding to the signal voltage flow through the light-emitting elements 22 in the sequentially scanned sub-pixels 20 and emit light. Each pixel 10 emits light with a light-emitting color and a luminance determined by the light-emitting colors and the luminances of the sub-pixels 20 of RGB colors and displays an image in the display area 2.

[0156] Figure 4 is a schematic plan view showing a part of the image display device according to this embodiment.

[0157] In this embodiment, as described in Figure 1 the light-emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction via the first interlayer insulating film 156. In other words, the light-emitting element 150 is formed on a layer different from the layer on which the transistor 103 is formed. The light-emitting element 150 corresponds to the light-emitting element 22 in Figure 3 The driving transistor 103 corresponds to the driving transistor 26 in Figure 3 and is also denoted as T2. For the sake of simplicity, in Figure 4 the representation of the light-transmitting electrode is omitted.

[0158] As Figure 4As shown, the anode of the light-emitting element 150 is disposed on the connection plate 130a and is electrically connected to the connection plate 130a. The connection plate 130a is provided at a lower layer than the transistor 103 or the wiring layer 110. The connection plate 130a is electrically connected to the wiring 110a via the via hole 161a. More specifically, one end of the via hole 161a is connected to the connection plate 130a, and the other end of the via hole 161a is connected to the wiring 110a via the contact hole 161a1.

[0159] The cathode of the light-emitting element 150 is provided by Figure 1 the n-type semiconductor layer 151 shown. The wiring 110d is covered by Figure 1 the light-transmissive electrode 159d shown. The light-transmissive electrode 159d covers the light-emitting surface 151S. The light-transmissive electrode 159d is also provided between the wiring 110d and the light-emitting surface 151S, so that the cathode of the light-emitting element 150 is electrically connected to the wiring 110d.

[0160] A part of the wiring 110d is connected to the drain of the transistor 103 via the via hole 111d. The drain of the transistor 103 is Figure 1 the region 104d shown. The source of the transistor 103 is connected to the wiring 110s via the via hole 111s. The source of the transistor 103 is Figure 1 the region 104s shown. In this example, the wiring layer 110 includes the ground wire 4, and the wiring 110s is connected to the ground wire 4.

[0161] In this example, the power supply line 3 is provided at a layer above the wiring layer 110. Although not shown in Figure 1 , an interlayer insulating film is also provided on the wiring layer 110. The power supply line 3 is provided on the uppermost interlayer insulating film and is insulated from the ground wire 4.

[0162] In this way, the light-emitting element 150 can be electrically connected to the wiring 110a provided at a layer above the light-emitting element 150 by using the via hole 161a. In addition, the light-emitting element 150 can be electrically connected to the transistor 103 provided at a layer above the light-emitting element 150 via the wiring 110d by providing the opening 158 that exposes the light-emitting surface 151S and providing the light-transmissive electrode 159d over the opening 158.

[0163] In addition, the outer periphery of the connection plate 130a includes the outer periphery of the light-emitting element 150. The outer periphery of the connection plate 130a is set so as not to include the outer periphery of the TFT channel 104. Thereby, the substantial light-emitting efficiency of the light-emitting element 150 can be improved, and malfunction due to light irradiation of the transistor including the TFT channel 104 can be prevented.

[0164] A method of manufacturing the image display device 1 of the present embodiment will be described.

[0165] Figure 5A and Figure 5B is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the present embodiment.

[0166] As Figure 5A shown, in the method of manufacturing the image display device 1 according to the present embodiment, a plurality of semiconductor growth substrates 1194 are prepared. The plurality of semiconductor growth substrates (second substrates) 1194 each include a crystal growth substrate 1001, a buffer layer 1140, and a semiconductor layer 1150. The crystal growth substrate 1001 (first substrate) is, for example, an Si substrate or a sapphire substrate. The Si substrate is preferably used as the crystal growth substrate 1001. In addition, as will be described later, in the case of using a low-temperature crystal growth process such as a low-temperature sputtering method or ALD (Atomic Layer Deposition), a cheaper glass substrate or the like can be used as the crystal growth substrate 1001.

[0167] The buffer layer 1140 is formed on one surface of the crystal growth substrate 1001. The buffer layer 1140 preferably uses a nitride such as AlN. By causing the semiconductor layer 1150 to grow crystallographically via the buffer layer 1140, the mismatch at the interface between the GaN crystal and the crystal growth substrate 1001 can be alleviated.

[0168] The semiconductor layer 1150 is formed on the buffer layer 1140. The semiconductor layer 1150 includes an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 are stacked in this order from the buffer layer 1140 side. In the formation of the semiconductor layer 1150, for example, a vapor growth method (Chemical Vapor Deposition, CVD method) is used, and the metal organic chemical vapor deposition method (Metal Organic Chemical Vapor Deposition, MOCVD method) is preferably used. In addition, even at a process temperature of 700°C or lower, the semiconductor layer 1150 can epitaxially grow crystallographically by a low-temperature sputtering method, whereby the manufacturing cost can be reduced by using a glass substrate or device with low heat resistance. The semiconductor layer 1150 includes, for example, GaN, and more specifically, includes InXAlYGa1-X-YN (0 ≦ X, 0 ≦ Y, X + Y < 1), etc.

[0169] In the initial stage of crystal growth, crystal defects sometimes occur due to the mismatch of crystal lattice constants, and the crystal with crystal defects is of n-type. Therefore, as in this example, when the semiconductor layer 1150 is formed of the n-type semiconductor layer 1151 on the crystal growth substrate 1001, the margin in the production process can be increased, and thus there is an advantage that the yield is easily improved.

[0170] As Figure 5B shown, a substrate 102 (third substrate) is prepared. A metal layer (first metal layer) 1130 is formed on a first surface 102a on one side of the substrate 102. The metal layer 1130 is formed, for example, by a laminated film of Al or an alloy of Al, a laminated film of Al and Ti, etc. Preferably, a metal material with high light reflectivity such as Ag is provided on a metal layer such as Al.

[0171] Among the plurality of semiconductor growth substrates 1194, the exposed surface of the p-type semiconductor layer 1153 is disposed opposite to the exposed surface of the metal layer 1130. The semiconductor layer 1150 is bonded to the substrate 102 via the metal layer 1130. A metal layer may also be formed on the exposed surface of the p-type semiconductor layer 1153, and the exposed surfaces of the metal layers may be disposed opposite to each other and bonded to each other.

[0172] In the substrate bonding process, for example, the substrates can be bonded to each other by heating each substrate and performing thermocompression bonding. When performing thermocompression bonding, a low melting point metal or a low melting point alloy can be used. The low melting point metal is, for example, Sn or In, etc., and the low melting point alloy is, for example, an alloy mainly composed of Zn, In, Ga, Sn, Bi, etc.

[0173] In the substrate bonding process as Figure 5B shown, in addition to the above, after planarizing the bonding surfaces of the respective substrates using Chemical Mechanical Polishing (CMP), etc., the bonding surfaces can be cleaned and closely adhered by plasma treatment in a vacuum.

[0174] The substrate 102 is, for example, a substantially rectangular glass substrate of about 1500 mm × 1800 mm. The semiconductor growth substrate 1194 has a rectangular or square shape with one side being about several tens of mm to 150 mm, and in terms of wafer size, it is, for example, a size of about 4 inches to 6 inches. The size of the substrate 102 is appropriately selected according to the size of the image display device, etc. When the size of the substrate 102 is, for example, a rectangular or square shape with one side being about several tens of mm to 150 mm, one semiconductor layer 1150 can be bonded to one substrate 102.

[0175] Figure 6 is a perspective view illustrating a method for manufacturing an image display device according to the present embodiment.

[0176] Figure 6 The upper diagram above the arrow of shows that a plurality of substrates 1194 are arranged in a grid pattern. Figure 6 The lower diagram below the arrow of shows the substrate 102 on which the metal layer 1130 is formed. In Figure 6As shown by the arrows, a plurality of substrates 1194 configured in a lattice pattern are arranged so that the semiconductor layer 1150 faces the metal layer 1130, and are bonded to each other.

[0177] At the end and in the vicinity of the semiconductor layer 1150, since the crystal quality deteriorates, it is necessary to pay attention not to form the light-emitting element 150 at the end and in the vicinity of the semiconductor layer 1150.

[0178] As Figure 6 shown, the end of the semiconductor layer 1150 is formed to be substantially aligned with the end of the crystal growth substrate 1001. Therefore, the plurality of semiconductor growth substrates 1194 are arranged so as to minimize the gap between adjacent substrates, for example, as shown by the solid line in Figure 6 , and are arranged in a lattice pattern so as to face the substrate 102. The semiconductor layer 1150 is bonded to the metal layer 1130 formed on the substrate 102, as shown by the two-dot chain line in Figure 6 .

[0179] When a plurality of semiconductor layers 1150 are bonded to one substrate 102, the substrate 102 to which the plurality of semiconductor layers 1150 are bonded is divided, so that an image display device having a number and size corresponding to the number of divisions can be obtained. The substrate 102 to which the plurality of semiconductor layers 1150 are bonded can be divided before the color filter is mounted or after the color filter is mounted. The end of the semiconductor layer 1150 with deteriorated crystal quality is preferably the end of the display area. Therefore, the division unit is preferably set to be consistent with the shape of the semiconductor growth substrate 1194. Regarding the assembly process of the color filter, it will be described later in connection with Figure 13 and Figures 14A to 14D .

[0180] Figures 7A to 8C is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the present embodiment.

[0181] In Figures 7A to 8C , two modification examples related to the substrate bonding process are illustrated. In the substrate bonding process, the processes of Figure 7A and Figure 7B can be used instead of the processes of Figure 5A and Figure 5B . In addition, the process of Figures 8A to 8C can be used instead of the processes of Figure 5A and Figure 5B .

[0182] In Figure 7A and Figure 7B shown in the manufacturing process, the semiconductor layer 1150 is formed on one surface of the crystal growth substrate 1001 without passing through the buffer layer 1140 shown in Figure 5A .

[0183] As Figure 7A shown, instead of Figure 5A the multiple semiconductor growth substrates 1194 shown, a plurality of semiconductor growth substrates 1194a are prepared. The plurality of semiconductor growth substrates 1194a each include a crystal growth substrate 1001 and a semiconductor layer 1150. The semiconductor layer 1150 is directly formed on one surface of the crystal growth substrate 1001. In the formation of the semiconductor layer 1150, the same as in the case of Figure 5A , a CVD method or an MOCVD method or the like is used.

[0184] As Figure 7B shown, the exposed surface of the p-type semiconductor layer 1153 is disposed opposite to the exposed surface of the metal layer 1130 formed on the first surface 102a. Thereafter, the exposed surface of the p-type semiconductor layer 1153 is bonded to the substrate 102 via the metal layer 1130.

[0185] In Figures 8A to 8C , the semiconductor layer 1150 formed on the crystal growth substrate 1001 is transferred to the support substrate 1190. The transferred semiconductor layer 1150 is bonded to the substrate 102 via the metal layer 1130 formed on the substrate 102.

[0186] As Figure 8A shown, a plurality of semiconductor growth substrates 1294 are prepared. The semiconductor growth substrate 1294 includes a crystal growth substrate 1001, a buffer layer 1140, and a semiconductor layer 1150. In the semiconductor growth substrate 1294, the buffer layer 1140 is formed on one surface of the crystal growth substrate 1001, and the semiconductor layer 1150 is formed via the buffer layer 1140. In the semiconductor layer 1150, the p-type semiconductor layer 1153, the light-emitting layer 1152, and the n-type semiconductor layer 1151 are sequentially formed in this order from the buffer layer 1140 side.

[0187] As Figure 8B shown, the support substrate 1190 is bonded to the exposed surface of the n-type semiconductor layer 1151. The support substrate 1190 is formed of, for example, quartz glass or Si or the like.

[0188] After the support substrate 1190 is bonded to the semiconductor layer 1150, the crystal growth substrate 1001 is removed to form a substrate 1295. In the removal of the crystal growth substrate 1001, for example, wet etching or laser lift-off is used.

[0189] As Figure 8C shown, Figure 8BThe buffer layer 1140 shown is removed by wet etching or the like, thereby forming a substrate 1295a. The exposed surface of the p-type semiconductor layer 1153 exposed by removing the buffer layer 1140 is disposed opposite to the metal layer 1130 formed on the first surface 102a. The semiconductor layer 1150 is bonded to the substrate 102 via the metal layer 1130.

[0190] In this manufacturing method, a buffer layer 1140 is formed on the crystal growth substrate 1001, and a semiconductor layer 1150 is formed via the buffer layer 1140. However, the semiconductor layer 1150 may be directly formed on the crystal growth substrate 1001 without passing through the buffer layer 1140.

[0191] The process of forming the semiconductor growth substrates 1194, 1194a, and 1294 may be performed in the same apparatus as the apparatus for performing the processes after bonding the semiconductor layer 1150 to the substrate 102, or may be performed in a different apparatus. For example, the semiconductor growth substrates 1194, 1194a, and 1294 or the substrate 1295 after bonding to the support substrate 1190 may be manufactured in a first apparatus, and the semiconductor growth substrate 1194 may be transferred to a second apparatus different from the first apparatus to perform the subsequent processes.

[0192] The method of bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above, and may be the following method. That is, after the semiconductor layer 1150 is formed on the crystal growth substrate 1001, it is stored in a container in a state where the crystal growth substrate 1001 has been removed. For example, the support substrate 1190 is installed and stored in the container. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102. Alternatively, the semiconductor layer 1150 is not installed on the support substrate 1190 but is stored in a container. After storage, the semiconductor layer 1150 is taken out of the container and directly bonded to the substrate 102.

[0193] The manufacturing process after returning to the substrate bonding process will be continued.

[0194] Figures 9A to 11B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the present embodiment.

[0195] As Figure 9A shown, Figure 5B the crystal growth substrate 1001 shown is removed by wet etching or laser lift-off or the like. In addition, Figure 5B the buffer layer 1140 shown is also removed by wet etching or the like.

[0196] As in Figure 6As described, a plurality of semiconductor growth substrates 1194 are arranged adjacent to each other and bonded to the substrate 102. Position X1 is the position where the respective ends of the semiconductor growth substrates 1194 arranged adjacent to each other are located. At position X1, the ends of the semiconductor layer 1150 are also adjacent to and close to each other.

[0197] As Figure 9B shown, Figure 9A the semiconductor layer 1150 shown is processed into a desired shape by etching to form the light-emitting element 150. The light-emitting element 150 is formed at a position sufficiently separated from the region including position X1. The crystal quality near the end of the semiconductor layer 1150 is evaluated, and the region including position X1 removed by etching is determined based on the evaluation result.

[0198] In the formation of the light-emitting element 150, for example, a dry etching process is used. Preferably, anisotropic ion etching (Reactive Ion Etching, RIE) is used. As Figure 9A shown, the buffer layer 1140 can be used as a mask when forming the light-emitting element 150. In this case, the buffer layer remaining on the light-emitting element 150 is removed by wet etching or the like after the formation of the light-emitting element 150.

[0199] After forming the light-emitting element 150, the metal layer 1130 shown by Figure 9A etching is formed into the conductive layer 130. In the formation process of the conductive layer 130, the connection plate 130a is formed. In this way, the connection plate 130a (the first part) is formed on the first surface 102a, and the light-emitting element 150 is formed on the connection plate 130a. The outer periphery of the connection plate 130a is set to include the outer periphery of the light-emitting element 150 when the light-emitting element 150 is projected in a plan view.

[0200] As Figure 10A shown, the first interlayer insulating film 156 (the first insulating film) covering the first surface 102a, the conductive layer 130, the connection plate 130a, and the light-emitting element 150 is formed.

[0201] As Figure 10B shown, the TFT lower layer film 106 is formed on the first interlayer insulating film 156. The TFT lower layer film 106 is formed by, for example, CVD or the like.

[0202] The TFT channel 104 is formed on the TFT lower layer film 106. For example, in the LTPS process, the TFT channel 104 is formed as follows. First, amorphous Si is formed into the shape of the TFT channel 104. In the formation of the amorphous Si, for example, CVD or the like is used. The formed amorphous Si film is polycrystallized by laser annealing to form the TFT channel 104.

[0203] Thereafter, the source and drain of the TFT channel 104 are formed, for example, by using ion implantation technology or the like to introduce impurity ions such as phosphorus (P) into regions 104s and 104d. The formation process of these source and drain can be carried out after the gate 107 formation process.

[0204] The insulating layer 105 is formed over the TFT lower layer film 106 and the TFT channel 104. The insulating layer 105 is formed by, for example, CVD or the like. The gate 107 is formed at a position over the TFT channel 104 via the insulating layer 105. In the formation of the gate 107, an appropriate formation method corresponding to the material of the gate 107 is used. For example, when the gate 107 is polycrystalline Si, it is formed by laser annealing of amorphous Si to polycrystallize in the same manner as the TFT channel 104. The transistor 103 is formed in this way.

[0205] The second interlayer insulating film 108 (second insulating film) is provided to cover the insulating layer 105 and the gate 107. In the formation of the second interlayer insulating film 108, an appropriate manufacturing method corresponding to the material of the second interlayer insulating film 108 is applied. For example, when the second interlayer insulating film 108 is formed of SiO2, techniques such as ALD or CVD are used.

[0206] The flatness of the second interlayer insulating film 108 only needs to be at a level where the wiring layer 110 can be formed, and a planarization process does not have to be performed. When the planarization process is not performed on the second interlayer insulating film 108, the number of processes can be reduced. For example, around the light-emitting element 150, when there is a position where the thickness of the second interlayer insulating film 108 becomes thin, the depth of the via hole penetrating the first interlayer insulating film 156 and the second interlayer insulating film 108 becomes shallow, so that the via hole can ensure a sufficient opening diameter. Therefore, it becomes easy to ensure the electrical connection based on the via hole, and thus the yield reduction due to poor electrical characteristics can be suppressed.

[0207] As Figure 11A shown, the via hole 162a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the connection plate 130a. The opening 158 is formed so as to reach the light-emitting surface 151S by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 on the light-emitting surface 151S. As in this example, the central portion of the n-type semiconductor layer 151 may be etched in the thickness direction of the n-type semiconductor layer 151 to form the light-emitting surface 151S. The light-emitting surface 151S is preferably roughened as in this example.

[0208] Via 112d is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 104d. Via 112s is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 104s. In the formation of vias 162a, 112d, 112s or the opening 158, for example, RIE or the like is used.

[0209] As Figure 11B shown, via 161a (first via) is formed by filling the via hole 162a shown in Figure 11A with a conductive material. Vias 111d and 111s are also respectively formed by filling the via holes 112d and 112s shown in Figure 11A with a conductive material. Thereafter, a wiring layer 110 is formed on the second interlayer insulating film 108, and wirings 110a, 110d, and 110s are formed. The wiring layer 110 may be formed simultaneously with the formation of vias 161a, 111d, and 111s.

[0210] Figure 12A And Figure 12B are schematic cross-sectional views illustrating a method of manufacturing an image display device according to a modified example of the present embodiment.

[0211] Figure 12A And Figure 12B illustrate the steps for forming the sub-pixel 20a shown in Figure 2 . In this example, up to the formation of the transistor 103 and the formation of the second interlayer insulating film 108, the steps are the same as those described above. Hereinafter, the steps of Figure 10B will be described, and the steps of Figure 12A and Figure 12B will be performed.

[0212] As Figure 12A shown, the same as the case of Figure 11A , vias 162a, 112d, and 112s are formed. The opening 158 is formed to reach the n-type semiconductor layer 151a. In this example, since the n-type semiconductor layer 151a is not roughened, the etching process for roughening can be omitted.

[0213] As Figure 12B shown, vias 161a, 111d, and 111s are formed by filling the via holes 162a, 112d, and 112s shown in Figure 12A with a conductive material. Thereafter, a wiring layer 110 is formed, and wirings 110a, 110d1, and 110s are formed. Here, one end of the wiring 110d1 is connected to the via 111d. The wiring 110d1 is provided to extend from the position connected to the via 111d to the light-emitting surface 151S. The other end of the wiring 110d1 is connected to the surface including the light-emitting surface 151S. That is, the wiring 110d1 is directly connected to the n-type semiconductor layer 151.

[0214] In this way, the sub-pixel 20a of the modified example is formed.

[0215] For example Figure 3 The circuit of, for example, is a driving circuit that drives the light-emitting element 150 by selecting the transistor 24, the driving transistor 26, and the capacitor 28. Such a driving circuit is formed within the sub-pixels 20 and 20a. A part of the circuit other than the driving circuit is formed, for example, Figure 1 at the peripheral portion of the display area 2 shown. For example Figure 3 The row selection circuit 5 shown is formed simultaneously with the driving transistor or the selection transistor, etc., and is formed at the peripheral portion of the display area 2. That is, the row selection circuit 5 can be loaded simultaneously through the above manufacturing process.

[0216] The signal voltage output circuit 7 is preferably loaded into a semiconductor device manufactured by a manufacturing process capable of high integration based on microfabrication. The signal voltage output circuit 7 is mounted on another substrate together with the CPU or other circuit elements. For example, before and after the color filter is loaded as described later, it is connected to the sub-pixels 20 and 20a via a connector provided at the peripheral portion of the display area, etc.

[0217] In the image display device 1 of the present embodiment, each light-emitting element 150 can form an image in the display area 2 by emitting light upward from the light-emitting surface 153S. However, if the light scatters downward more than the light-emitting surface 153S, since the substrate 102 has light-transmitting properties, the light-emitting efficiency substantially decreases. Therefore, for example, by providing a light-reflecting film or a light-reflecting plate, etc., on the side of the surface of the substrate 102 opposite to the first surface 102a, the scattered light in the direction of the substrate 102 can be reflected in the direction of the light-emitting surface 153S. Such a light-reflecting film, etc., can be provided on the substrate 102, or can be provided inside the case or frame, etc., that fixes the image display device 1.

[0218] Figure 13 is a schematic cross-sectional view illustrating a manufacturing method of the image display device of the present embodiment.

[0219] In Figure 13 the figure, the structure including the color filter 180 is shown above the arrow, and the structure including the light-emitting element 150, etc., formed in the above process is shown below the arrow. Figure 13 The process of bonding the color filter to the structure including the light-emitting element 150, etc., is shown by the arrow.

[0220] In Figure 13 to avoid complexity, the structure elements other than the structure elements on the substrate 102 shown are omitted from the illustration. The omitted structure elements include Figure 1The circuit 101 such as the TFT channel 104 or the wiring layer 110 shown, and the via 161a. In addition, in Figure 13 A part of a color conversion member such as the color filter 180 is shown. In reference to Figure 13 and Figures 14A to 14D In the description, a structure including the light-emitting element 150, the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, the second interlayer insulating film 108, and the surface resin layer 170 is referred to as the light-emitting circuit portion 172. A structure including the substrate 102, the conductive layer 130, the light-emitting circuit portion 172, and structural elements (not shown) is referred to as the structure 1192. In Figure 13 In Figure 1 In the circuit 101 shown, the TFT channel 104, the gate 107, the vias 111s, 111d, and the wiring layer 110 are not shown.

[0221] As Figure 13 shown, the color filter 180 (wavelength conversion member) is joined to the structure 1192 on one surface. The other surface of the color filter 180 is joined to the glass substrate 186. A transparent thin film bonding layer 188 is provided on one surface of the color filter 180, and is joined to the exposed surface of the surface resin layer 170 of the structure 1192 via the transparent thin film bonding layer 188.

[0222] In this example of the color filter 180, color conversion portions are arranged in the positive X-axis direction in the order of red, green, and blue. For red, a red color conversion layer 183R is provided on the first layer, and for green, a green color conversion layer 183G is provided on the first layer, and filter layers 184 are provided on the second layer respectively. For blue, a single-layer color conversion layer 183B may be provided, or a filter layer 184 may be provided. A light-shielding portion 181 is provided between the respective color conversion portions, and needless to say, the frequency characteristics of the filter layer 184 can be changed according to the color of the color conversion portion.

[0223] The positions of the color conversion layers 183R, 183G, 183B of each color are matched with the position of the light-emitting element 150, and the color filter 180 is attached to the structure 1192.

[0224] Figures 14A to 14D is a schematic cross-sectional view showing a modification of the manufacturing method of the image display device of the present embodiment.

[0225] In Figures 14A to 14D a method of forming a color filter by an inkjet method is exemplified.

[0226] As Figure 14A shown, a structure 1192 in which structural elements such as the light-emitting element 150 are formed on the substrate 102 is prepared.

[0227] As Figure 14B shown, a light-shielding portion 181 is formed on the structure 1192. The light-shielding portion 181 is formed, for example, using screen printing or lithography techniques, etc.

[0228] As Figure 14C shown, phosphors corresponding to the emission color are ejected from an inkjet nozzle to form a color conversion layer 183. The phosphors color the regions where the light-shielding portion 181 is not formed. The phosphors use a fluorescent coating material which uses, for example, general phosphor materials or perovskite phosphor materials, quantum dot phosphor materials. In the case of using perovskite phosphor materials or quantum dot phosphor materials, each emission color can be achieved, and the monochromaticity is high and the color reproducibility can be improved, so it is preferred. After the drawing by the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0229] As already described, regarding the sub-pixels that emit blue light, when the color conversion portion is not formed, the color conversion layer 183 is not formed. In addition, regarding the sub-pixels that emit blue light, when forming a blue color conversion layer, when the color conversion portion is only one layer, it is preferred that the thickness of the coating film of the blue phosphor is about the same as the thickness of the light-shielding portion 181.

[0230] As Figure 14D shown, the coating material for the light filtering layer 184 is ejected from an inkjet nozzle. The coating material is coated overlapping the coating film of the phosphors. The total thickness of the coating films of the phosphors and the coating material is about the same as the thickness of the light-shielding portion 181.

[0231] Whether it is a film-type color filter or an inkjet-type color filter, in order to improve the color conversion efficiency, the color conversion layer 183 is preferably as thick as possible. On the other hand, when the color conversion layer 183 is too thick, the emitted light of the color-converted light approximates Lambertian light. In contrast, the non-color-converted blue light has its emission angle limited by the light-shielding portion 181. Therefore, the following problem occurs: the display color of the displayed image has viewing angle dependence. In order to match the light distribution of the light of the sub-pixels provided with the color conversion layer 183 with the light distribution of the non-color-converted blue light, the thickness of the color conversion layer 183 is preferably about half of the opening size of the light-shielding portion 181.

[0232] For example, in the case of a high-precision image display device with a pitch of about 250 ppi (pitch per inch), the pitch of the sub-pixels 20 is about 30 μm. Therefore, the thickness of the color conversion layer 183 is preferably about 15 μm. Here, when the color conversion material is composed of spherical phosphor particles, in order to suppress light leakage from the light-emitting element 150, it is preferably stacked in the densest structure. For this purpose, at least the particle layer needs to be three layers. Therefore, the particle diameter of the phosphor material constituting the color conversion layer 183 is preferably about 5 μm or less, more preferably about 3 μm or less.

[0233] Figure 15 It is a schematic perspective view illustrating the image display device of the present embodiment.

[0234] As Figure 15 shown, the image display device of the present embodiment is provided with a light-emitting circuit unit 172 having a plurality of sub-pixels 20 on a substrate 102. Figure 13 The conductive layer 130 shown includes a connection plate 130a. The connection plate 130a is provided on the substrate 102 for each sub-pixel 20. A color filter 180 is provided on the light-emitting circuit unit 172. In the case of other embodiments or modified examples described later, it has the same structure as Figure 15 shown.

[0235] The effects of the image display device 1 of the present embodiment will be described.

[0236] In the manufacturing method of the image display device 1 of the present embodiment, after the semiconductor layer 1150 is bonded to the substrate 102, the semiconductor layer 1150 is etched to form the light-emitting element 150. Then, the light-emitting element 150 is covered with the first interlayer insulating film 156, and a circuit 101 including circuit elements such as a transistor 103 for driving the light-emitting element 150 is formed on the first interlayer insulating film 156. Therefore, compared with transferring the monolithic light-emitting elements to the substrate 102 individually, the manufacturing process is significantly shortened.

[0237] For example, in a 4K image display device, the number of sub-pixels exceeds 24 million, and in the case of an 8K image display device, the number of sub-pixels exceeds 99 million. Forming such a large number of light-emitting elements individually and mounting them on a circuit board requires a lot of time. Therefore, it is difficult to realize an image display device based on micro LEDs at a realistic cost. In addition, in the individual mounting of a large number of light-emitting elements, the yield decreases due to poor contact during mounting and the like, and a further increase in cost is inevitable. However, the following effects can be obtained in the manufacturing method of the image display device of the present embodiment.

[0238] As described above, in the method of manufacturing the image display device 1 according to the present embodiment, after the entire semiconductor layer 1150 is bonded to the substrate 102, a light-emitting element is formed by etching, so that the transfer process is completed in one step. Therefore, in the method of manufacturing the image display device 1 according to the present embodiment, compared with the conventional manufacturing method having the same number of transfer times as the number of light-emitting elements corresponding to the number of pixels, the time of the transfer process can be shortened and the number of processes can be reduced.

[0239] In addition, it is not necessary to previously singulate the semiconductor layer 1150 or form electrodes at positions corresponding to circuit elements, and it is bonded to the substrate 102 at the wafer level. Therefore, alignment at the bonding stage is not required. Therefore, the bonding process can be easily performed in a short time. Since alignment is not required during bonding, miniaturization of the light-emitting element 150 is also easy, which is suitable for high-definition displays.

[0240] In the present embodiment, for example, the glass substrate formed as described above can be covered with an interlayer insulating film, and a driving circuit including a TFT or a scanning circuit can be formed on the planarized surface using an LTPS process or the like. Therefore, it has the advantage of being able to use the manufacturing processes and equipment of existing flat panel displays.

[0241] In the present embodiment, the light-emitting element 150 formed in a layer lower than the transistor 103 or the like can be electrically connected to a power supply line or a ground line, a driving transistor, etc. formed in the upper layer by forming vias penetrating the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. By using such a multi-layer wiring technology established technically, a uniform connection structure can be easily realized and the yield can be increased. Therefore, a decrease in yield due to poor connection of light-emitting elements or the like is suppressed.

[0242] In the present embodiment, a conductive layer 130 is formed on the first surface 102a of the substrate 102. The conductive layer 130 includes a connection plate 130a. The light-emitting element 150 is formed on the connection plate 130a and is electrically connected to the connection plate 130a at the bottom surface 153B. The connection plate 130a is formed of a material having high conductivity such as a metal material. Therefore, the p-type semiconductor layer 153 of the light-emitting element 150 can be electrically connected to other circuits with low resistance.

[0243] In addition, since the lower p-type semiconductor layer 153 is connected to the connection plate 130a having a high conductivity at the bottom surface 153B, it is not necessary to form a lateral connection portion, so that the overall thickness of the light-emitting element 150 can be thinned. Therefore, the thickness of the first interlayer insulating film 156 can also be thinned, and the depth of the via 161a can be made shallower and the diameter can be made smaller. Therefore, the processing accuracy of the via for forming the via 161a can be substantially improved.

[0244] The connecting plate 130a can have a surface formed of a material with high light reflectivity such as Ag. The outer periphery of the connecting plate 130a is formed to include the outer periphery of the light-emitting element 150 when the light-emitting element 150 is projected in a plan view. Therefore, the connecting plate 130a also functions as a light reflecting plate, and scattered light and the like directed downward of the light-emitting element 150 are reflected toward the light-emitting surface 151S, so that the luminous efficiency of the light-emitting element 150 can be substantially improved.

[0245] (Second Embodiment)

[0246] Figure 16 FIG. is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.

[0247] In the present embodiment, the p-type semiconductor layer 253 provides the light-emitting surface 253S, and the structure of the transistor 203 is different from that of the above-described other embodiments. The same reference numerals are given to the constituent elements that are the same as those in the other embodiments, and the detailed description is appropriately omitted.

[0248] As Figure 16 shown, the sub-pixel 220 of the image display device of the present embodiment includes a substrate 102, a conductive layer 130, a light-emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, and a wiring layer 110.

[0249] The light-emitting element 250 is provided on the connecting plate 130a. The outer periphery of the connecting plate 130a is set to include the outer periphery of the light-emitting element 250 when the light-emitting element 250 is projected in a plan view. Therefore, scattered light and the like directed downward of the light-emitting element 250 can be reflected toward the light-emitting surface 253S side, and the luminous efficiency of the light-emitting element 250 can be substantially improved in the same manner as in the above-described other embodiments.

[0250] The light-emitting element 250 includes a light-emitting surface 253S. The light-emitting element 250 is a prismatic or cylindrical element having a bottom surface 251B on the connecting plate 130a, the same as in the above-described other embodiments. The light-emitting surface 253S is a surface opposite to the bottom surface 251B. The bottom surface 251B is connected to the connecting plate 130a.

[0251] The light-emitting element 250 includes an n-type semiconductor layer 251, a light-emitting layer 252, and a p-type semiconductor layer 253. The n-type semiconductor layer 251, the light-emitting layer 252, and the p-type semiconductor layer 253 are laminated in this order from the bottom surface 251B toward the light-emitting surface 253S. In the present embodiment, the light-emitting surface 253S is provided by the p-type semiconductor layer 253.

[0252] The light-emitting element 250 has the same as Figure 1The shape when viewed from the XY plane of the same light-emitting element 150 as shown. Select an appropriate shape according to the layout of circuit elements, etc.

[0253] The light-emitting element 250 is the same light-emitting diode as the light-emitting element 150 of the above-described other embodiments. That is, the wavelength of the light emitted by the light-emitting element 250 is, for example, blue light of about 467 nm ± 20 nm and blue-violet light of about 410 nm ± 20 nm. The wavelength of the light emitted by the light-emitting element 250 is not limited to the above values and can be an appropriate value.

[0254] The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is a p-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the case of the above-described other embodiments. In the present embodiment, the circuit 101 includes a TFT channel 204, an insulating layer 105, a second interlayer insulating film 108, vias 111s, 111d, and a wiring layer 110.

[0255] The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are provided on the TFT lower layer film 106. The regions 204s and 204d are doped with p-type impurities such as boron (B). The region 204s makes an ohmic contact with the via 111s. The region 204d makes an ohmic contact with the via 111d.

[0256] The gate 107 is provided on the TFT channel 204 via the insulating layer 105. The insulating layer 105 insulates the TFT channel 204 and the gate 107.

[0257] In the transistor 203, when a voltage lower than that of the region 204s is applied to the gate 107, a channel is formed in the region 204i. The current flowing between the regions 204s and 204d is controlled by the voltage of the region 204s of the gate 107. The TFT channel 204 and the gate 107 are formed of the same materials and by the same manufacturing method as in the case of the above-described other embodiments.

[0258] The wiring layer 110 includes wirings 110s, 110d, and 210k. The wirings 110s and 110d are the same as in the first embodiment. A part of the wiring 210k is provided above the connection plate 130a. The other part of the wiring 210k extends to, for example, the ground wire 4 described later Figure 17 and is connected to the ground wire 4.

[0259] Via holes 111s and 111d penetrate through the second interlayer insulating film 108. Via hole 111s is provided between the wiring 110s and the region 204s. Via hole 111s electrically connects the wiring 110s and the region 204s. Via hole 111d is provided between the wiring 110d and the region 204d. Via hole 111d electrically connects the wiring 110d and the region 204d. Via holes 111s and 111d are formed of the same materials and by the same manufacturing method as in the case of the above-described other embodiments.

[0260] Via hole 161k penetrates through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. Via hole 161k is provided between the wiring 210k and the connection board 130a, and electrically connects the wiring 210k and the connection board 130a.

[0261] The wiring 110s is electrically connected to, for example, the power supply line 3 shown below. Figure 17 The wiring 110d is electrically connected to the p-type semiconductor layer 253 via the light-transmissive electrode 159d.

[0262] In the case of the present embodiment, the light-transmissive electrode 159d is provided over the roughened light-emitting surface 253S of the p-type semiconductor layer 253. The light-transmissive electrode 159d is provided over the wiring 110d. The light-transmissive electrode 159d is also provided between the light-emitting surface 253S and the wiring 110d, and electrically connects the p-type semiconductor layer 253 and the wiring 110d. In the modification of the first embodiment described above, as shown in the example below, the wiring 110d1 can be extended to be directly connected to the p-type semiconductor layer 253. Figure 2 As shown in the example below, the wiring 110d1 can be extended to be directly connected to the p-type semiconductor layer 253.

[0263] Figure 17 FIG. is a schematic block diagram illustrating the image display device of the present embodiment.

[0264] As shown in Figure 17 below, the image display device 201 of the present embodiment includes a display region 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display region 2, as in the case of the above-described other embodiments, for example, the sub-pixels 220 are arranged in a lattice pattern when viewed in the XY plane.

[0265] The pixel 10, as in the case of the above-described other embodiments, includes a plurality of sub-pixels 220 that emit light of different colors. The sub-pixel 220R emits red light. The sub-pixel 220G emits green light. The sub-pixel 220B emits blue light. By causing the three sub-pixels 220R, 220G, and 220B to emit light with a desired luminance, the emission color and luminance of one pixel 10 are determined.

[0266] A pixel 10 includes three sub-pixels 220R, 220G, and 220B. The sub-pixels 220R, 220G, and 220B are arranged linearly on the X-axis as in this example. In each pixel 10, sub-pixels of the same color can be arranged in the same column, or as in this example, sub-pixels of different colors can be arranged in each column.

[0267] The sub-pixel 220 includes a light-emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. In Figure 15 this, the selection transistor 224 is denoted as T1, the driving transistor 226 is denoted as T2, and the capacitor 228 is denoted as Cm.

[0268] In the present embodiment, the light-emitting element 222 is provided on the ground wire 4 side, and the driving transistor 226 connected in series with the light-emitting element 222 is provided on the power supply line 3 side. That is, the driving transistor 226 is connected to the lower potential side than the light-emitting element 222. The driving transistor 226 is a p-channel transistor.

[0269] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the power supply line 3.

[0270] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity from that of the above-described other embodiments to the signal line 208 in order to drive the p-channel transistor, i.e., the driving transistor 226.

[0271] In the present embodiment, since the polarity of the driving transistor 226 is p-channel, the polarity of the signal voltage and the like are different from those in the above-described other embodiments. That is, the row selection circuit 205 supplies a selection signal to the scan line 206 in such a manner as to sequentially select one row from the arrangement of the sub-pixels 220 in the m-th row. The signal voltage output circuit 207 supplies a signal voltage having a necessary analog voltage value to each sub-pixel 220 in the selected row. The driving transistor 226 of the sub-pixel 220 in the selected row causes a current corresponding to the signal voltage to flow through the light-emitting element 222. The light-emitting element 222 emits light with a luminance corresponding to the flowing current.

[0272] A method for manufacturing the image display device of the present embodiment will be described.

[0273] Figures 18A to 21B is a schematic cross-sectional view illustrating a method for manufacturing the image display device of the present embodiment.

[0274] In this example, the semiconductor growth substrate 1194a described with reference to the above-described other embodiments is used. Hereinafter, the description will be made on the basis of having prepared Figure 7A the semiconductor growth substrate 1194a described with reference to the above-described other embodiments. Hereinafter, the description will be made on the basis of having prepared Figure 7AThe subsequent processes after the semiconductor growth substrate 1194a shown are applicable Figure 18A Subsequent processes.

[0275] As Figure 18A shown, in the manufacturing method of the image display device of the present embodiment, a plurality of semiconductor growth substrates 1194a shown are prepared, and support substrates 1190 are respectively bonded to the exposed surfaces of the p-type semiconductor layers 1153 to form a substrate 1195a. Figure 7A shown, a plurality of semiconductor growth substrates 1194a shown are prepared, and support substrates 1190 are respectively bonded to the exposed surfaces of the p-type semiconductor layers 1153 to form a substrate 1195a.

[0276] As Figure 18B shown, Figure 18A the crystal growth substrate 1001 shown is removed from the substrate 1195a by wet etching or laser lift-off or the like to form a substrate 1195b.

[0277] As Figure 18C shown, a substrate 102 having a metal layer 1130 formed on the first surface 102a is prepared. A plurality of substrates 1195b are arranged in a lattice pattern, for example, and the exposed surface of the n-type semiconductor layer 1151 is arranged to face the exposed surface of the metal layer 1130. The exposed surface of the n-type semiconductor layer 1151 is bonded to the substrate 102 via the metal layer 1130.

[0278] The process of bonding the semiconductor layer 1150 and the metal layer 1130 to the substrate 102 can be applied in the manner or a modified example described as the manufacturing method of the first embodiment. For example, a semiconductor growth substrate for growing the semiconductor layer 1150 may be used on the crystal growth substrate 1001 via a buffer layer. In this case, it is necessary to remove the buffer layer before bonding to the metal layer 1130. Alternatively, the crystal growth substrate 1001 may be grown from the p-type semiconductor layer, and the exposed surface of the n-type semiconductor layer 1151 may be bonded to the metal layer without being transferred to the support substrate. Alternatively, a metal layer may also be formed on the exposed surface of the n-type semiconductor layer 1151 of the substrate 1195b, and the metal layers may be bonded to each other, which is the same as in the case of the above-described other embodiments.

[0279] As Figure 19A shown, Figure 18B the support substrate 1190 shown is removed by wet etching or the like. The position X1 is the position where the ends to which a plurality of semiconductor layers 1150 are bonded are arranged.

[0280] As Figure 19B shown, Figure 19A the semiconductor layer 1150 shown is etched into a desired shape to form a light-emitting element 250. In the formation of the light-emitting element 250, for example, a dry etching process is used, and RIE is preferably used.

[0281] After the light-emitting element 250 is formed, Figure 19AThe shown metal layer 1130 is etched to form a conductive layer 130. Through the etching of the metal layer 1130, a connection plate 130a of the conductive layer 130 is formed under the light-emitting element 250.

[0282] As Figure 20A shown, a first interlayer insulating film 156 is formed to cover the first surface 102a, the conductive layer 130, the connection plate 130a, and the light-emitting element 250.

[0283] As Figure 20B shown, over the first interlayer insulating film 156, a TFT lower layer film 106 is formed by CVD or the like. A TFT channel 204 is formed over the planarized TFT lower layer film 106. An insulating layer 105 is formed to cover the TFT lower layer film 106 and the TFT channel 204. A gate 107 is formed over the TFT channel 204 via the insulating layer 105. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

[0284] As Figure 21A shown, a via hole 162k is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156, and reach the connection plate 130a. An opening 158 is formed by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 on the light-emitting surface 253S, and reach the light-emitting surface 253S. A via hole 112d is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105, and reach the region 204d. A via hole 112s is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105, and reach the region 204s. In the formation of the via holes 162k, 112d, 112s or the opening 158, for example, RIE or the like is used.

[0285] As Figure 21B shown, a via hole 161k is formed by filling a conductive material in the Figure 21A shown via hole 162k. Via holes 111d, 111s are also respectively formed by filling conductive materials in the Figure 21A shown via holes 112d, 112s. Thereafter, a wiring layer 110 is formed, and wirings 210k, 110d, 110s are formed. The wiring layer 110 can be formed simultaneously with the formation of the via holes 161k, 111d, 111s.

[0286] A light-transmissive conductive film is formed to cover the second interlayer insulating film 108, the light-emitting surface 253S, and the wiring layer 110. By photolithography of the formed conductive film, light-transmissive electrodes 159d, 159s are formed.

[0287] A transparent electrode 159d is formed on the light-emitting surface 253S and on the wiring 110d. The transparent electrode 159d is also formed between the light-emitting surface 253S and the wiring 110d to electrically connect the light-emitting surface 253S and the wiring 110d. The transparent electrode 159s is formed over the wiring 110s. The transparent electrode 159k is formed over the wiring 210k. The transparent electrodes 159d, 159s, and 159k are formed simultaneously.

[0288] Hereinafter, sub-pixels 220 of the image display device 201 of the present embodiment are formed by providing a color filter 180 (wavelength conversion member) and the like.

[0289] The effects of the image display device of the present embodiment will be described.

[0290] In the image display device of the present embodiment, as in the case of the above-described other embodiments, in addition to the effects of being able to shorten the time of the transfer process for forming the light-emitting element 250 and reducing the number of processes, by making the polarity of the TFT a p-channel, the light-emitting surface 253S can be a p-type semiconductor layer 253.

[0291] (Third Embodiment)

[0292] Figure 22 FIG. is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.

[0293] In the present embodiment, the conductive auxiliary plate 135a is provided between the connection plate 130a and the light-emitting element 150, which is different from the case of the above-described other embodiments. The same components as those in the first embodiment are denoted by the same reference numerals and the detailed description thereof is appropriately omitted.

[0294] As Figure 22 shown, the sub-pixel 320 of the image display device of the present embodiment includes a conductive auxiliary layer 135. The conductive auxiliary layer 135 is a layer provided on the conductive layer 130. The conductive auxiliary layer 135 includes a conductive auxiliary plate 135a, and the conductive auxiliary plate 135a is provided for each light-emitting element 150. The conductive auxiliary plate 135a is provided between the connection plate 130a and the p-type semiconductor layer 153. The p-type semiconductor layer 153 is in ohmic contact with the conductive auxiliary plate 135a at the bottom surface 153B, and the connection plate 130a and the p-type semiconductor layer 153 are electrically connected.

[0295] The conductive auxiliary layer 135 and the conductive auxiliary plate 135a are formed of a material having hole injection properties. Examples of the material having hole injection properties include ITO and the like. In the present embodiment, by bringing the material having hole injection properties into ohmic contact with the p-type semiconductor layer 153, the driving voltage of the light-emitting element 150 can be reduced.

[0296] In this example, the conductive auxiliary plate 135a and the connection plate 130a have the same square shape or the like when observed in the XY plane. The conductive auxiliary plate 135a is preferably connected over the bottom surface 153B with a large area, so that the outer periphery of the conductive auxiliary plate 135a coincides with the outer periphery of the bottom surface 153B, or may include the outer periphery of the bottom surface 153B.

[0297] The via hole 161a is provided between the conductive auxiliary plate 135a and the wiring 110a, and electrically connects the conductive auxiliary plate 135a and the wiring 110a. The p-type semiconductor layer 153 is electrically connected to the wiring 110a (first wiring) via the conductive auxiliary plate 135a, the connection plate 130a, and the via hole 161a. Since the conductive auxiliary plate 135a is for the purpose of electrically connecting to the p-type semiconductor layer 153, one end of the via hole 161a can penetrate the conductive auxiliary plate 135a and be connected to the connection plate 130a, for example.

[0298] The light emitting surface 151S is electrically connected to the wiring 110d (second wiring) via the light transmissive electrode 159d. Other detailed structures including the transistor 103 are the same as those in the first embodiment, and the description thereof is omitted.

[0299] A method for manufacturing the image display device of the present embodiment will be described.

[0300] Figures 23A to 25B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device of the present embodiment.

[0301] As Figure 23A shown, a semiconductor growth substrate 1194a is prepared. The semiconductor growth substrate 1194a has the same structure as that described with reference to Figure 7A That is, a semiconductor layer 1150 is formed on one surface of the crystal growth substrate 1001 of the semiconductor growth substrate 1194a. The semiconductor layer 1150 sequentially stacks an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153 from the side of the crystal growth substrate 1001.

[0302] A conductive auxiliary film 1235 is formed over the exposed surface of the p-type semiconductor layer 1153 of the semiconductor growth substrate 1194a. A metal layer (second metal layer) 1230 is formed over the exposed surface of the conductive auxiliary film 1235. The conductive auxiliary film 1235 is formed of a material having hole injection properties such as ITO. The metal layer 1230 is formed of Al or an Al alloy, a stacked film of Al and Ti, or the like.

[0303] The semiconductor growth substrate 1194a on which the conductive auxiliary film 1235 and the metal layer 1230 are formed is bonded to the first surface 102a of the substrate 102 via the metal layer 1230. Thereafter, the crystal growth substrate 1001 is removed by wet etching or laser lift-off or the like.

[0304] After preparing the substrate 102, a metal layer can be formed on the first surface 102a, and the exposed surface of the formed metal layer is opposed to the exposed surface of the metal layer 1230 formed on the semiconductor growth substrate 1194a, and they are bonded to each other.

[0305] In this example, the case where a single semiconductor growth substrate 1194a is bonded to the substrate 102 is described. However, similar to the cases of the above-described other embodiments, a plurality of semiconductor growth substrates can be arranged and bonded to one substrate 102, for example, in a lattice pattern. In addition, regarding the structure of the semiconductor growth substrate or the presence or absence of the support substrate, etc., the methods described in the above-described other embodiments can be applied.

[0306] As Figure 23B shown, Figure 23A The semiconductor layer 1150 shown is etched by RIE or the like and formed into a desired shape, thereby forming the light-emitting element 150. Figure 23A The metal layer 1230 and the conductive auxiliary film 1235 shown are etched and formed in a manner including the outer periphery of the light-emitting element 150, thereby forming the conductive layer 130 including the connection plate 130a (second part) and the conductive auxiliary layer 135 including the conductive auxiliary plate 135a.

[0307] As Figure 24A shown, the first interlayer insulating film 156 covering the first surface 102a, the connection plate 130a, the conductive auxiliary plate 135a, and the light-emitting element 150 is formed.

[0308] As Figure 24B shown, similar to the cases of the above-described other embodiments, the TFT lower layer film 106 is formed, the TFT channel 104 is formed, the insulating layer 105 is formed, and the gate 107 is formed. The second interlayer insulating film 108 covering the insulating layer 105 and the gate 107 is formed.

[0309] As Figure 25A shown, the via hole 162a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the conductive auxiliary plate 135a. The opening 158 and the via holes 112d, 112s are formed in the same manner as in the cases of the above-described other embodiments.

[0310] As Figure 25B shown, Figure 25A The via holes 162a, 112d, 112s shown are filled with a conductive material, thereby forming the vias 161a (second vias), 111d, 111s. The wiring layer 110 is formed on the second interlayer insulating film 108. A light-transmissive conductive film is formed on the wiring layer 110, and the light-transmissive electrodes 159a, 159d, 159s are formed.

[0311] The effects of the image display device according to this embodiment will be described.

[0312] In the image display device according to this embodiment, the conductive auxiliary layer 135 and the conductive auxiliary plate 135a are formed of a material having hole injection properties such as ITO. Since the p-type semiconductor layer 153 is connected to the conductive auxiliary plate 135a, the potential barrier decreases, and the operating voltage of the light-emitting element 150 can be reduced. By reducing the operating voltage of the light-emitting element 150, the power consumption of the light-emitting element 150 is reduced. As the operating voltage of the light-emitting element 150 decreases, the driving voltage of the sub-pixel 20 itself can also be reduced, thereby further reducing the overall power consumption of the image display device.

[0313] (Fourth Embodiment)

[0314] Figure 26 FIG. is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0315] In this embodiment, it is different from the third embodiment in that the via hole 461a is provided between the conductive auxiliary plate 135a and the wiring 110d. It is also different from the third embodiment in that the light-emitting element 150 is driven by a p-type transistor 203. The same components as those in the above-described other embodiments are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted.

[0316] As Figure 26 shown, the sub-pixel 420 of the image display device according to this embodiment includes a substrate 102, a conductive layer 130, a light-emitting element 150, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via hole 461a, and a wiring layer 110. The transistor 203 is a p-channel TFT. The light-emitting element 150 provides a light-emitting surface 151S based on the n-type semiconductor layer 151. The bottom surface 153B of the light-emitting element 150 is provided on the conductive auxiliary plate 135a, and the p-type semiconductor layer 153 is electrically connected to the conductive auxiliary plate 135a.

[0317] The light-emitting element 150 is provided on the conductive auxiliary plate 135a. The conductive auxiliary plate 135a is provided in the same manner as in the third embodiment. The connection plate 130a is provided directly below the light-emitting element 150 and also functions as a light reflector, thereby improving the substantial light-emitting efficiency of the light-emitting element 150.

[0318] The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes wirings 110k, 110d, 110s. The wiring 110k is connected to, for example, Figure 17 the ground wire 4 of the circuit shown.

[0319] A part of the wiring 110d is disposed above the transistor 203 and is connected to the region 204d via the via hole 111d. Another part of the wiring 110d (the third wiring) is disposed near the light-emitting element 150 and is connected to the conductive auxiliary plate 135a via the via holes 461a. That is, the via hole 461a is disposed between the conductive auxiliary plate 135a and the wiring 110d and electrically connects the conductive auxiliary plate 135a and the wiring 110d. The via hole 461a can penetrate the conductive auxiliary plate 135a and connect to the conductive auxiliary plate 135a, which is the same as in the case of the third embodiment.

[0320] The wiring 110s is connected to, for example, Figure 17 the power supply line 3 of the circuit shown.

[0321] The light-transmissive electrode 159k is disposed over the wiring 110k (the fourth wiring). The light-transmissive electrode 159k is disposed over the light-emitting surface 151S. The light-transmissive electrode 159k is disposed between the wiring 110k and the light-emitting surface 151S. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground line 4 via the light-transmissive electrode 159k and the wiring 110k.

[0322] The light-transmissive electrode 159d is disposed over the wiring 110d. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain of the transistor 203, i.e., the region 204d, via the conductive auxiliary plate 135a, the connection plate 130a, the via hole 461a, the wiring 110d, the light-transmissive electrode 159d, and the via hole 111d.

[0323] The light-transmissive electrode 159s is disposed over the wiring 110s. The wiring 110s and the light-transmissive electrode 159s are connected to, for example, Figure 13 the power supply line 3 shown. Therefore, the region 204s of the transistor 203 is electrically connected to the power supply line 3 via the via hole 111s, the wiring 110s, and the light-transmissive electrode 159s.

[0324] The via holes 461a, 111d, 111s and the wirings 110k, 110d1, 110s are formed of the same materials and by the same manufacturing method as in the above-described other embodiments and their modified examples.

[0325] Similar to the case of the above-described other embodiments, a color filter 180 or the like is also provided.

[0326] A method for manufacturing the image display device of the present embodiment will be described.

[0327] Figure 27A And Figure 27B are schematic cross-sectional views illustrating the method for manufacturing the image display device of the present embodiment.

[0328] In the manufacturing method of the present embodiment, the procedure is the same as that of the manufacturing method in the case of the third embodiment up to the middle. Hereinafter, after the process of forming the second interlayer insulating film 108 in Figure 24B the process of Figure 27A and Figure 27B is performed. However, compared with forming an n-channel transistor 103 on the TFT lower layer film 106 in Figure 24B , in the present embodiment, a p-channel transistor 203 is formed on the TFT lower layer film 106. The forming method of the p-channel transistor 203 is the same as that in the case of the second embodiment described above, and the detailed description is omitted.

[0329] As Figure 27A shows, the via hole 462a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156, and reaches the conductive auxiliary plate 135a. The opening 158 and the via holes 112d and 112s are formed in the same manner as in the case of the above-described other embodiments.

[0330] As Figure 27B shows, Figure 27A the via holes 462a, 112d, and 112s shown are filled with a conductive material to form via holes 461a, 111d, and 111s. A wiring layer 110 is formed on the second interlayer insulating film 108. A light-transmissive conductive film is formed on the wiring layer 110 to form light-transmissive electrodes 159k, 159d, and 159s.

[0331] The effects of the image display device of the present embodiment will be described.

[0332] According to the image display device of the present embodiment, in addition to the effects of the above-described third embodiment, it also has the following effects. That is, in the present embodiment, it is possible to have a circuit structure in which the n-type semiconductor layer 151 is the light-emitting surface 151S and the light-emitting element 150 is driven by the p-channel transistor 203. Therefore, the change in the circuit configuration and the like is expanded, and flexible circuit design becomes possible. In addition, by making the n-type semiconductor layer 151 the light-emitting surface 151S, the same effect as in the case of the first embodiment can be obtained, that is, the roughening of the light-emitting surface becomes easy. In addition, it is also possible to improve the light-emitting efficiency and obtain the effect of suppressing the increase in loss due to the contact resistance by roughening the light-emitting surface.

[0333] (Fifth Embodiment)

[0334] The image display device of the present embodiment includes a flexible substrate 502 instead of a glass substrate. Circuit elements such as light-emitting elements and transistors are formed on the first surface 502a of the substrate 502. In other respects, it is the same as in the case of the third embodiment described above, and the same reference numerals are given to the same components, and detailed descriptions are appropriately omitted.

[0335] Figure 28 FIG. is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.

[0336] As Figure 28 shown, the image display device of the present embodiment includes a sub-pixel 520. The sub-pixel 520 includes a substrate 502. The substrate 502 includes a first surface 502a. When the substrate 502 is formed of an organic material such as resin, a layer 507 including a silicon compound is formed on the first surface 502a. The layer 507 including a silicon compound is formed of SiO2 or SiNx, etc. Since the conductive layer 130 is formed of a metal material, the layer 507 including a silicon compound is provided to improve the adhesion between the substrate 502 and the conductive layer 130.

[0337] The conductive layer 130 and the connection plate 130a are provided on the first surface 502a via the layer 507 including a silicon compound. A conductive auxiliary plate 135a is preferably provided on the connection plate 130a, and the light-emitting element 150 is provided on the conductive auxiliary plate 135a. In this example, the structures and components above the conductive layer 130 and the connection plate 130a are the same as in the case of the third embodiment described above, and detailed descriptions are omitted.

[0338] The substrate 502 has flexibility. The substrate 502 is formed of, for example, a polyimide resin or the like. The first interlayer insulating film 156, the second interlayer insulating film 108, the wiring layer 110, etc. are preferably formed of a material having a certain degree of flexibility according to the flexibility of the substrate 502. It should be noted that the wiring layer 110 having the longest wiring length has the highest risk of being damaged during bending. Therefore, it is preferable to adjust various film thicknesses, film qualities, and materials so that the neutral plane including a plurality of protective films added on the surface or back as needed is located at the position of the wiring layer 110.

[0339] In this example, the structures and components above the layer 507 including a silicon compound are the same as in the case of the third embodiment, but can also be the above-described other embodiments or modified examples. In addition, it can also be applied to the structure of the sixth embodiment described later.

[0340] A method for manufacturing the image display device of the present embodiment will be described.

[0341] Figure 29A And Figure 29B FIG. is a schematic cross-sectional view illustrating a method for manufacturing the image display device of the present embodiment.

[0342] As Figure 29A shown, in the present embodiment, a substrate 1002 different from the cases of the above-described other embodiments is prepared. The substrate 1002 (fourth substrate) includes two layers of substrates 102 and 502. The substrate 102 is, for example, a glass substrate. The substrate 502 is provided on the first surface 102a of the substrate 102. For example, the substrate 502 is formed by coating polyimide on the first surface 102a and firing. Before forming the substrate 502, an inorganic film such as SiNx may be formed on the first surface 102a. In this case, the substrate 502 is formed by coating a polyimide material on the inorganic film and firing.

[0343] Over the first surface 502a of the substrate 502, a layer 507 including a silicon compound is formed. The first surface 502a of the substrate 502 is the surface opposite to the surface on which the substrate 102 is provided.

[0344] By applying the processes described, for example, in Figures 23A to 25B 、 Figure 13 and Figures 14A to 14D to such a substrate 1002, the upper structure of the sub-pixel 520 is formed.

[0345] As Figure 29B shown, the substrate 102 is removed from the structure in which an upper structure including a color filter (not shown) and the like is formed. In the removal of the substrate 102, for example, laser lift-off or the like is used.

[0346] The removal of the substrate 102 is not limited to the above-described time point and can be performed at an appropriate time point. If there is a process of being exposed to high temperature after removing the substrate 102 and the substrate 502 is made of an organic resin, the substrate 502 may shrink due to heating or the like. Therefore, in the processes after such a process of being exposed to high temperature, it is preferable to remove the substrate 102. For example, it is preferable to remove the substrate 102 after the process of forming the wiring layer 110 is completed. By removing the substrate 102 at an appropriate time point, it is sometimes possible to reduce defects such as cracks or notches in the manufacturing process.

[0347] The effects of the image display device of the present embodiment will be described.

[0348] In addition to the effects of the above-described other embodiments, the image display device of the present embodiment has the following effects. That is, since the substrate 502 has flexibility, the image display device can be bent and processed, and it is possible to realize attachment to a curved surface and utilization for a wearable terminal or the like without a sense of incongruity.

[0349] (Sixth Embodiment)

[0350] Figure 30It is a schematic cross-sectional view showing a part of the image display device according to the present embodiment.

[0351] In the present embodiment, an image display device with higher luminous efficiency is realized by forming a plurality of light-emitting surfaces 653S1 and 653S2 on a single semiconductor layer 650 including a light-emitting layer. In the following description, the same components as those in the above-described other embodiments are denoted by the same reference numerals, and the detailed description is appropriately omitted.

[0352] As Figure 30 shown, the image display device according to the present embodiment includes a sub-pixel group 620. The sub-pixel group 620 includes a substrate 102, a semiconductor layer 650, a first interlayer insulating film 156, transistors 203-1 and 203-2, a second interlayer insulating film 108, and a wiring layer 110. The semiconductor layer 650 is provided on a connection plate 630a, and the connection plate 630a is provided on a first surface 102a of the substrate 102. In each cross-sectional view of the present embodiment, in order to avoid complexity in representation, the reference numeral of the conductive layer 130 is shown side by side with the reference numeral of the connection plate 630a.

[0353] In the present embodiment, the conductive layer 130 and the connection plate 630a are connected to, for example, Figure 17 the ground wire 4 of the circuit. By turning on the p-channel transistor 203-1, holes are injected into the light-emitting surface 653S1 via the light-transmissive electrode 659d1. In addition, by turning on the p-channel transistor 203-2, holes are injected into the light-emitting surface 653S2 via the light-transmissive electrode 659d2. The semiconductor layer 650 causes the light-emitting layer 652 to emit light by the recombination of holes and electrons near each of the light-emitting surfaces 653S1 and 653S2 into which holes have been injected. The drive circuit for driving the light-emitting layer 652 is applicable to, for example, Figure 17 the circuit structure shown. As in the above-described other embodiments, a structure in which the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer are replaced up and down, and the semiconductor layer is driven by an n-channel transistor is possible. In this case, the drive circuit is applicable to Figure 3 the circuit structure of.

[0354] The structure of the sub-pixel group 620 will be described in detail.

[0355] The conductive layer 130 is provided on the first surface 102a. The conductive layer 130 includes a connection plate 630a. The semiconductor layer 650 is provided on the first surface 102a via the connection plate 630a. The semiconductor layer 650 has a bottom surface 651B, and the connection plate 630a is connected to the bottom surface 651B. The outer periphery of the connection plate 630a is set to include the outer periphery of the semiconductor layer 650 when the semiconductor layer 650 is projected onto the connection plate 630a as viewed in the XY plane. Therefore, the connection plate 630a reflects the scattered light below the semiconductor layer 650 upward toward the light emitting surfaces 653S1, 653S2. Therefore, the substantial light emitting efficiency of the semiconductor layer 650 is improved.

[0356] The semiconductor layer 650 includes a plurality of light emitting surfaces 653S1, 653S2. The semiconductor layer 650 is a prismatic or cylindrical laminate having a bottom surface 651B connected to the connection plate 630a. The light emitting surfaces 653S1, 653S2 are surfaces opposite to the bottom surface 651B. The light emitting surfaces 653S1, 653S2 are preferably surfaces in a plane substantially parallel to the bottom surface 651B. The plane including the light emitting surface 653S1 and the plane including the light emitting surface 653S2 may be the same plane or different planes. The light emitting surfaces 653S1, 653S2 are separated and provided in the X-axis direction.

[0357] The semiconductor layer 650 includes an n-type semiconductor layer 651, a light emitting layer 652, and a p-type semiconductor layer 653. The n-type semiconductor layer 651, the light emitting layer 652, and the p-type semiconductor layer 653 are laminated in order from the bottom surface 651B toward the light emitting surfaces 653S1, 653S2.

[0358] The bottom surface 651B is an n-type semiconductor, and the n-type semiconductor layer 651 is electrically connected to an external circuit connected via the bottom surface 651B and the connection plate 130a, such as Figure 17 the ground wire 4 of the circuit.

[0359] The p-type semiconductor layer 653 has two light emitting surfaces 653S1, 653S2 on the upper surface. That is, one sub-pixel group 620 substantially includes two sub-pixels. In the present embodiment, as in the case of the above-described other embodiments, the display region is formed by arranging the sub-pixel groups 620 substantially including two sub-pixels in a lattice pattern.

[0360] The first interlayer insulating film 156 (first insulating film) covers the first surface 102a, the conductive layer 130, the connection plate 630a, the side surfaces of the n-type semiconductor layer 651, the side surfaces of the light-emitting layer 652, and the side surfaces of the p-type semiconductor layer 653. The first interlayer insulating film 156 covers a part of the upper surface of the p-type semiconductor layer 653. In the p-type semiconductor layer 653, the light-emitting surfaces 653S1 and 653S2 are not covered by the first interlayer insulating film 156. The first interlayer insulating film 156 is preferably a white resin, as in the case of the above-described other embodiments.

[0361] The TFT lower layer film 106 is formed over the entire first interlayer insulating film 156. The TFT lower layer film 106 is not provided on the light-emitting surfaces 653S1 and 653S2. The TFT lower layer film 106 is planarized, and TFT channels 204-1, 204-2, etc. are formed on the TFT lower layer film 106.

[0362] The insulating layer 105 covers the TFT lower layer film 106 and the TFT channels 204-1, 204-2. The gate 107-1 is provided on the TFT channel 204-1 via the insulating layer 105. The gate 107-2 is provided on the TFT channel 204-2 via the insulating layer 105. The transistor 203-1 includes the TFT channel 204-1 and the gate 107-1. The transistor 203-2 includes the TFT channel 204-2 and the gate 107-2.

[0363] The second interlayer insulating film 108 (second insulating film) covers the insulating layer 105, the gates 107-1, 107-2.

[0364] The TFT channels 204-1, 204-2 are included in a p-type doped region, and the transistors 203-1, 203-2 are p-channel TFTs. The transistor 203-1 is provided at a position closer to the light-emitting surface 653S1 than the light-emitting surface 653S2. The transistor 203-2 is provided at a position closer to the light-emitting surface 653S2 than the light-emitting surface 653S1.

[0365] A light-transmissive electrode 659d1 is provided over the entire light-emitting surface 653S1. An opening 658-1 is provided above the light-emitting surface 653S1 and the light-transmissive electrode 659d1. A light-transmissive electrode 659d2 is provided over the entire light-emitting surface 653S2. An opening 658-2 is provided above the light-emitting surface 653S2 and the light-transmissive electrode 659d2. The second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 are not provided in the openings 658-1, 658-2. The light-emitting surfaces 653S1, 653S2 are exposed from the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156. The openings 658-1, 658-2 are filled with the surface resin layer 170.

[0366] The light-emitting surfaces 653S1 and 653S2 are square, rectangular, or other polygonal or circular shapes when observed in the XY plane. The shape of the uppermost part of the openings 658-1 and 658-2 can also be square, rectangular, or other polygonal or circular shapes. For the purpose of reducing the loss caused by the reflection of light from the wall surfaces of the openings 658-1 and 658-2, the openings 658-1 and 658-2 are preferably formed in a tapered shape, for example, in such a way that the area widens upward as in this example. When observed in the XY plane, the shapes of the light-emitting surfaces 653S1 and 653S2 and the shapes of the uppermost parts of the openings 658-1 and 658-2 may be similar or dissimilar.

[0367] The wiring layer 110 is provided on the second interlayer insulating film 108. The wiring layer 110 includes wirings 610s1, 610d1, 610d2, and 610s2. The wirings 610s1 and 610s2 are connected to, for example, Figure 17 the power supply line 3 of the circuit shown.

[0368] The vias 111d1, 111s1, 111d2, and 111s2 are formed to penetrate the second interlayer insulating film 108, the insulating layer 105, and the TFT lower layer film 106. The via 111d1 is provided between the p-type doped region on one side of the transistor 203-1 and the wiring 610d1. The via 111s1 is provided between the p-type doped region on the other side of the transistor 203-1 and the wiring 610s1. The via 111d2 is provided between the p-type doped region on one side of the transistor 203-2 and the wiring 610d2. The via 111s2 is provided between the p-type doped region on the other side of the transistor 203-2 and the wiring 610s2.

[0369] The wiring 610d1 is connected to the p-type region corresponding to the drain of the transistor 203-1 via the via 111d1. The wiring 610s1 is connected to the p-type region corresponding to the source of the transistor 203-1 via the via 111s1. The wiring 610d2 is connected to the region corresponding to the drain of the transistor 203-2 via the via 111d2. The wiring 610s2 is connected to the region of the source of the transistor 203-2 via the via 111s2.

[0370] The transparent electrode 659d1, together with the light-emitting surface 653S1, is provided over the wiring 610d1. The transparent electrode 659d1 is also provided between the light-emitting surface 653S1 and the wiring 610d1 and electrically connects the light-emitting surface 653S1 and the wiring 610d1. The transparent electrode 659s1 is provided over the wiring 610s1. Accordingly, the p-type semiconductor layer 653 is electrically connected to the drain-corresponding region of the channel region 204-1 via the light-emitting surface 653S1, the transparent electrode 659d1, the wiring 610d1, and the via hole 111d1. The source-corresponding region of the channel region 204-1 is electrically connected to the power supply line 3 via the via hole 111s1, the wiring 610s1, and the transparent electrode 659s1.

[0371] The transparent electrode 659d2, together with the light-emitting surface 653S2, is provided over the wiring 610d2. The transparent electrode 659d2 is also provided between the light-emitting surface 653S2 and the wiring 610d2 and electrically connects the light-emitting surface 653S2 and the wiring 610d2. The transparent electrode 659s2 is provided over the wiring 610s2. Accordingly, the p-type semiconductor layer 653 is electrically connected to the drain-corresponding region of the channel region 204-2 via the light-emitting surface 653S2, the transparent electrode 659d2, the wiring 610d2, and the via hole 111d2. The source-corresponding region of the channel region 204-2 is electrically connected to the power supply line 3 via the via hole 111s2, the wiring 610s2, and the transparent electrode 659s2.

[0372] The transistors 203-1 and 203-2 are, for example, driving transistors of adjacent sub-pixels and are driven in sequence. Holes supplied from either of the two transistors 203-1 and 203-2 are injected into the light-emitting layer 652, and electrons supplied from the connection plate 630a are injected into the light-emitting layer 652, whereby the light-emitting layer 652 emits light.

[0373] In the present embodiment, drift current flowing in a direction parallel to the XY plane is suppressed by the resistance of the n-type semiconductor layer 651 and the p-type semiconductor layer 653. Accordingly, holes injected from the light-emitting surfaces 653S1 and 653S2 or electrons injected from the connection plate 630a all advance along the stacking direction of the semiconductor layer 650. Since almost no light-emitting sources exist outside the light-emitting surfaces 653S1 and 653S2, the plurality of light-emitting surfaces 653S1 and 653S2 provided in one semiconductor layer 650 can be selectively caused to emit light by the transistors 203-1 and 203-2, respectively.

[0374] In this way, the light-emitting sources in the semiconductor layer 650 are almost determined by the arrangement of the light-emitting surfaces 653S1 and 653S2. Accordingly, the connection plate 630a can be provided for each of the light-emitting surfaces 653S1 and 653S2 according to the positions and shapes of the light-emitting surfaces 653S1 and 653S2.

[0375] A method for manufacturing the image display device according to this embodiment will be described.

[0376] Figures 31A to 33B FIG. is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0377] As Figure 31A shown, a semiconductor growth substrate (second substrate) 1294a and a substrate 102 (third substrate) are prepared. The semiconductor growth substrate 1294a includes a crystal growth substrate 1001 and a semiconductor layer. The semiconductor layer 1150 includes a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151, and is laminated in this order from the crystal growth substrate 1001 side. A metal layer 1230 is formed on the exposed surface of the n-type semiconductor layer 1151. The substrate 102 is the same substrate as in the case of the above-described other embodiments, and a detailed description thereof is omitted.

[0378] The semiconductor growth substrate 1294a on which the metal layer 1230 is formed is disposed such that the exposed surface of the metal layer 1230 faces the first surface 102a of the substrate 102. The semiconductor layer 1150 is bonded to the first surface 102a via the metal layer 1230.

[0379] The above is an example in which the metal layer 1230 is formed on the semiconductor layer 1150 side, but the metal layer may be formed on at least one of the substrate 102 side and the semiconductor layer 1150 side.

[0380] The metal layer has a function as a light reflector as described later, and is also used for electrical connection of the lower layer of the semiconductor layer 650. Therefore, in order to reduce the resistance value, it is preferable to make the metal layer thicker. For example, a metal layer may be formed on the first surface 102a, and the metal layers may be bonded to each other and used as a wiring layer having a lower resistance.

[0381] As Figure 31B shown, Figure 31A the crystal growth substrate 1001 shown is removed. In the removal of the crystal growth substrate 1001, for example, wet etching or laser lift-off is used. Figure 31A The semiconductor layer 1150 shown is processed into a desired shape by etching. After that, Figure 31A the metal layer 1230 shown is formed into a connection plate 630a by etching. The connection plate 630a constitutes Figure 30 the conductive layer 130 shown, and is connected to, for example, Figure 17 the ground wire 4 of the circuit.

[0382] The outer periphery of the connection plate 630a is set to include the outer periphery of the semiconductor layer 650 when the semiconductor layer 650 is projected onto the connection plate 630a as viewed in the XY plane. The outer periphery of the connection plate 630a is preferably set so that when the transistors 203-1 and 203-2 are projected onto the connection plate 630a as viewed in the XY plane, it does not include the outer perimeters of the transistors 203-1 and 203-2. The outer perimeters of the transistors 203-1 and 203-2 as viewed in the XY plane are the outer perimeters of the TFT channels 204-1 and 204-2 as viewed in the XY plane.

[0383] As Figure 32A shown, the first interlayer insulating film 156 is formed to cover the first surface 102a, the connection plate 630a, and the semiconductor layer 650.

[0384] As Figure 32B shown, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the TFT channels 204-1 and 204-2 are formed on the TFT lower layer film 106. An insulating layer 105 is formed over the TFT lower layer film 106 and the TFT channels 204-1 and 204-2. The gate 107-1 is formed over the TFT channel 204-1 via the insulating layer 105. The gate 107-2 is formed over the TFT channel 204-2 via the insulating layer 105. The second interlayer insulating film 108 is formed over the insulating layer 105 and the gates 107-1 and 107-2. The formation methods, materials, etc. of the TFT channels 204-1 and 204-2, the insulating layer 105, the gates 107-1 and 107-2, etc. can be the same as in the case of the above-described other embodiments.

[0385] As [[ID shown, vias 112d1 and 112s1 are formed that penetrate the second interlayer insulating film 108, the insulating layer 105, and the TFT lower layer film 106 and reach the TFT channel 204-1. Vias 112d2 and 112s2 are formed that penetrate the second interlayer insulating film 108, the insulating layer 105, and the TFT lower layer film 106 and reach the TFT channel 204-2. Openings 658-1 are formed that remove the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the light-emitting surface 653S1. Openings 658-2 are formed that remove the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the light-emitting surface 653S2.

[0386] As ​As shown, conductive materials are filled in via holes 112d1, 112s1, 112d2, and 112s2 to form via holes 111d1, 111s1, 111d2, and 111s2. A wiring layer 110 is formed, and wirings 610d1, 610s1, 610d2, and 610s2 are formed.

[0387] Light-emitting surfaces 653S1 and 653S2 are roughened respectively. Thereafter, a light-transmissive conductive film is provided so as to cover the wiring layer 110, thereby forming light-transmissive electrodes 659d1, 659s1, 659d2, and 659s2. The light-transmissive electrode 659d1 is formed so as to cover the light-emitting surface 653S1 and electrically connect the light-emitting surface 653S1 and the wiring 610d1. The light-transmissive electrode 659d2 is formed so as to cover the light-emitting surface 653S2 and electrically connect the light-emitting surface 653S2 and the wiring 610d2.

[0388] Thereafter, an upper structure such as a color filter is formed.

[0389] In this way, a sub-pixel group 620 having a semiconductor layer 650 is formed, and the semiconductor layer 650 has two light-emitting surfaces 653S1 and 653S2.

[0390] In the present embodiment, two light-emitting surfaces 653S1 and 653S2 are provided in one semiconductor layer 650, but the number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces may be provided in one semiconductor layer 650. As an example, one column and two columns of sub-pixels can be realized by a single semiconductor layer 650. Thus, as will be described later, the recombination current that does not contribute to the light emission of each light-emitting surface can be reduced, and the effect of realizing a finer light-emitting element can be enhanced.

[0391] (Modification example)

[0392] ​ FIG. is a schematic cross-sectional view showing a part of an image display device according to a modification example of the present embodiment.

[0393] In this modification example, two p-type semiconductor layers 6653a1 and 6653a2 are provided on the light-emitting layer 652, which is different from the sixth embodiment described above. In other respects, it is the same as the case of the sixth embodiment, and the same reference numerals are given to the same structural elements and the detailed description is appropriately omitted.

[0394] As ​As shown, the image display device of this modification example includes a sub-pixel group 620a. The sub-pixel group 620a includes a semiconductor layer 650a. The semiconductor layer 650a includes an n-type semiconductor layer 651, a light-emitting layer 652, and p-type semiconductor layers 6653a1 and 6653a2. The n-type semiconductor layer 651 and the light-emitting layer 652 are sequentially stacked from the bottom surface 651B. The p-type semiconductor layers 6653a1 and 6653a2 are both stacked on the light-emitting layer 652.

[0395] The p-type semiconductor layers 6653a1 and 6653a2 are formed in an island shape on the light-emitting layer 652 and are arranged at intervals along the X-axis direction. A first interlayer insulating film 156 is provided between the n-type semiconductor layers 6653a1 and 6653a2, and the p-type semiconductor layers 6653a1 and 6653a2 are separated by the first interlayer insulating film 156.

[0396] The p-type semiconductor layers 6653a1 and 6653a2 have substantially the same shape when viewed in the XY plane, and the shape is substantially square or rectangular, and may also be other polygonal shapes or circular shapes, etc.

[0397] The p-type semiconductor layer 6653a1 has a light-emitting surface 6653S1. The p-type semiconductor layer 6653a2 has a light-emitting surface 6653S2. The light-emitting surface 6653S1 is the surface of the p-type semiconductor layer 6653a1 exposed through the opening 658-1 from the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The light-emitting surface 6653S2 is the surface of the p-type semiconductor layer 6653a2 exposed through the opening 658-2 from the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108.

[0398] The shapes of the light-emitting surfaces 6653S1 and 6653S2 when viewed in the XY plane are the same as the shape of the light-emitting surface in the case of the sixth embodiment, having substantially the same shape, such as a substantially square shape. The shapes of the light-emitting surfaces 6653S1 and 6653S2 are not limited to the square shape of this embodiment, and may be polygonal shapes such as circular, elliptical, and hexagonal shapes. The shapes of the light-emitting surfaces 6653S1 and 6653S2 may be similar to the shapes of the openings 658-1 and 658-2, or may be different shapes.

[0399] The translucent electrode 659d1 is provided over the light-emitting surface 6653S1 and over the wiring 610d1. The translucent electrode 659d1 is provided between the light-emitting surface 6653S1 and the wiring 610d1 and electrically connects the light-emitting surface 6653S1 and the wiring 610d1. The translucent electrode 659d2 is provided over the light-emitting surface 6653S2 and over the wiring 610d2. The translucent electrode 659d2 is provided between the light-emitting surface 6653S2 and the wiring 610d2 and electrically connects the light-emitting surface 6653S2 and the wiring 610d2.

[0400] The manufacturing method of this modification will be described.

[0401] ​ It is a schematic cross-sectional view illustrating the manufacturing method of the image display device of this modification.

[0402] In this modification, up to the step of bonding the substrates to each other can be the same as in the case of the above-described sixth embodiment. Specifically, the steps up to the steps described with reference to ​ can be applied as the same steps. The subsequent steps will be described as the steps applicable to ​ the subsequent steps.

[0403] As ​ shown, in this modification, the semiconductor layer 1150 shown in ​ is etched to form the light-emitting layer 652 and the n-type semiconductor layer 651. Further etching is performed to form two p-type semiconductor layers 6653a1 and 6653a2.

[0404] When forming the p-type semiconductor layers 6653a1 and 6653a2, etching can be performed deeper. For example, the etching for forming the p-type semiconductor layers 6653a1 and 6653a2 can be performed to exceed the depth reaching the light-emitting layer 652 or the n-type semiconductor layer 651. In this way, when forming the p-type semiconductor layer by deep etching, it is preferable that the etching is more than 1 μm outside the outer periphery of the light-emitting surfaces 6653S1 and 6653S2 shown in ​ . By making the etching position more outside the outer periphery of the light-emitting surfaces 6653S1 and 6653S2, the recombination current can be suppressed.

[0405] After forming the semiconductor layer 650a, the metal layer 1230 shown in ​ is etched to form the connection plate 630a.

[0406] As ​ shown, the first surface 102a, the connection plate 630a, and the semiconductor layer 650a are covered to form the first interlayer insulating film 156.

[0407] As ​As shown, a TFT lower layer film 106 is formed on the first interlayer insulating film 156, and TFT channels 204-1 and 204-2 are formed on the TFT lower layer film 106. In addition, an insulating layer 105 is formed on the TFT channels 204-1 and 204-2, and gates 107-1 and 107-2 are formed on the insulating layer 105. The second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gates 107-1 and 107-2.

[0408] As ​ shown, via holes 112d1, 112s1, 112d2, and 112s2 are formed in the same manner as in the sixth embodiment. The opening 658-1 is formed in such a way as to remove the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the light emitting surface 6653S1. The opening 658-2 is formed in such a way as to remove the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the light emitting surface 6653S2.

[0409] As ​ shown, in the same manner as in the sixth embodiment, a wiring layer 110 is formed, and a light-transmissive conductive film covering the wiring layer 110 is formed. The light-transmissive conductive film is formed on the light-transmissive electrodes 659d1, 659s1, 659d2, and 659s2.

[0410] In the same manner as in the sixth embodiment, an upper structure such as a color filter is formed.

[0411] In this way, a sub-pixel group 620a having two light emitting surfaces 6653S1 and 6653S2 is formed.

[0412] This modification is also the same as in the sixth embodiment. The number of light emitting surfaces is not limited to two, and three or more light emitting surfaces can be provided on one semiconductor layer 650a.

[0413] The effects of the image display device of this embodiment will be described.

[0414] Figure 37 It is a chart illustrating the characteristics of the pixel LED element.

[0415] Figure 37 The vertical axis of [] represents the luminous efficiency [%]. The horizontal axis represents the relative value of the current density of the current flowing through the pixel LED element.

[0416] As Figure 37As shown, in a region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is substantially constant or monotonically increasing. In a region where the relative value of the current density is greater than 1.0, the luminous efficiency monotonically decreases. That is, there is an appropriate current density at which the luminous efficiency of the pixel LED element is maximized.

[0417] It is expected to achieve a high-efficiency image display device by suppressing the current density to an extent that sufficient luminance can be obtained from the light-emitting element. However, Figure 37 For example, at low current densities, as the current density decreases, the luminous efficiency tends to decrease.

[0418] As described from the first embodiment to the fifth embodiment, the light-emitting element is formed by individually separating the entire layer of the semiconductor layer 1150 including the light-emitting layer by etching or the like. At this time, the bonding surfaces of the light-emitting layer and the p-type semiconductor layer are exposed from the ends. Similarly, the bonding surfaces of the light-emitting layer and the n-type semiconductor layer are exposed from the ends.

[0419] In the presence of such ends, electrons and holes recombine at the ends. On the other hand, such recombination is not conducive to light emission. The recombination at the ends occurs almost independently of the current flowing through the light-emitting element. It is considered that the recombination occurs according to the length of the bonding surface that contributes to the light emission at the ends.

[0420] When two light-emitting elements having the same size and cubic shape are made to emit light, the four-sided sides become ends in each light-emitting element. Therefore, the two light-emitting elements have a total of eight ends, and recombination may occur at the eight ends.

[0421] In contrast, in the present embodiment, the semiconductor layers 650 and 650a have four-sided sides, and there are four ends on the two light-emitting surfaces. However, in the region between the openings 658-1 and 658-2, the injection of electrons or holes is small and hardly contributes to light emission. Therefore, the ends that contribute to light emission are considered to be six. Thus, in the present embodiment, by substantially reducing the number of ends of the semiconductor layer, the recombination that does not contribute to light emission is reduced. By reducing the recombination that does not contribute to light emission, the drive current for each light-emitting surface is reduced.

[0422] In the case of shortening the distance between sub-pixels for high definition or the like, or in the case of a relatively high current density, etc., in the sub-pixel group 620 of the sixth embodiment, the distance between the light-emitting surface 653S1 and the light-emitting surface 653S2 is substantially shortened. In this case, as in the sixth embodiment, if the p-type semiconductor layer is shared, a part of the holes injected into the driven light-emitting surface is shunted, and the non-driven light-emitting surface may emit weak light. In the sub-pixel group 620a of the modified example, the p-type semiconductor layer is separated into two, and each p-type semiconductor layer has a light-emitting surface. Therefore, it is possible to reduce the weak light emission generated on the non-driven side light-emitting surface.

[0423] In the present embodiment, the semiconductor layer including the light-emitting layer is stacked in the order of an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer from the side of the connection plate 630a. From the viewpoint of reducing manufacturing costs, it is preferable not to use a support substrate, and crystal growth is performed on the crystal growth substrate from the n-type semiconductor layer. As described above, similar to the case of other embodiments, instead of the stacking order of the n-type semiconductor layer and the p-type semiconductor layer, it may be stacked in the order of a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer from the side of the connection plate 630a. In addition, when the p-type semiconductor layer 653 is the lower layer and is connected to the connection plate 630a, as in the third embodiment, it is preferable to provide a conductive auxiliary plate between the connection plate 630a and the p-type semiconductor layer 653.

[0424] In the sub-pixels and sub-pixel groups of the image display device in the above-described embodiments, specific examples have been described. Each specific example is just an example, and by appropriately combining the structures or the order of processes of these embodiments, other configurations can be obtained. For example, in the first to fifth embodiments, instead of using vias, a connection plate is used for connecting power lines or ground lines, and in the sixth embodiment, vias can be used for electrical connection of the light-emitting elements.

[0425] (Seventh Embodiment)

[0426] The above-described image display device is an image display module having an appropriate number of pixels, and is, for example, a computer monitor, a television, a portable terminal such as a smartphone, and a vehicle navigation system.

[0427] Figure 38 It is a block diagram illustrating the image display device of the present embodiment.

[0428] In Figure 38 the main parts of the structure of a computer monitor are illustrated.

[0429] As Figure 38 shown, the image display device 701 includes an image display module 702. The image display module 702 is, for example, an image display device having the structure of the above-described first embodiment. The image display module 702 includes a display area 2 in which a plurality of sub-pixels including the sub-pixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

[0430] The image display device 701 further includes a controller 770. The controller 770 is separated by an interface circuit (not shown), inputs the generated control signal, and controls the driving and driving order of each sub-pixel for the row selection circuit 5 and the signal voltage output circuit 7.

[0431] (Modification Example)

[0432] The above-described image display device is an image display module having an appropriate number of pixels, such as a display for a computer, a television, a mobile terminal such as a smartphone, or a vehicle navigation system.

[0433] Figure 39 It is a block diagram of an image display device illustrating a modification example of the present embodiment.

[0434] In Figure 39 an example of the structure of a high-definition thin television is illustrated.

[0435] As Figure 39 shown, the image display device 801 includes an image display module 802. The image display module 802 is, for example, the image display device 1 having the structure of the above-described first embodiment. The image display device 801 includes a controller 870 and a frame memory 880. The controller 870 controls the driving order of each sub-pixel in the display area 2 based on a control signal supplied through a bus 840. The frame memory 880 stores display data for one frame and is used for processing such as smooth animation playback.

[0436] The image display device 801 has an I / O circuit 810. The I / O circuit 810 is abbreviated as "I / O" in Figure 39 . The I / O circuit 810 provides an interface circuit or the like for connecting to an external terminal or device. The I / O circuit 810 includes, for example, a USB interface for connecting to an external hard disk device or an audio interface.

[0437] The image display device 801 has a receiving unit 820 and a signal processing unit 830. An antenna 822 is connected to the receiving unit 820, and necessary signals are separated and generated from the radio waves received by the antenna 822. The signal processing unit 830 includes a DSP (Digital Signal Processor) or a CPU (Central Processing Unit), and the signals separated and generated by the receiving unit 820 are separated and generated into image data, sound data, or the like through the signal processing unit 830.

[0438] By making the receiving unit 820 and the signal processing unit 830 be high-frequency communication modules for sending and receiving mobile phones or for WiFi, GPS receivers, etc., it is also possible to be other image display devices. For example, an image display device having an image display module with an appropriate screen size and resolution can be a mobile information terminal such as a smartphone or a vehicle navigation system.

[0439] The image display module of the present embodiment is not limited to the structure of the image display device of the first embodiment, and can also be a modification example or other embodiments.

[0440] According to the embodiments described above, it is possible to shorten the transfer process of the light-emitting element and to realize a manufacturing method and an image display device of an image display device with an improved yield rate.

[0441] As described above, several embodiments of the present invention have been described, but these embodiments are merely examples and are not used to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made as long as the main content of the invention is not departed from. These embodiments or their modifications are included in the scope or main content of the invention and in the scope of the invention described in the claims and the scope of its equivalents. In addition, the above-described embodiments can be implemented in combination with each other.

[0442] Explanation of reference numerals

[0443] 1, 201, 701, 801: Image display device;

[0444] 2: Display area;

[0445] 3: Power supply line;

[0446] 4 Ground wire;

[0447] 5, 205: Row selection circuit;

[0448] 6, 206: Scan line;

[0449] 7, 207: Signal voltage output circuit;

[0450] 8, 208: Signal line;

[0451] 10: Pixel;

[0452] 20, 20a, 220, 320, 420, 520: Sub-pixel;

[0453] 22, 222: Light-emitting element;

[0454] 24, 224: Selection transistor;

[0455] 26, 226: Driving transistor;

[0456] 28, 228: Capacitor;

[0457] 101: Circuit;

[0458] 102, 502: Substrate;

[0459] 102a: First surface;

[0460] 103, 203, 203-1, 203-2: Transistor;

[0461] 104, 204, 204-1, 204-2: TFT channels;

[0462] 105: Insulating layer;

[0463] 107, 107-1, 107-2: Gates;

[0464] 108: Second interlayer insulating film;

[0465] 110: Wiring layer;

[0466] 130: Conductive layer;

[0467] 130a: Connecting plate;

[0468] 135: Conductive auxiliary layer;

[0469] 135a: Conductive auxiliary plate;

[0470] 150, 250: Light-emitting elements;

[0471] 151S, 253S, 653S1, 653S2, 6653S1, 6653S2: Light-emitting surfaces;

[0472] 156: First interlayer insulating film;

[0473] 159d, 159s, 159a, 159k, 659d1, 659d2: Transparent electrodes;

[0474] 161a, 161k, 461a: Through holes;

[0475] 180: Color filter;

[0476] 620, 620a: Sub-pixel groups;

[0477] 1001: Substrate for crystal growth;

[0478] 1140: Buffer layer;

[0479] 1150: Semiconductor layer;

[0480] 1190: Support substrate;

[0481] 1192: Structure;

[0482] 1194, 1194a, 1294, 1294a: Semiconductor growth substrates.

Claims

1. A manufacturing method of an image display device, comprising: a step of preparing a second substrate having a semiconductor layer including a light-emitting layer formed on a first substrate; a step of forming a first metal layer on a third substrate; a step of attaching the semiconductor layer to the first metal layer; a step of removing the first substrate; a step of etching the semiconductor layer to form a light-emitting element including a bottom surface on the first metal layer and a light-emitting surface disposed opposite to the bottom surface; a step of forming a first insulating film covering the third substrate and the light-emitting element; a step of forming circuit elements on the first insulating film; a step of forming a second insulating film covering the circuit elements and the first insulating film; a step of removing a part of the first insulating film and a part of the second insulating film to expose the surface including the light-emitting surface; a step of forming a wiring layer on the second insulating film.

2. The manufacturing method of the image display device according to claim 1, wherein: it further includes a step of processing the first metal layer after forming the light-emitting element to form a first portion having conductivity and light reflectivity, the light-emitting element is disposed on the first portion, when viewed from above, the outer periphery of the first portion includes the outer periphery of the light-emitting element when the light-emitting element is projected.

3. The manufacturing method of the image display device according to claim 2, wherein: it further includes a step of forming a first via hole that penetrates the first insulating film and the second insulating film and electrically connects the first portion and the wiring layer.

4. The manufacturing method of the image display device according to claim 1, wherein: the step of attaching the semiconductor layer to the third substrate includes attaching a plurality of the second substrates to one third substrate.

5. The manufacturing method of the image display device according to claim 1, wherein: the third substrate includes a light-transmissive substrate.

6. The manufacturing method of the image display device according to claim 5, wherein: the third substrate further includes a flexible fourth substrate disposed on the light-transmissive substrate, it further includes a step of removing the light-transmissive substrate after attaching the semiconductor layer to the fourth substrate in the step of attaching the semiconductor layer to the third substrate.

7. The manufacturing method of the image display device according to claim 1, wherein: it further includes a step of forming a light-transmissive electrode on the exposed light-emitting surface.

8. The manufacturing method of the image display device according to claim 1, wherein: the semiconductor layer includes a gallium nitride-based compound semiconductor.

9. The manufacturing method of the image display device according to claim 1, wherein: it further includes a step of forming a wavelength conversion member on the light-emitting element.

10. A manufacturing method of an image display device, comprising: a step of preparing a second substrate having a semiconductor layer including a light-emitting layer formed on a first substrate; a step of forming a second metal layer on the second substrate; a step of attaching the semiconductor layer to a third substrate via the second metal layer; a step of removing the first substrate; Etching the semiconductor layer to form a light-emitting element including a bottom surface on the second metal layer and a light-emitting surface disposed opposite to the bottom surface; Forming a first insulating film covering the third substrate and the light-emitting element; Forming circuit elements on the first insulating film; Forming a second insulating film covering the circuit elements and the first insulating film; Removing a part of the first insulating film and a part of the second insulating film to expose the surface including the light-emitting surface; Forming a wiring layer formed on the second insulating film.

11. The method of manufacturing an image display device according to claim 10, wherein, It further includes a step of forming a layer having hole injection properties on the semiconductor layer before forming the second metal layer, When the semiconductor layer is bonded to the third substrate, the first semiconductor layer of the first conductivity type, the light-emitting layer, and the second semiconductor layer of the second conductivity type different from the first conductivity type are stacked in this order from one side of the third substrate, The first conductivity type is p-type, The second conductivity type is n-type.

12. The method of manufacturing an image display device according to claim 10, wherein, It further includes a step of processing the second metal layer after forming the light-emitting element to form a second part having conductivity and light reflectivity, The light-emitting element is disposed on the second part, When viewed from above, the outer periphery of the second part includes the outer periphery of the light-emitting element when the light-emitting element is projected.

13. The method of manufacturing an image display device according to claim 12, wherein, It further includes a step of forming a second via hole that penetrates the first insulating film and the second insulating film and electrically connects the second part and the wiring layer.

14. An image display device, comprising: A substrate having a first surface; A conductive layer disposed on the first surface; A light-emitting element having a bottom surface on the conductive layer and including a surface opposite to the bottom surface, i.e., a light-emitting surface; A first insulating film covering the side surface of the light-emitting element and the conductive layer; Circuit elements disposed on the first insulating film; A second insulating film covering the circuit elements and the first insulating film; A wiring layer disposed on the second insulating film.

15. The image display device according to claim 14, wherein, The conductive layer includes a first part having conductivity and light reflectivity, The light-emitting element is disposed on the first part, When viewed from above, the outer periphery of the first part includes the outer periphery of the light-emitting element when the light-emitting element is projected onto the first part.

16. The image display device according to claim 15, wherein, The light-emitting element is stacked in the order of a first semiconductor layer of the first conductivity type, a light-emitting layer, and a second semiconductor layer of the second conductivity type different from the first conductivity type from one side of the first part toward the side of the light-emitting surface, The first conductivity type is p-type, The second conductivity type is n-type, A layer having hole injection property is further provided between the first part and the first semiconductor layer.

17. The image display device according to claim 16, wherein a via hole is further provided, which penetrates through the first insulating film and the second insulating film and electrically connects the first part and the wiring layer.

18. The image display device according to claim 17, wherein the wiring layer includes a first wiring connected to the via hole and a second wiring connected to the surface including the light emitting surface, the first semiconductor layer is electrically connected to the first wiring via the first part and the via hole, the second semiconductor layer is electrically connected to the circuit element via the surface including the light emitting surface and the second wiring.

19. The image display device according to claim 17, wherein the wiring layer includes a third wiring connected to the via hole and a fourth wiring connected to the surface including the light emitting surface, the first semiconductor layer is electrically connected to the circuit element via the first part, the via hole and the third wiring, the second semiconductor layer is electrically connected to the fourth wiring via the surface including the light emitting surface.

20. The image display device according to claim 14, wherein the substrate includes a light-transmissive substrate.

21. The image display device according to claim 14, wherein the substrate includes a flexible substrate.

22. The image display device according to claim 14, wherein a light-transmissive electrode provided on the light emitting surface is further provided, the light emitting element is connected to the wiring layer via the light-transmissive electrode.

23. The image display device according to claim 14, wherein the light emitting element includes a gallium nitride-based compound semiconductor.

24. The image display device according to claim 14, wherein the circuit element includes a thin film transistor.

25. The image display device according to claim 14, wherein a wavelength conversion component is further provided on the light emitting element.

26. An image display device, comprising: a substrate having a first surface; a conductive layer provided on the first surface; a semiconductor layer having a bottom surface on the conductive layer and including a plurality of light emitting surfaces on a surface opposite to the bottom surface; a first insulating film covering the side surface of the semiconductor layer and the conductive layer; a plurality of transistors provided on the first insulating film; a second insulating film covering the plurality of transistors and the first insulating film; a wiring layer provided on the second insulating film.

27. The image display device according to claim 26, wherein the semiconductor layer is stacked in the order of a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type from the conductive layer toward the plurality of light emitting surfaces, the second semiconductor layer is separated by the first insulating film.

Images