Method and communication device for constructing LDPC code

Abstract

The present application provides a method and communication device for constructing LDPC codes. When constructing LDPC codes, the PEXIT algorithm is used to select a base matrix that meets certain requirements to determine the optimal base matrix, rather than the traditional method of using a simple degree sequence of variable nodes and check nodes to generate a base matrix for the construction of LDPC codes. In addition, in the process of calculating the check matrix, the ACE algorithm is used, so that the constructed check matrix not only considers the impact of the ring length on the performance of the LDPC code, but also considers the impact of connectivity on the performance of the LDPC code. Compared with the traditional QC-LDPC code, the LDPC code has good waterfall performance and reduces the error floor, thereby improving the overall performance of the LDPC code from many aspects.

Description

Technical Field

[0001] The present application relates to the field of channel coding, and more specifically, to a method and a communication device for constructing LDPC codes. Background Art

[0002] Channel coding is an essential key technology for modern communication systems. The fundamental purpose of channel coding theory research is to achieve reliable communication that reaches the Shannon theoretical limit. In the process of digital signal transmission, due to various reasons, errors often occur in the transmitted data stream, causing image jumps and discontinuities at the receiving end. Channel coding can process the data stream accordingly, so that the system has certain error correction and anti-interference capabilities, which can greatly avoid the generation of errors in the code stream transmission process, thereby improving the efficiency of data transmission and reducing the bit error rate.

[0003] Low density parity check (LDPC) is a group error correction code with a sparse check matrix. It is applicable to almost all channels, and its performance is close to the Shannon limit. It has great application potential in the field of communications. There are many existing schemes for constructing LDPC codes, and different schemes consider different aspects of LDPC code performance improvement. For example, some schemes can reduce the bit error rate of LDPC codes, some schemes can simplify the construction complexity of LDPC codes, which is conducive to hardware implementation, and some schemes optimize the waterfall performance of LDPC codes.

[0004] However, when LDPC codes are applied to actual communication systems (e.g., satellite broadcast communication systems), LDPC codes need to meet multiple performance requirements to ensure the performance advantage of the entire communication system. Optimizing the performance of a single aspect is not enough. Therefore, how to improve the performance of LDPC codes as a whole and make them more suitable for application in actual communication systems is still a difficult point in promoting the application of LDPC codes. Summary of the invention

[0005] The present application provides a method for constructing an LDPC code and a communication device, which can improve the overall performance of the LDPC code.

[0006] In a first aspect, a method for constructing an LDPC code is provided, the method comprising:

[0007] Determine a base matrix of a QC-LDPC code, wherein the base matrix meets a required iterative decoding threshold, and the base matrix meets the iterative decoding threshold, indicating that when a signal-to-noise ratio is higher than the iterative decoding threshold, a check matrix constructed by the base matrix is ​​used to decode the LDPC code, and a bit error rate approaches 0;

[0008] A check matrix of the QC-LDPC code is constructed according to the base matrix, wherein the check matrix satisfies the following constraint: when the length of the ring where the j-th variable node in the check matrix is ​​located is not greater than 2d max In the case of, the approximate ring external information degree ACE value of the j-th variable node is at least η ACE , where 0≤j≤n-1, n is the total number of variable nodes, d max represents the maximum value of the degree of the n variable nodes, η ACE Represents the minimum value among the ACE values ​​corresponding to the n variable nodes;

[0009] Using the check matrix to construct the QC-LDPC code;

[0010] The QC-LDPC code is output.

[0011] The technical solution of the present application selects the optimal base matrix that meets the iterative decoding threshold when constructing the LDPC code, rather than the traditional method of using a simple degree sequence of variable nodes and check nodes to generate the base matrix for the construction of the LDPC code. When constructing the check matrix based on the optimal base matrix, by setting constraints on the check matrix, the constructed check matrix not only considers the impact of the ring length on the performance of the LDPC code, but also considers the impact of connectivity on the performance of the LDPC code. Compared with the traditional QC-LDPC code, it ensures that the LDPC code has good waterfall performance and reduces the error floor. In summary, the technical solution of the present application improves the overall performance of the LDPC code.

[0012] In combination with the first aspect, in some implementations of the first aspect, determining a basis matrix of a QC-LDPC code includes:

[0013] The basis matrix is ​​determined as follows:

[0014] Step 1: Initialize the degree distribution pairs of check nodes and variable nodes;

[0015] Step 2: Obtain an initial basis matrix according to the degree distribution pair;

[0016] Step 3: Using the PEXIT algorithm, determine whether the initial basis matrix meets the iterative decoding threshold;

[0017] Step 4: If the initial basis matrix meets the iterative decoding threshold, output the initial basis matrix as the basis matrix; or,

[0018] If the initial basis matrix does not meet the iterative decoding gate selection, the process returns to execute step 1.

[0019] In the process of constructing the basis matrix of QC-LDPC code, the PEXIT algorithm is used to determine whether the basis matrix constructed according to the degree distribution meets the required iterative decoding threshold. If not, the basis matrix is ​​regenerated, and the cycle is repeated until the optimal basis matrix that meets the iterative decoding threshold is constructed, and then the check matrix of QC-LDPC code is constructed based on the optimal basis matrix. Compared with the traditional method of using simple variable node and check node degree sequence pairs to generate the basis matrix for LDPC code construction, the waterfall area performance of LDPC code is improved.

[0020] In combination with the first aspect, in some implementations of the first aspect, the using the PEXIT algorithm to determine whether the initial basis matrix meets the iterative decoding threshold includes:

[0021] The initial basis matrix is ​​used as a derived group of the PEXIT algorithm, and it is determined whether the derived group meets the iterative decoding threshold.

[0022] In the process of determining the optimal basis matrix using the PEXIT algorithm, the method of first copying and then interleaving is not used. Instead, the initial basis matrix is ​​directly used as the derived group of the PEXIT algorithm to determine whether the derived group meets the iterative decoding threshold, thereby reducing the computational complexity.

[0023] In combination with the first aspect, in some implementations of the first aspect, generating a check matrix of a QC-LDPC code according to the base matrix includes:

[0024] The check matrix is ​​generated according to the following steps:

[0025] Step 5: construct an initial check matrix according to the base matrix;

[0026] Step 6: Using the ACE algorithm, determine whether the initial check matrix satisfies the constraint condition;

[0027] Step 7: If the initial check matrix meets the constraint condition, output the initial check matrix as the check matrix of the QC-LDPC code; or,

[0028] If the initial check matrix does not meet the constraint condition, return to execute step 1.

[0029] In the process of calculating the check matrix of the LDPC code, the ACE algorithm is used to ensure that the calculated check matrix meets certain constraints, so that the constructed check matrix not only takes into account the impact of the ring length on the performance of the LDPC code, but also takes into account the impact of connectivity on the performance of the LDPC code, thereby improving the connectivity of the LDPC code and reducing the error floor.

[0030] In combination with the first aspect, in some implementations of the first aspect, constructing the initial check matrix according to the base matrix includes:

[0031] According to the size (m×n) of the base matrix and the extended dimension L, the element 1 in the base matrix is ​​replaced by a cyclic shift matrix of size L×L, and the element 0 in the base matrix is ​​replaced by an all-zero matrix of size L×L to obtain the initial check matrix. The size of the initial check matrix is ​​(mL×nL), wherein m is the number of rows of the base matrix, n is the number of columns of the base matrix, and m, n and L are all positive integers.

[0032] In combination with the first aspect, in some implementations of the first aspect, the method further includes:

[0033] Determine whether the performance of the constructed QC-LDPC code meets the preset requirements, and if it does not meet the preset requirements, update the iterative decoding threshold and / or the n ACE ;

[0034] Based on the updated iterative decoding threshold and / or η ACE , construct the QC-LDPC code.

[0035] In combination with the first aspect, in certain implementations of the first aspect, the check matrix is ​​specifically the matrix A or the matrix B shown in the specification, or a matrix obtained by row interleaving the matrix A or the matrix B. In order to reduce space, they are not listed here one by one.

[0036] In a second aspect, the present application provides a method for generating a codebook of a QC-LDPC code, the method comprising:

[0037] Generate a codebook for the QC-LDPC code;

[0038] Output the codebook, wherein the codebook is such as the matrix A or the matrix B in the specification, or the codebook is such as the matrix A or the matrix B in the specification obtained by interleaving.

[0039] Similarly, in order to avoid redundancy, the details of matrix A and matrix B can be found in the specification and will not be listed here.

[0040] In a third aspect, a communication device is provided, wherein the communication device has the function of implementing the method in the first aspect or any possible implementation thereof, or the communication device has the function of implementing the method in the second aspect. The function may be implemented by hardware, or may be implemented by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0041] In a fourth aspect, the present application provides a communication device, comprising a logic circuit and a communication interface, wherein the communication interface is used to receive data and / or information to be processed, and transmit the received data and / or information to the logic circuit, and the logic circuit processes the data and / or information so that the communication device executes a method as in the first aspect or any possible implementation thereof, or, the communication device executes a method as in the second aspect.

[0042] Optionally, the above-mentioned communication interface can be replaced by an interface circuit, and the logic circuit can be replaced by a processing circuit.

[0043] Optionally, the communication device described in the fourth aspect may be a chip configured in the transmitting end, and the data and / or information to be processed may be information bits to be encoded. Specifically, the communication interface receives the information bits to be encoded and transmits them to the logic circuit; the logic circuit uses the method for constructing QC-LDPC codes in the first aspect or any possible implementation thereof to perform LDPC encoding on the information bits to generate the QC-LDPC code; and the chip outputs the QC-LDPC code through the communication interface.

[0044] Optionally, the communication interface may include an input interface and an output interface, wherein the input interface is used to receive the information bits to be encoded, and the output interface is used to output the QC-LDPC code.

[0045] Optionally, the communication device described in the fourth aspect may be a chip configured in the transmitting end, and the logic circuit of the chip is used to generate a codebook of the QC-LDPC code using the method of the second aspect; and the communication interface is used to output the codebook.

[0046] In a fifth aspect, the present application provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, wherein the at least one memory is used to store computer programs or instructions, and the at least one processor is used to call and run the computer program or instructions from the at least one memory, so that the communication device executes the method in the first aspect or any possible implementation thereof, or, the communication device executes the method in the second aspect.

[0047] Optionally, the at least one processor is integrated with the at least one memory.

[0048] Optionally, the communication device of the third aspect to the fifth aspect is specifically a coding device or an encoder, or a chip, an integrated circuit, etc. configured in the coding device or the encoder, such as a system on a chip (SOC) chip.

[0049] Exemplarily, the coding device can also be considered as a transmitting device of wireless communication. Therefore, the communication device of the third aspect to the fifth aspect above can also be a transmitting device (or a transmitting end), or a chip, integrated circuit, etc. configured in the transmitting device.

[0050] In a sixth aspect, the present application provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the method as described in the first aspect or any possible implementation thereof is executed, or the method as described in the second aspect is executed.

[0051] In a seventh aspect, the present application provides a computer program product, comprising a computer program code, which, when executed on a computer, enables the method described in the first aspect or any possible implementation thereof to be executed, or the method described in the second aspect to be executed.

[0052] In an eighth aspect, the present application provides a communication device, comprising a processor, a memory, and a transceiver. The memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory, and control the transceiver to send and receive signals, so that the communication device performs the method in the first aspect or any possible implementation thereof, or the communication device performs the method in the second aspect.

[0053] Optionally, the communication device may be a network device, such as a base station, or may be a terminal device.

[0054] In a ninth aspect, the present application provides a wireless communication system, comprising a communication device as in the eighth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is a basic flow chart of wireless communication.

[0056] Figure 2 Schematic diagram of the digital modulation process of the satellite broadcasting system.

[0057] Figure 3 is the Tanner graph representation of the check matrix H.

[0058] Figure 4 This is an example of how to construct the original model.

[0059] Figure 5 A schematic diagram of a device structure applicable to an embodiment of the present application.

[0060] Figure 6 2 is a hardware architecture diagram of a communication device applicable to an embodiment of the present application.

[0061] Figure 7 This is a flow chart of the method for constructing LDPC codes provided in this application.

[0062] Figure 8 This is an example of constructing a check matrix for a QC-LDPC code provided in this application.

[0063] Fig. 9 A schematic block diagram of a communication device 1000 provided in the present application. DETAILED DESCRIPTION

[0064] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0065] The technical solution of the present application is applicable to various wireless communication systems, including but not limited to satellite broadcasting system, code division multiple access (CDMA) system, wideband code division multiple access (WCDMA) system, general packet radio service (GPRS), long term evolution (LTE) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, universal mobile telecommunication system (UMTS), world wide interoperability for microwave access (WiMAX) communication system, the fifth generation (the 5G) communication system, the 4G LTE communication system, the 5 ... system, the 5G LTE system, the 5G LTE system, the 5G LTE system, the 5G LTE system, the 5G LTE system, the 5G LTE system, the th The three major application scenarios of 5G generation (5G) mobile communication systems, namely enhanced mobile broadband (eMBB), ultra reliable low latency communication (URLLC) and enhanced massive machine type communication (eMTC) or new communication systems that will appear in the future.

[0066] See also Figure 1 , Figure 1 This is the basic flow chart of wireless communication. Figure 1At the transmitting end, the information sent by the source is sequentially subjected to source coding, channel coding, and digital modulation, and converted into a signal suitable for transmission on the channel and sent on the channel. The receiving end receives the signal from the channel, and sequentially undergoes digital demodulation, channel decoding, and source decoding, and outputs it to the destination (i.e., the recipient of the information).

[0067] As an example, if the wireless communication system is a satellite broadcasting system, the main process of digital modulation can be as follows: Figure 2 See Figure 2 , Figure 2 Schematic diagram of the digital modulation process of the satellite broadcasting system. Exemplarily, the functions of the modules of the digital modulator of the satellite broadcasting system are as follows:

[0068] (1) Mode adaptive adjustment: mainly merging or splitting transport streams (TS), adding time information, deleting empty packets, adding cyclic redundancy checks (CRC), etc.

[0069] (2) Stream adjustment: Convert the mode adaptive adjustment output into a frame format suitable for channel coding and add a frame header;

[0070] (3) Channel coding and interleaving: For example, the new generation of satellite channel standards adopts LDPC long code + part of the broadcast channel (BCH) mode, and the interleaving mode can adopt codeword intra-row interleaving;

[0071] (4) Framing and mapping: The encoded output bit stream is mapped into a suitable constellation, such as quadrature phase shift keying (QPSK), 8phase shift keying (8PSK), 16-amplitude phase shift keying (16APSK), and 32-amplitude phase shift keying (32APSK), and the corresponding physical frame (plus the physical frame header) is formed at the same time.

[0072] (5) Shaping filter and quadrature modulation: Select an appropriate roll-off factor, for example, 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, perform shaping filter and quadrature modulation, and then output the intermediate frequency after passing through a digital to analog converter (DAC);

[0073] (6) First-stage frequency conversion to L-band output.

[0074] This application mainly involves Figure 1 or Figure 2 The process of channel coding in .

[0075] In order to facilitate understanding of the technical solution of the present application, the relevant technologies involved in the embodiments of the present application are first introduced.

[0076] Any (n, k) block code is called a linear block code if the relationship between its information element and the supervision element is linear, that is, it can be described by a linear equation. LDPC code is a linear block code. (n, k) means that the code length is n, the information bit is k, and the check bit is nk.

[0077] Linear block codes can be uniquely determined by the check matrix. The check matrix represents the correspondence between information bits and check bits. If the codeword is c = (s, p), the check matrix is ​​H, where s is the information bit and p is the check bit, then Hc T =0. In addition, the generator matrix G can be used to generate a transmission codeword sG=c from the information bit, and the relationship between them is: HG T =0.

[0078] The construction of the check matrix H of the LDPC code needs to meet the following three conditions:

[0079] (1) Each column has j 1s, j ≥ 2, and j is called the column weight;

[0080] (2) Each row has k 1s, k>j, k is called the row weight;

[0081] (3) The matrix has n columns, i.e., the code length, j, k should be much smaller than n, i.e., the matrix is ​​sparse.

[0082] In addition, in terms of construction methods, if you want to construct an (n, j, k) LDPC code, when j, k are fixed, the constructed code is called a regular LDPC code. When j, k are not fixed, the constructed code is called an irregular LDPC code. Most LDPC codes close to the Shannon limit are irregular in structure. These irregular LDPC codes have high coding complexity and are difficult to implement in hardware, which makes it difficult to meet the stringent requirements of modern communication systems on hardware costs. In order to solve this problem, various LDPC codes with specific structures, simple coding, and low hardware implementation complexity have emerged. This type of code type is collectively referred to as a structural LDPC code, among which quasi-cyclic (quasi cyslic-low density parity-check, QC-LDPC) code and paragraph LDPC code are the two most representative types of structural LDPC codes.

[0083] There are three common ways to represent LDPC codes: (1) matrix representation; (2) Tanner graph representation; and (3) degree distribution representation. For ease of understanding, the following is a simple example of using the Tanner graph to describe the parity check matrix (hereinafter referred to as the H matrix) of an LDPC code. When a (10, 5) LDPC code is represented using the matrix representation, its H matrix can be expressed as formula (1):

[0084]

[0085] The Tanner graph corresponding to the check matrix is ​​as follows Figure 3 shown.

[0086] See also Figure 3 , Figure 3 It is the Tanner graph representation of the check matrix H. It can be seen that the number of check nodes corresponds to the number of rows of the H matrix, the number of variable nodes represents the number of columns of the H matrix, and the connecting line (edge) in the middle represents the position of 1 in the H matrix.

[0087] Since the row weight and column weight of irregular LDPC codes are not constants, they cannot be expressed in the form of (n, j, k). Therefore, the degree distribution representation is usually used. This method is based on the distribution of edges associated with variable points and check points in the factor graph. The number of edges associated with the variable node is defined as the degree of the variable node, and the number of edges associated with the check node is defined as the degree of the check node. The reason why the degree distribution of edges is used instead of the degree distribution of nodes to describe LDPC codes is that in the LDPC code decoding process, information is transmitted on the edges. Using the distribution of edges to describe LDPC codes helps to analyze the actual performance of LDPC codes under a given decoding algorithm and the upper and lower bounds of the theoretical performance.

[0088] Assuming that the maximum degree of the variable node in the factor graph of the LDPC code is l, and the maximum degree of the check node is n0, the degree distribution pair of the LDPC code can be expressed as follows:

[0089]

[0090] It can be noted that the minimum degree is 2, Indicates the ratio of the number of edges associated with the variable node with degree k to the total number of edges, Indicates the ratio of the number of edges associated with the check nodes with degree t to the total number of edges.

[0091] Regular LDPC codes can be regarded as special cases of irregular LDPC codes. In this case, all variable nodes n have a constant degree l, and all check nodes m also have a constant degree n0, nl = mn0, that is, is of equal probability, It is also equally likely. Using the degree distribution method, it can be expressed as:

[0092]

[0093] For example, the degree distribution of the edges corresponding to the regular LDPC code (n, 3, 4) degenerates into the following polynomial distribution:

[0094]

[0095]

[0096] When the check matrix is ​​full rank, the relationship between the code rate R of the LDPC code and the degree distribution pair is as follows:

[0097]

[0098] When the check matrix is ​​not of full rank, the actual code rate is slightly higher than R(λ, ρ).

[0099] From the above degree distribution representation method, it can be seen that the key to constructing an LDPC code with excellent performance is to find suitable polynomials, and then the parity check matrix can be constructed based on these polynomials.

[0100] The above is all described from the perspective of the encoding end of the LDPC code. Next, the decoding of the LDPC code will be introduced.

[0101] From the characteristics of the belief propagation (BP) algorithm, we know that the stopping set is an important factor affecting the decoding success rate, and the loop and the stopping set are closely related. From the perspective of improving graph connectivity, some studies have analyzed the relationship between the short loops, stopping sets and linearly related columns of the check matrix of LDPC codes, as well as the constraints on code performance under the MP algorithm. Based on the connection characteristics of the Tanner graph of LDPC codes measured by the extrinsic message degree, a Viterbi-like algorithm was proposed to selectively remove short loops, minimize the generation of stopping sets or increase the size of stopping sets, and effectively reduce the error floor of the code.

[0102] Stopping set: If all neighbor nodes of a variable node set are connected to this set at least twice, then this variable node set is called a stopping set.

[0103] Cycle: A path from a node back to the same node without repeating edges is called a cycle.

[0104] Girth: refers to the shortest loop length on the Tanner graph. In particular, if there is no loop on the Tanner graph (the Tanner graph degenerates into a tree graph), then its girth is defined as infinite.

[0105] The MP algorithm of LDPC code is introduced below.

[0106] The MP algorithm is a decoding algorithm based on graph theory. During the operation of the algorithm, reliability information is transmitted back and forth between the variable nodes and the check nodes of the Tanner graph, so it is called a message passing algorithm. The other assumption of the algorithm is that there is no loop in the Tanner graph corresponding to the code. If there is a loop in the graph, the performance of the algorithm will be lost to a certain extent. The meaning of the MP algorithm can be understood as follows: each message represents an estimate of a specific codeword, which includes the estimate of the codeword bit and the reliability of the estimate.

[0107] The MP algorithm has a special decoding threshold phenomenon. When the signal-to-noise ratio of the channel is lower than the threshold, the bit error rate after decoding can tend to 0 arbitrarily, but when the signal-to-noise ratio is higher than the threshold, the bit error rate after decoding will not tend to 0. The size of the threshold is determined by factors such as the degree distribution pair of the code, the size of the message symbol set, and the form of the mapping function.

[0108] Since the message passing algorithm works on a simple Tanner graph model, and the messages sent during the algorithm are unrelated to the messages of the target node, its mathematical analysis is relatively simple. Under the assumption that there is no ring in the Tanner graph, the mathematical analysis of the algorithm has been fully given. However, when there is a ring in the graph, after a certain number of iterations of the algorithm, the information received by the nodes in the ring and the information output by the nodes are no longer independent of each other, forming a positive feedback, which leads to a decrease in the performance of the decoding algorithm.

[0109] The structured construction method of LDPC codes generally uses algebraic, geometric and graph theory methods. Their common feature is the use of a parity check matrix with a quasi-cyclic structure.

[0110] QC-LDPC code is an important subset of structured LDPC code. Its parity check matrix can be divided into multiple square matrices of equal size. Each square matrix is ​​a cyclic shift matrix of the unit matrix or an all-zero matrix, which is very convenient for storage and addressing, thereby greatly reducing the encoding and decoding complexity of LDPC code. Quasi-cyclic LDPC code with repeated accumulation structure can achieve fast encoding of linear complexity.

[0111] The submatrix of the QC-LDPC code check matrix has the following characteristics:

[0112] (1) Each submatrix is ​​a square matrix;

[0113] (2) Any row (column) of a circulant submatrix is ​​obtained by shifting the previous row (column) right by one position. In particular, the first row (column) of the matrix is ​​obtained by shifting the last row (column) right by one position;

[0114] (3) A circulant matrix can be completely determined by its first row or first column.

[0115] That is, the H matrix of the QC-LDPC code is composed of many circulant submatrices of the same dimension. The following matrix is ​​the circulant submatrix I1 obtained by cyclically shifting the identity matrix right by one position:

[0116]

[0117] Define the basis matrix H b , which is obtained by the above degree distribution representation and The further structure is specifically expressed as:

[0118]

[0119] Among them, a ij ∈ (0, 1), i=1,...,m; j=1,...,n.

[0120] Basis Matrix H b Each element of is expanded into a square matrix of size L×L, the 0 element is represented by a square matrix of all zeros, and the 1 element is represented by a circular shift square matrix I of the unit matrix of size L×L. The specific number of shifts is represented by the matrix P as follows:

[0121]

[0122] In particular, i，j =∞ to indicate that the corresponding cyclic shift matrix is ​​an L×L all-zero matrix, so we get the check matrix H as follows:

[0123]

[0124] Among them, any element H in H b (p ij ) represents an L×L all-zero matrix or the identity matrix cyclically shifted right by p ij The circulant matrix I(p ij ).

[0125] Therefore, if you want to construct a quasi-cyclic check matrix, first determine the dimension of the base matrix and the size of the cyclic shift submatrix according to the requirements, and then use the progressive edge growth (PEG) algorithm or other corresponding algorithms to generate the optimized base matrix according to the degree distribution, so that the base matrix has the largest possible ring length and eliminates the adverse effects of small rings. After constructing the base matrix, it is necessary to further determine the elements of the shift order matrix. Common methods include ring elimination algorithms or ring avoidance algorithms, etc., in order to ensure that there are no short rings in the expanded check matrix. Therefore, to construct the check matrix of QC-LDPC code, it is necessary to use methods to generate the base matrix and determine the shift order matrix. There are many methods, which need to be reasonably selected according to the requirements and actual conditions. The difficulty lies in how to eliminate small rings.

[0126] The original model LDPC code is introduced below.

[0127] (1) Definition of original graph LDPC code.

[0128] The original model graph LDPC code is obtained by multiple expansion and replication of the original model graph (a small factor graph containing very few variable nodes and check nodes), and then interweaving the same type of edges in all the replicated original model graphs to obtain a large derived graph, and constructing the original model graph LDPC code based on the derived graph.

[0129] Research shows that the performance of the original pattern LDPC code is completely determined by the structure of the original pattern. In addition, the unique construction method of the original pattern LDPC also determines that it has a very low encoding and decoding complexity. When implementing the original pattern LDPC code, it is only necessary to store the structure of the original pattern, and then complete the encoding of the entire code type by reusing this structure, thereby greatly saving hardware costs. In terms of performance, the original pattern LDPC code is significantly better than the traditional LDPC code.

[0130] At present, researchers have also proposed a protograph LDPC code with a quasi-cyclic structure, which further reduces the difficulty of hardware implementation. The many advantages of protograph LDPC codes in terms of structure, performance and hardware implementation have made it quickly become a new research hotspot in the field of error correction coding. Considering the comprehensive requirements of communication systems for error correction code performance and hardware cost, studying the performance of protograph LDPC codes in different transmission environments (especially non-standard transmission environments) and performing corresponding optimization designs will not only help improve the overall performance of communication systems and reduce the complexity of hardware implementation, but also further improve the theoretical system of protograph LDPC codes, which is of great significance to promoting the application of this excellent code type.

[0131] (2) Construction of the original graph LDPC code.

[0132] Similar to the definition of LDPC factor graph, the original model graph G = (V, C, E) is also composed of the variable node set V, the check node set C, and the edge set E connecting the variable nodes and the check nodes. In the original model graph, each edge e i，j ∈E connects a variable node v j ∈V and a check node c i ∈C, each edge is considered as a type of edge. Variable nodes and multiple edges with degree 1 are allowed in the original model graph. Therefore, e i，j →(v j , c i )∈V×C is not a one-to-one mapping, and the adjacency matrix corresponding to the original model graph is called the basic matrix B.

[0133] As mentioned above, the original model graph LDPC code is the LDPC code corresponding to the derived graph. The derived graph is obtained by repeating the original model graph and then interleaving the same type of edges. That is, first repeat the original model graph q times to obtain a large original model graph composed of q independent original model graphs. In the large original model graph, the interleaver distribution is used to rearrange each q edges of the same type. The new original model graph obtained after interleaving is the derived graph. The derived graph is the factor graph of the original model graph LDPC code, or in other words, the derived graph and the factor graph are equivalent. The derived group described in this article is the LDPC code corresponding to the derived graph.

[0134] Combine the following Figure 3 As a simple example, assume that the base matrix B is:

[0135]

[0136] See also Figure 4 , Figure 4 is an example of the original model construction method. Figure 4 The original model graph shown in (a) is repeated q = 2 times to obtain a large original model graph (b). Then, the edges associated with the same type of nodes in the large original model graph are permuted to obtain the derived graph (c).

[0137] The following introduces the extrinsic information transfer (EXIT) analysis of the original model LDPC code.

[0138] The EXIT algorithm of the original model LDPC code is also called the PEXIT algorithm, which can be used to analyze the threshold value γ of iterative decoding. th , the threshold reflects the performance of the original pattern LDPC code in the waterfall region. Therefore, the original pattern code type with excellent performance in the waterfall region can be designed by using the PEXIT algorithm.

[0139] In an additive white Gaussian noise (AWGN) channel, given a prototype graph with M check nodes and N variable nodes, the basic matrix is ​​B = (b i，j ), where b i，j For the element in row i and column j in B, define the following five types of mutual information:

[0140] (a)I av (i, j) represents the jth variable node v j With the i-th check node c i Each edge of the association is passed to v j The likelihood information L av (i, j) and v j The prior mutual information between

[0141] (b)I ac (i, j) represents the i-th check node c i With the jth variable node v j Each edge of the association is passed to c i The likelihood information L ac (i, j) and v j The prior mutual information between

[0142] (c)I ev (i, j) represents v j Pass to c i The likelihood information L ev (i, j) and v j External mutual information between ;

[0143] (d)I ec (i, j) means passing to v j The likelihood information L ec (i, j) and v j External mutual information between ;

[0144] (e)I app (j) represents v j The posterior likelihood information L app (j) and v j The posterior mutual information between .

[0145] Assume that the maximum number of iterations of the PEXIT algorithm is In each iteration, the following conditions are satisfied: ac (i, j) = I ev (i, j), I av (i, j) = I ec (i, j).

[0146] The specific steps of the PEXIT algorithm are as follows:

[0147] Step 1: Initialization.

[0148] Set the initial value of signal-to-noise ratio E b / N0 (in dB), the initial value of the number of iterations is t=0, v j →c i The initial value of the prior mutual information I av (i, j) = 0, calculate the variable node v j Initial likelihood information (i.e., initial channel information) of (j=1, 2, ..., N):

[0149]

[0150] Step 2:

[0151] like Then E b / N0=E b / N0+0.001dB, go to step 1;

[0152] Otherwise, for j = 1, 2, ..., N, and i = 1, 2, ..., M, calculate v j →c i External mutual information of:

[0153]

[0154] Order I ac (i, j) = I ev (i, j).

[0155] Step 3:

[0156] For j = 1, 2, ..., N, and i = 1, 2, ..., M, calculate c i →v j External mutual information of:

[0157]

[0158] Order I av (i, j) = I ec (i, j).

[0159] Step 4:

[0160] For j = 1, 2, ..., N, calculate v j The posterior mutual information of is:

[0161]

[0162] Step 5:

[0163] like All I app (j) = 1, then the iterative decoding threshold value E is output b / N0(i.e.γ th ), the algorithm ends; otherwise t=t+1, go to step 2.

[0164] When analyzing the impact of loops on iterative decoding performance, we realize that the smaller the loop length, the greater the impact on decoding performance. Sometimes, a loop with a slightly longer loop length but poor connectivity with the remaining graph has a greater impact on decoding performance than a loop with a slightly shorter loop length but good connectivity with the remaining graph. The approximate cycle extrinsic information transfer (ACE) algorithm not only considers the impact of the shortest loop length, but more importantly, it considers the impact of connectivity. Connectivity has a great impact on code performance, and improving the connectivity of the code can effectively reduce the error floor. Therefore, the essence of the ACE algorithm is to reduce the error floor by improving connectivity (the connectivity between the variable nodes in the loop and the check nodes in the remaining Tanner graph). The algorithm gives a standard for measuring the connectivity of a subset of variable nodes, the extrinsic message degree (EMD). This parameter is proposed for LDPC codes under Gaussian channels and can also be applied to other channels.

[0165] Definition of EMD: If a check node is connected to a set of variable nodes only once, then the check node is called an external node of the set of variable nodes. The number of external nodes in the set is represented by EMD.

[0166] Definition of ACE: The ACE value of a ring of length 2d is equal to Among them, d i is the value of the degree of the i-th variable node in the ring. Here, the ACE value of a variable node with degree d is considered to be equal to d-2, while the ACE value of a check node is equal to 0.

[0167] Therefore, we can see that EMD is for sets, while ACE is for rings. For a variable node in a ring, the ACE value is the upper limit of the EMD value, that is, the maximum value.

[0168] The basic idea of ​​the ACE algorithm is: when constructing LDPC codes, ensure that all rings with a length less than a certain value have a certain ACE value.

[0169] Assume that the (n, k) LDPC code satisfies the parameters (d ACE , η ACE ), then all ring lengths are no greater than 2d ACE The ACE value of the ring is at least η ACEThe constructed LDPC code is required to have information bits in the front and check bits in the back. Assume that the variable node set is {v0, v1, ..., v n-1}, the degree sequence is The set of check nodes is {c0, c1, ..., c n-k-1}, the degree sequence is Arrange the variable nodes from high to low degrees, because the decoding of nodes with high degrees converges quickly, which will give the information bits more protection.

[0170] The ACE algorithm is as follows:

[0171] Step 1: Initialization: i=n-1;

[0172] Step 2: Randomly generate column vector v according to the degree sequence i If i ≥ k, then v i If it is a check bit, go to step 3; otherwise, go to step 4.

[0173] Step 3: Use Gaussian elimination to determine v i Is it related to {v i+1 , v i+2 , ..., v n-1}Linearly independent, if linearly dependent, execute step 2; otherwise, execute step 4;

[0174] Step 4: Detect node v in the current graph i Whether the ACE value of the ring meets the constraint conditions: when the ring length l < 2d ACE , ACE value η>η ACE If not, go to step 2, otherwise go to step 5;

[0175] Step 5: i = i-1. If i ≥ 0, execute step 2; otherwise, the algorithm ends.

[0176] The technical solution of this application is introduced below.

[0177] See also Figure 5 , Figure 5 A schematic diagram of a device structure applicable to an embodiment of the present application. Figure 5 The device 200 shown in the figure may be a transmitting device in wireless communication, and has corresponding functions for executing the LDPC code method provided in the present application.

[0178] The device 200 includes: an application processor 201, a microcontroller unit (MCU) 202, a memory 203, a modem 204, a radio frequency (RF) module 205, a wireless fidelity (Wi-Fi) module 206, a Bluetooth module 207, a sensor 208, an input / output (I / O) device 209, a positioning module 210 and other components. Optionally, these components can communicate via one or more communication buses or signal lines.

[0179] Those skilled in the art will appreciate that the device 200 may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0180] Combine the following Figure 5 Each component of the device 200 is introduced in detail.

[0181] The application processor 201 is the control center of the device 200, and uses various interfaces and buses to connect various components of the device 200. In some embodiments, the processor 201 may include one or more processing units.

[0182] The memory 203 stores computer programs such as Figure 5 The operating system 211 and application 212 shown in the figure. The application processor 201 is configured to execute the computer program in the memory 203, so as to implement the functions defined by the computer program. For example, the application processor 201 executes the operating system 211, so as to implement various functions of the operating system on the device 200. The memory 203 also stores other data besides the computer program, such as data generated during the operation of the operating system 211 and the application 212. The memory 203 can be a non-volatile storage medium, generally including internal memory and external memory. The internal memory includes but is not limited to random access memory (RAM), read-only memory (ROM) or cache, etc. The external memory includes but is not limited to flash memory, hard disk, optical disk, universal serial bus (USB) disk, etc. The computer program is usually stored in the external memory, and the processor loads the program from the external memory to the internal memory before executing the computer program.

[0183] Optionally, the memory 203 may be independent and connected to the application processor 201 via a bus. Alternatively, the memory 203 and the application processor 201 may be integrated into a chip subsystem.

[0184] MCU 202 is a processor for acquiring and processing data from sensor 208. The processing capability and power consumption of MCU 202 are less than those of application processor 201, but it has the feature of "always on". It can continuously collect and process sensor data when application processor 201 is in sleep mode, and ensure the normal operation of the sensor with extremely low power consumption. In one embodiment, MCU 202 can be a smart sensor hub.

[0185] The sensor 208 may include a light sensor, a motion sensor, etc. The MCU 202 and the sensor 208 may be integrated into the same chip, or may be separate components connected via a bus.

[0186] The modem 204 and the radio frequency module 205 constitute the communication subsystem of the device 200, which is used to implement the main functions of the wireless communication standard protocol. Among them, the modem 204 is used for encoding and decoding, signal modulation and demodulation, equalization, etc. The radio frequency module 205 is used for receiving and sending wireless signals, and the radio frequency module 205 includes but is not limited to an antenna, at least one amplifier, a coupler, a duplexer, etc. The radio frequency module 205 cooperates with the modem 204 to implement the wireless communication function.

[0187] Optionally, modem 204 can be used as a separate chip, or can be combined with other chips or circuits to form a system-level chip or integrated circuit. These chips or integrated circuits can be applied to all devices that implement wireless communication functions, including: mobile phones, computers, notebooks, tablets, routers, wearable devices, cars, home appliances, etc.

[0188] The device 200 may also use a Wi-Fi module 206, a Bluetooth module 207, etc. for wireless communication. The Wi-Fi module 206 is used to provide the device 200 with network access that complies with Wi-Fi related standard protocols. The device 200 may access a Wi-Fi access point through the Wi-Fi module 206 and then access the Internet. In some other embodiments, the Wi-Fi module 206 may also serve as a Wi-Fi wireless access point to provide Wi-Fi network access for other devices.

[0189] The Bluetooth module 207 is used to implement short-range communication between the device 200 and other devices (e.g., mobile phones, smart watches, etc.). The Wi-Fi module 206 in the embodiment of the present application can be an integrated circuit or a Wi-Fi chip, etc., and the Bluetooth module 207 can be an integrated circuit or a Bluetooth chip, etc.

[0190] The positioning module 210 is used to determine the geographic location of the device 200. For example, the positioning module 210 may be a receiver of a positioning system such as a global positioning system (GPS) or a Beidou satellite navigation system or a Russian GLONASS.

[0191] The Wi-Fi module 206, the Bluetooth module 207 and the positioning module 210 can be separate chips or integrated circuits, or they can be integrated together. For example, in one embodiment, the Wi-Fi module 206, the Bluetooth module 207 and the positioning module 210 can be integrated into the same chip. In another embodiment, the Wi-Fi module 206, the Bluetooth module 207, the positioning module 210 and the MCU 202 can also be integrated into the same chip.

[0192] The input / output device 209 includes but is not limited to: a display 2091 , a touch screen 2092 , and an audio circuit 2093 and the like.

[0193] The display (also referred to as a display screen) 2091 is used to display information input by a user or information presented to a user. The display may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The touch screen 2092 may be overlaid on the display 2091. When the touch screen 2092 detects a touch event, it is transmitted to the application processor 201 to determine the type of the touch event, and then the application processor 201 may provide a corresponding visual output on the display 2091 according to the type of the touch event. Although in 5, the touch screen 2092 and the display 2091 are implemented as two independent components to implement the input and output functions of the device 200, in some embodiments, the touch screen 2092 and the display 2091 may be integrated to implement the input and output functions of the device 200. In addition, the touch screen 2092 and the display 2091 may be configured in the form of a full panel on the front of the device 200 to implement a frameless structure.

[0194] The audio circuit 2093, the speaker 2094, and the microphone 2095 can provide an audio interface between the user and the device 200. The audio circuit 2093 can transmit the electrical signal converted from the received audio data to the speaker 2094, which is converted into a sound signal for output. On the other hand, the microphone 2095 converts the collected sound signal into an electrical signal, which is received by the audio circuit 2093 and converted into audio data, and then the audio data is sent to another device through the modem 204 and the radio frequency module 205, or the audio data is output to the memory 203 for further processing.

[0195] In addition, the operating system 211 installed in the device 200 can be Or other operating systems, the embodiments of the present application do not impose any limitations on this.

[0196] Taking the device 200 equipped with the Android operating system as an example, the device 200 can be logically divided into a hardware layer, an operating system 211, and an application layer. The hardware layer includes hardware resources such as the application processor 201, MCU 202, memory 203, modem 204, Wi-Fi module 206, sensor 208, and positioning module 210 as described above. The application layer includes one or more application programs, such as application 212, which can be any type of application program such as a social application, an e-commerce application, a browser, etc. The operating system 211, as a software middleware between the hardware layer and the application layer, is a computer program that manages and controls hardware and software resources.

[0197] In one embodiment, the operating system 211 includes a kernel, a hardware abstraction layer (HAL), libraries and runtime, and a framework. The kernel is used to provide underlying system components and services, such as power management, memory management, thread management, hardware drivers, etc.; hardware drivers include Wi-Fi drivers, sensor drivers, positioning module drivers, etc. The hardware abstraction layer is an encapsulation of the kernel driver, providing an interface to the framework and shielding the implementation details of the lower layer. The hardware abstraction layer runs in user space, while the kernel driver runs in kernel space. The functions of each component of the operating system 211 described above can be implemented by the application processor 201 executing the program stored in the memory 203.

[0198] Those skilled in the art will appreciate that the device 200 may include Figure 5 Fewer or more components than shown, Figure 5 The device shown includes only the components that are more relevant to the various implementations disclosed in this application.

[0199] See also Figure 6 , Figure 6 FIG. 1 is a hardware architecture diagram of a device applicable to the technical solution of this application. Figure 6 As shown, the device 300 can be used for a transmitting device, such as a terminal device in uplink transmission, or a network device in downlink communication. Exemplarily, the device 300 can be a processor chip, and the device 300 includes: at least one CPU, a memory, an MCU, a GPU, an NPU, a memory bus, a receiving interface, and a sending interface. Figure 6 Not shown, the apparatus 300 may further include an application processor (AP), a decoder, and a dedicated video or image processor.

[0200] The above-mentioned parts of the device 300 are coupled via a connector. Exemplarily, the connector includes various interfaces, transmission lines or buses, etc. These interfaces are usually electrical communication interfaces, but may also be mechanical interfaces or other forms of interfaces, which are not limited in this embodiment.

[0201] Optionally, the CPU may be a single-CPU processor or a multi-CPU processor.

[0202] Optionally, the CPU may be a processor group consisting of multiple processors, and the multiple processors are coupled to each other through one or more buses. The receiving interface may be an interface for data input of a processor chip, and in an optional case, the receiving interface and the sending interface may be a high definition multimedia interface (HDMI), a V-By-One interface, an embedded display port (eDP), a mobile industry processor interface (MIPI), or a display port (DP), etc.

[0203] In an optional case, the above parts are integrated on the same chip.

[0204] In another optional case, the CPU, GPU, decoder, receiving interface and transmitting interface are integrated on one chip, and each part inside the chip accesses the external memory through a bus. The dedicated video / graphics processor can be integrated on the same chip as the CPU or exist as a separate processor chip.

[0205] The chip involved in the embodiments of the present application is a system manufactured on the same semiconductor substrate using an integrated circuit process, also called a semiconductor chip, which can be a collection of integrated circuits formed on a substrate (for example, a semiconductor material such as silicon) using an integrated circuit process, and its outer layer is usually encapsulated by a semiconductor packaging material. The integrated circuit may include various functional devices, each of which includes transistors such as logic gate circuits, metal-oxide-semiconductor (MOS) transistors, bipolar transistors or diodes, and may also include other components such as capacitors, resistors or inductors. Each functional device can work independently or under the action of necessary driver software, and can realize various functions such as communication, calculation, or storage.

[0206] See also Figure 7 , Figure 7A flow chart of the method for constructing LDPC codes provided in this application. Optionally, Figure 7 The method in can be used by the sender (for example, Figure 5 Device 200, or Figure 6 The method may be executed by a device 300, etc., or by a chip, an integrated circuit, etc. installed in the sending end, without limitation. The sending end is taken as an example for explanation.

[0207] 510. The transmitting end determines a base matrix of a QC-LDPC code, wherein the base matrix meets a required iterative decoding threshold.

[0208] Exemplarily, the sending end uses a message passing (MP) algorithm or other algorithms to determine the iterative decoding threshold, without limitation.

[0209] In the present application, the base matrix meets the iterative decoding threshold, which means that when the signal-to-noise ratio is higher than the iterative decoding threshold, the LDPC code is decoded using a check matrix constructed based on the base matrix, and the bit error rate approaches 0.

[0210] In other words, the decoding threshold of the LDPC code constructed based on the base matrix meets the iterative decoding threshold.

[0211] 520. The transmitter constructs a check matrix of the QC-LDPC code according to the base matrix, wherein the check matrix satisfies the following constraints:

[0212] When the length of the ring where the jth variable node in the check matrix is ​​located is not greater than 2d max In the case of, the ACE value of the j-th variable node is not less than η ACE , where 0≤j≤n-1, n is the total number of variable nodes, d max represents the maximum value of the degree of the n variable nodes, η ACE Represents the minimum value among the ACE values ​​corresponding to the n variable nodes.

[0213] 530. The transmitter uses the check matrix to construct the QC-LDPC code.

[0214] 540. The transmitter outputs the QC-LDPC code.

[0215] The technical solution of the present application selects the optimal base matrix that meets the iterative decoding threshold when constructing the LDPC code, rather than the traditional method of using a simple degree sequence of variable nodes and check nodes to generate the base matrix for the construction of the LDPC code. When constructing the check matrix based on the optimal base matrix, by setting constraints on the check matrix, the constructed check matrix not only considers the impact of the ring length on the performance of the LDPC code, but also considers the impact of connectivity on the performance of the LDPC code. Compared with the traditional QC-LDPC code, the overall waterfall performance of the LDPC code is improved, and the error floor is reduced, thereby improving the performance of the LDPC code.

[0216] Combine the following Figure 8 , Figure 8 This is an example of constructing a check matrix for a QC-LDPC code provided in this application. Figure 7 Similar to the method, Figure 8 The method in can be used by the sender (for example, Figure 5 The device 200 shown, or Figure 6 The method may be executed by the device 300 shown in the figure, or by a chip, integrated circuit, etc. installed in the sending end, without limitation.

[0217] 610. Initialize degree sequence pairs corresponding to check nodes and variable nodes. and

[0218] 620. According to the degree sequence distribution pair, obtain the basis matrix H b .

[0219] 630. Use the PEXIT algorithm to determine the basis matrix H b Whether it meets the iterative decoding threshold E b / N0 (ie, signal noise ratio (SNR) threshold), if it meets the requirements, execute step 640, otherwise go to step 610.

[0220] Regarding whether the base matrix meets the iterative decoding threshold, please refer to the description of step 510 above.

[0221] Optionally, in step 630, when the PEXIT algorithm is used to determine whether the base matrix meets the iterative decoding threshold, the base matrix can be directly used as a derived group of the PEXIT algorithm for determination without further construction in a copy-interleave manner.

[0222] Here, the export group of the PEXIT algorithm can refer to the detailed description of the PEXIT algorithm above, which will not be repeated here.

[0223] 640. According to the basis matrix H b , construct the check matrix of QC-LDPC code.

[0224] Specifically, according to the basis matrix H b The size (m, n) and the expansion dimension L are used to replace the element 1 in the base matrix with a circular shift matrix of dimension L×L. b The element 0 in is replaced by a square matrix of all zeros with dimension L×L. Thus, the final LDPC code check matrix H is obtained, with a size of mL×nL.

[0225] 650. Use the ACE algorithm to determine the node v in the check matrix H j Whether the ACE value of the ring meets the requirements of d max and η ACE Constraint condition: When the length l of the ring where the j-th variable node in the check matrix is ​​located is not greater than 2d max In the case of ACE .

[0226] Among them, 0≤j≤n-1, n is the total number of variable nodes, d max Represents the maximum value of the degree corresponding to all variable nodes, η ACE Indicates the minimum value of the ACE values ​​corresponding to all variable nodes

[0227] If yes, execute step 660 and the algorithm ends; if no, go to step 610.

[0228] 660. Output the check matrix.

[0229] Furthermore, an LDPC code is subsequently constructed according to the check matrix.

[0230] In the technical solution of the present application, the ACE algorithm is used to improve connectivity to reduce the error floor of the LDPC code, and the construction method of the QC-LDPC code is used, which is conducive to hardware implementation. In addition, since the base matrix involves very few variable nodes and check nodes, and the calculation of the mutual information of each variable node and check node is considered based on the entire Tanner graph structure, the PEXIT algorithm is used to determine the iterative decoding threshold, so that the waterfall area performance of the constructed LDPC code is good.

[0231] The following Table 1 compares the performance of LDPC codes constructed by the technical solution of the present application and other solutions.

[0232] Table 1

[0233]

[0234] In Table 1, DVB-S2 represents the second generation satellite digital video broadcasting standard (digital video broadcasting-satellite 2), ABS-S represents the advanced broadcasting system-satellite (ABS-S), and MODCOD represents the coding modulation mode.

[0235] It can be seen from Table 1 that, compared with the standards of some existing satellite broadcasting systems, the performance of the QC-LDPC code constructed using the solution of the present application is better.

[0236] In the process of constructing QC-LDPC codes using the scheme of the present application, more codebooks can be obtained. By setting the desired performance requirements, for example, the SNR value of the packet error ratio (PER) = 1e-7 performance corresponding to each code rate in DVB_S2, the obtained codebooks can be screened and a codebook that better meets the ideal performance requirements can be selected.

[0237] If the codebooks for different code rates obtained by the solution provided by the present application still fail to meet the expected performance requirements, the set iterative decoding threshold (such as Figure 7 Step 510, Figure 8 Step 630) and / or the set ACE value (specifically, the minimum value among the ACE values ​​corresponding to all variable nodes, i.e., n ACE ,like Figure 7 Then, based on the new iterative decoding threshold and / or the newly set ACE value, the codebook of the QC-LDPC code is reconstructed to obtain a codebook with good performance.

[0238] Here are some examples of some good-performance check matrices H (i.e., codebooks) obtained according to the technical solution of the present application, involving code rates of 5 / 6 and 3 / 4. Among them, the element -1 in the check matrix H represents an all-zero matrix; 0 represents a unit cyclic matrix, i.e., no shift operation is performed; other non-zero elements x represent rightward shifts x.

[0239] The size of the base matrix is ​​expressed as m×n below, that is, m rows and n columns, and the expanded dimension is denoted by L.

[0240] (1) Matrix A

[0241] The code rate is 5 / 6, the extended dimension L is 559, and the size is 110 columns and 20 rows (ie, n=110, m=20).

[0242] Row 1

[0243]

[0244] Row 2

[0245]

[0246] Row 3

[0247]

[0248] Row 4

[0249]

[0250] Row 5

[0251]

[0252] Row 6

[0253]

[0254] Row 7

[0255]

[0256] Row 8

[0257]

[0258] Line 9

[0259]

[0260] Line 10

[0261]

[0262] Row 11

[0263]

[0264] Line 12

[0265]

[0266] Line 13

[0267]

[0268] Line 14

[0269]

[0270] Line 15

[0271]

[0272] Line 16

[0273]

[0274] Line 17

[0275]

[0276] Line 18

[0277]

[0278]

[0279] Line 19

[0280]

[0281] Line 20

[0282]

[0283] (2) Matrix B

[0284] The code rate is 3 / 4, the extended dimension L is 539, and the size is 114 columns and 30 rows (ie, n=114, m=30).

[0285] Row 1

[0286]

[0287] Row 2

[0288]

[0289] Row 3

[0290]

[0291] Row 4

[0292]

[0293] Row 5

[0294]

[0295] Row 6

[0296]

[0297] Row 7

[0298]

[0299] Row 8

[0300]

[0301] Line 9

[0302]

[0303] Line 10

[0304]

[0305] Row 11

[0306]

[0307]

[0308] Line 12

[0309]

[0310] Line 13

[0311]

[0312] Line 14

[0313]

[0314] Line 15

[0315]

[0316] Line 16

[0317]

[0318] Line 17

[0319]

[0320] Line 18

[0321]

[0322]

[0323] Line 19

[0324]

[0325] Line 20

[0326]

[0327] Line 21

[0328]

[0329] Line 22

[0330]

[0331] Line 23

[0332]

[0333] Line 24

[0334]

[0335] Line 25

[0336]

[0337]

[0338] Line 26

[0339]

[0340] Line 27

[0341]

[0342] Line 28

[0343]

[0344] Line 29

[0345]

[0346] Line 30

[0347]

[0348] It should be noted that the check matrix of each code rate actually used can be the above-mentioned matrix A or matrix B, or it can also be a matrix obtained by row interleaving of matrix A or matrix B, without limitation. It can be understood that matrix A or matrix B is only an example of a check matrix of an LDPC code obtained according to the method provided in this application, and more check matrices with ideal performance can be obtained according to the method provided in this application.

[0349] The above is a detailed description of the method for constructing LDPC codes provided by the present application. The following is an introduction to the communication device provided by the present application.

[0350] See also Figure 7 , Figure 7 1 is a schematic block diagram of a communication device 1000 provided in this application. Figure 7 The communication device 1000 includes a processing unit 1100 and a transceiver unit 1200 .

[0351] Optionally, the transceiver unit 1200 may also be replaced by a sending unit or a receiving unit. For example, when the transceiver unit 1200 performs the sending step, it may be replaced by a sending unit. When the transceiver unit 1200 performs the receiving step, it may be replaced by a receiving unit.

[0352] The processing unit 1100 is configured to determine a base matrix of a quasi-cyclic QC-LDPC code, wherein the base matrix meets an iterative decoding threshold required by a decoding algorithm, wherein the base matrix meets the iterative decoding threshold, indicating that when a signal-to-noise ratio is higher than the iterative decoding threshold, a check matrix constructed by the base matrix is ​​used to decode the LDPC code, and a bit error rate approaches 0;

[0353] The processing unit 1100 is further configured to construct a check matrix of the QC-LDPC code according to the base matrix, wherein the check matrix satisfies the following constraint: when the length of the ring where the j-th variable node in the check matrix is ​​located is not greater than 2d max In the case of ACE , where 0≤j≤n-1, n is the total number of variable nodes, d max represents the maximum value of the degree of the n variable nodes, η ACE Represents the minimum value among the ACE values ​​corresponding to the n variable nodes;

[0354] The processing unit 1100 is further configured to construct the QC-LDPC code using the check matrix;

[0355] The transceiver unit 1200 is used to output the QC-LDPC code.

[0356] Optionally, in one embodiment, the processing unit 1100 is specifically configured to determine the basis matrix according to the following steps:

[0357] Step 1: Initialize the degree distribution pairs of check nodes and variable nodes;

[0358] Step 2: Obtain an initial basis matrix according to the degree distribution pair;

[0359] Step 3: Using the PEXIT algorithm, determine whether the initial basis matrix meets the iterative decoding threshold;

[0360] Step 4: If the initial basis matrix meets the iterative decoding threshold, output the initial basis matrix as the basis matrix; or,

[0361] If the initial basis matrix does not meet the iterative decoding gate selection, the process returns to execute step 1.

[0362] Optionally, in one embodiment, the processing unit 1100 is specifically configured to:

[0363] The initial basis matrix is ​​used as a derived group of the PEXIT algorithm, and it is determined whether the derived group meets the iterative decoding threshold.

[0364] Optionally, in one embodiment, the processing unit 1100 is specifically configured to generate the check matrix according to the following steps:

[0365] Step 5: construct an initial check matrix according to the base matrix;

[0366] Step 6: Using the ACE algorithm, determine whether the initial check matrix satisfies the constraint condition;

[0367] Step 7: If the initial check matrix meets the constraint condition, output the initial check matrix as the check matrix of the QC-LDPC code; or,

[0368] If the initial check matrix does not meet the constraint condition, return to execute step 1.

[0369] Optionally, in one embodiment, the processing unit 1100 is specifically configured to:

[0370] According to the size (m×n) of the base matrix and the extended dimension L, the element 1 in the base matrix is ​​replaced by a cyclic shift matrix of size L×L, and the element 0 in the base matrix is ​​replaced by an all-zero square matrix of size L×L to obtain the initial check matrix. The size of the initial check matrix is ​​(mL×nL), m is the number of rows of the base matrix, n is the number of columns of the base matrix, and m, n and L are all positive integers.

[0371] Optionally, in one embodiment, the processing unit 1100 is further configured to:

[0372] Determining whether the performance of the constructed QC-LDPC code meets the preset requirements, and updating the iterative decoding threshold if it does not meet the preset requirements;

[0373] The QC-LDPC code is constructed based on the updated iterative decoding threshold.

[0374] Optionally, in some embodiments, the LDPC code is the matrix A or the matrix B shown in the above embodiments, or is a matrix obtained by row interleaving the matrix A or the matrix B.

[0375] Optionally, the communication device 1000 may be a transmitting end, or the communication device 1000 may be a device, a module, etc. inside the transmitting end that has the function of implementing each method embodiment.

[0376] In one implementation, the communication device 1000 is a transmitting end in each of the above method embodiments, and the communication device 1000 may have any function of the transmitting end in each of the method embodiments. In this case, the processing unit 1100 may be a processor. The transceiver unit 1200 may be a transceiver. The transceiver may specifically include a receiver and a transmitter. Among them, the receiver has a receiving action, and the transmitter has a transmitting function.

[0377] Optionally, in another implementation, the communication device 1000 may be a circuit system in a transmitting end. In this case, the processing unit 1100 may be a chip, a logic circuit, an integrated circuit, a processing circuit, or a system on chip (SoC) chip, etc., and the transceiver unit 1200 may be a communication interface, which may be an interface circuit, an input / output interface, a pin on a chip for transmitting signals and / or data, etc.

[0378] In one embodiment, the communication device 1000 may be an encoder in a transmitting end.

[0379] In the above embodiments, the functions of the processing unit 1100 may be implemented by hardware, or by hardware executing corresponding software.

[0380] For example, the processing unit 1100 may include one or more processors, and the one or more processors are used to read and execute computer programs or instructions stored in the memory, so that the operations and / or processing performed by the sending end in each method embodiment are executed. The memory is located outside the one or more processors.

[0381] Alternatively, as an implementation method, the processing unit 1100 may also include one or more memories, and the one or more processors and the one or more memories are connected via circuits / wires, and the one or more processors can read computer programs or instructions stored in the one or more memories, so that the operations and / or processing performed by the sending end in the various method embodiments of the present application are executed.

[0382] For another example, the processing unit 1100 is a processor, and the transceiver unit 1200 may be an interface circuit. The interface circuit is used to receive computer codes or instructions and transmit them to the processor, and the processor executes the computer codes or instructions, so that the operations and / or processing performed by the sending end in each method embodiment of the present application are executed.

[0383] Optionally, the processing unit 1100 may also be a processing circuit or a logic circuit.

[0384] In one implementation, the communication device 10 may be a transmitting end in the method embodiment. In this implementation, the communication interface 13 may be a transceiver. The transceiver may include a receiver and a transmitter. Optionally, the processor 11 may be a baseband device, and the communication interface 13 may be a radio frequency device.

[0385] In this implementation, for example, the communication device 1000 can Figure 5 The device 200 shown is implemented, or by Figure 6 The device 300 shown is implemented.

[0386] Specifically, the processing unit 1100 may correspond to Figure 5 The modem 204 shown in FIG. 1 has corresponding functions of the modem 204, such as encoding and decoding, modulation and demodulation, etc. The transceiver unit 1200 may correspond to Figure 5 The RF module 205 shown in FIG. 2 has corresponding functions of the RF module 205 , such as receiving and sending wireless signals.

[0387] For example, the processing unit 1100 may be used to execute Figure 7 The processing or operation performed internally by the sender in Figure 7 In step 510, step 520 and step 530, the transceiver unit 1200 is used to perform Figure 7 The sending and / or receiving (i.e., input or output) actions performed by the sender in Figure 7 Step 540 in .

[0388] For another example, the processing unit 1100 is used to execute Figure 8 In steps 610-660, the transceiver unit 1200 is used to perform Figure 8 Step 660 in .

[0389] In another implementation, the communication device 1000 may be a chip or an integrated circuit installed in the transmitting end. In this implementation, the communication interface 13 may be an interface circuit or an input / output interface.

[0390] Optionally, the memory and processor in the above-mentioned device embodiments may be physically independent units, or the memory may be integrated with the processor, which is not limited in this document.

[0391] In addition, the present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the computer executes the method for constructing an LDPC code as in each embodiment of the present application.

[0392] The present application also provides a computer program product, which includes computer codes or instructions. When the computer codes or instructions are executed on a computer, the computer executes the method for constructing an LDPC code as described in the various method embodiments of the present application.

[0393] The present application also provides a communication device (for example, a chip), including a processor and an interface circuit, wherein the interface circuit is used to receive signals and / or data to be processed and transmit the signals and / or data to be processed to the processor, and the processor is used to process the signals and / or data to execute the method for constructing LDPC codes provided in each embodiment of the present application.

[0394] The present application also provides a chip, the chip comprising one or more processors. The one or more processors are used to execute a computer program stored in a memory to perform the operation and / or processing performed by the transmitting end in any one of the method embodiments. The memory is set independently of the chip.

[0395] Furthermore, the chip may further include one or more communication interfaces. The one or more communication interfaces may be input / output interfaces, interface circuits, etc. Furthermore, the chip may further include one or more memories.

[0396] In addition, the present application also provides a communication device (e.g., a chip), comprising a logic circuit and a communication interface, wherein the communication interface is used to receive data and / or information to be processed, and transmit the received data and / or information to the logic circuit, and the logic circuit processes the data and / or information so that the communication device implements the method for constructing QC-LDPC codes provided in an embodiment of the present application.

[0397] Specifically, the data and / or information to be processed may be information bits to be encoded. Specifically, the communication interface receives the information bits to be encoded and transmits them to the logic circuit; the logic circuit uses the method for constructing QC-LDPC codes provided in an embodiment of the present application to perform LDPC encoding on the information bits to generate the QC-LDPC codes; and the chip outputs the QC-LDPC codes through the communication interface.

[0398] The present application also provides a wireless communication system, including the transmitting end in the embodiment of the present application.

[0399] Optionally, the sending end may be a network device (eg, a base station) or a terminal device, without limitation.

[0400] The processor in the embodiment of the present application can be an integrated circuit chip with the ability to process signals. In the implementation process, each step of the above method embodiment can be completed by the hardware integrated logic circuit or software instructions in the processor. The processor can be a general processor, a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware coding processor to perform, or the hardware and software modules in the coding processor are combined to perform. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, and other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0401] The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DRRAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0402] The terms "unit", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread. A component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, for example, the Internet interacting with other systems through signals).

[0403] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0404] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0405] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0406] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for constructing a low-density parity check LDPC code, characterized in that: include: Determine a base matrix of a quasi-cyclic QC-LDPC code, wherein the base matrix meets a required iterative decoding threshold, wherein the base matrix meets the iterative decoding threshold, indicating that when a signal-to-noise ratio is higher than the iterative decoding threshold, a check matrix constructed by the base matrix is ​​used to decode the LDPC code, and a bit error rate approaches 0; A check matrix of the QC-LDPC code is constructed according to the base matrix, wherein the check matrix satisfies the following constraint: when the length of the ring where the j-th variable node in the check matrix is ​​located is not greater than 2d max In the case of, the approximate ring external information degree ACE value of the j-th variable node is at least η ACE , where 0≤j≤n-1, n is the total number of variable nodes, d max represents the maximum value of the degree of the n variable nodes, η ACE Represents the minimum value among the ACE values ​​corresponding to the n variable nodes; Using the check matrix to construct the QC-LDPC code; Outputting the QC-LDPC code; The code rate of the QC-LDPC code is 5 / 6, the extended dimension of the check matrix is ​​559, and the size is 20 rows and 110 columns, such as the following matrix A or a matrix obtained by row interleaving of the matrix A; Alternatively, the code rate of the QC-LDPC code is 3 / 4, the extended dimension of the check matrix is ​​539, and the size is 30 rows and 114 columns, such as the following matrix B or a matrix obtained by row interleaving of the matrix B; Matrix A: Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Line 9 Line 10 Row 11 Line 12 Line 13 Line 14 Line 15 Line 16 Line 17 Line 18 Line 19 Line 20 Matrix B: Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Line 9 Line 10 Row 11 Line 12 Line 13 Line 14 Line 15 Line 16 Line 17 Line 18 Line 19 Line 20 Line 21 Line 22 Line 23 Line 24 Line 25 Line 26 Line 27 Line 28 Line 29 Line 30 2. The method according to claim 1, characterized in that: The determining of the basis matrix of the QC-LDPC code comprises: The basis matrix is ​​determined as follows: Step 1: Initialize the degree distribution pairs of check nodes and variable nodes; Step 2: Obtain an initial basis matrix according to the degree distribution pair; Step 3: Using the original model external information transfer PEXIT algorithm to determine whether the initial basis matrix meets the iterative decoding threshold; Step 4: If the initial basis matrix meets the iterative decoding threshold, output the initial basis matrix as the basis matrix; or, If the initial basis matrix does not meet the iterative decoding gate selection, the process returns to execute step 1.

3. The method according to claim 2, characterized in that The using the PEXIT algorithm to determine whether the initial basis matrix meets the iterative decoding threshold includes: The initial basis matrix is ​​used as a derived group of the PEXIT algorithm, and it is determined whether the derived group meets the iterative decoding threshold.

4. The method according to claim 2, characterized in that: The step of generating a check matrix of a QC-LDPC code according to the base matrix comprises: The check matrix is ​​generated according to the following steps: Step 5: construct an initial check matrix according to the base matrix; Step 6: Using the ACE algorithm, determine whether the initial check matrix satisfies the constraint condition; Step 7: If the initial check matrix meets the constraint condition, output the initial check matrix as the check matrix of the QC-LDPC code; or, If the initial check matrix does not meet the constraint condition, return to execute step 1.

5. The method according to claim 4, characterized in that The step of constructing the initial check matrix according to the base matrix comprises: According to the size (m×n) of the base matrix and the extended dimension L, the element 1 in the base matrix is ​​replaced by a cyclic shift matrix of size L×L, and the element 0 in the base matrix is ​​replaced by an all-zero square matrix of size L×L to obtain the initial check matrix. The size of the initial check matrix is ​​(mL×nL), wherein m is the number of rows of the base matrix, n is the number of columns of the base matrix, and m, n and L are all positive integers.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Determine whether the performance of the constructed QC-LDPC code meets the preset requirements, and if it does not meet the preset requirements, update the iterative decoding threshold and / or the n ACE ; Based on the updated iterative decoding threshold and / or η ACE The QC-LDPC code is constructed.

7. A communication device, characterized in that: include: A processing unit, configured to determine a base matrix of a QC-LDPC code, wherein the base matrix meets a required iterative decoding threshold, and the base matrix meets the iterative decoding threshold, indicating that when a signal-to-noise ratio is higher than the iterative decoding threshold, a check matrix constructed by the base matrix is ​​used to decode the LDPC code, and a bit error rate approaches 0; A check matrix of the QC-LDPC code is constructed according to the base matrix, wherein the check matrix satisfies the following constraint: when the length of the ring where the j-th variable node in the check matrix is ​​located is not greater than 2d max In the case of, the approximate ring external information degree ACE value of the j-th variable node is at least η ACE , where 0≤j≤n-1, n is the total number of variable nodes, d max represents the maximum value of the degree of the n variable nodes, η ACE Represents the minimum value among the ACE values ​​corresponding to the n variable nodes; And, constructing the QC-LDPC code using the check matrix; A communication interface, used for outputting the QC-LDPC code; The check matrix is ​​such as the matrix A in method claim 1 or a matrix obtained by row interleaving the matrix A; or, the check matrix is ​​such as the matrix B in method claim 1 or a matrix obtained by row interleaving the matrix B.

8. The communication device according to claim 7, characterized in that: The processing unit is specifically used for: The basis matrix is ​​determined as follows: Step 1: Initialize the degree distribution pairs of check nodes and variable nodes; Step 2: Obtain an initial basis matrix according to the degree distribution pair; Step 3: Using the original model external information transfer PEXIT algorithm to determine whether the initial basis matrix meets the iterative decoding threshold; Step 4: If the initial basis matrix meets the iterative decoding threshold, output the initial basis matrix as the basis matrix; or, If the initial basis matrix does not meet the iterative decoding gate selection, the process returns to execute step 1.

9. The communication device according to claim 8, characterized in that: The processing unit is specifically used for: The initial basis matrix is ​​used as a derived group of the PEXIT algorithm, and it is determined whether the derived group meets the iterative decoding threshold.

10. The communication device according to claim 8, characterized in that: The processing unit is specifically used for: The check matrix is ​​generated according to the following steps: Step 5: construct an initial check matrix according to the base matrix; Step 6: Using the ACE algorithm, determine whether the initial check matrix satisfies the constraint condition; Step 7: If the initial check matrix meets the constraint condition, output the initial check matrix as the check matrix of the QC-LDPC code; or, If the initial check matrix does not meet the constraint condition, return to execute step 1.

11. The communication device according to claim 10, characterized in that: The processing unit is specifically used for: According to the size (m×n) of the base matrix and the extended dimension L, the element 1 in the base matrix is ​​replaced by a cyclic shift matrix of size L×L, and the element 0 in the base matrix is ​​replaced by an all-zero square matrix of size L×L to obtain the initial check matrix. The size of the initial check matrix is ​​(mL×nL), m is the number of rows of the base matrix, n is the number of columns of the base matrix, and m, n and L are all positive integers.

12. The communication device according to any one of claims 7 to 11, characterized in that: The processing unit is further used for: Determine whether the performance of the constructed QC-LDPC code meets the preset requirements, and if it does not meet the preset requirements, update the iterative decoding threshold and / or the n ACE ; Based on the updated iterative decoding threshold and / or η ACE , construct the QC-LDPC code.

13. A communication device, characterized in that: The device comprises a processor configured to call software instructions stored in a memory so as to enable the communication device to perform the method according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions. When the computer instructions are executed on a computer or a processor, the method according to any one of claims 1 to 6 is implemented.

Images