Solid-state image pickup device

Abstract

A solid-state imaging device including an AD converter having a wide dynamic range is provided. The solid-state imaging device according to the present application includes: a pixel section including a plurality of pixels; a pixel signal line transmitting a pixel signal of the pixel; a reference signal line transmitting a reference signal to be compared with the pixel signal; a first comparator outputting a first output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a second comparator outputting a second output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a first capacitor section provided between the pixel signal line or the reference signal line and the first comparator and set to a first gain; and a second capacitor section provided between the pixel signal line or the reference signal line and the second comparator and set to a second gain.

Description

TECHNICAL FIELD

[0001] The present application relates to a solid-state image pickup element. BACKGROUND

[0002] There is a complementary metal oxide semiconductor (CMOS: complementary metal oxide semiconductor) image sensor that performs analog-to-digital (AD) conversion of a pixel signal by comparing an analog pixel signal with a linearly changing reference signal using a comparator and calculating a time until the reference signal crosses the pixel signal.

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 2018-148541

[0006] Patent Literature 2: Japanese Patent Application Laid-Open No. 2019-165313 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] However, in the AD converter of the conventional image sensor, the dynamic range of the comparator is relatively narrow, and it is difficult to perform AD conversion of a wide luminance of irradiation light.

[0009] Therefore, an object of the present application is to provide a solid-state image pickup element including an AD converter having a wide dynamic range.

[0010] TECHNICAL SOLUTION TO THE PROBLEM

[0011] The solid-state image pickup element according to one aspect of the present application includes: a pixel section including a plurality of pixels; a pixel signal line that transmits a pixel signal of the pixel; a reference signal line that transmits a reference signal to be compared with the pixel signal; a first comparator that outputs a first output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a second comparator that outputs a second output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a first capacitor section that is provided between the pixel signal line or the reference signal line and the first comparator and is set to a first gain; and a second capacitor section that is provided between the pixel signal line or the reference signal line and the second comparator and is set to a second gain.

[0012] The first capacitor portion can include a first input capacitance element disposed between the reference signal line and the first comparator, and a second input capacitance element disposed between the pixel signal line and the first comparator. Also, the second capacitor portion can include a third input capacitance element disposed between the reference signal line and the second comparator, and a fourth input capacitance element disposed between the pixel signal line and the second comparator.

[0013] A capacitance ratio between the first input capacitance element and the second input capacitance element can be different from a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

[0014] Capacitances of the first input capacitance element and the third input capacitance element can be substantially equal, and capacitances of the second input capacitance element and the fourth input capacitance element can be different from each other.

[0015] A gain of the first capacitor portion can be determined by a capacitance ratio between the first input capacitance element and the second input capacitance element, and a gain of the second capacitor portion can be determined by a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

[0016] One end of each of the first input capacitance element and the third input capacitance element can be commonly connected to the reference signal line, and one end of each of the second input capacitance element and the fourth input capacitance element can be commonly connected to the pixel signal line. The first comparator can include a first transistor, a gate of the first transistor being commonly connected to the other end of the first input capacitance element and the other end of the second input capacitance element. Also, the second comparator can include a second transistor, a gate of the second transistor being commonly connected to the other end of the third input capacitance element and the other end of the fourth input capacitance element.

[0017] The first comparator can further include a first constant current source connected to one end of the first transistor, and can output the first output signal from between the first transistor and the first constant current source. Also, the second comparator can further include a second constant current source connected to one end of the second transistor, and can output the second output signal from between the second transistor and the second constant current source.

[0018] The first comparator can further include a first constant current source connected to one end of the first transistor, a third transistor connected to the first constant current source, and a first mirror circuit connected to the other end of the first transistor and the other end of the third transistor, and the first comparator can output the first output signal from between the third transistor and the first mirror circuit. Also, the second comparator can further include a second constant current source connected to one end of the second transistor, a fourth transistor connected to the second constant current source, and a second mirror circuit connected to the other end of the second transistor and the other end of the fourth transistor, and the second comparator can output the second output signal from between the fourth transistor and the second mirror circuit.

[0019] The first comparator can include the first transistor having a gate connected to the first input capacitive element and one end connected to the second input capacitive element, and the second comparator can include the second transistor having a gate connected to the third input capacitive element and one end connected to the fourth input capacitive element.

[0020] The first input capacitive element and the third input capacitive element are commonly connected to the reference signal line, and one end of the first transistor and one end of the second transistor can receive the pixel signal via the second input capacitive element and the fourth input capacitive element, respectively.

[0021] The solid-state imaging device of the present application can further include a reference signal generator that supplies the same reference signal to the first input capacitive element and the third input capacitive element.

[0022] The solid-state imaging device of the present application can further include a signal processing circuit that selects the first output signal or the second output signal according to the illumination of the irradiation light toward the pixel portion, and outputs the selected signal as image data.

[0023] The solid-state imaging device of the present application can further include a controller that changes the exposure time of the pixel portion according to the illumination of the irradiation light toward the pixel portion.

[0024] The solid-state imaging device of the present application can further include a controller that controls the slope of the reference signal according to the illumination of the irradiation light toward the pixel portion.

[0025] The solid-state imaging device of the present application can further include a controller that controls the first gain or the second gain according to the illumination of the irradiation light toward the pixel portion.

[0026] The solid-state imaging device of the present application can further include a signal processing circuit that acquires an illumination of the irradiated light toward the pixel section, and a controller that sets the first gain or the second gain in accordance with the illumination. Here, the pixel section can perform imaging with the set first gain or second gain, thereby generating the pixel signal, and the signal processing circuit can convert the pixel signal to generate image data.

[0027] One end of each of the first input capacitor element and the third input capacitor element can be commonly connected to the reference signal line. One end of each of the second input capacitor element and the fourth input capacitor element can be commonly connected to the pixel signal line. The first comparator can include a first transistor and a third transistor, a gate of the first transistor being connected to the other end of the first input capacitor element, and a gate of the third transistor being connected to the other end of the second input capacitor element. Further, the second comparator can include a second transistor and a fourth transistor, a gate of the second transistor being connected to the other end of the third input capacitor element, and a gate of the fourth transistor being connected to the other end of the fourth input capacitor element. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment.

[0029] Figure 2 is a conceptual view showing an example of a solid-state imaging device in which a semiconductor chip of a pixel section and a semiconductor chip of a processing circuit are stacked.

[0030] Figure 3 is a circuit diagram showing a configuration example of a pixel provided in a pixel section.

[0031] Figure 4 is a block diagram showing a configuration example of a pixel section and an ADC group.

[0032] Figure 5 is a diagram showing an example of an internal configuration of a capacitor section and a comparator.

[0033] Figure 6 is a timing chart showing an operation example of a solid-state imaging device according to the first embodiment.

[0034] Figure 7 is a block diagram showing a configuration example of a pixel section and an ADC group.

[0035] Figure 8A is a diagram showing a configuration example of a solid-state imaging device according to a second embodiment.

[0036] Figure 8Bis a diagram showing a configuration example of a solid-state imaging device according to a modification of the second embodiment.

[0037] Figure 8C is a diagram showing a configuration example of a solid-state imaging device according to another modification of the second embodiment.

[0038] Figure 9 is a diagram showing a configuration example of a solid-state imaging device according to the third embodiment.

[0039] Figure 10 is a timing chart showing an operation example of the solid-state imaging device according to the third embodiment.

[0040] Figure 11 is a diagram showing a configuration example of a solid-state imaging device according to the fourth embodiment.

[0041] Figure 12 is a diagram showing a configuration example of a solid-state imaging device according to Modification 1 of the first embodiment.

[0042] Figure 13 is a table showing a relationship between an exposure time and an input capacitance gain of the solid-state imaging device according to Modification 2.

[0043] Figure 14 is a timing chart showing an operation example of the solid-state imaging device according to Modification 3.

[0044] Figure 15 is a table showing a combination of a reference signal and an input capacitance gain according to Modification 3.

[0045] Figure 16 is a block diagram showing a configuration example of a solid-state imaging device according to the fifth embodiment.

[0046] Figure 17 is a block diagram showing a configuration example of an ADC group according to the fifth embodiment.

[0047] Figure 18 is a diagram showing a configuration example of an input capacitance element.

[0048] Figure 19 is a flowchart showing an operation of the solid-state imaging device according to the fifth embodiment.

[0049] Figure 20 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology of the present application can be applied.

[0050] Figure 21 is a diagram showing an example of a setting position of an imaging section. DETAILED DESCRIPTION

[0051] Hereinafter, specific embodiments to which the present technology is applied will be explained in detail with reference to the drawings. The drawings are schematic or conceptual, and, for example, the proportions of the parts are not necessarily the same as those in reality. In the description and drawings, elements similar to those explained previously with reference to the drawings already discussed previously are given the same reference numerals, and detailed explanation thereof is omitted as appropriate.

[0052] (First Embodiment)

[0053] Figure 1 is a block diagram showing a configuration example of a solid-state imaging element 100 according to the first embodiment. The solid-state imaging element 100 includes a pixel section 101, a timing control circuit 102, a vertical scanning circuit 103, a digital-analog conversion device (DAC) 104, an analog-digital conversion device (ADC) group 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0054] In the pixel section 101, unit pixels (hereinafter, also simply referred to as pixels) each including a photoelectric conversion element that photoelectrically converts incident light into an amount of electric charge corresponding to a light quantity thereof are arranged in a matrix form. The specific circuit configuration of the unit pixel will be described later with reference to Figure 2 The specific circuit configuration of the unit pixel will be described later with reference to Figure 1 In the pixel section 101, a pixel drive line 109 is wired for each row in the left-right direction (pixel arrangement direction in the pixel row / horizontal direction) in the drawing with respect to the pixel array in the matrix form, and a vertical signal line 110 is wired for each column in the up-down direction (pixel arrangement direction in the pixel column / vertical direction) in the drawing. One end of the pixel drive line 109 is connected to an output terminal of the vertical scanning circuit 103 corresponding to each row. Note that, in the present embodiment, although one pixel drive line 109 is provided for each pixel row, two or more pixel drive lines 109 can be provided in each pixel row.

[0055] The timing control circuit 102 includes a timing generator (not shown) that generates various timing signals. Based on a control signal or the like supplied from the outside, the timing control circuit 102 performs drive control of the vertical scanning circuit 103, the DAC 104, the ADC group 105, the horizontal transfer scanning circuit 106, and the like in accordance with the various timing signals generated by the timing generator.

[0056] The vertical scanning circuit 103 includes a shift register and an address decoder, or the like. In the present embodiment, although the specific configuration is not shown, the vertical scanning circuit 103 includes a readout scanning system and a sweep scanning system.

[0057] The readout scanning system sequentially performs the selective scanning with respect to unit pixels from which a signal is to be read out in units of lines. On the other hand, with respect to a readout line which is to be subjected to readout scanning by the readout scanning system, the sweep scanning system performs sweep scanning which precedes the readout scanning by an amount of time corresponding to a shutter speed, and with this sweep scanning, useless charges are swept out from the photoelectric conversion elements of the unit pixels of the readout line (reset). The so-called electronic shutter operation is performed by the sweep (reset) of the useless charges performed by the sweep scanning system. The so-called electronic shutter operation herein refers to an operation of discarding the photocharges of the photoelectric conversion elements and starting exposure again (i.e., starting accumulation of the photocharges again). The signal read out by the readout operation performed by the readout scanning system corresponds to the amount of light incident after the previous readout operation or the electronic shutter operation. Also, the time period between the readout timing of the previous readout operation or the sweep timing of the electronic shutter operation and the readout timing of the present readout operation is the accumulation time (exposure time) of the photocharges in the unit pixels.

[0058] The pixel signal VSL output from each unit pixel in the pixel row selectively scanned by the vertical scanning circuit 103 is supplied to the ADC group 105 via a plurality of vertical signal lines 110 corresponding to the respective columns.

[0059] The DAC 104 as the reference signal generator generates a signal of a linearly varying ramp waveform, i.e., a reference signal RAMP, and supplies the reference signal RAMP to the ADC group 105. The DAC 104 is commonly connected to the plurality of comparators 121 via a reference signal line 114, and supplies the same reference signal RAMP to the plurality of comparators 121. The reference signal line 114 transmits the reference signal RAMP to the plurality of comparators 121.

[0060] The ADC group 105 includes a plurality of comparators 121, a plurality of counters 122, and a plurality of latch circuits 123. Note that although only one ADC group 105 is shown in Figure 1 , the ADC group 105 can be divided into a plurality of ADC groups 105a and 105b as shown in Figure 2 or Figure 3 The configuration of the ADC groups 105a and 105b will be described later.

[0061] The comparators 121, the counters 122, and the latch circuits 123 are provided corresponding to the pixel columns of the pixel section 101, respectively, thereby constituting an ADC.

[0062] The comparator 121 compares the voltage of a signal obtained by adding the pixel signal VSL output from each pixel and the reference signal RAMP via a capacitor, and a predetermined reference voltage, and supplies an output signal indicating the comparison result to the counter 122.

[0063] Based on the output signal from the comparator 121, the counter 122 counts the time until the signal obtained by adding the pixel signal VSL and the reference signal RAMP via the capacitance exceeds a predetermined reference voltage, thereby converting the analog pixel signal into a digital pixel signal represented by a count value. The counter 122 supplies the count value to the latch circuit 123.

[0064] The latch circuit 123 holds the count value supplied from the counter 122. Further, the latch circuit 123 performs correlated double sampling (CDS) by taking the difference between the D-phase count value corresponding to the pixel signal of the signal level and the P-phase count value corresponding to the pixel signal of the reset level.

[0065] The horizontal transfer scanning circuit 106 includes a shift register and an address decoder, and the like, and selectively scans the circuit portions corresponding to the pixel columns of the ADC group 105 in order. Through the selective scanning by the horizontal transfer scanning circuit 106, the digital pixel signal held in the latch circuit 123 is transferred to the amplifier circuit 107 in order via the horizontal transfer line 111.

[0066] The amplifier circuit 107 amplifies the digital pixel signal supplied from the latch circuit 123, and supplies the amplified digital pixel signal to the signal processing circuit 108.

[0067] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signal supplied from the amplifier circuit 107, to generate two-dimensional image data. For example, the signal processing circuit 108 performs correction of vertical line defects and point defects or clamping of signals, or performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 outputs the generated image data to a device in a later stage.

[0068] Note, Figure 1 The illustrated solid-state imaging device 100 can be configured as one semiconductor chip as a whole, or can be constituted by a plurality of semiconductor chips. In the case where the solid-state imaging device 100 is configured as a plurality of semiconductor chips, the pixel section 101 and the processing circuit other than the same can be formed as separate semiconductor chips 511 and 512, respectively, and the semiconductor chip 511 and the semiconductor chip 512 can be stacked.

[0069] For example, Figure 2 is a conceptual view illustrating an example of the solid-state imaging device 100 in which the semiconductor chip 511 of the pixel section 101 and the semiconductor chip 512 of the processing circuit are stacked. As Figure 2As shown, the solid-state imaging device 100 includes two semiconductor chips 511 and 512 stacked. Note that the number of semiconductor chips stacked can be three or more.

[0070] The semiconductor chip 511 includes the pixel section 101 formed on a semiconductor substrate. The semiconductor chip 512 includes the ADC groups 105a and 105b, the logic circuit 516, and the peripheral circuit 517 formed on another semiconductor substrate. The ADC groups 105 are divided into a plurality of sections (105a, 105b), and are, for example, set to have different gains. The logic circuit 516 includes the timing control circuit 102, the vertical scanning circuit 103, the DAC 104, the horizontal transfer scanning circuit 106, and the like. The peripheral circuit 517 includes the signal processing circuit 108, and the like.

[0071] For example, each pixel of the pixel section 101 of the semiconductor chip 511 and the elements of the processing circuit (105a, 105b, 516, 517) of the semiconductor chip 512 can be electrically connected using a through electrode such as a TSV (Through Silicon VIA) provided in the via regions 513 and 514. The ADC groups 105a and 105b can transmit and receive signals with the pixel section 101 via the TSVs. Further, the two semiconductor chips can be attached (Cu-Cu bonding) in a manner such that the wiring of the semiconductor chip 511 and the wiring of the semiconductor chip 512 are in contact with each other. In addition, although not shown, the pixel section 101 and part of the processing circuit (105a, 105b, 516, 517) can be configured as one semiconductor chip 511, and the other configuration can be configured as another semiconductor chip 512.

[0072] Figure 3 is a circuit diagram showing a configuration example of a pixel 150 provided in the pixel section 101. For example, the pixel 150 includes a photodiode 151 as a photoelectric conversion element, and further includes four transistors, a transfer transistor 152, an amplification transistor 154, a selection transistor 155, and a reset transistor 156, provided corresponding to the photodiode 151 as active elements.

[0073] The photodiode 151 photoelectrically converts incident light into an amount of electric charge (electrons in this example) corresponding to the light quantity thereof.

[0074] The transfer transistor 152 is connected between the photodiode 151 and a floating diffusion section (FD) 153. When the transfer transistor 152 is turned on by a drive signal TX supplied from the vertical scanning circuit 103, the transfer transistor 152 transfers the electric charge accumulated in the photodiode 151 to the FD 153.

[0075] The gate of the amplification transistor 154 is connected to the FD 153. The amplification transistor 154 is connected to the vertical signal line 110 via the selection transistor 155, and forms a source follower together with a constant current source 157 outside the pixel section 101. When the selection transistor 155 is turned on by a drive signal SEL supplied from the vertical scanning circuit 103, the amplification transistor 154 amplifies the potential of the FD 153 and outputs a pixel signal representing the voltage corresponding to the potential to the vertical signal line 110. Then, the pixel signal output from each of the pixels 150 is supplied to each of the comparators 121 of the ADC group 105 via the vertical signal line 110.

[0076] The reset transistor 156 is connected between the power supply VDD and the FD 153. When the reset transistor 156 is turned on by a drive signal RST supplied from the vertical scanning circuit 103, the potential of the FD 153 is reset to the potential of the power supply VDD.

[0077] Figure 4 is a block diagram showing a configuration example of the pixel section 101 and the ADC groups 105a and 105b. Each of the pixel columns of the plurality of pixels 150 included in the pixel section 101 is connected to both of the ADC groups 105a and 105b via the vertical signal line 110. The vertical signal line 110 is provided corresponding to each of the pixel columns containing the plurality of pixels 150, and transmits the same pixel signal VSL from the selected pixel 150 in the pixel column. Note that although only one pixel 150 is shown for the vertical signal line 110, as Figure 4 indicated, the vertical signal line 110 is shared by the plurality of pixels 150 in the pixel column. Figure 5

[0078] The ADC group 105a includes a plurality of capacitor sections 120a and a plurality of comparators 121a provided corresponding to each of the pixel columns. The capacitor section 120a is connected to the vertical signal line 110 and transmits the pixel signal VSL from the pixel 150 to the comparator 121a. At this time, the capacitance of the capacitor section 120a is changeable so as to set the input capacitance gain of the pixel signal VSL. The comparator 121a receives the pixel signal VSL via the capacitor section 120a, and outputs the comparison result between the pixel signal VSL and a reference signal RAMP to the counter 122 in the ADC group 105a. Figure 1

[0079] ​​The ADC group 105b includes a plurality of capacitor sections 120b and a plurality of comparators 121b provided corresponding to each pixel column. The capacitor section 120b is connected to the vertical signal line 110, and transfers the pixel signal VSL from the pixel 150 to the comparator 121b. At this time, the capacitance of the capacitor section 120b is changeable so as to set the input capacitance gain of the pixel signal VSL. The comparator 121b receives the pixel signal VSL via the capacitor section 120b, and outputs the comparison result between the pixel signal VSL and the reference signal RAMP to the counter 122. Figure 1

[0080] The capacitor sections 120a and 120b have mutually different input capacitance gains. For example, the capacitor section 120a has a relatively low input capacitance gain, and the capacitor section 120b has a relatively high input capacitance gain. The input capacitance gain is the transfer rate of the pixel signal VSL with respect to the reference signal RAMP. In the case where the input capacitance gain becomes high, the transfer rate of the pixel signal VSL becomes large, and the solid-state imaging device 100 can accurately detect even in the case of low-illuminance irradiation light. In the case where the input capacitance gain becomes low, the transfer rate of the pixel signal VSL becomes small, and the solid-state imaging device 100 can detect high-illuminance irradiation light in a short time. The input capacitance gain can be controlled by changing the capacitance ratio between the capacitance element for transferring the pixel signal VSL and the capacitance element for transferring the reference signal RAMP.

[0081] The capacitor section 120a is used to detect high-illuminance irradiation light because it has a relatively low input capacitance gain. The capacitor section 120b is used to low-illuminance irradiation light because it has a relatively high input capacitance gain.

[0082] As described above, each pixel 150 is connected to a plurality of ADC groups 105a and 105b having mutually different input capacitance gains via the corresponding vertical signal line 110.

[0083] Figure 5 is a diagram showing an example of the internal configuration of the capacitor sections 120a and 120b and the comparators 121a and 121b.

[0084] ​The capacitor section 120a as the first capacitor section is provided between the vertical signal line 110 or the reference signal line 114 and the comparator 121a, and is set to a low gain (LG) as a first gain. The capacitor section 120a includes an input capacitance element Crmpa and an input capacitance element Cvsla. The input capacitance element Crmpa as a first input capacitance element is provided between the reference signal line 114 and a gate of a transistor Tp1a of the comparator 121a. The input capacitance element Cvsla as a second input capacitance element is provided between the vertical signal line 110 and the comparator 121a.

[0085] That is, one end of the input capacitance element Crmpa and one end of the input capacitance element Cvsla are connected to the vertical signal line 110 and the reference signal line 114, respectively. The other end of the input capacitance element Crmpa and the other end of the input capacitance element Cvsla are commonly connected to the gate of the transistor Tp1a.

[0086] The capacitor section 120b as the second capacitor section is provided between the vertical signal line 110 or the reference signal line 114 and the comparator 121b, and is set to a high gain (HG) as a second gain. The second gain is higher than the first gain. The capacitor section 120b includes an input capacitance element Crmpb and an input capacitance element Cvslb. The input capacitance element Crmpb as a third input capacitance element is provided between the reference signal line 114 and a gate of a transistor Tp1b of the comparator 121b. The input capacitance element Cvslb as a fourth input capacitance element is provided between the vertical signal line 110 and the comparator 121b.

[0087] That is, one end of the input capacitance element Crmpb and one end of the input capacitance element Cvslb are connected to the vertical signal line 110 and the reference signal line 114, respectively. The other end of the input capacitance element Crmpb and the other end of the input capacitance element Cvslb are commonly connected to the gate of the transistor Tp1b.

[0088] Further, the capacitor sections 120a and 120b share the corresponding reference signal line 114, and share the corresponding vertical signal line 110. Therefore, one end of the input capacitance element Crmpa and one end of the input capacitance element Crmpb are commonly connected to the reference signal line 114. One end of the input capacitance element Cvsla and one end of the input capacitance element Cvslb are commonly connected to the vertical signal line 110 by means of the vertical signal line 110.

[0089] In the present embodiment, while the capacitances of the input capacitance elements Crmpa and Crmpb are substantially equal to each other, the capacitances of the input capacitance elements Cvsla and Cvslb are different from each other. Thus, the capacitance ratio between the input capacitance element Crmpa and the input capacitance element Cvsla (input capacitance gain Ga of the capacitor section 120a) is different from the capacitance ratio between the input capacitance element Crmpb and the input capacitance element Cvslb (input capacitance gain Gb of the capacitor section 120b). The input capacitance gain Ga of the capacitor section 120a is determined by the capacitance ratio of the input capacitance element Cvsla with respect to the input capacitance element Crmpa (e.g., Cvsla / (Cvsla+Crmpa)). The input capacitance gain Gb of the capacitor section 120b is determined by the capacitance ratio of the input capacitance element Cvslb with respect to the input capacitance element Crmpb (e.g., Cvslb / (Cvslb+Crmpb)).

[0090] In the present embodiment, for example, since the input capacitance element Cvslb is larger than the input capacitance element Cvsla, the input capacitance gain Gb of the capacitor section 120b is set to be larger than the input capacitance gain Ga of the capacitor section 120a.

[0091] The input capacitance elements Crmpa, Crmpb, Cvsla, and Cvslb are variable capacitance elements. For example, the input capacitance elements Crmpa, Crmpb, Cvsla, and Cvslb can be adjusted by fine adjustment of the number of elements of the same capacitance connected in parallel or in series, or can be adjusted by changing using a switch (not shown) or the like. The fine adjustment or switching of the input capacitance elements Crmpa, Crmpb, Cvsla, and Cvslb only needs to be performed at the time of manufacturing or shipping the solid-state imaging device 100. Alternatively, as explained with reference to Figure 18 As explained above, the switching of the input capacitance elements Crmpa, Crmpb, Cvsla, and Cvslb can be performed by switching the switches SWc1 and SWc2 based on the illuminance of the irradiation light.

[0092] The comparator 121a as the first comparator is a single-stage amplifier connected to the capacitor section 120a and outputs an output signal OUTa (amplified) corresponding to the pixel signal VSL based on the voltage difference between the pixel signal VSL and the reference signal RAMP.

[0093] The comparator 121a includes an n-type transistor Tn1a, a p-type transistor Tp1a, and an n-type transistor Tn2a. The transistors Tn1a, Tp1a, and Tn2a are connected in series between the power supply Vdd and the ground GND in this order.

[0094] The drain of the transistor Tn1a is connected to the power supply Vdd, and its source is connected to the source of the transistor Tp1a. The transistor Tn1a functions as a low dropout (LDO) linear regulator.

[0095] As described above, the gate of the transistor Tp1a as the first transistor is commonly connected to the other end of the input capacitive element Crmpa and the other end of the input capacitive element Cvsla. The source of the transistor Tp1a is connected to the source of the transistor Tn1a, and the drain of the transistor Tp1a is connected to the output terminal and the drain of the transistor Tn2a. When the added signal of the pixel signal VSL from the capacitor section 120a and the reference signal RAMP from the DAC 104 exceeds the reference voltage, the transistor Tp1a changes from the on state to the off state, and inverts the level of the output signal OUTa. That is, the transistor Tp1a functions as an amplifier that amplifies and detects the level of the pixel signal VSL.

[0096] The transistor Tn2a functions as a constant current source for causing a constant current to flow through the transistor Tp1a.

[0097] The AZ switch SW1a is connected between the gate of the transistor Tp1a and the output terminal Touta, and performs an automatic zeroing operation by equalizing the potentials of both the gate of the transistor Tp1a and the output terminal Touta before detecting the pixel signal VSL.

[0098] With this configuration, the comparator 121a outputs the output signal OUTa as the first output signal from the output section between the transistors Tp1a and Tn2a.

[0099] The comparator 121b as the second comparator is connected to the capacitor section 120b, and outputs the output signal OUTb from the pixel signal VSL based on the voltage difference between the pixel signal VSL and the reference signal RAMP.

[0100] The comparator 121b includes an n-type transistor Tn1b, a p-type transistor Tp1b, and an n-type transistor Tn2b. The transistors Tn1b, Tp1b, and Tn2b are connected in series between the power supply Vdd and the ground GND in this order.

[0101] The drain of the transistor Tn1b is connected to the power supply Vdd, and the source is connected to the source of the transistor Tp1b. The transistor Tn1b functions as an LDO linear regulator similarly to the transistor Tn1a.

[0102] As described above, the gate of the transistor Tp1b as the second transistor is commonly connected to the other end of the input capacitive element Crmpb and the other end of the input capacitive element Cvslb. The source of the transistor Tp1b is connected to the source of the transistor Tn1b, and the drain of the transistor Tp1b is connected to the output terminal and the drain of the transistor Tn2b. When the added signal of the pixel signal VSL from the capacitor portion 120b and the reference signal RAMP from the DAC 104 exceeds the reference voltage, the transistor Tp1b changes from the on state to the off state, and inverts the level of the output signal OUTb. That is, the transistor Tp1b functions as an amplifier that amplifies and detects the level of the pixel signal VSL.

[0103] The transistor Tn2b functions as a constant current source for causing a constant current to flow through the transistor Tp1b.

[0104] The AZ switch SW1b is connected between the gate of the transistor Tp1b and the output terminal Toutb, and performs an auto-zero operation by equalizing the potential of both the gate of the transistor Tp1b and the output terminal Toutb before detecting the pixel signal VSL.

[0105] With this configuration, the comparator 121b outputs the output signal OUTb as the second output signal from the output portion between the transistors Tp1b and Tn2b.

[0106] Note that the current sources CS1a and CS1b are connected to the vertical signal line 110, and are configured to cause a constant current to flow through the vertical signal line 110.

[0107] The configuration of the comparator 121b is the same as that of the comparator 121a. That is, the transistors Tnla and Tnlb have the same configuration, the transistors Tpla and Tplb have the same configuration, and the transistors Tn2a and Tn2b have the same configuration. Thereby, the gain Ga of the ADC group 105a and the gain Gb of the ADC group 105b are substantially determined by the difference between the capacitance ratio of the input capacitance element Cvsla with respect to the input capacitance element Crmpa and the capacitance ratio of the input capacitance element Cvslb with respect to the input capacitance element Crmpb. Therefore, the ADC group 105a outputs the comparison result between the pixel signal VSL and the reference signal RAMP at a low gain as the output signal OUTa. The ADC group 105b outputs the comparison result between the pixel signal VSL and the reference signal RAMP at a high gain as the output signal OUTb. As a result, the solid-state imaging device 100 can detect irradiation light of a wide dynamic range (High Dynamic Range (HDR)) from low illumination to high illumination. Further, by making the configurations of the comparators 121a and 121b the same, the comparators 121a and 121b can be formed at the same time in the same process, and manufacturing cost can be suppressed to be low.

[0108] Next, the operation of the solid-state imaging device 100 according to the present embodiment will be described.

[0109] Figure 6 is a timing chart showing an operation example of the solid-state imaging device 100 according to the first embodiment. The horizontal axis represents time. The vertical axis represents the drive signals of the AZ switches SWla and SWlb, the pixel signal VSL, the reference signal RAMP, the gate voltages of the transistors Tpla and Tplb, and the voltage levels (signal levels) of the output signals OUTa and OUTb. Note that it is assumed that the transistors Tnla and Tnlb are always turned on during the signal detection period. Further, it is assumed that the transistors Tn2a and Tn2b cause a constant current to flow into the transistors Tpla and Tplb.

[0110] At time t1, the FD 153 of the pixel 150 as a readout target is reset, and the pixel signal VSL is set to a reset level. At this time, the reference signal RAMP is set to a predetermined reset level.

[0111] At time t2, the drive signals of the AZ switches SWla and SWlb are set to high level, and the auto-zero operation of the comparators 121a and 121b is performed. Specifically, the AZ switch SWla is turned on, the gate of the transistor Tpla and the output section Touta are connected, and the input and output of the comparator 121a are short-circuited. As a result, the gate voltage of the transistor Tpla and the voltage of the output signal OUTa converge to a voltage close to the middle between the high level and the low level of the output signal OUTa. The converged voltage becomes the reference voltage of the comparator 121a. Therefore, thereafter, when the AZ switch SWla is turned off, if the gate voltage of the transistor Tpla (the input voltage of the comparator 121a) rises above the reference voltage, the voltage of the output signal OUTa falls and becomes the low level. On the other hand, if the gate voltage of the transistor Tpla (the input voltage of the comparator 121a) falls below the reference voltage, the voltage of the output signal OUTa rises and becomes the high level.

[0112] Similarly to the AZ switch SWla, the AZ switch SWlb also performs the auto-zero operation on the comparator 121b. That is, the AZ switch SWlb is turned on, the gate of the transistor Tplb and the output section Toutb are connected, and the input and output of the comparator 121b are short-circuited. As a result, the gate voltage of the transistor Tplb and the voltage of the output signal OUTb converge to a voltage close to the middle between the high level and the low level of the output signal OUTb. The converged voltage becomes the reference voltage of the comparator 121b. Therefore, thereafter, when the AZ switch SWlb is turned off, if the gate voltage of the transistor Tplb (the input voltage of the comparator 121b) rises above the reference voltage, the voltage of the output signal OUTb falls and becomes the low level. On the other hand, if the gate voltage of the transistor Tplb (the input voltage of the comparator 121b) falls below the reference voltage, the voltage of the output signal OUTb rises and becomes the high level.

[0113] At time t3, the drive signals of the AZ switches SWla and SWlb are set to low level, the AZ switches SWla and SWlb are turned off, and the auto-zero operation of the comparators 121a and 121b is ended. The voltages of the transistors Tpla and Tplb and the voltages of the output signals OUTa and OUTb remain unchanged from the state of the reference voltage. Since the configurations of the comparators 121a and 121b are the same, the reference voltages of the comparators 121a and 121b become substantially the same.

[0114] At time t4, the voltage of the reference signal RAMP falls from the reset level by a predetermined value. As a result, the gate voltages of the transistors Tpla and Tplb fall below the reference voltage, and the output signals OUTa and OUTb become the high level.

[0115] At time t5, the voltage level of the reference signal RAMP is linearly increased. In correspondence therewith, the gate voltage of the transistors Tp1a and Tp1b is also linearly increased. Further, Figure 1 The counter 122 in the time t5-1 starts counting.

[0116] At the time point t5-1, when the gate voltage of the transistors Tp1a and Tp1b exceeds the reference voltage, the voltage of the output signals OUTa and OUTb is inverted to a low level. When the output signals OUTa and OUTb are inverted to a low level, the count value of the counter 122 is held as the value of the pixel signal VSL of the P phase (reset level) in the latch circuit 123 of Figure 1 The latch circuit 123 latches both of the output signals OUTa and OUTb.

[0117] At time t6, the voltage of the reference signal RAMP is again set to the reset voltage. As a result, the gate voltage of the transistors Tp1a and Tp1b returns to the reference voltage, and the output signals OUTa and OUTb become substantially equal to the reference voltage.

[0118] At time t7, the transfer transistor 152 of the pixel 150 is turned on, and the charge accumulated in the photodiode 151 during the exposure period is transferred to the FD 153. As a result, the pixel signal VSL becomes a signal level, and the gate voltage of the transistors Tp1a and Tp1b drops from the reference voltage by a value corresponding to the signal level. As a result, the output signals OUTa and OUTb become high levels. However, in the case where the signal level of the pixel signal VSL is small, the output signals OUTa and OUTb are held at a value substantially close to the reference voltage.

[0119] At time t8, similarly to time t4, the voltage of the reference signal RAMP is decreased from the reset level by a predetermined value. As a result, the gate voltage of the transistors Tp1a and Tp1b is further decreased from the signal level.

[0120] At time t9, similarly to time t5, the voltage level of the reference signal RAMP is linearly increased. In correspondence therewith, the gate voltage of the transistors Tp1a and Tp1b is also linearly increased. Further, the counter 122 starts counting.

[0121] From time t9-1 to time t9-3, the output signals OUTa and OUTb are inverted to low levels when the gate voltages of the transistors Tp1a and Tp1b exceed the reference voltage. For example, in a case where the illuminance of the irradiation light is low and the pixel signal VSL is small, as indicated by line L1, the levels of the gate voltages of the transistors Tp1a and Tp1b hardly decrease in the pixel signal VSL. In this case, at a relatively early time t9-1, the gate voltages of the transistors Tp1a and Tp1b exceed the reference voltage, and the output signals OUTa and OUTb are inverted to low levels. In a case where the illuminance of the irradiation light is moderate and the pixel signal VSL is moderate, as indicated by line L2, at t9-2, the gate voltages of the transistors Tp1a and Tp1b exceed the reference voltage, and the output signals OUTa and OUTb are inverted to low levels. In a case where the illuminance of the irradiation light is high and the pixel signal VSL is high, as indicated by line L3, at a relatively late time t9-3, the gate voltages of the transistors Tp1a and Tp1b exceed the reference voltage, and the output signals OUTa and OUTb are inverted to low levels. As described above, the period from the start of the increase of the reference signal RAMP to the inversion of the output signals OUTa and OUTb varies depending on the illuminance of the irradiation light.

[0122] When the output signals OUTa and OUTb are inverted to low levels, the count value of the counter 122 is held as the value of the pixel signal VSL of the D phase (reset level) in the latch circuit 123 of Figure 1 The latch circuit 123 latches both of the output signals OUTa and OUTb. The latch circuit 123 performs CDS by taking the difference between the D phase pixel signal VSL and the P phase pixel signal VSL read between time t5 and time t6. In this way, AD conversion of the pixel signal VSL is performed. The AD conversion is performed in each of the ADC groups 105a and 105b, and is performed for the pixel signal VSL detected under mutually different input capacitance gains. The digital image data from the ADC group 105a and the digital image data from the ADC group 105b are transferred to the signal processing circuit 108.

[0123] Since the period from the start of the increase of the reference signal RAMP to the inversion of the output signals OUTa and OUTb varies depending on the illuminance of the irradiation light, the digital image data from the ADC groups 105a and 105b also have values based on the illuminance of the irradiation light.

[0124] Thereafter, the signal processing circuit 108 selects or generates a pixel signal by using either or both of the output signals OUTa and OUTb, and generates image data. At this time, the signal processing circuit 108 can select the output signals OUTa and OUTb depending on the illuminance of the irradiation light.

[0125] At time t10, similarly to time t6, the voltage of the reference signal RAMP is set to the reset voltage. As a result, the gate voltage of the transistors Tp1a and Tp1b returns to the reference voltage, and the output signal OUTa becomes substantially equal to the reference voltage. Thereafter, after time t11, operations similar to those of times t1 to t10 are repeated.

[0126] According to the present embodiment, in the solid-state imaging device 100, the ADC group corresponding to each pixel column is divided into the plurality of ADC groups 105a and 105b having different gains. The gain of each of the ADC groups 105a and 105b is set by the input capacitance gain Ga and Gb of the capacitor sections 120a and 120b, respectively. As a result, the signal processing circuit 108 can select or generate a pixel signal using either or both of the output signals OUTa and OUTb generated by detecting a pixel signal at a plurality of gains, and generate image data. At this time, the signal processing circuit 108 can select the output signals OUTa and OUTb in accordance with the illuminance (light intensity) of the irradiation light. For example, in a case where the illuminance of the irradiation light is relatively high, the signal processing circuit 108 selects the output signal OUTa detected by the ADC group 105a at a low gain, and generates image data. In a case where the illuminance of the irradiation light is relatively low, the signal processing circuit 108 selects the output signal OUTb detected by the ADC group 105b at a high gain, and generates image data. As a result, the solid-state imaging device 100 can perform imaging with high sensitivity (fine gradation) even under irradiation light of low illuminance, and can perform imaging without saturation in a short time (low power consumption) even under irradiation light of high illuminance. That is, the solid-state imaging device 100 according to the present embodiment can perform imaging with a wide dynamic range (HDR) in accordance with the illuminance of the irradiation light.

[0127] Further, in the solid-state imaging device 100 according to the present embodiment, as shown in Figure 2 The ADC groups 105a and 105b are provided on both sides of the logic circuit 516 and the peripheral circuit 517, and are spaced apart from each other. In a case where a plurality of ADCs having different gains are adjacent to each other, the output signals from the plurality of ADCs can influence each other due to a proximity effect. In contrast, since the ADC groups 105a and 105b according to the present embodiment are spaced apart from each other, the influence on each other can be suppressed even if the ADC groups have different gains. This allows the solid-state imaging device 100 to generate accurate image data.

[0128] According to the present embodiment, the gains of the ADC groups 105a and 105b are set by the capacitance ratio between the input capacitance elements Crmpa and Cvsla of the capacitor section 120a and the capacitance ratio between the input capacitance elements Crmpb and Cvslb of the capacitor section 120b, respectively. Thus, for the ADC groups 105a and 105b, the pixel signal VSL and the reference signal RAMP can be the same or common to the ADC groups 105a and 105b. For example, as shown in FIG. 6, the DAC 104 is provided to be common to the ADC groups 105a and 105b, and it is only necessary to supply the same reference signal RAMP to the ADC groups 105a and 105b via the reference signal line 114. Even if a plurality of ADC groups 105a and 105b are provided, since the DAC 104 can be common, the overall size of the solid-state imaging device 100 can be suppressed to be small. Of course, if the size of the solid-state imaging device 100 is not required to be considered, the DAC 104 can be provided corresponding to each of the plurality of ADC groups 105a and 105b. Figure 7

[0129] Further, in the present embodiment, the comparators 121a and 121b are constituted by single-stage amplifiers. Thus, compared to the case where a differential amplifier is used as in the second embodiment, the solid-state imaging device 100 according to the first embodiment can substantially halve the current consumption and reduce the power consumption.

[0130] In addition, the input voltage of the comparators 121a and 121b becomes the sum signal of the pixel signal VSL and the reference signal RAMP. In the case where the pixel signal VSL and the reference signal RAMP have opposite polarities, the input voltage of the comparators 121a and 121b becomes the differential voltage between the pixel signal VSL and the reference signal RAMP, and the amplitude becomes small. As a result, the voltage fluctuation of the comparators 121a and 121b can be reduced, and the voltage of the power supply Vdd can be reduced. As a result, the power consumption of the solid-state imaging device 100 can be reduced.

[0131] (Second Embodiment)

[0132] Figure 8A is a diagram showing a configuration example of the solid-state imaging device 100 according to the second embodiment. The second embodiment differs from the first embodiment in the configuration of the comparators 121a and 121b. The other configurations including the capacitor sections 120a and 120b can be similar to the corresponding configurations of the first embodiment.

[0133] The comparator 121a is a differential circuit connected to the capacitor section 120a and outputs an output signal OUTa corresponding to the pixel signal VSL based on the voltage difference between the pixel signal VSL and the reference signal RAMP. ​

[0134] The comparator 121a includes p-type transistors Tp2a to Tp4a, a current mirror circuit CMa, AZ switches SW2a and SW3a, and a capacitive element C1a.

[0135] The source of the transistor Tp2a is connected to a power supply Vdd, and its drain is commonly connected to the sources of the transistors Tp3a and Tp4a.

[0136] The gate of the transistor Tp3a as the first transistor is commonly connected to the other end of the input capacitive element Crmpa and the other end of the input capacitive element Cvsla. The source of the transistor Tp3a is connected to the drain of the transistor Tp2a, and the drain of the transistor Tp3a is connected to the current mirror circuit CMa.

[0137] The gate of the transistor Tp4a as the third transistor is connected to the ground GND via the capacitive element C1a. The source of the transistor Tp4a is commonly connected to the drain of the transistor Tp2a with the source of the transistor Tp3a. The drain of the transistor Tp4a is connected to the current mirror circuit CMa and the output section Touta.

[0138] The current mirror circuit CMa as the first mirror circuit is connected between the drains of the transistors Tp3a and Tp4a and the ground GND, and is configured to cause substantially equal currents to flow through the transistors Tp3a and Tp4a. More specifically, the current mirror circuit CMa includes an n-type transistor Tn3a connected between the transistor Tp3a and the ground GND, and an n-type transistor Tn4a connected between the transistor Tp4a and the ground GND. The gates of the transistors Tn3a and Tn4a are commonly connected to the drain of the transistor Tn3a.

[0139] The AZ switch SW2a is connected between the gate and the drain of the transistor Tp3a, and performs an automatic zeroing operation by equalizing the potentials of both the gate and the drain of the transistor Tp3a before detecting the pixel signal VSL.

[0140] The AZ switch SW3a is connected between the gate and the drain of the transistor Tp4a, and performs an automatic zeroing operation by equalizing the potentials of both the gate and the drain of the transistor Tp4a before detecting the pixel signal VSL.

[0141] When the voltage level of the added signal of the pixel signal VSL and the reference signal RAMP exceeds the reference voltage, the transistor Tp3a changes from the on state to the off state. The current mirror circuit CMa causes a current obtained by multiplying the current flowing through the transistor Tp3a by a predetermined mirror ratio to flow to the transistor Tp4a. The transistor Tp4a generates the voltage level of the output signal OUTa in accordance with the current flowing through the transistor Tp3a. At the time when the transistor Tp3a changes from the on state to the off state, the transistor Tp4a similarly to the transistor Tn3a causes a predetermined current to flow, thereby causing the output signal OUTa to invert from the low level to the high level. That is, similarly to the first embodiment, when the voltage level of the added signal of the pixel signal VSL and the reference signal RAMP exceeds the reference voltage, the comparator 121a inverts the level of the output signal OUTa.

[0142] The comparator 121b is a differential circuit that is connected to the capacitor section 120b and outputs an output signal OUTb corresponding to the pixel signal VSL on the basis of the voltage difference between the pixel signal VSL and the reference signal RAMP.

[0143] The comparator 121b includes p-type transistors Tp2b to Tp4b, a current mirror circuit CMb, AZ switches SW2b and SW3b, and a capacitor element C1b.

[0144] The source of the transistor Tp2b is connected to the power supply Vdd, and its drain is commonly connected to the sources of the transistors Tp3b and Tp4b.

[0145] The gate of the transistor Tp3b as the second transistor is commonly connected to the other end of the input capacitor element Crmpb and the other end of the input capacitor element Cvslb. The source of the transistor Tp3b is connected to the drain of the transistor Tp2b, and the drain of the transistor Tp3b is connected to the current mirror circuit CMb.

[0146] The gate of the transistor Tp4b as the fourth transistor is connected to the ground GND via the capacitor element C1b. The source of the transistor Tp4b is commonly connected to the drain of the transistor Tp2b with the source of the transistor Tp3b. The drain of the transistor Tp4b is connected to the current mirror circuit CMb and the output section Toutb.

[0147] The current mirror circuit CMb as the second mirror circuit is connected between the drains of the transistors Tp3b and Tp4b and the ground GND, and is configured to cause substantially equal currents to flow through the transistors Tp3b and Tp4b. More specifically, the current mirror circuit CMb includes an n-type transistor Tn3b connected between the transistor Tp3b and the ground GND, and an n-type transistor Tn4b connected between the transistor Tp4b and the ground GND. The gates of the transistors Tn3b and Tn4b are commonly connected to the drain of the transistor Tn3b.

[0148] The AZ switch SW2b is connected between the gate and the drain of the transistor Tp3b, and performs an auto-zero operation by equalizing the potentials of both the gate and the drain of the transistor Tp3b before detecting the pixel signal VSL.

[0149] The AZ switch SW3b is connected between the gate and the drain of the transistor Tp4b, and performs an auto-zero operation by equalizing the potentials of both the gate and the drain of the transistor Tp4b before detecting the pixel signal VSL.

[0150] When the voltage level of the added signal of the pixel signal VSL and the reference signal RAMP exceeds the reference voltage, the transistor Tp3b changes from the on state to the off state. The current mirror circuit CMb causes a current obtained by multiplying the current flowing through the transistor Tp3b by a predetermined mirror ratio to flow to the transistor Tp4b. The transistor Tp4b generates the voltage level of the output signal OUTb in accordance with the current flowing through the transistor Tp3b. As a result, when the transistor Tp3b changes from the on state to the off state, the transistor Tp4b similarly to the transistor Tn3b causes a predetermined current to flow, thereby causing the output signal OUTb to invert from the low level to the high level. That is, similarly to the first embodiment, when the voltage level of the added signal of the pixel signal VSL and the reference signal RAMP exceeds the reference voltage, the comparator 121b inverts the level of the output signal OUTb.

[0151] The other configurations and operations of the second embodiment can be the same as those of the first embodiment. Therefore, although the second embodiment consumes more power than the first embodiment, the other effects of the first embodiment can be obtained in addition.

[0152] (Modified Example)

[0153] Figure 8Bis a diagram showing a configuration example of the solid-state imaging device 100 according to a modification of the second embodiment. In the present modification, the comparators 121a and 121b function as a differential circuit between the pixel signal VSL and the reference signal RAMP. The other end of the input capacitance element Cvsla is not connected to the gate of the transistor Tp3a but is connected to the gate of the transistor Tp4a. The other end of the input capacitance element Cvslb is not connected to the gate of the transistor Tp3b but is connected to the gate of the transistor Tp4b.

[0154] The input capacitance elements Cgnda and Cgndb are connected between the gates of the transistors Tp3a and Tp3b and the ground GND, respectively. The input capacitance elements Cgnda and Cgndb are variable capacitance elements. Variable capacitance elements similar to the input capacitance elements Crmpa and Crmp can be used. In the present modification, the input capacitance element gains Ga and Gb are respectively set by making the capacitances of the input capacitance elements Cgnda and Cgndb different from each other.

[0155] The comparator 121a amplifies the difference between the pixel signal VSL and the reference signal RAMP and outputs the amplified difference as the output signal OUTa. The comparator 121b amplifies the difference between the pixel signal VSL and the reference signal RAMP and outputs the amplified difference as the output signal OUTb. At this time, the input capacitance gain Ga of the capacitor section 120a is determined by the capacitance ratio of the input capacitance elements Crmpa and Cgnda. The input capacitance gain Gb of the capacitor section 120b is determined by the capacitance ratio of the input capacitance elements Crmpb and Cgndb.

[0156] The operation of the present modification can be the same as that of the second embodiment. Therefore, the present modification can obtain the same effects as those of the second embodiment.

[0157] (Modification)

[0158] Figure 8C is a diagram showing a configuration example of the solid-state imaging device 100 according to another modification of the second embodiment. In the present modification, the input capacitance elements Cgnda and Cgndb are connected between the gates of the transistors Tp4a and Tp4b and the ground GND, respectively. Also in the present modification, the input capacitance element gains Ga and Gb are respectively set by making the capacitances of the input capacitance elements Cgnda and Cgndb different from each other. The input capacitance gain Ga of the capacitor section 120a is determined by the capacitance ratio of the input capacitance elements Cvsla and Cgnda. The input capacitance gain Gb of the capacitor section 120b is determined by the capacitance ratio of the input capacitance elements Cvslb and Cgndb. The other configurations of the present modification can be similar to those of the second embodiment. Figure 8BA configuration example of a modification of the second embodiment will be described. The operation of this modification can be the same as that of the second embodiment. Therefore, this modification can also obtain the same effect as that of the second embodiment.

[0159] (Third Embodiment)

[0160] Figure 9 is a view showing a configuration example of the solid-state imaging device 100 according to the third embodiment. The third embodiment differs from the first embodiment in the configuration of the comparators 121a and 121b and the vertical signal line 110. The other configurations including the capacitor sections 120a and 120b can be similar to the corresponding configurations of the first embodiment.

[0161] In the third embodiment, the constant current source CS1a is connected to each vertical signal line 110. When detecting a pixel signal, the constant current source CS1a causes a predetermined constant current to flow through the vertical signal line 110, and a pixel signal VSL is generated in the vertical signal line 110.

[0162] The comparator 121a includes an n-type transistor Tn5a, a p-type transistor Tp5a, a constant current source CS2a, and AZ switches SW4a and SW5a.

[0163] The gate of the transistor Tn5a is connected to the other end of the input capacitive element Cvsla. The drain of the transistor Tn5a is connected to the power supply Vdd, and its source is connected to the source of the transistor Tp5a. The transistor Tn5a generates a signal of a voltage level corresponding to the pixel signal VSL, and transmits the signal to the source of the transistor Tp5a.

[0164] The gate of the transistor Tp5a as the first transistor is connected to the other end of the input capacitive element Crmpa. The source of the transistor Tp5a is connected to the source of the transistor Tn5a, and its drain is connected to the constant current source CS2a and the output section Touta. The transistor Tp5a becomes in an on state based on a voltage difference Vgs between the source voltage and the gate voltage.

[0165] For example, in the third embodiment, when the pixel signal VSL is detected, the voltage level of the reference signal RAMP is linearly decreased from a level higher than that of the pixel signal VSL. As a result, when the reference signal RAMP is lower than the pixel signal VSL, the transistor Tp5a changes from a non-conducting state to a conducting state. The constant current source CS2a causes a constant current to flow through the transistors Tn5a and Tp5a. Therefore, when the transistor Tp5a is in the non-conducting state, the output signal OUTa becomes a low level, and when the transistor Tp5a is in the conducting state, the output signal OUTa becomes a high level. That is, when the reference signal RAMP is lower than the pixel signal VSL, the output signal OUTa is inverted from a low level to a high level. As described above, in the third embodiment, the transistor Tp5a can generate the output signal OUTa obtained by amplifying the differential voltage between the pixel signal VSL and the reference signal RAMP.

[0166] The input capacitive elements Cgnda and Cgndb are connected between the gates of the transistors Tp5a and Tp5b and the ground GND, respectively. The input capacitive elements Cgnda and Cgndb are variable capacitive elements. Variable capacitive elements similar to the input capacitive elements Crmpa and Crmp can be used. In the third embodiment, the input capacitive element gains Ga and Gb are respectively set by making the capacitances of the input capacitive elements Cgnda and Cgndb different from each other.

[0167] The AZ switch SW4a is connected between the gate and the drain of the transistor Tn5a, and before the pixel signal VSL is detected, an automatic zeroing operation is performed by making the potentials of both the gate and the drain of the transistor Tn5a equal.

[0168] The AZ switch SW5a is connected between the gate and the drain of the transistor Tp5a, and before the pixel signal VSL is detected, an automatic zeroing operation is performed by making the potentials of both the gate and the drain of the transistor Tp5a equal.

[0169] The comparator 121b includes an n-type transistor Tn5b, a p-type transistor Tp5b, a constant current source CS2b, and AZ switches SW4b and SW5b.

[0170] The gate of the transistor Tn5b is connected to the other end of the input capacitive element Cvslb. The drain of the transistor Tn5b is connected to the power supply Vdd, and its source is connected to the source of the transistor Tp5b. The transistor Tn5b generates a signal of a voltage level corresponding to the pixel signal VSL, and transmits the signal to the source of the transistor Tp5b.

[0171] The gate of the transistor Tp5b as the second transistor is connected to the other end of the input capacitive element Crmpb. The source of the transistor Tp5b is connected to the source of the transistor Tn5b, and its drain is connected to the constant current source CS2b and the output section Toutb. The transistor Tp5b becomes an on state based on the voltage difference Vgs between the source voltage and the gate voltage.

[0172] As a result, when the reference signal RAMP is lower than the pixel signal VSL, the transistor Tp5b changes from the off state to the on state. The constant current source CS2b causes a constant current to flow through the transistors Tn5b and Tp5b. Therefore, when the transistor Tp5b is in the off state, the output signal OUTb becomes a low level, and when the transistor Tp5b is in the on state, the output signal OUTb becomes a high level. That is, when the reference signal RAMP is lower than the pixel signal VSL, the output signal OUTb is inverted from the low level to the high level. As described above, the transistor Tp5b can generate the output signal OUTb obtained by amplifying the differential voltage between the pixel signal VSL and the reference signal RAMP.

[0173] The AZ switch SW4b is connected between the gate and the drain of the transistor Tn5b, and performs an auto-zero operation by equalizing the potentials of both the gate and the drain of the transistor Tn5b before detecting the pixel signal VSL.

[0174] The AZ switch SW5b is connected between the gate and the drain of the transistor Tp5b, and performs an auto-zero operation by equalizing the potentials of both the gate and the drain of the transistor Tp5b before detecting the pixel signal VSL.

[0175] Figure 10 is a timing chart showing an operation example of the solid-state imaging device 100 according to the third embodiment. In the third embodiment, the reference signal RAMP is linearly decreased from a level higher than the pixel signal VSL. That is, this reference signal RAMP can be obtained by inverting the polarity of the reference signal RAMP of the first embodiment. Therefore, when the reference signal RAMP is lower than the pixel signal VSL, the output signals OUTa and OUTb are inverted. Since the other operations of the third embodiment can be similar to the corresponding operations of the first embodiment, detailed description thereof will be omitted. Note that the operations of the AZ switches SW4a, SW4b, SW5a, and SW5b can be the same as those of the AZ switches SW1a and SW1b of the first embodiment.

[0176] The third embodiment has the capacitor sections 120a and 102b similarly to the first embodiment, and can obtain the same effects as those of the first embodiment.

[0177] (Fourth Embodiment)

[0178] Figure 11 is a diagram showing a configuration example of the solid-state imaging device 100 according to the fourth embodiment. The fourth embodiment differs from the third embodiment in that the input capacitance elements Cvsla and Cvslb, the constant current source CSla, the transistors Tn5a and Tn5b, and the AZ switches SW4a and SW4b are omitted, and the input capacitance elements Cgnda and Cgndb are added. The gate of the transistor Tp5a is connected to one end of the input capacitance element Crmpa, and receives the reference signal RAMP via the input capacitance element Crmpa. Further, the gate of the transistor Tp5a is connected to one end of the input capacitance element Cgnda, and is connected to the ground GND via the input capacitance element Cgnda. The source of the transistor Tp5a is connected to the vertical signal line 110, and receives the pixel signal VSL. The gate of the transistor Tp5b is connected to one end of the input capacitance element Crmpb, and receives the reference signal RAMP via the input capacitance element Crmpb. Further, the gate of the transistor Tp5b is connected to one end of the input capacitance element Cgndb, and is connected to the ground GND via the input capacitance element Cgndb. The source of the transistor Tp5b is connected to the vertical signal line 110, and receives the pixel signal VSL. The transistors Tp5a and Tp5b receive the same reference signal RAMP at their gates via the input capacitance elements Crmpa and Crmpb. Further, the transistors Tp5a and Tp5b receive the same pixel signal VSL from the vertical signal line 110.

[0179] One end of the input capacitance element Crmpa and one end of the input capacitance element Crmpb are commonly connected to the reference signal line 114, and their other ends are connected to the gates of the transistors Tp5a and Tp5b, respectively. The sources of the transistors Tp5a and Tp5b are commonly connected to the vertical signal line 110. One end of the input capacitance element Cgnda and one end of the input capacitance element Cgndb are connected to the gates of the transistors Tp5a and Tp5b, and their other ends are connected to the ground GND.

[0180] The input capacitance elements Cgnda and Cgndb can be variable capacitance elements similar to the input capacitance elements Crmpa and Crmpb. In the fourth embodiment, the input capacitance gains Ga and Gb are respectively set by making the capacitances of the input capacitance elements Cgnda and Cgndb different from each other. For example, the input capacitance gain Ga is determined by the capacitance ratio of the input capacitance element Cgnda with respect to the input capacitance element Crmpa (e.g., Cgnda / (Cgnda+Crmpa)). The input capacitance gain Gb is determined by the capacitance ratio of the input capacitance element Cgndb with respect to the input capacitance element Crmpb (e.g., Cgndb / (Cgndb+Crmpb)).

[0181] The constant current sources that cause current to flow through the vertical signal lines 110 and that cause current to flow through the comparators Tp5a and Tp5b are shared as constant current sources CS2a and CS2b. Therefore, the constant current sources CS2a and CS2b cause constant current to flow through the vertical signal lines 110 and cause constant current to flow through the comparators Tp5a and Tp5b, respectively. As a result, the power consumption of the solid-state imaging device 100 according to the fourth embodiment is less than the power consumption of the solid-state imaging device according to the third embodiment.

[0182] In addition, the pixel signal VSL is input directly to the transistor Tp5a without passing through the transistor Tn5a in the Figure 9 In addition, the pixel signal VSL is input directly to the transistor Tp5b without passing through the transistor Tn5b in the Figure 9 In this way, since the constant current sources CS1a, the transistors Tn5a and Tn5b, and the AZ switches SW4a and SW4b are omitted, the layout area of the ADC groups 105a and 105b in the fourth embodiment is less than the layout area in the third embodiment.

[0183] The other configurations of the fourth embodiment can be similar to the corresponding configurations of the third embodiment. In addition, the operation of the fourth embodiment can be similar to the operation of the third embodiment. Therefore, the fourth embodiment can also obtain the same effects as the effects of the third embodiment.

[0184] (Modified Example 1)

[0185] Figure 12 is a diagram that shows a configuration example of the solid-state imaging device 100 according to Modified Example 1 of the first embodiment. In the first embodiment, two ADC groups 105a and 105b are connected in parallel with respect to each pixel column. In contrast to this, in Modified Example 1, three or more ADC groups 105a, 105b, 105c,... are connected in parallel with respect to each pixel column. The ADC groups 105a, 105b, 105c,... respectively have capacitor sections 120a, 120b, 120c,... that have different input capacitance gains. As described above, in the solid-state imaging device 100, three or more ADC groups 105a, 105b, 105c,... can be provided in correspondence with each pixel column. As a result, the dynamic range of the irradiation light that can be detected can be further increased.

[0186] (Modified Example 2)

[0187] Figure 13is a table showing a relationship between an exposure time and an input capacitance gain of the solid-state imaging device 100 according to Modification 2. In the above-described embodiment, although the exposure time of the pixel section 101 can be the same, the exposure time can be changed according to the illuminance of the irradiation light. The exposure time can be changed by the timing control circuit 102. For example, the solid-state imaging device 100 is capable of selecting the exposure time of the pixel section 101 between a relatively long first exposure time and a relatively short second exposure time. In this case, the ADC groups 105a and 105b respectively detect the pixel signals VSL of the first and second exposure times with the input capacitance gains Ga and Gb. Thus, a total of four types of first to fourth image data are obtained. That is, the first image data is image data obtained by detecting the pixel signal VSL obtained in the relatively long first exposure time with the relatively low input capacitance gain Ga. The second image data is image data obtained by detecting the pixel signal VSL obtained in the relatively short second exposure time with the relatively low input capacitance gain Ga. The third image data is image data obtained by detecting the pixel signal VSL obtained in the relatively long first exposure time with the relatively high input capacitance gain Gb. The fourth image data is image data obtained by detecting the pixel signal VSL obtained in the relatively short second exposure time with the relatively high input capacitance gain Gb.

[0188] The signal processing circuit 108 selects appropriate image data from the four image data, or combines a plurality of image data among the four image data to generate one image data. For example, in a case where the illuminance of the irradiation light is low (dark), the signal processing circuit 108 only needs to select the third image data having a long exposure time and a high gain. For example, in a case where the illuminance of the irradiation light is high (bright), the signal processing circuit 108 only needs to select the second image data having a short exposure time and a low gain.

[0189] As described above, in Modification 2, by the combination of the exposure time and the input capacitance gain, the dynamic range of the pixel signal detectable by the solid-state imaging device 100 is widened.

[0190] (Modification 3)

[0191] Figure 14 is a timing chart showing an operation example of the solid-state imaging device 100 according to Modification 3. Figure 15 is a table showing a combination of the reference signal and the input capacitance gain according to Modification 3.

[0192] In the above-described embodiment, although the voltage level of the reference signal RAMP is linearly increased or decreased with approximately equal slopes, the slope of the reference signal RAMP can be switched. For example, Figure 14 is shownFigure 10 The reference signal RAMP is from t9 to t10. The reference signal RAMPa decreases linearly with a relatively small ramp, while the reference signal RAMPb decreases linearly with a relatively large ramp.

[0193] Reference signals RAMPa and RAMPb are switched in DAC 104. Low-intensity illumination light where the voltage level of pixel signal VSL is higher than a threshold can be detected with high sensitivity using reference signal RAMPa. On the other hand, high-intensity illumination light where the voltage level of pixel signal VSL is lower than a threshold can be detected with reference signal RAMPb in a relatively short time (with low power consumption).

[0194] like Figure 15 As shown, in Modification 3, the reference signals RAMPa and RAMPb are combined with the input capacitance gains Ga and Gb according to this embodiment. That is, ADC groups 105a and 105b use either the reference signal RAMPa or RAMPb to detect the pixel signal VSL with input capacitance gains Ga and Gb. Therefore, in Modification 3, similar to Modification 2, a total of four types of first to fourth image data are obtained. Specifically, the first image data is obtained by detecting the pixel signal VSL using the reference signal RAMPa with a relatively low input capacitance gain Ga. The second image data is obtained by detecting the pixel signal VSL using the reference signal RAMPb with a relatively low input capacitance gain Ga. The third image data is obtained by detecting the pixel signal VSL using the reference signal RAMPa with a relatively high input capacitance gain Gb. The fourth image data is obtained by detecting the pixel signal VSL using the reference signal RAMPb with a relatively high input capacitance gain Gb.

[0195] The signal processing circuit 108 selects appropriate image data from these four image data sets, or combines multiple image data sets from the four image data sets to generate a single image data set. For example, in cases of low (dark) illumination, the signal processing circuit 108 only needs to use a reference signal RAMPa with a small slope to select the third image data set detected with high gain Gb. Conversely, in cases of high (bright) illumination, the signal processing circuit 108 only needs to use a reference signal RAMPb with a large slope to select the second image data set detected with low gain Ga.

[0196] As described above, in Modification 3, the dynamic range of the pixel signal that can be detected by the solid-state imaging element 100 is widened by combining the reference signal and the input capacitor gain.

[0197] The modified examples 1 to 3 can be applied to any one of the first to fifth embodiments. Further, the modified examples 1 to 3 can be combined with each other. For example, by combining the modified examples 2 and 3, the dynamic range of the pixel signal detectable by the solid-state imaging device 100 can be further widened by the combination of the exposure time, the reference signal, and the input capacitance gain.

[0198] (Fifth Embodiment)

[0199] Figure 16 is a block diagram showing a configuration example of the solid-state imaging device 100 according to the fifth embodiment. Figure 17 is a block diagram showing a configuration example of the ADC groups 105a and 105b according to the fifth embodiment. The solid-state imaging device 100 according to the fifth embodiment switches or controls the gain of the ADC groups 105a and 105b according to the illuminance of the irradiated light. For this purpose, the solid-state imaging device 100 further includes a controller 130 and a register 140.

[0200] Before imaging, the signal processing circuit 108 detects the illuminance of the incident light irradiated to the pixel section 101 based on the pixel signal supplied from the amplifier circuit 107. The signal processing circuit 108 acquires the illuminance by using all or part of the pixel signals of the pixel section 101. Since the illuminance does not require a high resolution as the image data, it is not necessary to perform CDS, and the slope of the reference signal RAMP can be steep. Thus, the illuminance can be detected in a short time. The signal processing circuit 108 can calculate the illuminance data based on a statistical value (e.g., average, median, mode) of the pixel signals from predetermined pixels. The statistical value can be interpolated by any linear or nonlinear operation. Note that the illuminance detection and calculation can be performed outside the solid-state imaging device 100.

[0201] The controller 130 obtains the illuminance data from the signal processing circuit 108, and changes the settings of the DAC 104 and / or the capacitor sections 120a and 120b based on the setting data from the register 140. For example, in a case where the illuminance is lower than a threshold value, the controller 130 increases the capacitances of the input capacitance elements Cvsla and Cvslb of the capacitor sections 120a and 120b to increase the input capacitance gain. In a case where the illuminance is equal to or greater than the threshold value, the controller 130 reduces the capacitances of the input capacitance elements Cvsla and Cvslb of the capacitor sections 120a and 120b, and reduces the input capacitance gain. Note that the controller 130 and the register 140 can be provided inside or outside the solid-state imaging device 100.

[0202] Figure 18is a diagram illustrating a configuration example of the input capacitance elements Cvsla and Cvslb. The input capacitance elements Cvsla and Cvslb are variable capacitance elements including a plurality of capacitance elements Ce connected in parallel via switches SWc1 and SWc2. The SW control signal from the controller 130 controls the switches SWc1 and SWc2 to be turned on or off to control the number of the capacitance elements Ce connected in parallel. As a result, the capacitance of the input capacitance elements Cvsla and Cvslb can be changed. Note that the number of the switches SWc1 and SWc2 and the number of the capacitance elements Ce are not particularly limited. Furthermore, Figure 18 The configuration example of the input capacitance elements Crmpa and Crmpb can be applied.

[0203] Referring again to Figure 17 The register 140 stores the threshold value of the illuminance in advance and transmits the threshold value to the controller 130 as setting data. The register 140 can store a plurality of threshold values. As a result, the controller 130 can control the plurality of switches SWc1 and SWc2 in the Figure 18 For example, in a case where the illuminance is lower than a first threshold value, the controller 130 can turn on the switch SWc1, and when the illuminance is further lower than a second threshold value (< the first threshold value), the controller 130 can further turn on the switch SWc2.

[0204] After the controller 130 sets the input capacitance gain of the capacitor sections 120a and 120b, the pixel section 101 performs imaging with the set input capacitance gain, and the signal processing circuit 108 converts the pixel signal and outputs the image data.

[0205] Figure 19 is a flowchart illustrating the operation of the solid-state imaging device 100 according to the fifth embodiment. The solid-state imaging device 100 measures the illuminance of the incident light to the pixel section 101 for each frame, and then performs imaging.

[0206] In the imaging of a certain frame, first, the vertical scanning circuit 103 sets the read row of the pixel section 101 (S100). Next, the pixel signal is output based on the incident light detected by the pixel row of the pixel section 101 (S110). Next, the ADC groups 105a and 105b perform AD conversion on the pixel signal (S120). Next, the latching circuit 123 outputs the AD-converted illuminance data to the signal processing circuit 108 (S130). Steps S100 to S130 are performed until the last row of the pixel section 101 (NO in S140).

[0207] When the signal processing circuit 108 acquires the luminance data up to the last row of the pixel section 101 (Yes in S140), the signal processing circuit 108 generates the luminance data of the entire frame (S150), and outputs the luminance data to the controller 130 (S160). Next, based on the setting data from the register 140, the controller 130 determines the luminance, and sets and outputs the SW control signal or the DAC control signal corresponding to the luminance for each pixel row. The input capacitance gain of the capacitor sections 120a and 120b is controlled by the SW control signal. Alternatively, the slope of the reference signal RAMP from the DAC 104 is controlled by the DAC control signal.

[0208] Next, the solid-state imaging element 100 starts imaging of the frame.

[0209] Steps S180 to S220 are similar to steps S100 to S140.

[0210] Next, the signal processing circuit 108 generates the image data of the entire frame (S230), and outputs the image data to the outside of the solid-state imaging element 100 (S240). As a result, the image data can be generated with an appropriate input capacitance gain or reference signal RAMP according to the luminance of the irradiation light.

[0211] As described above, by repeating the luminance measurement and imaging for each frame, the solid-state imaging element 100 can perform imaging with the optimum gain for each frame. The luminance measurement does not necessarily have to be performed in each frame, and for example, can be performed once every several frames.

[0212] In a case where the measurement and imaging of the luminance are performed using the pixel section 101, the controller 130 can switch the input capacitance gain of the capacitor sections 120a and 120b between a measurement mode for measuring the luminance and an imaging mode for imaging an image. For example, in the measurement mode, since it is enough to detect the pixel signal with low sensitivity in a short time, the controller 130 can reduce the input capacitance gain. Alternatively, in the measurement mode, the signal processing circuit 108 can select the output signal OUTa obtained using the low gain.

[0213] The controller 130 can control the DAC 104 together with or instead of the switches SWc1 and SWc2. For example, the controller 130 changes the slope of the reference signal RAMP by the DAC control signal. As a result, the slope of the reference signal RAMP can be changed according to the luminance of the irradiation light, and the same operation as the above-described modification example 3 can be performed.

[0214] Furthermore, in the first to fourth embodiments, the signal processing circuit 108 selects output signals OUTa and OUTb. In this case, the signal processing circuit 108 can select output signals OUTa and OUTb based on the detected illuminance.

[0215] The technology according to the present invention (the technology) can be applied to a variety of products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, autonomous two-wheelers, bicycles, personal motor vehicles, airplanes, unmanned aerial vehicles, ships, robots, etc.

[0216] Figure 20 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present invention can be applied.

[0217] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 20 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional structure of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0218] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for various devices such as: drive force generating devices for generating vehicle driving force, such as internal combustion engines and drive motors; drive force transmission mechanisms for transmitting driving force to the wheels; steering mechanisms for adjusting the vehicle's steering angle; and braking devices for generating vehicle braking force.

[0219] The vehicle body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the vehicle body system control unit 12020 functions as a control device for various devices such as: keyless entry system; smart key system; power windows; or various lights such as headlights, reversing lights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from a portable device that replaces the key can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0220] The vehicle exterior information detection unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031. The vehicle exterior information detection unit 12030 causes the imaging section 12031 to take an image of the outside of the vehicle, and receives the taken image. Based on the received image, the vehicle exterior information detection unit 12030 can execute processing of detecting an object such as a person, a vehicle, an obstacle, a sign, a character on a road surface, or processing of detecting a distance thereto. The solid-state imaging device 100 according to the present application can be provided in the imaging section 12031.

[0221] The imaging section 12031 is an optical sensor that receives light, and outputs an electrical signal corresponding to the light quantity of the received light. The imaging section 12031 can output the electrical signal as an image, or can output the electrical signal as ranging information. In addition, the light received by the imaging section 12031 can be visible light or can be non-visible light such as infrared rays. The solid-state imaging device 100 according to the present application can be the imaging section 12031, or can be separately provided from the imaging section 12031.

[0222] The vehicle interior information detection unit 12040 detects information about the inside of the vehicle. For example, the vehicle interior information detection unit 12040 is connected with a driver state detection section 12041 that detects the state of the driver. For example, the driver state detection section 12041 includes a camera that images the driver. Based on the detection information input from the driver state detection section 12041, the vehicle interior information detection unit 12040 can calculate the degree of fatigue of the driver or the degree of concentration of the driver, or can determine whether the driver is dozing off.

[0223] Based on the information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate a control target value of a driving force generation device, a steering mechanism, or a braking device, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can execute coordinated control for realizing functions of an advanced driver assistance system (ADAS: advanced driver assistance system) including vehicle collision avoidance or impact mitigation, following travel based on an inter-vehicle distance, vehicle constant speed travel, vehicle collision warning, vehicle lane departure warning, and the like.

[0224] In addition, based on information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform coordinated control aimed at enabling the vehicle to autonomously travel without the operation of the driver by controlling the driving force generation device, the steering mechanism, the brake device, and the like.

[0225] In addition, based on information about the vehicle exterior acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlamp to switch from high beam to low beam, for example.

[0226] The sound / image output section 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or aurally notifying information to the vehicle occupant or outside the vehicle. As the output device, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are shown. The display section 12062 can include at least one of an on-board display and a head-up display, for example.

[0227] Figure 21 FIG. 1 is a view showing an example of the arrangement position of the imaging section 12031.

[0228] In Figure 21 , the vehicle 12100 includes imaging sections 12101, 12102, 12103, 12104, and 12105 as the imaging section 12031.

[0229] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided at positions of the front nose, the side mirror, the rear bumper, and the trunk door of the vehicle 12100, and a position of the upper portion of the windshield inside the cabin, for example. The imaging section 12101 provided at the front nose and the imaging section 12105 provided at the upper portion of the windshield inside the cabin mainly acquire images of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided at the side mirror mainly acquire images of the side of the vehicle 12100. The imaging section 12104 provided at the rear bumper or the trunk door mainly acquires images of the rear of the vehicle 12100. The front images acquired by the imaging sections 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal lamp, a traffic sign, a lane, and the like.

[0230] Incidentally, Figure 21Examples of the imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging section 12101 provided to the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging sections 12102 and 12103 provided to the side mirrors. The imaging range 12114 indicates the imaging range of the imaging section 12104 provided to the rear bumper or the trunk door. For example, by superimposing the image data taken by the imaging sections 12101 to 12104, an overhead view image of the vehicle 12100 viewed from above is obtained.

[0231] At least one of the imaging sections 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera constituted by a plurality of imaging devices, or can be an imaging device having phase difference detection pixels.

[0232] For example, based on the distance information obtained by the imaging sections 12101 to 12104, the microcomputer 12051 can determine the distance to each of the three-dimensional objects within the imaging ranges 12111 to 12114 and the change in the distance over time (relative speed with respect to the vehicle 12100), and thereby extract, as the preceding vehicle, the closest three-dimensional object that is present on the travel path of the vehicle 12100 and is traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). Further, the microcomputer 12051 can pre-set the inter-vehicle distance to be ensured in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, it is possible to perform coordinated control aimed at enabling the vehicle to autonomously travel without the need for the operation of the driver.

[0233] For example, based on distance information obtained by the imaging sections 12101 to 12104, the microcomputer 12051 can classify three-dimensional object data of a three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a normal automobile, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be visually recognized by a driver of the vehicle 12100 and obstacles that cannot be visually recognized by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk for indicating a risk of collision with each obstacle. In a case where the collision risk is equal to or greater than a set value and there is a possibility of collision, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the drive system control unit 12010. The microcomputer 12051 can thus assist in avoiding collision driving.

[0234] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in an image captured by the imaging sections 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a process of extracting feature points from an image captured by the imaging sections 12101 to 12104 as infrared cameras, and a process of determining whether an object is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian is present in an image captured by the imaging sections 12101 to 12104 and thereby recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 to display a square outline for emphasis superimposed on the recognized pedestrian. The sound / image output section 12052 can control the display section 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0235] As described above, the technology according to the present disclosure can be applied to, for example, the outside information detection unit 12030. Specifically, the above-described imaging section 12031 can be mounted on the outside information detection unit 12030. By applying the technology according to the present disclosure to the imaging section 12031, accurate distance information can be obtained in an environment with a wide luminance dynamic range, and the functionality and safety of the vehicle 12100 can be improved.

[0236] Note that the present technology can have the technical solutions described below.

[0237] (1) A solid-state imaging element including:

[0238] a pixel section including a plurality of pixels;

[0239] a pixel signal line that transmits a pixel signal of the pixel;

[0240] a reference signal line that transmits a reference signal to be compared with the pixel signal;

[0241] a first comparator that outputs a first output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal;

[0242] a second comparator that outputs a second output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal;

[0243] a first capacitor section that is provided between the pixel signal line or the reference signal line and the first comparator and is set to a first gain; and

[0244] a second capacitor section that is provided between the pixel signal line or the reference signal line and the second comparator and is set to a second gain.

[0245] (2) The solid-state imaging device according to (1), wherein

[0246] the first capacitor section includes a first input capacitance element provided between the reference signal line and the first comparator and a second input capacitance element provided between the pixel signal line and the first comparator, and

[0247] the second capacitor section includes a third input capacitance element provided between the reference signal line and the second comparator and a fourth input capacitance element provided between the pixel signal line and the second comparator.

[0248] (3) The solid-state imaging device according to (2), wherein

[0249] a capacitance ratio between the first input capacitance element and the second input capacitance element is different from a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

[0250] (4) The solid-state imaging device according to (2) or (3), wherein

[0251] a capacitance of the first input capacitance element and a capacitance of the third input capacitance element are substantially equal, and a capacitance of the second input capacitance element and a capacitance of the fourth input capacitance element are different from each other.

[0252] (5) The solid-state imaging device according to (3) or (4), wherein

[0253] a gain of the first capacitor section is determined by a capacitance ratio between the first input capacitance element and the second input capacitance element, and

[0254] a gain of the second capacitor section is determined by a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

[0255] (6) The solid-state imaging element according to any one of (2) to (5), wherein

[0256] one end of each of the first input capacitance element and the third input capacitance element is commonly connected to the reference signal line,

[0257] one end of each of the second input capacitance element and the fourth input capacitance element is commonly connected to the pixel signal line,

[0258] the first comparator includes a first transistor whose gate is commonly connected to the other end of the first input capacitance element and the other end of the second input capacitance element, and

[0259] the second comparator includes a second transistor whose gate is commonly connected to the other end of the third input capacitance element and the other end of the fourth input capacitance element.

[0260] (7) The solid-state imaging element according to (6), wherein

[0261] the first comparator further includes a first constant current source connected to one end of the first transistor, and the first comparator outputs the first output signal from between the first transistor and the first constant current source, and

[0262] the second comparator further includes a second constant current source connected to one end of the second transistor, and the second comparator outputs a second output signal from between the second transistor and the second constant current source.

[0263] (8) The solid-state imaging element according to (6), wherein

[0264] the first comparator further includes a first constant current source connected to one end of the first transistor, a third transistor whose one end is connected to the first constant current source, and a first mirror circuit connected to the other end of the first transistor and the other end of the third transistor, and the first comparator outputs the first output signal from between the third transistor and the first mirror circuit, and

[0265] The second comparator further includes a second constant current source connected to one end of the second transistor, a fourth transistor connected to the second constant current source at one end, and a second mirror circuit connected to the other end of the second transistor and the other end of the fourth transistor, and the second comparator outputs the second output signal from between the fourth transistor and the second mirror circuit.

[0266] (9) The solid-state imaging device according to (2), wherein

[0267] The first comparator further includes the first transistor having a gate connected to the first input capacitive element and one end connected to the second input capacitive element, and

[0268] The second comparator further includes the second transistor having a gate connected to the third input capacitive element and one end connected to the fourth input capacitive element.

[0269] (10) The solid-state imaging device according to (9), wherein

[0270] The first input capacitive element and the third input capacitive element are commonly connected to the reference signal line, and

[0271] One end of the first transistor and one end of the second transistor receive the pixel signal via the second input capacitive element and the fourth input capacitive element, respectively.

[0272] (11) The solid-state imaging device according to any one of (2) to (10), further comprising:

[0273] a reference signal generator that supplies the same reference signal to the first input capacitive element and the third input capacitive element.

[0274] (12) The solid-state imaging device according to any one of (1) to (10), further comprising:

[0275] a signal processing circuit that selects the first output signal or the second output signal according to an illuminance of an irradiation light toward the pixel portion, and outputs the selected signal as image data.

[0276] (13) The solid-state imaging device according to any one of (1) to (12), further comprising:

[0277] a controller that changes an exposure time of the pixel portion according to an illuminance of an irradiation light toward the pixel portion.

[0278] (14) The solid-state imaging device according to any one of (1) to (13), further comprising:

[0279] a controller that controls a slope of the reference signal in accordance with an illuminance of the irradiation light toward the pixel section.

[0280] (15) The solid-state imaging device according to any one of (1) to (14), further comprising:

[0281] a controller that controls the first gain or the second gain in accordance with an illuminance of the irradiation light toward the pixel section.

[0282] (16) The solid-state imaging device according to any one of (1) to (10), further comprising:

[0283] a signal processing circuit (108) that acquires an illuminance of the irradiation light toward the pixel section; and

[0284] a controller (130) that sets the first gain or the second gain in accordance with the illuminance,

[0285] wherein the pixel section performs imaging with the set first gain or second gain, thereby generating the pixel signal, and

[0286] the signal processing circuit converts the pixel signal to generate image data.

[0287] (17) The solid-state imaging device according to any one of (2) to (5), wherein

[0288] one end of each of the first input capacitance element and the third input capacitance element is commonly connected to the reference signal line,

[0289] one end of each of the second input capacitance element and the fourth input capacitance element is commonly connected to the pixel signal line,

[0290] the first comparator includes a first transistor and a third transistor, a gate of the first transistor is connected to the other end of the first input capacitance element, and a gate of the third transistor is connected to the other end of the second input capacitance element, and

[0291] the second comparator includes a second transistor and a fourth transistor, a gate of the second transistor is connected to the other end of the third input capacitance element, and a gate of the fourth transistor is connected to the other end of the fourth input capacitance element.

[0292] The present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present application. The effects described in this specification are merely examples and are not limiting, and other effects can be exerted.

[0293] List of Reference Signs

[0294] 101: pixel portion

[0295] 150: pixel

[0296] 105a, 105b: ADC group

[0297] 110: vertical signal line

[0298] 120a, 120b: capacitor portion

[0299] 121a, 121b: comparator

[0300] Crmpa, Cvsla, Crmpb, Cvslb: input capacitance element

[0301] Tp1a to Tp5a, Tp1b to Tp5b, Tn1a to Tn5a, Tn1b to Tn5b: transistor

Claims

1. A solid-state imaging device comprising: a pixel section including a plurality of pixels; a pixel signal line that transmits a pixel signal of the pixel; a reference signal line that transmits a reference signal to be compared with the pixel signal; a first comparator that outputs a first output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a second comparator that outputs a second output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a first capacitor section that is provided between the pixel signal line or the reference signal line and the first comparator and is set to a first gain; and a second capacitor section that is provided between the pixel signal line or the reference signal line and the second comparator and is set to a second gain, wherein the first capacitor section includes a first input capacitance element provided between the reference signal line and the first comparator and a second input capacitance element provided between the pixel signal line and the first comparator, the second capacitor section includes a third input capacitance element provided between the reference signal line and the second comparator and a fourth input capacitance element provided between the pixel signal line and the second comparator, one end of each of the first input capacitance element and the third input capacitance element is commonly connected to the reference signal line, one end of each of the second input capacitance element and the fourth input capacitance element is commonly connected to the pixel signal line, the first comparator includes a first transistor whose gate is commonly connected to the other end of the first input capacitance element and the other end of the second input capacitance element, and the second comparator includes a second transistor whose gate is commonly connected to the other end of the third input capacitance element and the other end of the fourth input capacitance element.

2. The solid-state imaging device according to claim 1, wherein a capacitance ratio between the first input capacitance element and the second input capacitance element is different from a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

3. The solid-state imaging device according to claim 1, wherein a capacitance of the first input capacitance element and a capacitance of the third input capacitance element are substantially equal, and a capacitance of the second input capacitance element and a capacitance of the fourth input capacitance element are different from each other.

4. The solid-state imaging device according to claim 2, wherein a gain of the first capacitor section is determined by a capacitance ratio between the first input capacitance element and the second input capacitance element, and a gain of the second capacitor section is determined by a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

5. The solid-state imaging device according to claim 1, wherein the first comparator further includes a first constant current source connected to one end of the first transistor, and the first comparator outputs the first output signal from between the first transistor and the first constant current source, and the second comparator further includes a second constant current source connected to one end of the second transistor, and the second comparator outputs the second output signal from between the second transistor and the second constant current source. The second comparator further includes a second constant current source connected to one end of the second transistor, and the second comparator outputs the second output signal from between the second transistor and the second constant current source.

6. The solid-state image pickup element according to claim 1, wherein The first comparator further includes a first constant current source connected to one end of the first transistor, a third transistor connected to the first constant current source at one end, and a first mirror circuit connected to the other end of the first transistor and the other end of the third transistor, and the first comparator outputs the first output signal from between the third transistor and the first mirror circuit, and The second comparator further includes a second constant current source connected to one end of the second transistor, a fourth transistor connected to the second constant current source at one end, and a second mirror circuit connected to the other end of the second transistor and the other end of the fourth transistor, and the second comparator outputs the second output signal from between the fourth transistor and the second mirror circuit.

7. The solid-state image pickup element according to any one of claims 1 to 6, further comprising: a reference signal generator that supplies the same reference signal to the first input capacitive element and the third input capacitive element.

8. The solid-state image pickup element according to any one of claims 1 to 6, further comprising: a signal processing circuit that selects the first output signal or the second output signal according to an illumination of incident light toward the pixel section, and outputs the selected signal as image data.

9. The solid-state image pickup element according to any one of claims 1 to 6, further comprising: a controller that changes an exposure time of the pixel section according to an illumination of incident light toward the pixel section.

10. The solid-state image pickup element according to any one of claims 1 to 6, further comprising: a controller that controls a slope of the reference signal according to an illumination of incident light toward the pixel section.

11. The solid-state image pickup element according to any one of claims 1 to 6, further comprising: a controller that controls the first gain or the second gain according to an illumination of incident light toward the pixel section.

12. The solid-state image pickup element according to any one of claims 1 to 6, further comprising: a signal processing circuit that acquires an illumination of incident light toward the pixel section; and a controller that sets the first gain or the second gain according to the illumination, wherein the pixel section performs image pickup with the set first gain or second gain, thereby generating the pixel signal, and the signal processing circuit converts the pixel signal to generate image data.

13. A solid-state image pickup element comprising: a pixel section including a plurality of pixels; a pixel signal line that transmits a pixel signal of the pixel; a reference signal line that transmits a reference signal to be compared with the pixel signal; a first comparator that outputs a first output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a second comparator that outputs a second output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; and a controller that sets the first gain or the second gain according to the illumination, wherein the pixel section performs image pickup with the set first gain or second gain, thereby generating the pixel signal, and the signal processing circuit converts the pixel signal to generate image data. a second comparator that outputs a second output signal corresponding to the pixel signal based on a voltage difference between the pixel signal and the reference signal; a first capacitor section that is provided between the pixel signal line or the reference signal line and the first comparator and that is set to a first gain; and a second capacitor section that is provided between the pixel signal line or the reference signal line and the second comparator and that is set to a second gain, wherein the first capacitor section includes a first input capacitance element provided between the reference signal line and the first comparator and a second input capacitance element provided between the pixel signal line and the first comparator, the second capacitor section includes a third input capacitance element provided between the reference signal line and the second comparator and a fourth input capacitance element provided between the pixel signal line and the second comparator, the first comparator further includes a first transistor whose gate is connected to one end of the first input capacitance element and one end of the second input capacitance element, and one end of which is connected to the pixel signal line, and the second comparator further includes a second transistor whose gate is connected to one end of the third input capacitance element and one end of the fourth input capacitance element, and one end of which is connected to the pixel signal line.

14. The solid-state imaging device according to claim 13, wherein a capacitance ratio between the first input capacitance element and the second input capacitance element is different from a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

15. The solid-state imaging device according to claim 13, wherein a capacitance of the first input capacitance element and a capacitance of the third input capacitance element are substantially equal, and a capacitance of the second input capacitance element and a capacitance of the fourth input capacitance element are different from each other.

16. The solid-state imaging device according to claim 14, wherein a gain of the first capacitor section is determined by a capacitance ratio between the first input capacitance element and the second input capacitance element, and a gain of the second capacitor section is determined by a capacitance ratio between the third input capacitance element and the fourth input capacitance element.

17. The solid-state imaging device according to claim 13, wherein the other end of the first input capacitance element and the other end of the third input capacitance element are commonly connected to the reference signal line, the other end of the second input capacitance element and the other end of the fourth input capacitance element are grounded, and one end of the first transistor and one end of the second transistor receive the same pixel signal from the pixel signal line.

18. The solid-state imaging device according to any one of claims 13 to 17, further comprising: a reference signal generator that supplies the same reference signal to the first input capacitance element and the third input capacitance element. ​ 19. The solid-state image pickup element according to any one of claims 13 to 17, further comprising: a signal processing circuit that selects the first output signal or the second output signal in accordance with an illuminance of an irradiation light toward the pixel section, and outputs the selected signal as image data.

20. The solid-state image pickup element according to any one of claims 13 to 17, further comprising: a controller that changes an exposure time of the pixel section in accordance with an illuminance of an irradiation light toward the pixel section.

21. The solid-state image pickup element according to any one of claims 13 to 17, further comprising: a controller that controls a slope of the reference signal in accordance with an illuminance of an irradiation light toward the pixel section.

22. The solid-state image pickup element according to any one of claims 13 to 17, further comprising: a controller that controls the first gain or the second gain in accordance with an illuminance of an irradiation light toward the pixel section.

23. The solid-state image pickup element according to any one of claims 13 to 17, further comprising: a signal processing circuit that acquires an illuminance of an irradiation light toward the pixel section; and a controller that sets the first gain or the second gain in accordance with the illuminance, wherein the pixel section performs image pickup with the set first gain or second gain, thereby generating the pixel signal, and the signal processing circuit converts the pixel signal to generate image data. ​

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