Capacitance measurement system, measurement circuit and computing device

Abstract

The application provides a capacitance measurement system, comprising an AC power supply, a measurement circuit and a computing device. The measurement circuit comprises a circuit input end, a circuit output end, an operational amplifier and a switch, wherein the circuit input end is electrically connected with the AC power supply, and the switch is electrically connected with a capacitance to be measured. The computing device is electrically connected with the circuit output end. When the switch is off, the measurement circuit outputs at least one output signal, and when the switch is on, the measurement circuit outputs another output signal. The computing device calculates a first amplification gain and a second amplification gain of the operational amplifier according to the output signals output by the measurement circuit, and calculates a capacitance value of the capacitance to be measured according to the first amplification gain and the second amplification gain.

Description

TECHNICAL FIELD

[0001] The present application relates to a measurement system, a measurement circuit and a computing device, in particular, to a capacitance measurement system, a measurement circuit and a computing device capable of measuring a capacitance value. BACKGROUND

[0002] Before performing electrical property tests on some products (for example, wafer tests), the capacitance to be used may need to be measured to avoid affecting the electrical property tests. The current method of measuring capacitance is to charge and discharge the capacitance to be measured by providing a current from a power supply, and to estimate the capacitance value of the capacitance to be measured according to the charging and discharging time. However, this measurement method not only requires a long measurement time, but also causes measurement errors during the charging and discharging of the capacitance, because the measurement environment (for example, a measurement machine or a measurement instrument) usually generates a parasitic capacitance. If the parasitic capacitance is to be eliminated, the capacitance value of the parasitic capacitance must be calculated first, but the capacitance value of the parasitic capacitance must be calculated by adjusting a large number of measurement parameters, which increases the time cost and may also cause measurement errors.

[0003] In addition, the current technology has limitations in accurately measuring capacitance values, for example, the current measurement machine can only support the measurement of capacitance values above the nanofarad (nF) level (for example, a capacitance value greater than or equal to 1 nF). If the capacitance value of the picofarad (pF) level (for example, a capacitance value less than 1.0 nF) is directly measured, a large error will be generated, which does not meet the requirements.

[0004] Therefore, the present application provides a capacitance measurement system, a measurement circuit and a computing device to solve the above problems. SUMMARY

[0005] One object of the present application is to provide a capacitance measurement system, comprising an alternating current power supply, a measurement circuit and a computing device. The measurement circuit comprises a circuit input end electrically connected to the alternating current power supply, a circuit output end electrically connected to the computing device, an operational amplifier and a switch. The switch is electrically connected to the capacitance to be measured. When the switch is open, the measurement circuit outputs at least one output signal, and when the switch is closed, the measurement circuit outputs another output signal. The computing device calculates a first amplification gain and a second amplification gain of the operational amplifier according to all the output signals output by the measurement circuit, and calculates the capacitance value of the capacitance to be measured according to the first amplification gain and the second amplification gain.

[0006] Another object of the present application is to provide a measuring circuit, which is arranged in the aforementioned capacitive measuring system and comprises a circuit input end electrically connected with the AC power supply of the capacitive measuring system, a circuit output end electrically connected with the computing device of the capacitive measuring system, an operational amplifier and at least one switch electrically connected with the operational amplifier, wherein the AC power supply is electrically connected with the operational amplifier through the circuit input end, and the at least one switch is electrically connected with the capacitive to be measured.

[0007] Still another object of the present application is to provide a computing device, which is arranged in the aforementioned capacitive measuring system and is electrically connected with the circuit output end of the measuring circuit of the capacitive measuring system. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic diagram of the architecture of the capacitive measuring system of an embodiment of the present application;

[0009] Figure 2 is a detailed circuit diagram of the measuring circuit of the first embodiment of the present application;

[0010] Figure 3 is a flow chart of the operation of the computing device of an embodiment of the present application;

[0011] Figure 4 is a diagram of the experimental data results of an embodiment of the present application;

[0012] Figure 5 is a circuit diagram of the measuring circuit of the second embodiment of the present application;

[0013] Figure 6 is a circuit diagram of the measuring circuit of the third embodiment of the present application;

[0014] Figure 7 is a diagram of the experimental data of the frequency modulation of the input signal of an embodiment of the present application;

[0015] Figure 8 is a diagram of the experimental data of the suitable frequency corresponding to the capacitive to be measured of an embodiment of the present application.

[0016] REFERENCE SIGNS

[0017] 1 - capacitive measuring system

[0018] 10 - measuring circuit

[0019] IN - circuit input end

[0020] OUT - circuit output end

[0021] 11-13 - switches (11 - first switch, 12 - second switch, 13 - third switch)

[0022] 14 - operational amplifier

[0023] 20 - computing device

[0024] 30 - AC power source

[0025] 40 - capacitor to be measured

[0026] 11a - first end of first switch

[0027] 11b - second end of first switch

[0028] 12a - first end of second switch

[0029] 12b - second end of second switch

[0030] 13a - first end of third switch

[0031] 13b - second end of third switch

[0032] 14a - first input

[0033] 14b - second input

[0034] 14c - output

[0035] 15 - rectifier

[0036] 16 - first resistor

[0037] 17 - second resistor

[0038] A - node

[0039] B - node

[0040] S31-S37 - steps 18 - fourth switch

[0041] 19 - fifth switch

[0042] 50 - reference capacitor

[0043] Vo1 - potential of first output signal

[0044] Vo2 - potential of second output signal

[0045] Vo3 - potential of third output signal

[0046] Av1 - first amplification gain

[0047] Av2 - second amplification gain

[0048] Xc - reactance value

[0049] Freq - frequency

[0050] C2 - measured value

[0051] C1-target value DETAILED DESCRIPTION

[0052] The operation principles and implementation states of the capacitive measurement system, the measurement circuit and the computing device of the present application will be illustrated by the following embodiments. Those skilled in the art of the present application can understand the features and effects of the present application through the above embodiments, and can make combinations, modifications, substitutions or adaptations based on the spirit of the present application.

[0053] It should be noted that, in this document, a "group of components" is not limited to a single component unless specifically indicated, but can also refer to one or more components.

[0054] In addition, the descriptions such as "when" or "when" in the present disclosure represent the state of "now, before or after" and are not limited to the case of simultaneous occurrence, which is indicated by the previous description. The similar descriptions such as "disposed on" in the present disclosure represent the corresponding positional relationship between the two components, and are not limited to whether the two components are in contact with each other, unless specifically limited, which is indicated by the previous description. Furthermore, when the word "or" is used between the effects in the present disclosure, it means that the effects can exist independently, but it does not exclude the possibility that multiple effects can exist at the same time.

[0055] The ordinal numbers used in this document, such as "first", "second", etc., are used to modify the requested components, and do not inherently mean and represent any previous ordinal number of the requested components, nor represent the order of one requested component and another requested component, or the order of the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a requested component with a certain name from another requested component with the same name.

[0056] In addition, the words such as "connection" or "coupling" in the specification and claims not only mean direct connection with another component, but also mean indirect connection or electrical connection with another component. In addition, electrical connection includes direct connection, indirect connection or the state of wireless signal exchange between two components.

[0057] In addition, the words "about", "approximately", "substantially", "generally" in the specification and claims generally mean that the difference between a value and a given value is within the range of 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of the given value. The given number is an approximate number, that is, without specific indication of "about", "approximately", "substantially", "generally", the meaning of "about", "approximately", "substantially", "generally" is still implied. In addition, the words "range from a first numerical value to a second numerical value" or "range between a first numerical value and a second numerical value" mean that the range includes the first numerical value, the second numerical value and other numerical values between them.

[0058] Furthermore, the components can be implemented in a single circuit or an integrated circuit as appropriate, and can include one or more active or passive components, such as transistors, logic gates, resistors, capacitors, or inductors, but are not limited thereto. The components can be connected to each other as appropriate, for example, to form a series or parallel connection, using one or more wires, and can be connected to each other in a way that allows input signals and output signals to pass through in sequence or in parallel. The above-described configurations are determined according to the application.

[0059] Furthermore, the technical features of different embodiments disclosed herein can be combined to form another embodiment.

[0060] Furthermore, in this document, the terms "system," "device," "apparatus," "module," or "unit" refer to an electronic component or a digital circuit, an analog circuit, or other more general circuit composed of a plurality of electronic components, and unless otherwise specified, they do not necessarily have a hierarchical or layered relationship.

[0061] Figure 1 is a schematic diagram of the basic architecture of a capacitance measurement system 1 according to an embodiment of the present application. As shown in Figure 1 The capacitance measurement system 1 includes a measurement circuit 10, a computing device 20, and an AC power supply 30. The measurement circuit 10 can include a circuit input terminal IN, a circuit output terminal OUT, an operational amplifier 14, and a plurality of switches 11-13 (hereinafter referred to as first to third switches 11-13), and one of the switches (e.g., the third switch 13) is electrically connected to a capacitance to be measured 40. The circuit input terminal IN is electrically connected to the AC power supply 30. The circuit output terminal OUT is electrically connected to the computing device 20. The computing device 20 can perform calculations based on the output results of the circuit output terminal OUT and can output the capacitance value of the capacitance to be measured 40.

[0062] The AC power supply 30 can provide an input signal Vin to the measurement circuit 10. The measurement circuit 10 can output different output signals Vo to the computing device 20 at different time points by switching at least one of the switches 11-13, for example, when at least one of the switches 11-13 (e.g., the third switch 13) is turned off, the measurement circuit 10 can output at least one output signal Vo to the computing device 20, and the computing device 20 can calculate a first amplification gain of the operational amplifier 14 based on the at least one output signal Vo; when at least one of the switches 11-13 (e.g., the first switch 11) is turned on, the measurement circuit 10 can output at least one output signal Vo to the computing device 20, and the computing device 20 can calculate a second amplification gain of the operational amplifier 14 based on the at least one output signal Vo. Figure 2 Figure 2 ​When the third switch 13 is turned on, the measurement circuit 10 can output another output signal to the computing device 20, and the computing device 20 can calculate a second amplification gain of the operational amplifier 14 according to the at least one output signal Vo previously obtained and the output signal Vo currently obtained, and further calculate the capacitance value of the capacitor 40 under test according to the first amplification gain and the second amplification gain. In this way, the present application can measure the capacitance value of the capacitor 40 under test.

[0063] The details of each component will be described next.

[0064] The details of the AC power source 30 will be described first.

[0065] The AC power source 30 can provide an input signal Vin to the circuit input end IN of the measurement circuit 10. In an embodiment, the AC power source 30 can be, for example, an arbitrary waveform generator (AWG) that can provide signals of waveforms such as sine waves, square waves, triangular waves, and the like, and is not limited thereto; for the convenience of description, the following will be exemplified with the AC power source 30 providing a sine wave. In addition, in an embodiment, the frequency of the signal generated by the AC power source 30 can be modulated, and is not limited thereto.

[0066] The details of the computing device 20 will be described next.

[0067] In an embodiment, the computing device 20 can be, for example, a processor that includes a computer program product or hardware stored on a non-transitory computer readable medium to perform specific computing functions. In an embodiment, the computing device 20 can be disposed in a measurement machine (not shown in the figure) or can be disposed in a computer (not shown in the figure), and is not limited thereto. In an embodiment, the computing device 20 can also be an integrated circuit with computing functions that can be loaded with special hardware or software to achieve computing functions. It should be noted that the form of the computing device 20 is not limited thereto.

[0068] The details of the measurement circuit 10 will be described next.

[0069] The measurement circuit 10 can output different output signals Vo to the computing device 20 through switching of, for example, the switches 11-13. Figure 2 is a detailed circuit diagram of the measurement circuit 10 of the first embodiment of the present application, and please refer to Figure 1 .

[0070] As Figure 2As shown, the measurement circuit 10 can include a circuit input IN, a circuit output OUT, a first switch 11, a second switch 12, a third switch 13, an operational amplifier 14, a rectifier 15, a first resistor 16, and a second resistor 17. The first switch 11 can include a first terminal 11a and a second terminal 11b. The second switch 12 can include a first terminal 12a and a second terminal 12b. The third switch 13 can include a first terminal 13a and a second terminal 13b, wherein the second terminal 13b of the third switch 13 can be electrically connected to the capacitor under test 40. The operational amplifier 14 can include a first input 14a, a second input 14b, and an output 14c.

[0071] The first switch 11 can be disposed between the circuit input IN and the circuit output OUT, for example, the first terminal 11a of the first switch 11 can be electrically connected to the circuit input IN, and the second terminal 11b of the first switch 11 can be electrically connected to the anode terminal of the rectifier 15, and through the rectifier 15 to the circuit output OUT.

[0072] The operational amplifier 14 and the second switch 12 can be disposed between the circuit input IN and the circuit output OUT, for example, the first input 14a of the operational amplifier 14 can be electrically connected to the circuit input IN, the output 14c of the operational amplifier 14 can be electrically connected to the first terminal 12a of the second switch 12, and the second terminal 12b of the second switch 12 can be electrically connected to the anode terminal of the rectifier 15, and through the rectifier 15 to the circuit output OUT. In addition, the output 14c of the operational amplifier 14 can also be electrically connected to the first resistor 16, for example, the output 14c, the first terminal 12a of the second switch 12, and the first resistor 16 can be electrically connected at a node A of the measurement circuit 10. In addition, the second input 14b of the operational amplifier 14, the first resistor 16, the second resistor 17, and the third switch 13 can be electrically connected at a node B of the measurement circuit 10.

[0073] The first terminal 13a of the third switch 13 can be electrically connected to the second input 14b of the operational amplifier 14, the first resistor 16, and the second resistor 17 at the node B, and the second terminal 13b of the third switch 13 can be electrically connected to the capacitor under test 40.

[0074] In an embodiment, the AC power source 30 can be electrically connected to the first terminal 11a of the first switch 11 and the first input 14a of the operational amplifier 14 via the circuit input IN, respectively, thus, the input signal Vin provided by the AC power source 30 can enter the signal path where the first switch 11 is located or the signal path where the operational amplifier 14 is located.

[0075] In an embodiment, the first switch 11, the second switch 12, and the third switch 13 can be, for example, a relay, a switch, or a multiplexer, and are not limited thereto. In an embodiment, the aforementioned switches 11, 12, and 13 can be, for example, a mechanical switch or an electronic switch, and are not limited thereto. In an embodiment, the aforementioned switches 11, 12, and 13 can include a transistor, or be a transistor per se, but are not limited thereto. In an embodiment, the first switch 11, the second switch 12, or the third switch 13 can be controlled by an external control component (for example, but not limited to, a timing controller or other mechanical controller, not shown in the figure), and present an on or off state, and are not limited thereto.

[0076] In an embodiment, the operational amplifier 14 can be, for example, a non-inverting amplifier, in which the first input terminal 14a can be a positive input terminal, and the second input terminal 14b can be a negative input terminal, and are not limited thereto.

[0077] In an embodiment, the rectifier 15 can be, for example, a diode, or an integrated circuit including a diode, in which the anode of the diode can be electrically connected to the first switch 11 and the second switch 12 respectively, and the cathode of the diode can be electrically connected to the circuit output terminal OUT, and are not limited thereto.

[0078] The operation mode of the measurement circuit 10 and the computing device 20 will be described in detail.

[0079] In an embodiment, the first switch 11, the second switch 12, and the third switch 13 can be turned on at different time points, so that the input signal Vin can pass through different signal paths at different time points, and the circuit output terminal OUT can output different output signals Vo at different time points. In an embodiment, the on period of the first switch 11 does not overlap with the on period of the other switches 12 and 13. In an embodiment, the on period of the second switch 12 can partially overlap with the on period of the third switch 13.

[0080] In more detail, in an embodiment, during a first period, the first switch 11 can be turned on, and the second switch 12 and the third switch 13 can be turned off. At this time, the signal path in which the first switch 11 is located is in an on state, and the signal paths in which the second switch 12 and the third switch 13 are located are in an off state, so that the input signal Vin provided by the alternating current power supply 30 can pass through the first switch 11, and after being rectified by the rectifier 15, a first output signal is formed, and then the first output signal is output to the computing device 20 at the circuit output terminal OUT. Since there is no operational amplifier in the aforementioned signal path, the first output signal can be the same as or similar to the rectified input signal Vin, so that the first output signal can be regarded as a direct current signal after the input signal Vin is rectified.

[0081] In one embodiment, during a second period, the second switch 12 is turned on, while the first switch 11 and the third switch 13 are turned off. At this time, the signal path in which the second switch 12 is located is in an on state, while the signal paths in which the first switch 11 and the third switch 13 are located are in an off state, so the input signal Vin can pass through the operational amplifier 14 (the signal is thus amplified), the second switch 12 and the rectifier 15, and after being rectified by the rectifier 15, a second output signal is formed, and then the second output signal is output to the computing device 20 at the circuit output end OUT. Since the signal path has the operational amplifier 14, the second output signal can be regarded as a direct current signal obtained by amplifying and rectifying the input signal Vin.

[0082] At this time, the computing device 20 can calculate the gain of the operational amplifier 14 at the present time (i.e., the first amplification gain) by using the first output signal obtained previously and the second output signal obtained at the present time, wherein the first amplification gain can be expressed as equation (1):

[0083] Av1 = Vo2 / Vo1;... equation (1)

[0084] wherein Av1 is defined as the first amplification gain, Vo1 is defined as the potential of the first output signal, and Vo2 is defined as the potential of the second output signal.

[0085] In addition, according to the configuration of the operational amplifier 14, the first resistor 16 and the second resistor 17, it can be known that the first amplification gain (Av1) can also be expressed as equation (2):

[0086] Av1 = 1 + (R1 / R2);... equation (2)

[0087] wherein R1 is defined as the resistance value of the first resistor 16, and R2 is defined as the resistance value of the second resistor 17. It should be noted that R1 and R2 are default values, i.e., the resistance values of the first resistor 16 and the second resistor 17 are default values (i.e., known parameters).

[0088] In one embodiment, during a third period, the second switch 12 and the third switch 13 are turned on, while the first switch 11 is turned off. At this time, the signal path in which the second switch 12 and the third switch 13 are located is in an on state, while the signal path in which the first switch 11 is located is in an off state, so the input signal Vin passes through the operational amplifier 14 (the signal is thus amplified), the second switch 12, and the rectifier 15, and a third output signal is formed after the third output signal is rectified by the rectifier 15, and then the third output signal is output to the computing device 20 at the circuit output end OUT. Since the signal path has the operational amplifier 14, the third output signal can be regarded as a direct current signal in which the input signal Vin is amplified and rectified, and since the third switch 13 is turned on, the amplification gain of the operational amplifier 14 is affected by the reactance value Xc of the capacitor under test 40, so the potential of the third output signal is not the same as that of the second output signal.

[0089] At this time, the computing device 20 can calculate the gain of the operational amplifier 14 at present (that is, the second amplification gain) by using the first output signal obtained previously and the third output signal obtained at present, and the second amplification gain can be expressed as equation (3):

[0090] Av2 = Vo3 / Vol;... equation (3)

[0091] wherein Av2 is defined as the second amplification gain, and Vo3 is defined as the potential of the third output signal.

[0092] In addition, according to the configuration of the operational amplifier 14 and the first resistor 16, the second resistor 17, and the capacitor under test 40, it can also be known that the second amplification gain can also be expressed as equation (4):

[0093] Av2 = 1 + [R1 / (R2 / / Xc)]

[0094] = 1 + [R1 / (R2*Xc) / (R2+Xc)]

[0095] = 1 + [(R1*R2+R1*Xc) / (R2*Xc)]

[0096] = 1 + (R1 / Xc) + (R1 / R2)

[0097] = (R1 / Xc) + Avl;... equation (4)

[0098] wherein Xc is defined as the reactance value of the capacitor under test 40, and R2 / / Xc is defined as the resistance value of the parallel connection of the second resistor 17 and the capacitor under test 40.

[0099] Further, in one embodiment, after the calculation module 20 calculates the first amplification gain and the second amplification gain by the equation (1) and the equation (3), the calculation module 20 can calculate the reactance value of the capacitor 40 under test according to the first amplification gain, the second amplification gain, the resistance value of the first resistor and the equation (4) (e.g. Xc = Rl / (Av2-Avl)). Alternatively, the reactance value of the capacitor 40 under test can also be expressed as the equation (5):

[0100] Xc = 1 / (2πfC); equation (5)

[0101] wherein π is the circular constant, f is the frequency of the input signal Vin (is a variable value which can be adjusted and is a known parameter), and C is the capacitance value. Therefore, after the calculation module 20 calculates the reactance value of the capacitor 40 under test, the capacitance value of the capacitor 40 under test can be calculated according to the equation (5).

[0102] Thus, the capacitance value of the capacitor 40 under test can be calculated by the calculation module 20.

[0103] For the sake of clarity, the operation process of the calculation device 20 will be summarized as follows. Figure 3 is the operation flowchart of the calculation device 20 of one embodiment of the present application, and please refer to Figure 1 and Figure 2 simultaneously.

[0104] As shown in Figure 3 , first, step S31 is performed, and the calculation device 20 acquires the first output signal output by the measurement circuit 10. Then, step S32 is performed, and the calculation device 20 acquires the second output signal output by the measurement circuit 10. Then, step S33 is performed, and the calculation device 20 calculates the first amplification gain of the operational amplifier 14 according to the first output signal and the second output signal (please refer to the equation (1)), wherein the first amplification gain can be regarded as the gain of the operational amplifier 14 when the capacitor 40 under test is not connected to the measurement circuit 10. Then, step S34 is performed, and the calculation device 20 acquires the third output signal output by the measurement circuit 10. Then, step S35 is performed, and the calculation device 20 calculates the second amplification gain of the operational amplifier 14 according to the first output signal and the third output signal (please refer to the equation (3)), wherein the second amplification gain can be regarded as the gain of the operational amplifier 14 when the capacitor 40 under test is connected to the measurement circuit 10. Then, step S36 is performed, and the calculation device 20 calculates the reactance value of the capacitor 40 under test according to the first amplification gain and the second amplification gain (please refer to the equation (4)). Then, step S37 is performed, and the calculation device 20 calculates the capacitance value of the capacitor 40 under test according to the reactance value of the capacitor 40 under test and the frequency of the input signal Vin (please refer to the equation (5)).

[0105] Thus, the operation flow of the calculation device 20 can be understood.

[0106] Figure 4 This is a schematic diagram of experimental data results according to an embodiment of the present invention, which shows the results obtained by... Figure 2 The capacitance measurement system 1 measures the capacitance values ​​(hereinafter referred to as measured values ​​C2) of multiple capacitors 40 to be tested. The actual capacitance values ​​of the capacitors 40 to be tested are known (hereinafter referred to as target values ​​C1). The comparison results between target values ​​C1 and measured values ​​C2 are obtained by the calculation device 20. Target values ​​C1 can be, for example, an actual capacitance value or a standard value tested by a standard laboratory. It has high accuracy and can be used as a basis for numerical comparison or reference. Where C1 represents the target capacitance value (in pF), C2 represents the measured capacitance value (in pF), Vo1 represents the potential of the first output signal (in volts, V), Vo2 represents the potential of the second output signal (in volts, V), Vo3 represents the potential of the third output signal (in volts, V), Av1 represents the first amplification gain, Av2 represents the second amplification gain, Freq represents the frequency of the input signal Vin (in hertz, Hz), and Xc represents the reactance of the capacitor under test 40 (in ohms).

[0107] Next Figure 2 The circuit architecture is matched with parameter settings, and references are made. Figure 4 The data will be used to further illustrate the actual calculation method of the present invention. Among them, Figure 2 The AC power supply 30 can be set to 0.2 (V), the first resistor 16 can be set to 25000 (ohm), and the second resistor 17 can be set to 5000 (ohm).

[0108] like Figure 4As shown, when the target value C1 of the capacitor under test 40 is 33 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 1091000 (Hz). When the first switch 11 is turned on and the rest of the switches are turned off, the first output signal Vo1 is detected by the computing device 20 to be 0.194 (V). When the second switch is turned on and the rest of the switches are turned off, the second output signal Vo2 is detected by the computing device 20 to be 1.19 (V). When the second switch 12 and the third switch 13 are turned on and the first switch 11 is turned off, the third output signal Vo3 is detected by the computing device 20 to be 2.292 (V). Then, the computing device 20 calculates the first amplification gain (i.e., Av1 = Vo2 / Vo1 = 1.19 / 0.194 = 6.134) according to equation (1), and the first amplification gain Av1 is about 6.134, and the computing device 20 calculates the second amplification gain (i.e., Av2 = Vo3 / Vo1 = 2.292 / 0.194 = 11.8144) according to equation (3), and the second amplification gain Av2 is about 11.814. Then, the computing device 20 calculates the reactance value Xc (i.e., Xc = R1 / (Av2-Av1) = 25000 / (11.814-6.134) = 4401.089) according to equation (4), and the reactance value Xc of the capacitor under test 40 is about 4401.089 (ohm). Then, the computing device 20 calculates the measured value C2 (i.e., C2 = 1 / (2πfXc) = 1 / (2π.1091000.4401.088929 = 33.163.10 -12 ), and the measured value C2 of the capacitor under test 40 is about 33.163 (pF). Accordingly, the error value between the target value C1 and the measured value C2 of the capacitor under test 40 (i.e., |(C1-C2)| / C1 = |(33.10-12-33.163.10-12)| / 33.10-12 = 0.00494) is about 0.494%.

[0109] When the target value C1 of the capacitor under test 40 is 305 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 329000 (Hz). When the first switch 11 is turned on and the other switches are turned off, the first output signal Vo1 is detected by the computing device 20 to be 0.194 (V). When the second switch is turned on and the other switches are turned off, the second output signal Vo2 is detected by the computing device 20 to be 1.19 (V). When the second switch 12 and the third switch 13 are turned on and the first switch 11 is turned off, the third output signal Vo3 is detected by the computing device 20 to be 4.24 (V). Thereafter, the computing device 20 calculates the first amplification gain Av1 to be about 6.134, the second amplification gain Av2 to be about 21.856, the reactance value Xc of the capacitor under test 40 to be about 1590.164 (ohm), and the measured value C2 of the capacitor under test 40 to be about 304.371 (pF) according to the equations (1), (3), (4), and (5), wherein the error value between the target value C1 and the measured value C2 of the capacitor under test 40 is about 0.206%.

[0110] When the target value C1 of the capacitor under test 40 is 557 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 228000 (Hz). When the first switch 11 is turned on and the other switches are turned off, the first output signal Vo1 is detected by the computing device 20 to be 0.194 (V). When the second switch is turned on and the other switches are turned off, the second output signal Vo2 is detected by the computing device 20 to be 1.19 (V). When the second switch 12 and the third switch 13 are turned on and the first switch 11 is turned off, the third output signal Vo3 is detected by the computing device 20 to be 4.24 (V). Thereafter, the computing device 20 calculates the first amplification gain Av1 to be about 6.134, the second amplification gain Av2 to be about 26.082, the reactance value Xc of the capacitor under test 40 to be about 1253.23 (ohm), and the measured value C2 of the capacitor under test 40 to be about 557.282 (pF) according to the equations (1), (3), (4), and (5), wherein the error value between the target value C1 and the measured value C2 of the capacitor under test 40 is about 0.051%.

[0111] When the target value C1 of the capacitor under test 40 is 792 (pF), the frequency of the input signal Vin provided by the AC power source 30 is set to 184000 (Hz). When the first switch 11 is turned on and the rest of the switches are turned off, the first output signal Vo1 is detected by the computing device 20 to be 0.194 (V). When the second switch is turned on and the rest of the switches are turned off, the second output signal Vo2 is 1.19 (V). When the second switch 12 and the third switch 13 are turned on and the first switch 11 is turned off, the third output signal Vo3 is 5.63 (V). Thereafter, the computing device 20 calculates the first amplification gain Av1 to be about 6.134 and the second amplification gain Av2 to be about 29.021, the reactance value Xc of the capacitor under test 40 to be about 1092.342 (ohm), and the measured value C2 of the capacitor under test 40 to be about 792.253 (pF) according to the equations (1), (3), (4), and (5), wherein the error between the target value C1 and the measured value C2 of the capacitor under test 40 is about 0.032%.

[0112] As shown in Figure 4 , the error between the measured value and the target value shown by each set of experimental data is less than 1%, thus indicating that the capacitor measurement system 1 of the present application has good accuracy.

[0113] In addition, the measurement circuit 10 of the present application can have different embodiments. Figure 5 is a circuit diagram of the measurement circuit 10 of a second embodiment of the present application, Figure 6 is a circuit diagram of the measurement circuit 10 of a third embodiment of the present application, and please refer to Figures 1 to 4 .

[0114] As shown in Figure 2 , Figure 5 , and Figure 6 , the measurement circuit 10 of the second embodiment Figure 5 and the third embodiment Figure 6 is substantially similar to the first embodiment Figure 2 , so only the differences will be described below.

[0115] First, the structure will be described.

[0116] Regarding the second embodiment Figure 5Compared to the first embodiment, the measurement circuit 10 in the second embodiment further includes a fourth switch 18 and a fifth switch 19. Furthermore, the third switch 13 in the second embodiment is indirectly connected to the capacitor 40 under test. For example, one end of the fourth switch 18 can be electrically connected to the second end 13b of the third switch 13, and the other end of the fourth switch 18 can be electrically connected to a reference capacitor 50. One end of the fifth switch 19 can be electrically connected to the second end 13b of the third switch 13, and the other end of the fifth switch 19 can be electrically connected to the capacitor 40 under test, thus forming a series electrical connection between the third switch 13 and the fourth switch 18 and the fifth switch 19. In one embodiment, the conduction of the fourth switch 18 and the fifth switch 19 can also be controlled by an external control component (not shown in the figure), but this is not a limitation.

[0117] Regarding the third embodiment ( Figure 6 The structure of the third embodiment is different from that of the first embodiment. Figure 6 The measurement circuit 10 of the third embodiment also includes a fourth switch 18. In the third embodiment, the third switch 13 is directly connected to the capacitor under test 40. One end of the fourth switch 18 can be electrically connected to the first end 13a of the third switch 13, forming a parallel electrical connection between the third switch 13 and the fourth switch 18. The other end of the fourth switch 18 can be electrically connected to a reference capacitor 50. The second end 13b of the third switch 13 can be electrically connected to the capacitor under test 40. By controlling the electrical connection of the capacitor under test 40 through the third switch 13 and the electrical connection of the reference capacitor 50 through the fourth switch 18, the circuit has a simple structure and reduces the cost of circuit manufacturing.

[0118] exist Figure 5 or Figure 6 In one embodiment, the reference capacitor 50 may be of the same specification as the capacitor under test 40 (e.g., having the same capacitance value class or the same capacitance value range, but not limited thereto). Furthermore, the target value (e.g., the actual capacitance value) of the reference capacitor 50 may be a known parameter. For example, the target value of the reference capacitor 50 may be a standard value tested in a standard laboratory, possessing high accuracy, thus allowing the reference capacitor 50 to serve as a benchmark for comparison or reference. Therefore, the reference capacitor 50 can serve as a reference for the measurement results of the capacitance measurement system 1.

[0119] Therefore, before measuring the capacitor 40 to be tested, Figure 5 or Figure 6 The measurement circuit 10 can first measure the reference capacitor 50, and adjust the most suitable input signal Vin frequency based on the measured value of the reference capacitor 50 and the target value, and then measure the capacitor 40 under test. The details of the operation process of the second and third embodiments will be explained next.

[0120] In a second embodiment ( Figure 5 ), during a first period, the first switch 11 is turned on, and the rest of the switches 12, 13, 18, 19 are turned off. At this time, the measurement circuit 10 can output a first output signal to the computing device 20. During a second period, the second switch 12 is turned on, and the rest of the switches 11, 13, 18, 19 are turned off. At this time, the measurement circuit 10 can output the first output signal to the computing device 20. The computing device 20 can thus calculate a first amplification gain of the operational amplifier 14. During a third period, the second switch 12, the third switch 13, and the fourth switch 18 are turned on, and the rest of the switches 11, 19 are turned off. At this time, the measurement circuit 10 can output a third output signal to the computing device 20. The computing device 20 can thus calculate a second amplification gain of the operational amplifier 14, and further calculate a measured value of the reference capacitor 50.

[0121] In a third embodiment ( Figure 6 ), during a first period, the first switch 11 is turned on, and the rest of the switches 12, 13, 18 are turned off. At this time, the measurement circuit 10 can output a first output signal to the computing device 20. During a second period, the second switch 12 is turned on, and the rest of the switches 11, 13, 18 are turned off. At this time, the measurement circuit 10 can output the first output signal to the computing device 20. The computing device 20 can thus calculate a first amplification gain of the operational amplifier 14. During a third period, the second switch 12 and the fourth switch 18 are turned on, and the rest of the switches 11, 13 are turned off. At this time, the measurement circuit 10 can output a third output signal to the computing device 20. The computing device 20 can thus calculate a second amplification gain of the operational amplifier 14, and further calculate a measured value of the reference capacitor 50. The third embodiment can have less switches, and can have a simple structure, and can reduce the cost of circuit design.

[0122] Afterwards, the measured value of the reference capacitor 50 can be compared with a target value, and the accuracy of the capacitor measurement system 1 can be determined. In an embodiment, the accuracy of the capacitor measurement system 1 can be adjusted by modulating the frequency of the input signal Vin provided by the AC power source 30. In an embodiment, the frequency of the input signal Vin can be continuously modulated according to the difference between the measured value of the reference capacitor 50 and the target value, and the frequency corresponding to the smallest difference between the measured value and the target value can be found. The frequency can be considered as a suitable frequency for the reference capacitor 50 or the capacitor under test 40. When the suitable frequency is determined, the measurement of the capacitor under test 40 can be performed.

[0123] In addition, in an embodiment, the capacitor measurement system 1 can automatically perform the aforementioned steps of modulating the frequency and finding the suitable frequency. For example, the capacitor measurement system 1 can include a controller ( Figure 5 and Figure 6 not shown), a memory ( Figure 5 andFigure 6 Not shown) and a processor ( Figure 5 and Figure 6 (Not shown), wherein the controller can be used to control the AC power supply 30 to modulate the frequency of the input signal Vin within a specific period or a preset number of times, the computing device 20 can compare the difference between the measured value and the target value of each frequency, the memory can record each comparison result, and the processor can select the frequency corresponding to the result with the smallest difference from the comparison results as the appropriate frequency, so that the AC power supply 30 outputs an output signal of the appropriate frequency.

[0124] In one embodiment, the capacitance measurement system 1 stores data on the frequency of the input signal Vin corresponding to the capacitance value or capacitance value range. When the target value C1 of the reference capacitor 50 is a known parameter, the target value C1 of the reference capacitor 50 is input to the capacitance measurement system 1, and the AC power supply 30 can generate a suitable frequency corresponding to the target value of the reference capacitor 50. The setting of the suitable frequency can be as follows: First, the AC power supply 30 provides an input signal Vin of arbitrary frequency. When the first switch 11 is turned on and the other switches are turned off, the computing device 20 detects the first output signal Vo1. When the second switch is turned on, the other switches are turned off. When all switches are off, the computing device 20 detects the second output signal Vo2. When the second switch 12, the third switch 13 and the fourth switch 18 are on, and the first switch 11 and the fifth switch 19 are off, the computing device 20 detects the third output signal Vo3. Then the computing device 20 calculates the first amplification gain Av1 and the second amplification gain Av2 according to formulas (1) and (3). The computing device 20 then calculates the reactance value of the reference capacitor 50 (e.g., Xc = R1 / (Av2 - Av1)) based on the first amplification gain Av1, the second amplification gain Av2, formulas (2) and (4).

[0125] Since the target value of the reference capacitor 50 is a known parameter, the reactance value of the reference capacitor 50 is also calculated. By using formula (5), the appropriate frequency f provided by the AC power supply 30 is derived as f = 1 / (2πC1Xc). The above calculation can be performed by the processor (not shown in the figure) in the capacitance measurement system 1. Then, the capacitance measurement system 1 uses the appropriate frequency as the input signal Vin of the AC power supply 30. The target value C1 of the reference capacitor 50 and the appropriate frequency provided by the corresponding AC power supply 30 can be stored in the memory (not shown in the figure) of the capacitance measurement system 1. This makes it convenient for the controller (not shown in the figure) of the capacitance measurement system 1 to control the AC power supply 30 to generate an input signal Vin with an appropriate frequency corresponding to the input capacitance value when the same capacitance value or capacitance value range is input later. The above method of obtaining the frequency of the input signal Vin has the advantage of being obtained quickly according to the corresponding capacitance value, and the measurement error of the capacitance measurement system 1 has a certain degree of accuracy.

[0126] In addition, the input signal frequency obtaining method can be further combined with the method in the previous embodiment, that is, first obtaining the basis value of the input signal Vin frequency adjustment of the AC power supply 30 in a calculated manner, then controlling the AC power supply 30 to modulate the input signal Vin frequency in a specific period or a preset number of times, and then obtaining the measurement value of the reference capacitor 50. The computing device 20 compares the difference between the measurement value of each frequency and the target value, and the memory records the comparison results each time. The processor selects the input signal Vin frequency corresponding to the smallest difference result from the comparison results as the appropriate frequency. Because there may be parasitic elements in the measurement circuit 10, which affect the measurement circuit 10 and cause errors in the measurement results. In order to reduce the influence of parasitic elements on the measurement circuit 10, the frequency of the input signal Vin is modulated by the AC power supply 30 in a specific period or a preset number of times, and the frequency is adjusted to obtain the appropriate frequency of the AC power supply 30 output for the reference capacitor 50 or the capacitor to be measured 40, so that the measurement error of the capacitor measurement system 1 is minimized, and the frequency obtaining process of the AC power supply 30 has the advantages of efficiency and accuracy.

[0127] Figure 7 is the experimental data diagram of the input signal frequency modulation of an embodiment of the application.

[0128] As shown in Figure 7 , when the target value C1 of the reference capacitor 50 is 33 (pF), if the frequency of the input signal Vin is not adjusted to the appropriate frequency (for example, the frequency is 1000000 Hz), the measurement value C2 of the reference capacitor 50 is 34.847 (pF), and the error value between the measurement value C2 and the target value C1 is about 5.597%. When the frequency of the input signal Vin is the appropriate frequency (for example, the frequency is 1090000 Hz), the measurement value C2 of the reference capacitor 50 is 33.133 (pF), and the error value between the measurement value C2 and the target value C1 is about 0.403%.

[0129] As shown in Figure 7 , when the target value C1 of the reference capacitor 50 is 305 (pF), if the frequency of the input signal Vin is not adjusted to the appropriate frequency (for example, the frequency is 300000 Hz), the measurement value C2 of the reference capacitor 50 is 281.261 (pF), and the error value between the measurement value C2 and the target value C1 is about 7.783%. When the frequency of the input signal Vin is the appropriate frequency (for example, the frequency is 333000 Hz), the measurement value C2 of the reference capacitor 50 is 305.437 (pF), and the error value between the measurement value C2 and the target value C1 is about 0.143%.

[0130] As shown in Figure 7As shown, in the case where the target value C1 of the reference capacitor 50 is 557 (pF), in the case where the frequency of the input signal Vin is not adjusted to the appropriate frequency (for example, the frequency is 200000 Hz), the measured value C2 of the reference capacitor 50 is 505.614 (pF), and the error between the measured value C2 and the target value C1 is about 9.225%. In the case where the frequency of the input signal Vin is the appropriate frequency (for example, the frequency is 230000 Hz), the measured value C2 of the reference capacitor 50 is 557.281 (pF), and thus the error between the measured value C2 and the target value C1 is about 0.05%.

[0131] Accordingly, each set of experimental data shows that when the frequency of the input signal Vin is adjusted to the appropriate frequency, the error between the measured value and the target value can be greatly reduced. Therefore, it is known that adjusting the frequency of the input signal Vin can indeed change the accuracy of the capacitor measurement system 1.

[0132] By setting the appropriate frequency, the influence of the parasitic capacitance in the measurement environment can be greatly reduced. Moreover, by adjusting the frequency, the capacitor measurement system 1 can support the measurement of smaller capacitance values (for example, pF level), thus solving the problem of the measurement capacitance value capacity limitation of the prior art.

[0133] Through the above experimental verification, it is indeed that the appropriate frequency can make the error between the measured value C2 of the reference capacitor 50 and the target value C1 less than a default value (for example, less than 1%). Then, the same specification of the to-be-measured capacitor 40 as the reference capacitor 50 can be measured according to the appropriate frequency. Then, the details of measuring the to-be-measured capacitor 40 in the second embodiment ( Figure 5 ) and the third embodiment ( Figure 6 ) are described.

[0134] In the second embodiment, after the appropriate frequency is determined, the measurement circuit 10 can output the corresponding first output signal and second output signal. Then, the second switch 12, the third switch 13 and the fifth switch 19 are turned on, and the remaining switches 11, 18 are turned off. At this time, the measurement circuit 10 can output the third output signal to the computing device 20, and the computing device 20 can calculate the second amplification gain of the operational amplifier 14, and further calculate the capacitance value of the to-be-measured capacitor 40.

[0135] In addition, in the third embodiment, after the appropriate frequency is determined, the measurement circuit 10 can output the corresponding first output signal and second output signal. Then, the second switch 12 and the third switch 13 are turned on, and the remaining switches 11, 18 are turned off. At this time, the measurement circuit 10 can output the third output signal to the computing device 20, and the computing device 20 can calculate the second amplification gain of the operational amplifier 14, and further calculate the capacitance value of the to-be-measured capacitor 40.

[0136] Figure 8 is the experimental data graph of the suitable frequency corresponding to the measured capacitance of an embodiment of the present application.

[0137] As shown in Figure 8 , the measurement circuit 10 adopts the circuit design of the second embodiment or the third embodiment, and the measured capacitance 40 adopts a capacitor with a known actual capacitance value (hereinafter referred to as a target value C1) to facilitate the calculation of the error value between the target value C1 and the measured value C2. In addition, the measured capacitance 40 is selected to have values of 33 (pF), 305 (pF), and 557 (pF) to meet the condition of the same specification as each reference capacitance 50, and to cooperate with the suitable frequency corresponding to the target value C1 of each reference capacitance 50 in the Figure 7 , the measurement circuit 10 is operated to obtain the measured value C2 of the measured capacitance, and the error value result between the target value C1 and the measured value C2 is obtained by the calculation device 20.

[0138] As shown in Figure 8 , when the target value C1 of the measured capacitance 40 is 33 (pF), according to the result of Figure 7 , the suitable frequency (for example, the frequency is 1090000 Hz) obtained by using the reference capacitance 50 (the target value C1 is also 33 (pF)) with the same specification as the measured capacitance 40 as the input signal Vin, the measured value C2 of the measured capacitance 40 is 33.193 (pF), and the error value between the measured value C2 and the target value C1 is about 0.585%. By selecting the suitable frequency, the result of the measurement circuit 10 detecting the measured capacitance 40 will be more accurate.

[0139] As shown in Figure 8 , when the target value C1 of the measured capacitance 40 is 305 (pF), according to the result of Figure 7 , the suitable frequency (for example, the frequency is 333000 Hz) obtained by using the reference capacitance 50 (the target value C1 is also 305 (pF)) with the same specification as the measured capacitance 40 as the input signal Vin, the measured value C2 of the measured capacitance 40 is 306.432 (pF), and the error value between the measured value C2 and the target value C1 is about 0.470%. By selecting the suitable frequency, the result of the measurement circuit 10 detecting the measured capacitance 40 will be more accurate.

[0140] As shown in Figure 8 , when the target value C1 of the measured capacitance 40 is 557 (pF), according to the result of Figure 7As a result, the reference capacitor 50 (target value C1 is 557 (pF)) of the same specification as the to-be-measured capacitor 40 is used to obtain a suitable frequency (for example, a frequency of 230000 Hz) as the input signal Vin, the measured value C2 of the to-be-measured capacitor 40 is 560.161 (pF), and the error value between the measured value C2 and the target value C1 is about 0.568%. By selecting a suitable frequency, the result of the measurement circuit 10 detecting the to-be-measured capacitor 40 is more accurate.

[0141] Accordingly, according to the above experiments, it is found that different specifications of the to-be-measured capacitor 40 can first be connected to the measurement circuit 10 through the reference capacitor 50 of the same specification, the input signal Vin is modulated to obtain a suitable frequency, and then the input signal of the suitable frequency is applied to the to-be-measured capacitor 40 of the same specification, so that the measured value C2 of each to-be-measured capacitor 40 detected by the measurement circuit 10 can be maintained below a predetermined error value (for example, the error value is less than 1%), thereby making the result of the measurement circuit 10 detecting the to-be-measured capacitor 40 more accurate.

[0142] In addition, when the accuracy of the capacitor measurement system of the present application needs to be adjusted, the user only needs to modulate the frequency of the input signal of the alternating current power supply to achieve this, compared with the prior art which must adjust a large number of parameters to adjust the accuracy, the present application can have high convenience in use.

[0143] Therefore, the present application provides a capacitor measurement system, a measurement circuit and a computing device, which can provide high-accuracy measurement results and solve the problems of the prior art.

[0144] The above embodiments are only examples for convenience of illustration, and the scope of the rights claimed by the present application should be subject to the description in the patent application range, and is not limited to the above embodiments.

Claims

1. A capacitance measurement system (1), characterized in that, Include: One AC power supply (30); A measurement circuit (10) includes a circuit input terminal (IN), a circuit output terminal (OUT), an operational amplifier (14), and at least one switch (13), wherein the AC power supply (30) is electrically connected to the circuit input terminal (IN), and the at least one switch (13) is electrically connected to a capacitor (40) under test; and A computing device (20) is electrically connected to the output terminal (OUT) of the circuit; When at least one switch (13) is off, the measurement circuit (10) outputs at least one output signal (Vo1, Vo2), and when at least one switch (13) is on, the measurement circuit (10) outputs another output signal (Vo3). The computing device (20) calculates a first amplification gain (Av1) and a second amplification gain (Av2) of the operational amplifier (14) based on the output signals (Vo1, Vo2, Vo3) output by the measurement circuit (10), and calculates a capacitance value (C1) of the capacitor under test (40) based on the first amplification gain (Av1) and the second amplification gain (Av2). The measurement circuit (10) includes a first switch (11), a second switch (12), and a third switch (13). The third switch (13) is electrically connected to the capacitor under test (40). The AC power supply (30) is electrically connected to a first input terminal (14a) of the operational amplifier (14) and a first terminal (11a) of the first switch (11) through the circuit input terminal (IN). An output terminal (14c) of the operational amplifier (14) is electrically connected to a first terminal (12a) of the second switch (12) and a first terminal (13a) of the third switch (13). A second terminal (13b) of the third switch (13) is used to electrically connect to the capacitor under test (40). A second terminal (11b) of the first switch (11) and a second terminal (12b) of the second switch (12) are electrically connected to the circuit output terminal (OUT).

2. The capacitance measurement system (1) according to claim 1, characterized in that, The measurement circuit (10) also includes a first resistor (16) and a second resistor (17), and the output terminal (14c) of the operational amplifier (14) is electrically connected to the second resistor (17) and the third switch (13) through the first resistor (16).

3. The capacitance measurement system (1) according to claim 2, characterized in that, The operational amplifier (14) also includes a second input terminal (14b), and the second input terminal (14b), the first resistor (16), the second resistor (17) and the third switch (13) are electrically connected to a node (B) on the measurement circuit (10).

4. The capacitance measurement system (1) according to claim 1, characterized in that, The measurement circuit (10) also includes a rectifier (15), and the second terminal (11b) of the first switch (11) and the second terminal (12b) of the second switch (12) are electrically connected to the circuit output terminal (OUT) through the rectifier (15).

5. The capacitance measurement system (1) according to claim 1, characterized in that, During a first period, the first switch (11) is turned on, and the circuit output terminal (OUT) outputs a first output signal (Vo1) to the computing device (20). During a second period, the second switch (12) is turned on, and the circuit output terminal (OUT) outputs a second output signal (Vo2) to the computing device (20). The computing device (20) calculates the first amplification gain (Av1) based on the first output signal (Vo1) and the second output signal (Vo2).

6. The capacitance measurement system (1) according to claim 5, characterized in that, During a third period, the second switch (12) and the third switch (13) are turned on, and the circuit output terminal (OUT) outputs a third output signal (Vo3) to the computing device (20). The computing device (20) calculates the second amplification gain (Av2) based on the first output signal (Vo1) and the third output signal (Vo3), and the computing device (20) calculates a reactance value (Xc) of the capacitor under test (40) based on the first amplification gain (Av1) and the second amplification gain (Av2), and calculates the capacitance value (C1) of the capacitor under test (40) based on the reactance value (Xc).

7. The capacitance measurement system according to claim 1, characterized in that, It also includes a fourth switch (18) electrically connected to a reference capacitor (50), and the third switch (13) and the fourth switch (18) are electrically connected in parallel or in series.

8. A measuring circuit (10), disposed in a capacitance measuring system (1), characterized in that, Include: A circuit input terminal (IN) is electrically connected to an AC power supply (30) of the capacitance measurement system (1); A circuit output terminal (OUT) is electrically connected to a computing device (20) of the capacitance measurement system (1); An operational amplifier (14); and At least one switch (13) is electrically connected to the operational amplifier (14); The AC power supply (30) is electrically connected to the operational amplifier (14) through the circuit input terminal (IN), and the at least one switch (13) is electrically connected to a capacitor under test (40). When at least one switch (13) is off, the measurement circuit (10) outputs at least one output signal (Vo1, Vo2), and when at least one switch (13) is on, the measurement circuit (10) outputs another output signal (Vo3). The computing device (20) calculates a first amplification gain (Av1) and a second amplification gain (Av2) of the operational amplifier (14) based on the output signals (Vo1, Vo2, Vo3) output by the measurement circuit (10), and calculates a capacitance value (C1) of the capacitor under test (40) based on the first amplification gain (Av1) and the second amplification gain (Av2). The measurement circuit (10) includes a first switch (11) and a second switch (12), and the switch (13) electrically connected to the capacitor under test (40) is a third switch (13). The AC power supply (30) is electrically connected to a first input terminal (14a) of the operational amplifier (14) and a first terminal (11a) of the first switch (11) through the circuit input terminal (IN). An output terminal (14c) of the operational amplifier (14) is electrically connected to a first terminal (12a) of the second switch (12) and a first terminal (13a) of the third switch (13). A second terminal (13b) of the third switch (13) is used to electrically connect to the capacitor under test (40). A second terminal (11b) of the first switch (11) and a second terminal (12b) of the second switch (12) are electrically connected to the circuit output terminal (OUT).

9. The measurement circuit (10) according to claim 8, characterized in that, It also includes a first resistor (16) and a second resistor (17), and the output terminal (14c) of the operational amplifier (14) is electrically connected to the second resistor (17) and the third switch (13) through the first resistor (16).

10. The measurement circuit (10) according to claim 9, characterized in that, The operational amplifier (14) also includes a second input terminal (14b), and the second input terminal (14b), the first resistor (16), the second resistor (17) and the third switch (13) are electrically connected to a node (B) on the measurement circuit (10).

11. The measurement circuit (10) according to claim 8, characterized in that, It also includes a rectifier (15), and the second terminal (11b) of the first switch (11) and the second terminal (12b) of the second switch (12) are electrically connected to the circuit output terminal (OUT) through the rectifier (15).

12. The measurement circuit (10) according to claim 8, characterized in that, During a first period, the first switch (11) is turned on, and the circuit output terminal (OUT) outputs a first output signal (Vo1) to the computing device (20). During a second period, the second switch (12) is turned on, and the circuit output terminal (OUT) outputs a second output signal (Vo2) to the computing device (20).

13. The measurement circuit (10) according to claim 12, characterized in that, During a third period, the second switch (12) and the third switch (13) are turned on, and the circuit output (OUT) outputs a third output signal (Vo3) to the computing device (20), wherein the measurement circuit (10) calculates the second amplification gain (Av2) based on the first output signal (Vo1) and the third output signal (Vo3).

14. The measurement circuit (10) according to claim 8, characterized in that, It also includes a fourth switch (18) electrically connected to a reference capacitor (50), and the third switch (13) and the fourth switch (18) are electrically connected in parallel or in series.

15. A computing device (20) disposed in the capacitance measurement system (1) according to claim 1, characterized in that, It is used to electrically connect to the output terminal (OUT) of the measurement circuit (10) of the capacitance measurement system (1).

16. The computing device (20) according to claim 15, characterized in that, During a first period (T1), the computing device (20) obtains a first output signal (Vo1) from the circuit output terminal (OUT), and during a second period (T2), the computing device (20) obtains a second output signal (Vo2) from the circuit output terminal (OUT), and calculates the first amplification gain (Av1) based on the first output signal (Vo1) and the second output signal (Vo2).

17. The computing device (20) according to claim 16, characterized in that, During a third period (T3), the computing device (20) obtains a third output signal (Vo3) from the circuit output terminal (OUT), calculates the second amplification gain (Av2) based on the first output signal (Vo1) and the third output signal (Vo3), and calculates a reactance value (Xc) of the capacitor under test (40) based on the first amplification gain (Av1) and the second amplification gain (Av2), and calculates the capacitance value (C1) of the capacitor under test (40) based on the reactance value (Xc).

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