FPGA-based stepping frequency high-resolution short-range radar detection system and method

Abstract

The application discloses a kind of based on FPGA's step frequency high-resolution short-range radar detection system and method, the system includes: transmitting receiving combination module, for generating, sending step frequency signal, and receiving its target reflection echo signal in turn into intermediate frequency echo signal;Signal processing combination module is connected with transmitting receiving combination module and receives intermediate frequency echo signal therein;Control module is connected with signal processing combination module and receives one-dimensional range image;Signal processing combination module includes FPGA operation module, and intermediate frequency echo signal is preprocessed, velocity compensation, range gate division, high-resolution imaging, same distance selects big method to remove redundancy, timing control obtains one-dimensional range image, FPGA operation module receives the control instruction issued by control module and sends it to transmitting receiving combination module.Its advantages are: the system is detected by step frequency broadband synthesis method, and the advantages of FPGA operation module parallel processing are fully utilized, and high-resolution, high-speed signal processing is realized.

Description

Technical Field

[0001] This invention relates to the field of high-speed target detection with short-range high-resolution radar, and specifically to a step-frequency high-resolution short-range radar detection system and method based on FPGA. Background Technology

[0002] High range resolution not only benefits radar target detection in strong clutter backgrounds but also enables target imaging, creating better conditions for target identification. Stepped-frequency radar signals are an important type of high-resolution radar signal. They synthesize a large signal bandwidth and achieve high range resolution by transmitting a series of uniformly hopping single-frequency coherent pulses. Furthermore, because stepped-frequency radar uses narrowband transmission and reception, it further reduces the implementation difficulty and cost of radar transmitters and receivers, achieving good application results in both one-dimensional and two-dimensional imaging fields.

[0003] In practical applications, the detection of short-range high-speed targets requires not only high range resolution but also high processing speed. However, existing stepped-frequency radar detection systems cannot simultaneously achieve high resolution and high real-time processing speed. Therefore, further research is needed to meet the detection requirements for high-resolution imaging of short-range high-speed moving targets. Summary of the Invention

[0004] The purpose of this invention is to provide a step-frequency high-resolution short-range radar detection system and method based on FPGA. This system combines a transmit / receive module, a signal processing module, and a measurement and control module. It achieves high-resolution detection through a step-frequency broadband synthesis method and utilizes an FPGA-based implementation, fully leveraging the parallel processing advantages of FPGA modules to achieve high-resolution, high-speed signal processing. Furthermore, it employs ping-pong processing to improve signal processing throughput and uses multiple range gates in parallel processing for range selection and redundancy removal, further enhancing signal processing speed.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0006] A step-frequency high-resolution short-range radar detection system based on FPGA, comprising:

[0007] The transmit-receive combination module is used to generate and transmit a stepped frequency signal and receive the target reflected echo signal of the stepped frequency signal. The transmit-receive combination module is also used to convert the target reflected echo signal into an intermediate frequency echo signal.

[0008] A signal processing module is connected to the transmit-receive module. The signal processing module receives the intermediate frequency echo signal. The signal processing module includes an FPGA operation module. The FPGA operation module is used to perform preprocessing, velocity compensation, range gate division, high-resolution imaging, redundancy removal using the same range selection method, and timing control on the intermediate frequency echo signal to obtain a one-dimensional range image.

[0009] The measurement and control module is connected to the signal processing combination module and receives the one-dimensional range image sent by it. The measurement and control module is used to issue control commands to the FPGA operation module. The FPGA operation module sends the control commands to the transmit and receive combination module. The transmit and receive combination module generates and sends a step frequency signal according to the control commands and receives the target reflected echo signal, and then sends an intermediate frequency echo signal to the signal processing combination module to obtain a one-dimensional range image.

[0010] Optional, also includes:

[0011] A host computer is connected to the signal processing module and is used to display the one-dimensional distance image processed by the signal processing module.

[0012] Optionally, the transmit-receive combination module includes:

[0013] Frequency synthesis and modulation waveform generation components are used to generate step frequency signals;

[0014] A transmitting component, which is connected to the frequency synthesis and modulation waveform generation component, receives the stepped frequency signal and transmits it through a transmitting antenna;

[0015] A receiving antenna, used to receive the target reflected echo signal of the stepped frequency signal;

[0016] A frequency converter receiver, connected to the receiving antenna, is used to process and convert the target reflected echo signal into an intermediate frequency echo signal.

[0017] Optionally, the signal processing combination includes:

[0018] An A / D sampling module is connected to the transmit-receive combination module. The A / D sampling module is used to sample the intermediate frequency echo signal of the transmit-receive combination module and send the collected intermediate frequency echo signal to the FPGA operation module.

[0019] An external clock module, which provides an external clock source;

[0020] A clock module is connected to the external clock module. The clock module receives external clock source information from the external clock module and generates multiple clock signals. The clock module is also connected to the A / D sampling module and the FPGA operation module and provides clock information to them.

[0021] Optionally, the FPGA operation module includes:

[0022] A digital downconversion module is connected to the A / D sampling module. The digital downconversion module is used to convert the intermediate frequency echo signal to baseband to output I and Q channels of baseband echo data.

[0023] A speed compensation module, which is connected to the digital down-conversion module, is used to perform speed compensation on the I and Q baseband echo data to output the compensated echo signal.

[0024] The distance gate segmentation module is connected to the speed compensation module. The distance gate segmentation module divides the compensated echo signal according to the distance gate and outputs the data of each distance gate in parallel.

[0025] A data ping-pong cache module is connected to the distance gate division module, and the data ping-pong cache module is used to alternately store the data output by each distance gate;

[0026] A one-dimensional high-resolution distance imaging module is connected to the data ping-pong buffer module. The one-dimensional high-resolution distance imaging module is used to perform one-dimensional high-resolution distance imaging on the data of each distance gate.

[0027] A distance gate selection and redundancy removal module is connected to the one-dimensional distance high-resolution imaging module. The distance gate selection and redundancy removal module performs redundancy removal and distance image stitching on the one-dimensional distance high-resolution images of each distance gate to obtain a one-dimensional distance image.

[0028] Optionally, a method for a step-frequency high-resolution short-range radar detection system based on FPGA includes:

[0029] S1. The measurement and control module sends control commands to the FPGA operation module of the signal processing combination module, and the FPGA operation module sends the control commands to the transmission and reception combination module.

[0030] S2. The transmit-receive combination module generates and transmits a step-frequency signal according to the control command, and receives the target reflected echo signal of the step-frequency signal, and then converts it into an intermediate frequency echo signal and sends it to the signal processing combination module.

[0031] S3. The FPGA running module of the signal processing combination module performs preprocessing, velocity compensation, range gate division, high-resolution imaging, redundancy removal by the same distance selection method, and timing control on the intermediate frequency echo signal to obtain a one-dimensional range image.

[0032] S4. The FPGA operation module sends the one-dimensional distance image to the measurement and control module.

[0033] Optionally, step S2 includes:

[0034] S21. The frequency synthesis and modulation waveform generation component in the transmit and receive combination module receives the control command sent by the FPGA operation module and generates a step frequency signal according to the control command.

[0035] S22, The frequency synthesis and modulation waveform generation component sends the step frequency signal to the transmitting component, and the transmitting component receives the step frequency signal and transmits it through the transmitting antenna;

[0036] S23. The receiving antenna receives the target reflected echo signal of the stepped frequency signal and sends it to the frequency converter receiver;

[0037] S24. The frequency converter receiver processes and converts the target reflected echo signal into an intermediate frequency echo signal and sends it to the signal processing combination module.

[0038] Optionally, step S3 includes:

[0039] S31, the A / D sampling module samples the intermediate frequency echo signal of the transmit-receive combination module at a set frequency, and sends the acquired intermediate frequency echo signal to the down-conversion module. At the same time, the A / D sampling module sends the signal to the measurement and control module through the SRIO encoding module for system testing and analysis.

[0040] S32. The digital downconversion module receives the intermediate frequency echo signal sent by the A / D sampling module and performs digital downconversion processing on it to convert it to baseband, and then outputs I and Q channels of baseband echo data.

[0041] S33. The speed compensation module receives the I and Q baseband echo data sent by the digital downconverter module, performs speed compensation on it, and then outputs the compensated echo signal.

[0042] S34. The distance gate partitioning module receives the compensated echo signal sent by the speed compensation module, partitions it according to the distance gate, and outputs the data of each distance gate in parallel.

[0043] S35. The data ping-pong buffer module receives the data of each distance gate sent by the distance gate division module and stores them alternately;

[0044] S36. The one-dimensional distance high-resolution imaging module receives data that is alternately stored by the data ping-pong buffer module, and performs one-dimensional distance high-resolution imaging on the data of each distance gate respectively.

[0045] S37. The distance gate selection and redundancy removal module receives the one-dimensional high-resolution distance images from each distance gate, performs redundancy removal on them, and stitches the distance images together to obtain a one-dimensional distance image.

[0046] Optionally, in step S32, the digital down-conversion processing includes digital quadrature baseband transformation processing and filtering decimation processing, wherein,

[0047] The digital quadrature baseband transform is multiplied by the digital local oscillator and the intermediate frequency echo signal, due to the sampling rate f. s With the intermediate frequency echo signal frequency f I The relationship is satisfy And f s >2B, n=1, 2, ..., the digital local oscillator is a cyclic sequence of three data points: "1", "0", and "-1". The intermediate frequency echo signal is directly zeroed, negativeed, and held to achieve digital quadrature baseband conversion. The filtering and decimation processing is implemented using an FIR filter. After D-fold decimation, the final output is I and Q channels of baseband echo data.

[0048] In step S33, the speed compensation coefficient is calculated before the start of each pulse repetition cycle. The formula for calculating the compensation coefficient is as follows:

[0049]

[0050] Where c is the speed of light, c = 3 × 10 8 v is the relative velocity, f0 is the center frequency of the transmitted signal, ΔF is the step frequency interval, [f0 + (k-1)ΔF] is the transmission frequency of each pulse, and (k-1)T r At the start time of each pulse transmission, if a frame of signal contains N pulses, then k = 1, ..., N, T r The pulse repetition period is defined; the specific implementation process is as follows:

[0051] a) The fixed phase part other than velocity in the velocity compensation coefficient calculation formula Stored in ROM, the fixed phase value is read according to the pulse number and used as the input of the speed compensation coefficient calculation module;

[0052] b) Convert the velocity data from fixed point to floating point, and use the conversion result as input to the velocity compensation coefficient calculation module;

[0053] c) The speed compensation coefficient calculation IP is developed using VIVADO HLS. It multiplies the input fixed phase value with the speed value to obtain the speed compensation phase, and then performs e-exponential calculation to obtain the complex speed compensation coefficient value.

[0054] d) Convert the speed compensation coefficient value from floating point to fixed point, and convert it into 16-bit fixed-point data;

[0055] e) In order to synchronize the input baseband echo signal with the speed compensation coefficient, the baseband echo signal is stored in a FIFO for buffering;

[0056] f) Read the baseband echo signal in the FIFO, multiply it by the speed compensation coefficient, and obtain the compensated echo signal;

[0057] In step S34, the distance gate division module mainly divides the serial echo signal according to the distance gate. Specifically, the distance gate is divided by the oversampling factor P of each transmitted pulse. When the valid data flag of the module input is high, the data is counted. Each distance gate has P sampling points.

[0058] In step S35, the sampling data within each distance gate is ping-pong buffered, and the same CPI data is stored in one storage area. The two storage areas are stored alternately. The RAM is divided into two storage areas according to the address, namely storage area 1 and storage area 2. When the system starts working, the first CPI data input by the module is stored in storage area 1, the second CPI data is stored in storage area 2, and so on.

[0059] In step S36, the same-distance selection method is used to remove redundancy. After comparing duplicate information, a decision is made on whether to discard it. In each group of IFFT results, a length of r is selected. τ Valid points are provided for comparison, and the distance between adjacent component image results and the innovation length is N. s Distance alignment is performed when caching each group of valid data, and 0 is stored at addresses outside the valid data;

[0060] Specifically, it includes:

[0061] 1) Acquisition of one-dimensional distance image amplitude

[0062] P groups of data corresponding to P distance cells of the same distance gate are read out sequentially, and N-point IFFT processing is performed sequentially using the Xilinx FFT IP core. The IFFT output is converted from amplitude to phase by the Xilinx cordic IP core to obtain the one-dimensional range image amplitude.

[0063] 2) For imaging results inside the gate, select the largest distance to remove redundancy.

[0064] Valid data from each distance profile is selected and written into RAM for caching. The relevant parameter calculation formulas are as follows:

[0065] Single-pulse range resolution (coarse range resolution): τ is the emission pulse width, and c is the speed of light, c = 3 × 10⁻⁶. 8 ,

[0066] Distance resolution: c is the speed of light, c = 3 × 10 8 ,

[0067] Number of valid points per pulse: Trunc is the truncation operator.

[0068] Sampling distance resolution: T s The sampling interval is c, where c is the speed of light, c = 3 × 10⁻⁶. 8 ,

[0069] Number of points corresponding to one sampling distance: Trunc is the truncation operator.

[0070] Single-point unambiguous distance: c is the speed of light, c = 3 × 10 8 ΔF is the step frequency and step interval.

[0071] Number of imaging points per pulse: Trunc is the truncation operator;

[0072] The effective data selection method for the same distance selection method is as follows:

[0073] P m =Trunc(mr s / Δr)Mod(N) represents the starting position of valid data in the m-th IFFT result.

[0074] Q m =Trunc((mr s +r τ ) / Δr)Mod(N) represents the end position of valid data in the m-th IFFT result.

[0075] Where m = 1, 2, ..., M, M is the number of echo sampling points in one PRT cycle, and Mod is the remainder; if P m <Q m The number of valid data points is P. m ~Q m Otherwise, distance folding occurs, and the number of valid points is P. m ~N,1~Q m When using the same distance selection method to remove redundancy, the imaging results need to be aligned by distance. In cases of distance folding, 1~Qm Points correspond to greater distances, and when storing valid data from each IFFT result, they are arranged according to P. m ~N,1~Q m Store in the order they appear;

[0076] In step S37, the distance rearrangement of each distance gate deduplication imaging result is performed and cached into the dual-port RAM, requiring N storage units. r =N rk +(K-1)·N τ The effective data consists of the imaging results of each range gate in S36 after redundancy removal and ensuring the range ratio is the largest. Simultaneously, data stored in K RAMs are read, and the largest value among data at the same address is selected to obtain the image containing N... r A one-dimensional distance image composed of stitched-together points;

[0077] In step S4, the FPGA operation module packages the obtained one-dimensional distance image through the SRIO encoding module and transmits it to the measurement and control module for storage, and then transmits it to the host computer for display.

[0078] Optional, also includes:

[0079] S5. Target detection is performed using the constant false alarm rate (CFAR) method.

[0080] S6. The target detection results are packaged by the SRIO encoding module and transmitted to the measurement and control module for storage, and then transmitted to the host computer for real-time display.

[0081] Compared with the prior art, the present invention has the following advantages:

[0082] In this invention, an FPGA-based step-frequency high-resolution short-range radar detection system and method combines a transmit-receive module, a signal processing module, and a measurement and control module. The signal processing module configures the frequency synthesis and modulation waveform generation components to generate a step-frequency signal, which is radiated out via a transmit antenna. The receive antenna receives the target reflected echo signal from the step-frequency signal, and a frequency converter converts the target reflected echo signal into an intermediate frequency (IF) echo signal. The FPGA operating module, as the core processing unit, performs preprocessing, velocity compensation, range gating, high-resolution imaging, redundancy removal using the same-range selection method, and range image stitching on the IF echo data to obtain a one-dimensional range image, achieving both high resolution and system processing speed. Attached Figure Description

[0083] Figure 1 This is a schematic diagram of a step-frequency high-resolution short-range radar detection system based on FPGA according to the present invention;

[0084] Figure 2This is a schematic diagram of a method for a step-frequency high-resolution short-range radar detection system based on FPGA according to the present invention;

[0085] Figure 3 This is a schematic diagram of the processing of a digital downconversion module according to the present invention;

[0086] Figure 4 This is a schematic diagram of a distance gate division according to the present invention;

[0087] Figure 5 This is a schematic diagram of a ping-pong storage device according to the present invention;

[0088] Figure 6 This is a schematic diagram of effective data extraction and caching for a single-distance gate according to the present invention;

[0089] Figure 7 This is a schematic diagram illustrating the big data alignment and caching method between distance gates according to the present invention. Detailed Implementation

[0090] The present invention will be further described below with reference to the accompanying drawings and by providing a detailed description of a preferred embodiment.

[0091] like Figure 1 As shown, this invention provides a step-frequency high-resolution short-range radar detection system based on FPGA. The system includes a transmit-receive combination module, a signal processing combination module, and a measurement and control module, i.e., a measurement and control system.

[0092] The transmit-receive module generates and transmits a stepped-frequency signal and receives the target reflected echo signal from the stepped-frequency signal. It also converts the target reflected echo signal into an intermediate-frequency (IF) echo signal. A signal processing module is connected to the transmit-receive module. This signal processing module receives the IF echo signal and includes an FPGA (FPGA chip) as its core processing module. The FPGA module performs preprocessing (down-conversion), velocity compensation, range gating, high-resolution imaging, redundancy removal using the same-range selection method, and timing control on the IF echo signal to obtain a one-dimensional range image. Furthermore, the FPGA module also has data transmission and communication control functions, enabling it to detect and perform high-resolution imaging of short-range, high-speed moving targets. The measurement and control module is connected to the signal processing combination module and receives the one-dimensional range image sent by it. The measurement and control module is used to issue control commands to the FPGA operation module. The FPGA operation module sends the control commands to the transmit and receive combination module. The transmit and receive combination module generates and sends a step frequency signal according to the control commands and receives the target reflected echo signal, and then sends an intermediate frequency echo signal to the signal processing combination module to obtain a one-dimensional range image.

[0093] Furthermore, the system also includes a host computer connected to the signal processing module. The host computer is used to display the one-dimensional range image processed by the signal processing module. In this embodiment, the host computer mainly transmits data at low speed to the FPGA operating module via 422 communication. Besides displaying the one-dimensional range image, the host computer can also be configured to have system control functions (similar to a control module), etc., which is not limited in this respect. Furthermore, in this embodiment, the measurement and control module mainly uses an SRIO encoding module (Serial Rapid Input / Output) to issue system operating commands, transmit parameters, and transmit high-speed data with the FPGA operating module, such as the transmission of AD sampling data, one-dimensional range images, and detection results.

[0094] like Figure 1 As shown, the transmit-receive combination module includes: a frequency synthesis and modulation waveform generation component, a transmit component, a receive antenna, and a frequency conversion receiver. The frequency synthesis and modulation waveform generation component generates a stepped-frequency signal. The transmit component is connected to the frequency synthesis and modulation waveform generation component, receives the stepped-frequency signal, and transmits it through the transmit antenna. The receive antenna receives the target reflected echo signal of the stepped-frequency signal. The frequency conversion receiver is connected to the receive antenna and processes the target reflected echo signal to convert it into an intermediate-frequency (IF) echo signal, thereby achieving IF output.

[0095] In this embodiment, the signal processing assembly includes not only an FPGA operating module, but also an A / D sampling module (A / D sampling chip), an external 80MHz clock module, and a clock module (clock chip). The A / D sampling module is connected to the transmit-receive assembly module and samples the intermediate frequency (IF) echo signal from the transmit-receive assembly module, sending the acquired IF echo signal to the FPGA operating module. The external 80MHz clock module provides an external clock source. The clock module is connected to the external 80MHz clock module, receives the external clock source information from the external 80MHz clock module, and generates multiple clock signals. The clock module is also connected to the A / D sampling module, the FPGA operating module, and the frequency synthesis and modulation waveform generation component, providing them with clock information. Of course, the external clock source of the external 80MHz clock module can also be based on the clock information from the frequency synthesis and modulation waveform generation component to generate multiple clock signals; this invention does not limit this.

[0096] Furthermore, the FPGA operation module includes: a digital down-conversion module, a speed compensation module, a range gate partitioning module, a data ping-pong buffer module, a one-dimensional range high-resolution imaging module, and a range gate selection and redundancy removal module. Specifically, the digital down-conversion module is connected to the A / D sampling module, and is used to convert the intermediate frequency echo signal to baseband to output I and Q channel baseband echo data; the speed compensation module is connected to the digital down-conversion module, and is used to perform speed compensation on the I and Q channel baseband echo data to output compensated echo signals; the range gate partitioning module is connected to the speed compensation module, and divides the compensated echo signal according to the range gates, and outputs the data of each range gate in parallel; the data ping-pong buffer... The storage module is connected to the distance gate partitioning module, and the data ping-pong cache module is used to alternately store the data output from each distance gate; the one-dimensional distance high-resolution imaging module is connected to the data ping-pong cache module, and the one-dimensional distance high-resolution imaging module is used to perform one-dimensional distance high-resolution imaging on the data of each distance gate respectively; the distance gate same-distance selection and redundancy removal module is connected to the one-dimensional distance high-resolution imaging module, and the distance gate same-distance selection and redundancy removal module performs selection and redundancy removal on the one-dimensional distance high-resolution imaging of each distance gate and stitches the distance images to obtain a one-dimensional distance image.

[0097] Based on the same inventive concept, this invention also provides a method for a step-frequency high-resolution short-range radar detection system based on FPGA, such as... Figure 2 As shown, this method mainly includes:

[0098] S1. The measurement and control module sends control commands to the FPGA operation module of the signal processing combination module, and the FPGA operation module sends the control commands to the transmission and reception combination module.

[0099] Optionally, before step S1, the system can be initialized after power-on, mainly to complete the FPGA operation module configuration, perform an internal system reset (the reset duration can be set as needed), and complete the SRIO encoding module configuration. Further, the system performs a self-test, primarily a communication self-test, using the sending and receiving of self-test communication frames to confirm normal communication; the data received by the SRIO encoding module is decoded, the received 256 bytes are decomposed into the bytes required by the protocol, and verification is performed simultaneously with the decoded data, comparing it with the received checksum (the SRIO communication protocol includes a checksum bit; during communication, a checksum data bit is sent to the other end along with the packaged data; here, it is the checksum of the SRIO data packet sent by the measurement and control module).

[0100] S2. The transmit-receive combination module generates and transmits a step-frequency signal according to the control command, and receives the target reflected echo signal of the step-frequency signal, and then converts it into an intermediate frequency echo signal and sends it to the signal processing combination module.

[0101] Specifically, step S2 includes:

[0102] S21. The frequency synthesis and modulation waveform generation component in the transmit-receive combination module receives control commands sent by the FPGA operation module and generates a step frequency signal according to the control commands. In this embodiment, the FPGA operation module configures the frequency synthesis and modulation waveform generation component via 422 communication.

[0103] S22, The frequency synthesis and modulation waveform generation component sends the step frequency signal to the transmitting component, and the transmitting component receives the step frequency signal and transmits it through the transmitting antenna.

[0104] S23. The receiving antenna receives the target reflected echo signal of the stepped frequency signal and sends it to the frequency converter receiver.

[0105] S24. The frequency converter receiver processes and converts the target reflected echo signal into an intermediate frequency echo signal and sends it to the signal processing combination module.

[0106] Furthermore, in step S3, the FPGA operation module of the signal processing combination module performs preprocessing (down-conversion processing), velocity compensation, range gate division, high-resolution imaging, redundancy removal using the same distance selection method, and timing control on the intermediate frequency echo signal to obtain a one-dimensional range image.

[0107] Specifically, step S3 includes:

[0108] S31, the A / D sampling module mainly implements A / D chip configuration and sampling data reception. The A / D sampling module samples the intermediate frequency echo signal of the transmit and receive combination module at a set frequency, and sends the acquired intermediate frequency echo signal to the down-conversion module for processing. At the same time, the A / D sampling module also sends the intermediate frequency echo signal to the measurement and control module through the SRIO encoding module for system testing and analysis.

[0109] S32. The digital down-conversion module receives the intermediate frequency echo signal sent by the A / D sampling module and performs digital down-conversion (DDC) processing on it to convert the echo data to baseband, thereby outputting I and Q channel baseband echo data. Compared with analog device processing, the digital down-conversion processing mode of this application has better amplitude consistency and orthogonality.

[0110] like Figure 3As shown, in step S32, the digital down-conversion processing mainly includes digital quadrature baseband transformation processing and filtering decimation processing. Specifically, the digital quadrature baseband transformation involves multiplying the digital local oscillator signal by the intermediate frequency echo signal. Since the sampling rate f of the A / D sampling module... s With the intermediate frequency echo signal frequency f I The relationship is satisfy And f s >2B, n=1,2,…, the digital local oscillator is a cyclic sequence of three data values: “1”, “0”, and “-1”. This allows for direct zeroing, negativeing, and holding of the sampled intermediate frequency echo signal to achieve digital quadrature baseband conversion. This method is simple, adaptable to higher clock frequencies, and requires less FPGA resources. The filtering and decimation process uses an FIR filter, and after D-fold decimation, the final output consists of two baseband echo data channels: I and Q (D can be any constant).

[0111] S33. The speed compensation module receives the I and Q baseband echo data sent by the digital downconverter module and performs speed compensation on them, thereby outputting the compensated echo signal.

[0112] In step S33, the speed compensation coefficient is calculated before the start of each PRT (pulse repetition cycle). The calculation formula for the compensation coefficient is as follows:

[0113]

[0114] Where j represents a complex number, and c is the speed of light c = 3 × 10 8 v is the relative velocity, f0 is the center frequency of the transmitted signal, ΔF is the step frequency interval, [f0 + (k-1)ΔF] is the transmission frequency of each pulse, and (k-1)T r At the start time of each pulse transmission, if a frame of signal contains N pulses, then k = 1, ..., N, T r This is the pulse repetition period. The specific implementation process is as follows:

[0115] a) The fixed phase part other than velocity in the velocity compensation coefficient calculation formula Stored in ROM, the fixed phase value is read according to the pulse number and used as the input of the speed compensation coefficient calculation module;

[0116] b) Convert the velocity data from fixed point to floating point, and use the conversion result as input to the velocity compensation coefficient calculation module;

[0117] c) The speed compensation coefficient calculation IP (Intellectual Property Core) is developed using VIVADO HLS. It multiplies the input fixed phase value with the speed value to obtain the speed compensation phase, and then performs e-exponential calculation to obtain the complex speed compensation coefficient value.

[0118] d) Convert the speed compensation coefficient value from floating point to fixed point, and convert it into 16-bit fixed-point data;

[0119] e) In order to synchronize the input baseband echo signal with the speed compensation coefficient, the baseband echo signal is stored in a FIFO for buffering;

[0120] f) Read the baseband echo signal from the FIFO (First-In-First-Out data buffer), multiply it by the speed compensation coefficient (implemented by Xilinx complex multiplication IP core) to obtain the compensated echo signal.

[0121] S34. The distance gate partitioning module receives the compensated echo signal sent by the speed compensation module, partitions it according to the distance gate, and outputs the data of each distance gate in parallel.

[0122] In step S34, the range gate partitioning module mainly divides the serial echo signal according to range gates, and the data of each range gate is output in parallel. In this embodiment, the range gate partitioning is performed by the oversampling factor P of each transmitted pulse. The module counts the data when the valid input data flag is high. Each range gate has P sampling points, and the range gate partitioning is as follows: Figure 4 As shown.

[0123] To achieve the detection of short-range, high-speed targets, the system's pulse repetition period (PRT) and pulse accumulation period (CPI) are both relatively short. Data processing cannot be completed within one CPI. Therefore, ping-pong processing of adjacent CPI data is adopted to improve the system's processing capacity. Specifically, in S35, the data from each range gate sent by the range gate partitioning module is received through the data ping-pong buffer module and stored alternately.

[0124] In step S35, the sampled data within each distance gate are buffered using a ping-pong buffer. Data of the same CPI is stored in one storage area, and the two storage areas are used alternately. In this embodiment, the RAM ping-pong storage area is divided as follows: Figure 5 As shown, the RAM is divided into two storage areas, storage area 1 and storage area 2, based on address hierarchy. When the system starts working, the first CPI data input from the module is stored in storage area 1, the second CPI data is stored in storage area 2, and so on. Since the sampling rate is lower than the processing speed after down-conversion, an address skipping method is used for storage, with a skipping address interval of N. During reading, N sampling points corresponding to each distance unit are read continuously, using a higher read clock frequency to further improve the system's processing speed.

[0125] S36. The one-dimensional range high-resolution imaging module receives data alternately stored by the data ping-pong buffer module and performs one-dimensional range high-resolution imaging on the data of each range gate. Due to oversampling redundancy and range mismatch redundancy in this system, redundancy removal processing of the imaging results is required. In this application, the same-range selection method is used for redundancy removal. The specific implementation is as follows:

[0126] 1) Acquisition of one-dimensional distance image amplitude

[0127] P sets of data corresponding to P distance cells of the same distance gate are read out sequentially, and N-point IFFT processing is performed sequentially using the Xilinx FFT IP core. The IFFT output is then converted from amplitude to phase using the Xilinx cordic IP core to obtain the one-dimensional range image amplitude.

[0128] 2) For imaging results inside the gate, select the largest distance to remove redundancy.

[0129] Valid data from each distance image is selected and written into RAM for caching. A storage diagram is shown below. Figure 6 As shown, the formulas for calculating the relevant parameters are as follows:

[0130] Single-pulse range resolution (coarse range resolution): τ is the emission pulse width, and c is the speed of light, c = 3 × 10⁻⁶. 8 .

[0131] Distance resolution: c is the speed of light, c = 3 × 10 8 .

[0132] Number of valid points per pulse: Trunc is the truncation operator.

[0133] Sampling distance resolution: T s The sampling interval is c, where c is the speed of light, c = 3 × 10⁻⁶. 8 .

[0134] Number of points corresponding to one sampling distance: Trunc is the truncation operator.

[0135] Single-point unambiguous distance: c is the speed of light, c = 3 × 10 8 ΔF is the step frequency step interval.

[0136] Number of imaging points per pulse: Trunc is the truncation operator.

[0137] The redundancy after synthesizing the step frequency signal pulses in this system has two types: one is distance mismatch redundancy, that is, when r τ / r IThe redundancy generated when =τ·Δf<1 is related to r I and r τ Another type is oversampling redundancy, which is related to r. τ and r s Regarding step S36, the idea behind the same-distance selection method is that it does not easily discard duplicate information, but rather compares the duplicate information before deciding whether to discard it, selecting a length of r from each IFFT result. τ Valid points are provided for comparison, and the distance between adjacent component image results and the innovation length is N. s Distance alignment is performed during the caching of each set of valid data, and addresses outside the valid data are stored as 0. Assuming the oversampling redundancy factor P = 4, taking distance gate 1 as an example, the corresponding valid data extraction and data storage diagram is as follows: Figure 6 As shown, each RAM storage depth is N. rk =N τ +(P-1)·N s When comparing data at the same distance, data from P RAMs are read simultaneously, and the data at the same storage address is selected to be larger, thus obtaining the single distance gate's distance-selected redundancy-removing imaging result.

[0138] The effective data selection method for the same distance selection method is as follows:

[0139] P m =Trunc(mr s / Δr)Mod(N) represents the starting position of valid data in the m-th IFFT result.

[0140] Q m =Trunc((mr s +r τ ) / Δr)Mod(N) represents the end position of valid data in the m-th IFFT result.

[0141] Where m = 1, 2, ..., M, M is the number of echo sampling points in one PRT cycle, and Mod is the remainder. If P m <Q m The number of valid data points is P. m ~Q m Otherwise, distance folding occurs, and the number of valid points is P. m ~N,1~Q m When using the same distance selection method to remove redundancy, the imaging results need to be aligned by distance. In cases of distance folding, 1~Q m Points correspond to greater distances, and when storing valid data from each IFFT result, they are arranged according to P. m ~N,1~Q m Store them in the order they appear.

[0142] S37. The distance gate selection and redundancy removal module receives one-dimensional high-resolution distance images from each distance gate, performs distance gate data selection and redundancy removal, and stitches the distance images together to obtain a one-dimensional distance image.

[0143] In step S37, the distance rearrangement of each distance gate deduplication imaging result is performed and cached into the dual-port RAM. A schematic diagram of the distance rearrangement and caching is shown below. Figure 7 As shown, the required number of storage units is N. r =N rk +(K-1)·N τ The effective data consists of the imaging results of each range gate in S36 after redundancy removal and ensuring the range ratio is the largest. Simultaneously, data from K RAMs are read, and the largest value among data at the same address is selected to obtain the image containing N... r A one-dimensional distance image composed of stitched-together points.

[0144] S4. The FPGA operation module sends the one-dimensional distance image to the measurement and control module.

[0145] In step S4, the FPGA operation module packages the obtained one-dimensional distance image through the SRIO encoding module and transmits it to the measurement and control module for storage, and then transmits it to the host computer for display via 422 communication.

[0146] Furthermore, the method of the FPGA-based step-frequency high-resolution short-range radar detection system also includes: S5, using the constant false alarm rate method for target detection; S6, packaging the target detection results through the SRIO encoding module and transmitting them to the measurement and control module for storage, and transmitting them to the host computer for real-time display via 422 communication.

[0147] In summary, the FPGA-based stepped-frequency high-resolution short-range radar detection system and method of this invention combines a transmit / receive module, a signal processing module, and a measurement and control module. It achieves high-resolution detection through a stepped-frequency broadband synthesis method. Furthermore, to meet the detection requirements of short-range high-speed targets, an FPGA-based implementation method is adopted, fully utilizing the parallel processing advantages of FPGA modules to achieve high-resolution, high-speed signal processing. Further, ping-pong processing is used to improve signal processing throughput; multiple range gates are used in parallel processing for range selection and redundancy removal, further improving the signal processing speed.

[0148] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. An FPGA-based stepped frequency high-resolution short-range radar detection system, characterized in that, Comprise: a transmitting-receiving combination module for generating, emitting a step frequency signal, and receiving a target reflected echo signal of the step frequency signal, the transmitting-receiving combination module also being used for converting the target reflected echo signal into an intermediate frequency echo signal; a signal processing combination module connected with the transmitting-receiving combination module, the signal processing combination module receiving the intermediate frequency echo signal, the signal processing combination module comprising an FPGA running module, the FPGA running module being used for pre-processing, velocity compensation, range gate division, high-resolution imaging, same distance selection and redundancy elimination of the intermediate frequency echo signal to obtain a one-dimensional range image; a measurement and control module connected with the signal processing combination module and receiving the one-dimensional range image sent by the signal processing combination module, the measurement and control module being used for issuing a control instruction to the FPGA running module, the FPGA running module sending the control instruction to the transmitting-receiving combination module, the transmitting-receiving combination module generating, emitting a step frequency signal and receiving a target reflected echo signal according to the control instruction, and then sending the intermediate frequency echo signal to the signal processing combination module to obtain a one-dimensional range image; wherein the FPGA running module comprises: a digital down-conversion module connected with an A / D sampling module, the digital down-conversion module being used for converting the intermediate frequency echo signal to a baseband to output I and Q two-way baseband echo data; a velocity compensation module connected with the digital down-conversion module, the velocity compensation module being used for velocity compensation of the I and Q two-way baseband echo data to output a compensated echo signal; a range gate division module connected with the velocity compensation module, the range gate division module dividing the compensated echo signal according to a range gate and making data of each range gate output in parallel; a data ping-pong buffer module connected with the range gate division module, the data ping-pong buffer module being used for alternately storing data output by each range gate; a one-dimensional range high-resolution imaging module connected with the data ping-pong buffer module, the one-dimensional range high-resolution imaging module being used for one-dimensional range high-resolution imaging of data of each range gate respectively; a same distance selection and redundancy elimination module between range gates connected with the one-dimensional range high-resolution imaging module, the same distance selection and redundancy elimination module between range gates performing same distance selection and redundancy elimination of one-dimensional range high-resolution imaging of each range gate and range image splicing to obtain a one-dimensional range image.

2. The FPGA-based stepped-frequency high-resolution short-range radar detection system of claim 1, wherein, Further comprise: a host computer connected with the signal processing combination module, the host computer being used for displaying the one-dimensional range image processed by the signal processing combination module.

3. The FPGA-based stepped-frequency high-resolution short-range radar detection system of claim 1, wherein, The transmitting-receiving combination module comprises: a frequency synthesis and modulated waveform generation component for generating a step frequency signal; a transmitting component connected with the frequency synthesis and modulated waveform generation component, the transmitting component receiving the step frequency signal and emitting it through a transmitting antenna; a receiving antenna for receiving a target reflected echo signal of the step frequency signal; a frequency conversion receiver connected with the receiving antenna, the frequency conversion receiver being used for processing and converting the target reflected echo signal into an intermediate frequency echo signal.

4. The FPGA-based stepped-frequency high-resolution short-range radar detection system of claim 1, wherein, The signal processing combination comprises: An A / D sampling module connected with the transmitting-receiving combination module, used for sampling the intermediate frequency echo signal of the transmitting-receiving combination module and sending the collected intermediate frequency echo signal to the FPGA running module; An external clock module used for providing an external clock source; A clock module connected with the external clock module, used for receiving the external clock source information of the external clock module and generating multi-path clock information, and connected with the A / D sampling module and the FPGA running module and used for providing clock information for them.

5. The method of the FPGA-based stepped-frequency high-resolution short-range radar detection system according to any one of claims 1 to 4, characterized in that, Comprise: S1, the control module sends control instructions to the FPGA running module of the signal processing combination module, and the FPGA running module sends the control instructions to the transmitting-receiving combination module; S2, the transmitting-receiving combination module generates and transmits the step frequency signal according to the control instructions, receives the target reflected echo signal of the step frequency signal, and then converts the intermediate frequency echo signal into the signal processing combination module; S3, the FPGA running module of the signal processing combination module pre-processes, velocity compensates, distance gate divides, high-resolution images, same distance selects large method to remove redundancy, and time sequence control to obtain one-dimensional range image; S4, the FPGA running module sends the one-dimensional range image to the control module.

6. The method of FPGA-based stepped-frequency high-resolution short-range radar detection system according to claim 5, wherein, The step S2 comprises: S21, the frequency synthesis and modulation waveform generation component in the transmitting-receiving combination module receives the control instructions sent by the FPGA running module, and generates the step frequency signal according to the control instructions; S22, the frequency synthesis and modulation waveform generation component sends the step frequency signal to the transmitting component, and the transmitting component receives the step frequency signal and sends it out through the transmitting antenna; S23, the receiving antenna receives the target reflected echo signal of the step frequency signal and sends it to the frequency conversion receiver; S24, the frequency conversion receiver processes and converts the target reflected echo signal into the intermediate frequency echo signal and sends it to the signal processing combination module.

7. The method of FPGA-based stepped-frequency high-resolution short-range radar detection system according to claim 5, wherein, The step S3 comprises: S31, the A / D sampling module samples the intermediate frequency echo signal of the transmitting-receiving combination module at a set frequency, and sends the obtained intermediate frequency echo signal to the frequency down conversion module, while the A / D sampling module sends the system test analysis to the control module through the SRIO encoding module; S32, the digital frequency down conversion module receives the intermediate frequency echo signal sent by the A / D sampling module and performs digital frequency down conversion processing to convert it to baseband, and then outputs I and Q two-way baseband echo data; S33, the velocity compensation module receives the I and Q two-way baseband echo data sent by the digital frequency down conversion module and performs velocity compensation, and then outputs the compensated echo signal; S34, the distance gate division module receives the compensated echo signal sent by the velocity compensation module, divides it according to the distance gate, and makes the data of each distance gate output in parallel; S35, the data ping-pong buffer module receives the data of each distance gate sent by the distance gate division module and alternately stores them. S36, the one-dimensional distance high-resolution imaging module receives the data alternately stored by the data ping-pong buffer module, and performs one-dimensional distance high-resolution imaging on the data of each distance gate respectively; S37, the distance gate inter-distance same distance selection and redundancy removal module receives the one-dimensional distance high-resolution imaging of each distance gate, performs selection and redundancy removal, and splices the distance images to obtain a one-dimensional distance image.

8. The FPGA-based step frequency high-resolution short-range radar detection system method of claim 7, wherein, in the step S32, the digital down-conversion processing includes digital quadrature baseband conversion processing and filtering and decimation processing, wherein, in the step S33, the velocity compensation coefficient is calculated before the start of each pulse repetition period, and the compensation coefficient calculation formula is as follows: b) converting the velocity data from fixed point to floating point, and taking the conversion result as the input of the velocity compensation coefficient calculation module; The digital quadrature baseband conversion is multiplication of the digital local oscillator and the intermediate frequency echo signal, and the sampling rate f s The frequency f I The relationship is Satisfies And f s > 2B, n = 1, 2, L, the digital local oscillator is a cycle of a number sequence composed of three data groups of "1", "0", and "-1", and the intermediate frequency echo signal is directly zeroed, negated, and kept to realize the digital quadrature baseband conversion; the filtering and decimation processing is realized by using the FIR filter, and after D times of decimation, the final output is I and Q two-way baseband echo data; c) developing the velocity compensation coefficient calculation IP through VIVADO HLS, multiplying the input fixed phase value and the velocity value to obtain the velocity compensation phase, and then performing e exponential calculation to obtain the complex velocity compensation coefficient value; wherein c is the speed of light c = 3 x 10 8 , v is the relative speed, f0is the center frequency of the transmitted signal, ΔF is the frequency step interval, [f0+ (k-1) ΔF] is the transmission frequency of each pulse, (k-1) T r is the start time of each pulse transmission, if a frame signal contains N pulses, then k = 1, L, N, T r is the pulse repetition period; the specific implementation process is as follows: a) The fixed phase part of the velocity compensation coefficient calculation formula, except for the velocity is stored in the ROM, and the fixed phase value is read according to the pulse number as the input of the velocity compensation coefficient calculation module; d) converting the velocity compensation coefficient value from floating point to fixed point, and converting it into 16-bit fixed point data; e) in order to synchronize the input baseband echo signal with the velocity compensation coefficient, the baseband echo signal is stored in the FIFO for buffering; f) reading the baseband echo signal in the FIFO, multiplying it by the velocity compensation coefficient to obtain the compensated echo signal; In the step S34, the distance gate division module divides the serial echo signal according to the distance gate, specifically using the oversampling multiple P of each transmission pulse to divide the distance gate, and counting the data when the module input data valid flag is high; In the step S35, the sampling data in each distance gate is respectively ping-pong buffered, the same CPI data is stored in one storage area, and two storage areas are alternately stored, the RAM is divided into two storage areas according to the high and low addresses, which are storage area 1 and storage area 2 respectively, when the system starts working, the first CPI data input by the module is stored in storage area 1, the second CPI data is stored in storage area 2, and so on; Specifically, it includes: 1) one-dimensional distance image amplitude acquisition In the step S36, the same distance selection method is used to remove redundancy, and after comparing the repeated information, it is decided whether to discard or not. In each group of IFFT results, the effective points with the length of r τ are selected for comparison. The distance between adjacent groups of imaging results is N s , and the distance alignment is performed when the effective data is buffered. The addresses outside the effective data are stored as 0. P groups of data corresponding to the same distance gate P are sequentially read out, N-point IFFT processing is performed in turn by using the Xilinx FFT IP core, and the IFFT output is converted into amplitude and phase by the Xilinx cordic IP core to obtain the one-dimensional distance image amplitude; 2) distance gate imaging result same distance selection and redundancy removal The valid data in each distance image is selected and written into the RAM for buffering, and the relevant parameter calculation formula is as follows: The same distance selection method is as follows: In the step S4, the FPGA running module packages the obtained one-dimensional distance image through the SRIO encoding module, and transmits it to the control module for storage and to the upper computer for display. Single pulse range resolution: where τ is the pulse width and c is the speed of light c = 3 x 10 8 Range resolution: where c is the speed of light c = 3 x 10 8 , Single pulse effective number of bits: Trunc is a truncation operation, Sampling distance resolution: T s is the sampling interval and c is the speed of light c = 3 x 10 8 , The number of points corresponding to one sampling distance: Trunc is a truncation operation, Single point unambiguous range: c is the speed of light c = 3 x 10 8 ΔF is the frequency step interval, Number of single pulse imaging points: Trunc is a truncation operation; Further comprising: P m = Trunc(mr s / Δr) Mod(N) is the start position of the effective data of the mth group of IFFT results, Q m = Trunc((mr s + r τ ) / Δr)Mod(N) is the end position of the valid data of the mth group of IFFT results, where m = 1, 2, …, L M, M is the number of echo sampling points in a PRT period, Mod is the remainder; if P m < Q m , the number of valid data points is P m ~ Q m , otherwise distance folding occurs, the number of valid data points is P m ~ N, 1 ~ Q m ; when the distance is selected to be large to remove redundancy, the imaging results need to be aligned in distance, and the 1 ~ Q m point corresponding to the farther distance in the case of distance folding, when the valid data of each group of IFFT results is stored, it is stored in the order of P m ~ N, 1 ~ Q m ; The step S37, each distance gate de-redundant imaging result is rearranged in distance, respectively, into the dual-port RAM, the number of storage units required is N r =N rk +(K-1)·N τ , the effective data is the imaging result after de-redundant of each distance gate in S36; while reading the storage data of K RAM, the data in the same address is selected, that is, the spliced one-dimensional range image containing N r points can be obtained; wherein, the storage depth of each RAM is N rk =N τ +(P-1)·N s ; S5, using the constant false alarm method for target detection; 9. The method of FPGA-based stepped-frequency high-resolution short-range radar detection system according to claim 5, wherein, ​ ​ S6, the target detection result is packaged by the SRIO encoding module and transmitted to the control module for storage, and transmitted to the host computer for real-time display.

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