A memory allocation system and a server

Abstract

The present invention relates to a memory allocation system and a server. The system includes: a main board including a baseboard management controller, a complex programmable logic device, and multiple central processing units, where the baseboard management controller is used to monitor the memory demand status of each central processing unit; a conversion board including a CXL protocol conversion chip and several DIMM slots for inserting memory, and the several DIMM slots are respectively connected to several CXL output pins of the CXL protocol conversion chip; a first connection component configured to connect the PCIE pins of each central processing unit to several PCIE input pins of the CXL protocol conversion chip; a second connection component configured to connect the baseboard management controller and the complex programmable logic device to the control pins of the CXL protocol conversion chip to adjust the memory of each central processing unit based on the memory demand status. The solution of the present invention pools the memory, increasing the memory capacity and enabling dynamic adjustment of the memory of each central processing unit.

Description

Technical Field

[0001] The present invention relates to hardware circuit design, and particularly to a memory allocation system and a server. Background Art

[0002] The Gen-Z Alliance has developed a new architecture aimed at solving certain problems in memory and computer interconnectivity. The emergence of GEN-Z is accompanied by the construction of data centers. However, with the development of the entire computer architecture, this architecture has significant drawbacks. With the development of technology, the requirements for information transmission rate, power consumption of computing nodes, and storage specifications have led to the trend of pooling and separating each node in the entire data center, which will break the layout of storage, memory, and processors in one box. Once they are separated into different boxes due to heat dissipation or other reasons, GEN-Z will be similar to a connector, so its design drawbacks will go against the development of servers.

[0003] Therefore, Intel proposed a new architecture for memory pooling - the CXL (Compute ExpressLink) protocol in 2019 and attracted important members of the previous GEN-Z Alliance to the CXL Alliance. It is worth noting that several manufacturers such as AMD and Ampere have also joined this alliance. Therefore, the CXL protocol will be a development direction in the server industry. With the development of cloud computing applications, informatization has gradually covered all fields of society. People's daily work and life increasingly rely on network communication, and the network data volume is also continuously increasing. The memory of servers is also facing many challenges. Data centers are composed of a large number of servers. Dynamic Random Access Memory (DRAM) accounts for a considerable cost in each data center. Companies such as Microsoft even reach 50%. However, servers are not homogeneous, and the workload is dynamic, constantly changing and evolving.

[0004] In the existing solutions, the link for directly outputting MEMORY from the Central Processing Unit (CPU) currently uses DDR5. When the memory in the memory pool is insufficient, DDR5 is configured from 1SPC (SLOT PER CHANNEL) to 2SPC or even 3SPC, or a DDR5 memory module with a larger memory capacity is configured. Or when the memory cannot be further expanded, data is preferentially exchanged in the server to free up more memory space for use. Therefore, many chip manufacturers have added CPU interconnection channels and channels that can directly connect to DDR5 in the next generation of CPUs. In addition, the number of DIMMs (Dual-Inline-Memory-Modules) mounted will seriously affect the information transmission and data processing rate, and the up and down values are also fixed, and cannot be supplied on demand.

[0005] Please refer to Figure 1A As shown, in Intel's previous-generation platform EGS, each CPU supports 8 DIMM CHANNELs, the UPI for the interconnection of two CPUs is 4X24, and the maximum capacity of the memory pool of this two-way server (1SPC) is 4096GB (4T). In Figure 1A 's design, in addition to using the memory modules mounted on the processor itself, in some cases, CPU0 and CPU1 can also call each other's memory resources through the UPI. However Figure 1A the information transmission rate drops significantly in the design, which is unacceptable to current cloud service providers. Please refer to Figure 1B As shown, in Intel's current-generation platform BHS, each CPU supports 12 DIMM CHANNELs, the UPI for the interconnection of two CPUs is 6X24, and the maximum capacity of the memory pool of this two-way server (1SPC) is 6144GB (6T). Simply increasing the number of channels of the memory modules that each CPU can mount, the memory capacity has increased, but problems such as power consumption have also emerged, and higher requirements are needed for heat dissipation, structure, and layout wiring. With the further development of artificial intelligence and the cloud, Figure 1B the limitations of the design are getting greater and greater, and a new architecture is still needed. However Figure 1A and Figure 1B 's design has the following disadvantages: (1) Improving the process and adding channels will reach the peak as the process becomes more and more mature and cannot be further optimized. (2) The smaller the process, the more cores are stacked, and it is not easy to meet the heat dissipation requirements.

[0006] Please refer to Figure 1C As shown, DDR5 supports inserting 2 - 3 DIMMs per CHANNEL, but this will cause other adverse factors: for example, the transmission rate will theoretically drop by about 33%, and this 3SPC is just a conceptual architecture proposed in the design guide of the processor manufacturer. However, Figure 1C 's design has the following defects: (1) Difficult layout, not easy to meet the current 4U chassis. (2) It is difficult for Layout engineers to route the wires, and the design difficulty is too great. 2SPC is feasible, and 3SPC has too low feasibility. (3) When changing from 1SPC to 2SPC, the working rate of DDR will drop from 4800 - 5600MT / s of 1SPC to 4400MT / s, and the transmission delay will increase by dozens of nanoseconds, which is not advisable for commercial users such as the cloud.

[0007] Based on the above, it can be analyzed that the existing CPU memory allocation methods have the following deficiencies: First, the existing designs are difficult to meet the memory requirements of the entire cloud architecture, server ecosystem, and data center. Second, even if the memory capacity requirements are met, the required cost is too high, and users pay for product functions they do not need, resulting in poor versatility. Third, the memory pool cannot dynamically optimize and supply memory according to the changes in the server system load, resulting in poor flexibility. Summary of the Invention

[0008] In view of this, in order to address the problems existing in the existing CPU memory allocation, the present invention proposes a memory allocation system and a server.

[0009] According to the first aspect of the present invention, a memory allocation system is provided. The memory allocation system includes:

[0010] A motherboard, the motherboard includes a baseboard management controller, a complex programmable logic device, and a plurality of central processors with PCIE pins. The baseboard management controller is used to monitor the memory demand status of each central processor;

[0011] A conversion board, the conversion board includes a CXL protocol conversion chip and a plurality of DIMM slots for inserting memory. The plurality of DIMM slots are respectively connected to a plurality of CXL output pins of the CXL protocol conversion chip;

[0012] A first connection component, the first connection component is configured to connect the PCIE pins of each central processor to a plurality of PCIE input pins of the CXL protocol conversion chip;

[0013] A second connection component, the second connection component is configured to connect the baseboard management controller and the complex programmable logic device to the control pins of the CXL protocol conversion chip, so that the baseboard management controller and the complex programmable logic device adjust the allocated memory of each central processor based on the memory demand status.

[0014] In some embodiments, the motherboard includes a first central processor and a second central processor, and the first central processor and the second central processor are interconnected through a UPI bus.

[0015] In some embodiments, the first connection component includes a first Slimline interface provided on the motherboard and a second Slimline interface provided on the conversion board, and the first Slimline interface and the second Slimline interface are connected by a cable;

[0016] The PCIE pins of the first central processing unit and the second central processing unit are both connected to the first Slimline interface, and the PE0 X16 pin of the CXL protocol conversion chip is connected to the second Slimline interface.

[0017] In some embodiments, the second connection component includes a third Slimline interface disposed on the motherboard and a fourth Slimline interface disposed on the conversion board, and the third Slimline interface and the fourth Slimline interface are connected by a cable;

[0018] The baseboard management controller and the complex programmable logic device are both connected to the third Slimline interface, and the UART pin, PERST pin, and GPIO pin of the CXL protocol conversion chip are all connected to the fourth Slimline interface.

[0019] In some embodiments, the second connection component further includes a data selector disposed on the motherboard, two input / outputs of the data selector are respectively connected to the baseboard management controller and the complex programmable logic device, and the output of the data selector is connected to the fourth Slimline interface.

[0020] In some embodiments, the data selector is configured to switch the PCIE resources input to the conversion board.

[0021] In some embodiments, the data selector is further configured to:

[0022] In response to a memory emergency of one of the first central processing unit and the second central processing unit, the PCIE resources of the central processing unit with the memory emergency are used as the only input of the CXL protocol conversion chip.

[0023] In some embodiments, the number of the conversion boards is multiple, and the connection manners of the multiple conversion boards to the motherboard are the same.

[0024] In some embodiments, the central processing unit is equipped with an X86 architecture or an ARM architecture.

[0025] According to the second aspect of the present invention, a server is further provided, and the server includes the above-mentioned memory allocation system.

[0026] The above-mentioned memory allocation system and server at least have the following beneficial technical effects: pooling the memory, increasing the capacity of the memory DRAM, realizing dynamic adjustment of the memory of each central processing unit, optimizing the ratio of system cores, improving the ability to process storage and computing resources, increasing the memory density on a single system, and reducing the cost of memory resources within a unit system. Description of the Drawings

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0028] Figure 1A Schematic diagram of memory allocation for the existing EGS platform;

[0029] Figure 1B Schematic diagram of memory allocation for the existing BHS platform;

[0030] Figure 1C Schematic diagram of the existing DDR5 supporting multiple DIMMs inserted;

[0031] Figure 2 Schematic diagram of the structure of a memory allocation system provided by an embodiment of the present invention;

[0032] Figure 3A Schematic diagram of the overall structure of another memory allocation system provided by an embodiment of the present invention;

[0033] Figure 3B For Figure 3A Schematic diagram of the circuit connection on one side of the main board in

[0034] Figure 3C For Figure 3A Schematic diagram of the circuit connection on one side of the conversion board in

[0035] Figure 4 Schematic diagram of the overall structure of a memory allocation system including two conversion boards provided by another embodiment of the present invention. Detailed implementation manners

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following will further elaborate on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0037] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationships shown in the accompanying drawings. These are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations to the present invention.

[0038] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined. In addition, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] In some embodiments, please refer to Figure 2 as shown, the present invention provides a memory allocation system, which specifically includes the following structures:

[0040] A main board 100 (i.e., Main Board, abbreviated as MB), the main board 100 includes a baseboard management controller 110 (i.e., BMC), a complex programmable logic device 120 (i.e., CPLD), and a plurality of central processing units with PCIE pins, and the baseboard management controller 110 is used to monitor the memory demand status of each central processing unit;

[0041] A conversion board 200 (i.e., SWITCH BOARD), the conversion board 200 includes a CXL protocol conversion chip 210 (i.e., CXLSWITCH) and several DIMM slots 220 (i.e., DIMM SLOT) for inserting memory, and several DIMM slots 220 are respectively connected to several CXL output pins of the CXL protocol conversion chip 210;

[0042] A first connection component 300, the first connection component 300 is configured to connect the PCIE pins of each central processing unit to several PCIE input pins of the CXL protocol conversion chip 210;

[0043] A second connection component 400, the second connection component 400 is configured to connect the baseboard management controller 110 and the complex programmable logic device 120 to the control pins of the CXL protocol conversion chip 210, so that the baseboard management controller 110 and the complex programmable logic device 120 adjust the memory allocated to each central processing unit based on the memory demand status.

[0044] The above-mentioned memory allocation system has at least the following beneficial technical effects: pooling the memory, increasing the capacity of the memory DRAM, dynamically adjusting the memory of each central processing unit, optimizing the ratio of system cores, improving the ability to process storage and computing resources, increasing the memory density on a single system, and reducing the cost of memory resources within a unit system.

[0045] In some embodiments, the motherboard 100 includes a first central processing unit 130 (i.e., CPU0) and a second central processing unit 140 (i.e., CPU1), and the first central processing unit 130 and the second central processing unit 140 are interconnected through a UPI bus.

[0046] In some embodiments, please refer to Figures 3A to 3C As shown, the first connection component 300 includes a first Slimline interface SLIMLINE_1 disposed on the motherboard 100 and a second Slimline interface SLIMLINE_2 disposed on the conversion board 200, and the first Slimline interface SLIMLINE_1 and the second Slimline interface SLIMLINE_2 are connected by a cable;

[0047] The PCIE pins of the first central processing unit 130 and the second central processing unit 140 are both connected to the first Slimline interface SLIMLINE_1, and the PE0 X16 pin of the CXL protocol conversion chip 210 is connected to the second Slimline interface SLIMLINE_2.

[0048] In some embodiments, please refer to Figures 3A to 3C As shown, the second connection component 400 includes a third Slimline interface SLIMLINE_3 disposed on the motherboard 100 and a fourth Slimline interface SLIMLINE_4 disposed on the conversion board 200, and the third Slimline interface SLIMLINE_3 and the fourth Slimline interface SLIMLINE_4 are connected by a cable;

[0049] Both the baseboard management controller 110 and the complex programmable logic device 120 are connected to the third Slimline interface SLIMLINE_3, and the UART pin, PERST pin, and GPIO pin of the CXL protocol conversion chip 210 are all connected to the fourth Slimline interface SLIMLINE_4.

[0050] In some embodiments, please refer to Figures 3A to 3CAs shown, the second connection component 400 further includes a data selector SIGNAL MUX disposed on the main board 100. Two input / outputs of the data selector SIGNAL MUX are respectively connected to the baseboard management controller 110 and the complex programmable logic device, and the output of the data selector SIGNAL MUX is connected to the fourth Slimline interface SLIMLINE_4.

[0051] In some embodiments, the data selector SIGNAL MUX is configured to switch the PCIe resources input to the conversion board 200.

[0052] In some embodiments, the data selector SIGNAL MUX is further configured to: in response to a memory emergency of one of the first central processing unit 130 and the second central processing unit 140, take the PCIe resources of the central processing unit with the memory emergency as the only input of the CXL protocol conversion chip 210.

[0053] In some embodiments, please refer to Figure 4 As shown, the number of the conversion boards 200 is multiple, and the connection manners of the multiple conversion boards 200 to the main board 100 are the same.

[0054] In some embodiments, the central processing unit is equipped with an X86 architecture or an ARM architecture.

[0055] In yet another embodiment, to facilitate understanding of the solution of the present invention, the memory adjustment system of the present invention will be described in detail below in conjunction with the working principle. In order to avoid over-configuring the server, the concept of pooling memory resources is adopted to achieve dynamic allocation to solve the excessive DRAM requirements of users. Therefore, the CXL SWITCH chip using the CXL protocol can not only achieve memory expansion but also change the memory resources mounted under each processor according to the system requirements, truly pooling the memory. The memory resources in the pool can be dynamically allocated according to the system requirements, and this memory pool will communicate through the CXL protocol.

[0056] Among them, CXL 2.0 is defined based on PCIe 5.0 and allows alternative protocols to use the PCIe5.0 features of the physical PCIe layer. When a CXL accelerator or expansion card and a PCIE device are inserted into the host port at the same time, the pcie protocol 1.0 rate negotiation will be prioritized. After both parties confirm support for CXL, the CXL interconnection protocol will be activated. Using a CXL SWITCH, the physical form will be to convert the PCIE interface into a DDR5 interface and be compatible with the interconnection and expansion of PCIE. Then, there will be a greater improvement in the flexibility and scalability of memory resources and transmission.

[0057] As Figure 2As shown, according to the current latest Intel platform design, it supports the CXL 2.0 protocol. Place the CXL resource (physically PCIE 5.0) connector MCIO at the motherboard end, route other signals including (SMB, PRSNT, 100M_CLKDP\DN, etc.) to the MISC CON, connect all signals to the switch board through a cable, route them to the switch IC through internal board traces, and connect the corresponding signals to the corresponding DIMM slots after conversion. In fact, in a dual-way or multi-way system, management signals and selection signals can be sent from the CPLD or BMC, and these logic control signals are sent to the CXL switch chip through the MISC CON. When the workload of CPU0 is too large and the memory demand increases, the memory resources in the memory pool are connected to CPU0. The same processing can be done when the workload and memory demand of CPU1 increase. Just write the memory CXL conversion memory resource allocation strategy into the EEPROM that stores the BIOS CODE.

[0058] To clearly illustrate the implementation of this system in combination with Figure 3B and 3C illustrate, the following will detail the specific structures of the motherboard and the conversion:

[0059] The design of the motherboard MB end remains the current mainstream server motherboard MB end design architecture, consisting of two CPUs, BMC, CPLD, and DIMM. Just made some minor changes outside of these, added the logic control signals of the BMC and CPLD to the switch board SWITCHBOARD, and added a MUX in the middle of some logic control signals. This MUX is used to switch the source of the PCIE resources transmitted to the switch board SWITCH BOARD. When the memory of CPU0 is in an emergency, the PCIE resources of CPU0 will be enabled as the input to the CXL switch chip on the SWITCHBORAD. When the memory of CPU1 is in an emergency, the PCIE resources of CPU1 will be enabled as the input to the CXL switch chip on the SWITCHBORAD. In this way, the dynamic allocation of the memory in the memory pool can be achieved.

[0060] The design of the conversion board is as follows: slimline_4: The connector for the logic control signal routed through the cable on the main board MB. Slimline_2: The connector for the PCIE signal routed through the cable on the main board MB. I2C: The communication signal, connected to the PCA9548 on the switch board SWITCH BOARD, will convert a group of I2C into 8 groups of I2C to access each device. Currently, it accesses VR information, firmware information of the CXL SWITCH, CLOCK GENERATOR information, etc. UART: The interface for the CXL SWITCH chip to transmit the working log. Through the UART to USB HUB, it is sent to the main board MB and transmitted to the main board MB end through the USB2.0 protocol, and the LOG is printed through the USB connector. PERST: Reset the PCIE transmitted through slimline_2. GPIO: Some configuration pins of the CXL SWITCH chip. These pins can control the CXL SWITCH to work in different modes and need to be paired with a dedicated firmware to achieve. RESET: The pin used to reset the entire CXL SWITCH chip, with an external reset button. SYS_REF_CLK: The reference clock of the system. DIMM SLOT: The memory slot with a standard DDR5 interface. CLOCK GENERATOR: The device that generates a 100M clock.

[0061] The working process of the entire system or the dynamic allocation of the memory in the memory pool is implemented through the following steps:

[0062] Step 1, the AUX power of the switch board SWITCH BOARD and the AUX power of the main board MB are powered on together, and the MAIN power is also powered on together. When the PWRGD on the switch board SWITCH BOARD is sent to the main board MB, the CXL SWITCH chip starts to convert, sending the PCIE resources to the switch board SWITCH BOARD, converting them into CXL resources and then into the memory in the memory pool. In the default state, these memories will be mounted on the LEGACY-CPU, that is, CPU0. Through the current default GPIO configuration, they will be converted into the memory resources of two DIMMs. The CXL link bandwidth is x8, the capacity is 512GB, based on DDR5 design, and the maximum bandwidth reaches 32GB / s.

[0063] Step 2: Write the strategy for converting PCIe to CXL resources in advance in the EEPROM of the BMC. The system monitors and manages the entire system through the BMC. The specific communication methods are I2C and I3C. When it is found that the system memory resources are insufficient, the BMC will be informed. The BMC will send a signal to the CPLD to control the emission of logic signals, and control the MUX to control the input source of the CXL SWITCH chip. Thus, the memory can be mounted under the NON-LEGACY CPU, that is, CPU1. In this way, the expansion and dynamic allocation of memory resources in the system memory pool can be achieved.

[0064] Step 3: In addition, when the capacities of the two DIMMs cannot meet the system usage requirements, I2C will notify the BMC. The BMC will return an instruction through I2C to control the high and low levels of the GPIO of the CXL SWITCH chip, so as to control the working mode of the CXL SWICTH. The CXL signal will be expanded to 4 DIMM SLOTs to meet the system's memory requirements, and firmware adaptation is required. The port control and up / downlink rate firmware need to be properly configured in the mounted EEPROM. When the memory resources of CPU1 are insufficient, the previous step will be repeated. In this way, the expansion and dynamic allocation of memory resources in the system memory pool can be further achieved.

[0065] Step 4: Of course, the expansion of the CXL BOARD is not an unlimited expansion of memory. When it is expanded to a certain number, other problems will occur. When it exceeds a certain number, the bandwidth of CXL will not be able to meet the bandwidth requirements for expanding more DIMM ports. Subsequently, the problem is that the up / downlink rate does not meet the transmission rate of DDR5, which does not conform to the purpose and application scenario of the system design. Currently, INTEL's EGS platform and subsequent platforms will increase the number of PCIe ports, so more resources will be available, and more PCIe can be converted into CXL resources. The system design can be implemented for expansion according to the following standards: Figure 4 as shown below:

[0066] Standard 1: Using a larger slimline can connect more PCIe signals on the motherboard MB side to the conversion board SWITCH BOARD for conversion.

[0067] Standard 2: Add external connectors for other PCIE PORTs on the motherboard MB side, and connect more conversion boards SWITCH BOARD through cables.

[0068] Standard 3: When using multiple conversion boards SWITCH BOARD, also use a MUX on the motherboard MB side to control the input of the CXL SWITCH chip. In this way, the expansion and dynamic allocation of resources in the memory pool can also be achieved.

[0069] The memory adjustment system of this embodiment has the following beneficial effects:

[0070] First, it changes the layout of only placing DIMM resources at the motherboard MB end in the traditional server architecture. The DIMM resources are placed on the daughter board through a cable-connected daughter board, optimizing the layout at the motherboard MB end and the spatial structure in the close chassis.

[0071] Second, by using the CXL protocol, the PCIE resources are converted into CXL resources and then into DIMM memory resources that meet the JDEC protocol standard, expanding the capacity of the memory pool. It changes the traditional solution of converting PCIE into RSSD for storage. The data processing and information exchange rate between RSSD and the processor is 300ms, while the DIMM resources converted by CXL increase this rate to dozens of microseconds, improving by four orders of magnitude.

[0072] Third, changes are made to the hardware link and firmware. On the hardware link, the logic control of MUX with CPLD is used to complete the logic signal link for controlling the process of converting memory resources. With the adaptation made on the firmware, corresponding conversion strategies are prepared in advance in the CXLSWITCH chip and the EEPROM of BMC, enabling the server system to form a closed-loop feedback during application and realizing the dynamic allocation of memory resources in the memory pool.

[0073] Fourth, the memory resource expansion of the entire system is controllable. Memory will be converted according to system requirements, and many designs are reserved. When the system memory requirement is not large, the SLIMLINE can be converted into a standard PCIE X16 SLOT through a customized cable (paddle card) for connecting PCIE devices such as network cards, improving the resource utilization rate of the entire system.

[0074] Fifth, there is also a significant reduction in cost, not only in the ratio of DRAM to core, but also in production cost and manufacturing cost. Using different boards across boards (ultra loss for MB and very low loss for the switch board SWITCH BOARD) can reduce costs.

[0075] According to another aspect of the present invention, a server is also provided, and the server includes the above-mentioned memory allocation system.

[0076] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combinations of these technical features do not conflict, they should be considered as the scope described in this specification.

[0077] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A memory allocation system, characterized in that, The system includes: A main board, which includes a baseboard management controller, a complex programmable logic device, and multiple central processing units with PCIE pins. The baseboard management controller is used to monitor the memory demand status of each central processing unit; A conversion board, which includes a CXL protocol conversion chip and several DIMM slots for inserting memory. The several DIMM slots are respectively connected to several CXL output pins of the CXL protocol conversion chip; A first connection component, which is configured to connect the PCIE pins of each central processing unit to several PCIE input pins of the CXL protocol conversion chip; A second connection component, which is configured to connect the baseboard management controller and the complex programmable logic device to the control pins of the CXL protocol conversion chip, so that the baseboard management controller and the complex programmable logic device adjust the memory allocated to each central processing unit based on the memory demand status; The second connection component includes a third Slimline interface provided on the main board and a fourth Slimline interface provided on the conversion board. The third Slimline interface and the fourth Slimline interface are connected by a cable; Both the baseboard management controller and the complex programmable logic device are connected to the third Slimline interface. The UART pin, PERST pin, and GPIO pin of the CXL protocol conversion chip are all connected to the fourth Slimline interface.

2. The memory allocation system according to claim 1, wherein The main board includes a first central processing unit and a second central processing unit. The first central processing unit and the second central processing unit are interconnected through a UPI bus.

3. The memory allocation system according to claim 2, wherein The first connection component includes a first Slimline interface provided on the main board and a second Slimline interface provided on the conversion board. The first Slimline interface and the second Slimline interface are connected by a cable; The PCIE pins of the first central processing unit and the second central processing unit are both connected to the first Slimline interface. The PE0 X16 pin of the CXL protocol conversion chip is connected to the second Slimline interface.

4. The memory allocation system according to claim 1, characterized in that, The second connection component further includes a data selector provided on the main board. The two input-outputs of the data selector are respectively connected to the baseboard management controller and the complex programmable logic device. The output of the data selector is connected to the fourth Slimline interface.

5. The memory allocation system according to claim 4, wherein The data selector is configured to switch the PCIE resources input to the conversion board.

6. The memory allocation system according to claim 5, wherein The data selector is further configured to: In response to a memory emergency of one of the first central processing unit and the second central processing unit, use the PCIE resources of the central processing unit with the memory emergency as the only input to the CXL protocol conversion chip.

7. The memory allocation system according to claim 5, wherein The number of the conversion boards is multiple, and the connection methods of the multiple conversion boards to the main board are the same.

8. The memory allocation system according to claim 1, wherein The central processing unit is equipped with an X86 architecture or an ARM architecture.

9. A server, characterized in that, The server includes the memory allocation system according to any one of claims 1-8.

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