A method, apparatus and quantum computer for constructing a quantum program to be mapped

Abstract

The application discloses a kind of methods for constructing to be mapped quantum program, device and quantum computer, method includes: obtaining the topology structure of physical bit in quantum chip, initial quantum program's logic gate set and the initial mapping relationship of logic bit and physical bit, determine the execution timing of initial quantum program's logic gate set, according to the topology structure of physical bit and initial mapping relationship, the mapping relationship of each logic gate corresponding logic bit and physical bit is adjusted according to execution timing, obtain final mapping relationship, according to final mapping relationship, construct and initial quantum program identical to-be mapped quantum program, to make the number of SWAP quantum logic gate in to-be mapped quantum program least, solve the influence of increasing SWAP gate to the whole quantum circuit operation, improve the resource utilization of whole quantum chip.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum computing, and particularly relates to a method and device for constructing a quantum program to be mapped and a quantum computer. BACKGROUND

[0002] In the noisy intermediate-scale quantum (NISQ) stage, each quantum chip has its own specific topology, which reflects the connection relationship between the quantum bits supported by the quantum chip. In actual quantum programming, after obtaining the logical gate set of the quantum program and the initial mapping of the logical-physical bits, the two-qubit logical gate implemented on two adjacent quantum bits may be limited by the chip structure, and the two-qubit logical gate cannot be adapted to two quantum bits to form a two-qubit logical gate. Therefore, it is necessary to exchange and transform any two-qubit logical gate until it is transformed into a quantum logical gate supported by the chip.

[0003] In the prior art, for a two-qubit quantum logical gate that cannot be adapted to two quantum bits on a quantum chip, a SWAP gate is added to the quantum program to transform the two-qubit quantum logical gate that cannot be adapted into a quantum logical gate supported by the chip. For example, the quantum program includes a CNOT(q1, q3) quantum logical gate. Although the quantum chip supports the CNOT gate, the physical quantum bits q1 and q3 in the quantum chip are not directly connected, and therefore cannot be directly executed. Therefore, the two-qubit logical gate in the quantum program needs to be exchanged to a quantum logical gate that can be directly executed by the chip. For example, the quantum program includes CNOT(q1, q3). The existing exchange method is briefly described as follows: according to the connection relationship between the quantum bits on the quantum chip, the connection path between the two quantum bits q1 and q3 of the CNOT operation is found. Assuming that the quantum bits on the path are q1, q2, then CNOT(q1, q3) is equivalent to sequentially executing: SWAP(q1, q2), SWAP(q2, q3), CNOT(q2, q3), SWAP(q3, q2), and SWAP(q2, q1). The SWAP gate represents an exchange operation on the quantum bits. As can be seen, in order to adapt to the quantum chip, the exchange process will add a large number of quantum logical gates to a two-qubit logical gate, and the number of quantum logical gates in the quantum program after transformation will be larger, thereby greatly reducing the computing efficiency of the quantum program.

[0004] Therefore, it is necessary to provide an optimal scheme for constructing a quantum program to be mapped, which is used to solve the influence of adding SWAP gates on the operation of the entire quantum circuit and improve the resource utilization rate of the entire quantum chip. SUMMARY

[0005] The application aims to provide a method and device for constructing a quantum program to be mapped and a quantum computer, so as to solve the problem of the influence of the increase of SWAP gates on the operation of the whole quantum circuit and improve the resource utilization rate of the whole quantum chip.

[0006] One embodiment of the application provides a method for constructing a quantum program to be mapped, which comprises the following steps:

[0007] obtaining the topology of physical bits in a quantum chip, a logical gate set of an initial quantum program and an initial mapping relationship between logical bits and physical bits;

[0008] determining the execution time sequence of the logical gate set of the initial quantum program;

[0009] adjusting the mapping relationship between logical bits and physical bits corresponding to each logical gate according to the topology of the physical bits and the initial mapping relationship and in the execution time sequence to obtain a final mapping relationship;

[0010] constructing a quantum program to be mapped which is equivalent to the initial quantum program according to the final mapping relationship, so that the number of SWAP quantum logical gates in the quantum program to be mapped is minimized.

[0011] Optionally, the logical gate set of the initial quantum program comprises:

[0012] a first rule logical gate set, wherein the first rule logical gate set comprises single-bit quantum logical gates and two-bit quantum logical gates whose logical bits are adjacent;

[0013] a second rule logical gate set, wherein the second rule logical gate set comprises two-bit quantum logical gates whose logical bits are not adjacent.

[0014] Optionally, the determination of the execution time sequence of the logical gate set of the initial quantum program comprises:

[0015] obtaining a quantum circuit corresponding to the initial quantum program;

[0016] traversing the quantum circuit, setting the execution time sequence of the first rule logical gate set of each quantum bit in the first time sequence as a priority execution time sequence and setting the execution time sequence of the second rule logical gate set of each quantum bit in the first time sequence as a sub-priority execution time sequence;

[0017] deleting the logical gates whose execution time sequence division is completed and continuing to execute the step of setting the execution time sequence of the first rule logical gate set of each quantum bit in the first time sequence as a priority execution time sequence and setting the execution time sequence of the second rule logical gate set of each quantum bit in the first time sequence as a sub-priority execution time sequence until the execution time sequence division of the logical gates of the quantum circuit is completed.

[0018] Optionally, the adjusting, according to the topology of the physical bits and the initial mapping relationship, of the mapping relationship between the logical bits and the physical bits corresponding to each logic gate in the execution sequence, to obtain a final mapping relationship, comprises:

[0019] According to the topology of the physical bits, the initial mapping relationship, and the execution sequence, traversing each logic gate in a forward direction and adjusting the physical bits mapped by each logic gate under a previous mapping relationship, the previous mapping relationship is adjusted until the forward traversal is completed, and a target forward mapping relationship is obtained.

[0020] According to the target forward mapping relationship, traversing each logic gate in a reverse direction according to the execution sequence and adjusting the physical bits mapped by each logic gate under a previous mapping relationship, the previous mapping relationship is adjusted until a target reverse mapping relationship is obtained after the reverse traversal is completed, which is taken as the final mapping relationship.

[0021] Optionally, the constructing, according to the final mapping relationship, of a to-be-mapped quantum program equivalent to the initial quantum program, comprises:

[0022] According to the final mapping relationship, inserting a SWAP quantum logic gate corresponding to each logic gate in the quantum logic gate set according to the execution sequence, and determining the quantum program obtained after the insertion as the to-be-mapped quantum program equivalent to the initial quantum program.

[0023] One embodiment of the present application provides a device for constructing a to-be-mapped quantum program, which comprises:

[0024] An acquisition module is configured to acquire a topology of physical bits in a quantum chip, a logic gate set of an initial quantum program, and an initial mapping relationship between logical bits and physical bits.

[0025] A determination module is configured to determine an execution sequence of the logic gate set of the initial quantum program.

[0026] An adjustment module is configured to adjust, according to the topology of the physical bits and the initial mapping relationship, the mapping relationship between the logical bits and the physical bits corresponding to each logic gate in the execution sequence, to obtain a final mapping relationship.

[0027] A construction module is configured to construct, according to the final mapping relationship, a to-be-mapped quantum program equivalent to the initial quantum program, so that the number of SWAP quantum logic gates in the to-be-mapped quantum program is minimized.

[0028] Optionally, the determination module comprises:

[0029] An acquisition unit is configured to acquire a quantum circuit corresponding to an initial quantum program.

[0030] traversing the quantum circuit, setting an execution time of a first set of regular logic gates of each quantum bit in the first time sequence as a priority execution time, and setting an execution time of a second set of regular logic gates of each quantum bit in the first time sequence as a sub-priority execution time;

[0031] iterating the step of setting the execution time of the first set of regular logic gates of each quantum bit in the first time sequence as the priority execution time, and setting the execution time of the second set of regular logic gates of each quantum bit in the first time sequence as the sub-priority execution time until the execution time of the quantum circuit logic gate is divided.

[0032] Optionally, the adjusting module comprises:

[0033] the first execution unit is configured to traverse each logic gate in the forward direction according to the topology of the physical bits and the initial mapping relationship, and adjust the physical bit mapped by each logic gate under a previous mapping relationship, and adjust the previous mapping relationship until the forward traversal is completed to obtain a target forward mapping relationship;

[0034] the second execution unit is configured to traverse each logic gate in the reverse direction according to the target forward mapping relationship, and adjust the physical bit mapped by each logic gate under a previous mapping relationship, and adjust the previous mapping relationship until a target reverse mapping relationship obtained after the reverse traversal is completed is taken as the final mapping relationship.

[0035] Optionally, the constructing module comprises:

[0036] the inserting unit is configured to insert a SWAP quantum logic gate corresponding to each logic gate running according to the execution time into a corresponding position in the set of quantum logic gates according to the final mapping relationship, and determine the quantum program obtained after the insertion as a to-be-mapped quantum program equivalent to the initial quantum program.

[0037] Yet another embodiment of the present application provides a storage medium having a computer program stored therein, wherein the computer program is configured to execute the method described in any of the above embodiments when running.

[0038] Yet another embodiment of the present application provides an electronic device comprising a memory and a processor, wherein the memory has a computer program stored therein, and the processor is configured to execute the computer program to execute the method described in any of the above embodiments.

[0039] Yet another embodiment of the present application provides a quantum computer operating system, which is configured to implement the method according to any one of the above embodiments to build a quantum program to be mapped.

[0040] Yet another embodiment of the present application provides a quantum computer, which comprises the quantum computer operating system.

[0041] Compared with the prior art, the present application first acquires the topology of physical bits in a quantum chip, a set of logical gates of an initial quantum program, and an initial mapping relationship between logical bits and physical bits, determines the execution timing of the set of logical gates of the initial quantum program, adjusts the mapping relationship between logical bits and physical bits corresponding to each logical gate according to the topology of physical bits and the initial mapping relationship according to the execution timing, obtains a final mapping relationship, and builds a quantum program to be mapped which is equivalent to the initial quantum program according to the final mapping relationship, so as to minimize the number of SWAP quantum logical gates in the quantum program to be mapped, solve the problem of the influence of the increase of SWAP gates on the operation of the entire quantum circuit, and improve the resource utilization rate of the entire quantum chip. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A hardware structure block diagram of a computer terminal for a method for building a quantum program to be mapped according to an embodiment of the present application is provided.

[0043] Figure 2 A flowchart of a method for building a quantum program to be mapped according to an embodiment of the present application is provided.

[0044] Figure 3 A topology diagram of physical bits of a quantum chip according to an embodiment of the present application is provided.

[0045] Figure 4 A quantum circuit diagram corresponding to an initial quantum program according to an embodiment of the present application is provided.

[0046] Figure 5 A quantum program to be mapped which is equivalent to an initial quantum program according to an embodiment of the present application is provided.

[0047] Figure 6 A structure diagram of a device for building a quantum program to be mapped according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0048] The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as a limitation on the present application.

[0049] The embodiments of the present application first provide a method for building a quantum program to be mapped, which can be applied to electronic devices such as computer terminals, specifically, common computers, quantum computers, etc.

[0050] The following will be described in detail taking a computer terminal as an example. Figure 1 A hardware structure block diagram of a computer terminal for providing a method of constructing a quantum program to be mapped is provided. As shown in the figure, the computer terminal can include one or more (only one is shown in the figure) processors 102 (the processor 102 can include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. Optionally, the above computer terminal can also include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that the structure shown in the figure is only illustrative, and does not limit the structure of the above computer terminal. For example, the computer terminal can also include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 1 Figure 1 The computer terminal can also include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 1 Figure 1 The computer terminal can also include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 1 The memory 104 can be used to store software programs and modules of application software, such as program instructions / modules corresponding to the method of constructing a quantum program to be mapped in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implements the above method. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the computer terminal through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0051] The transmission device 106 is used to receive or send data via a network. Specific examples of the above network can include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to be able to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet in a wireless manner.

[0052]

[0053] ​​​It should be noted that the real quantum computer is a hybrid structure, which includes two parts: one part is a classical computer responsible for performing classical computing and control; the other part is a quantum device responsible for running a quantum program to realize quantum computing. The quantum program is a sequence of instructions written in a quantum language such as QRunes language that can run on a quantum computer, which realizes the support for quantum logic gate operations and finally realizes quantum computing. Specifically, the quantum program is a sequence of instructions for operating quantum logic gates in a certain time sequence.

[0054] In practical applications, due to the limitation of the development of quantum device hardware, quantum computing simulation is usually needed to verify quantum algorithms, quantum applications, etc. Quantum computing simulation is a process of simulating the running of a quantum program corresponding to a specific problem by means of the resources of an ordinary computer (i.e. a quantum virtual machine). Usually, a quantum program corresponding to a specific problem needs to be constructed. The quantum program referred to in the embodiments of the present application is a program written in a classical language representing qubits and their evolution, in which quantum bits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.

[0055] As an embodiment of a quantum program, a quantum circuit, also known as a quantum logic circuit, is the most commonly used general quantum computing model, representing a circuit for operating qubits in an abstract concept, which consists of qubits, circuits (time lines), and various quantum logic gates, and finally the results need to be read out through quantum measurement operations.

[0056] Unlike traditional circuits connected by metal wires to transmit voltage signals or current signals, in a quantum circuit, the circuit can be regarded as being connected by time, that is, the state of the qubit naturally evolves with time, and in this process, it is operated according to the instructions of the Hamiltonian operator until it encounters a logic gate.

[0057] A quantum program corresponds to a total quantum circuit as a whole, and the quantum program described in the present application refers to the total quantum circuit, wherein the total number of qubits in the total quantum circuit is the same as the total number of qubits of the quantum program. It can be understood that: a quantum program can be composed of a quantum circuit, a measurement operation for the qubits in the quantum circuit, a register for storing the measurement results, and a control flow node (jump instruction), and a quantum circuit can contain tens, hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is the process of executing all quantum logic gates in a certain time sequence. It should be noted that the time sequence is the time order in which the single quantum logic gate is executed.

[0058] It should be noted that in classical computing, the most basic unit is a bit, and the most basic control mode is a logic gate, which can be combined to achieve the purpose of controlling the circuit. Similarly, the way to handle quantum bits is quantum logic gates. Using quantum logic gates, quantum states can evolve, and quantum logic gates are the basis of quantum circuits, including single-bit quantum logic gates such as Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, and the like; multi-bit quantum logic gates such as CNOT gate, CR gate, iSWAP gate, Toffoli gate, and the like. Quantum logic gates are generally represented by unitary matrices, which are not only in matrix form but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the quantum state right vector corresponding matrix on the left.

[0059] The quantum state, i.e., the logical state of the quantum bit, is represented in binary in quantum algorithms (or quantum programs), for example, a group of quantum bits q0, q1, q2 represents the 0th, 1st, and 2nd quantum bits, and the order from high to low is q2q1q0. The quantum state corresponding to the group of quantum bits is the superposition of the eigenstates corresponding to the group of quantum bits. The eigenstates corresponding to the group of quantum bits have 2 raised to the power of the total number of quantum bits, i.e., 8 eigenstates (determined states): |000>, |001>, |010>, |011>, |100>, |101>, |110>, |111>, each eigenstate corresponds to a bit corresponding to a quantum bit, such as |000> state, 000 corresponds to q2q1q0 from high to low, and |> is the Dirac symbol.

[0060] Taking a single quantum bit as an example, the logical state of a single quantum bit may be in the |0> state, the |1> state, the superposition state (indeterminate state) of the |0> state and the |1> state, which can be represented as where c and d are complex numbers representing the amplitude (probability amplitude) of the quantum state, and the square of the amplitude c 2 and d 2 represent the probability of the |0> state and the |1> state, respectively, |c| 2 +|d| 2 =1. In short, the quantum state is a superposition of eigenstates, and when the probability of other eigenstates is 0, it is in a unique eigenstate.

[0061] Referring to Figure 2 , Figure 2 is a flowchart of a method for constructing a quantum program to be mapped according to an embodiment of the present application.

[0062] The embodiment of the present application provides a method for constructing a quantum program to be mapped, which comprises the following steps:

[0063] S201: acquiring a topology structure of physical bits in a quantum chip, a logical gate set of an initial quantum program, and an initial mapping relationship between logical bits and the physical bits.

[0064] Specifically, each quantum chip has a specific topology structure, and the topology structure reflects the entanglement relationship between the physical bits supported by the quantum chip. At present, the number of physical bits of the quantum chip is limited, and the chip topology structure is simple, and usually exists in the form of a simple two-dimensional chain (or one-dimensional chain). For a certain physical bit in the quantum chip, it can only be connected with a limited number of physical bits.

[0065] For example, referring to Figure 3 , Figure 3 A topology structure diagram of physical bits of a quantum chip is provided in the embodiment of the present application, and the quantum chip comprises eight physical bits, namely Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6] and Q[7]. The eight physical bits can be coupled by capacitors, and only adjacent physical bits have a coupling relationship. Q[0] is connected with Q[1] and Q[4], Q[5] is connected with Q[1], Q[4] and Q[6], Q[2] is connected with Q[1], Q[6] and Q[3], and Q[7] is connected with Q[3] and Q[6].

[0066] The logical gate set of the initial quantum program mainly comprises tens, hundreds or even thousands of quantum logical gates. Specifically, the logical gate set of the initial quantum program comprises a first rule logical gate set and a second rule logical gate set. The first rule logical gate set comprises a single-bit quantum logical gate and a two-bit quantum logical gate of adjacent logical bits. The second rule logical gate set comprises a two-bit quantum logical gate of non-adjacent logical bits. The execution process of the initial quantum program is a process of executing all quantum logical gates in a certain time sequence. It should be noted that the distance between two quantum bits can be used to determine whether the two-bit quantum logical gate is adjacent, and the distance between two quantum bits can be represented by the number of quantum bits between the two quantum bits. For example Figure 3As shown, there are 0 quantum bits between quantum bits Q[0] and Q[1], so the distance therebetween can be represented as 0; there are 1 quantum bit between quantum bits Q[1] and Q[3], so the distance therebetween can be represented as 1; and there are 2 quantum bits between quantum bits Q[0] and Q[3], so the distance therebetween can be represented as 2. Thus, by determining whether the distance between two quantum bits is 0, it can be determined whether the two bits of the quantum logic gate are adjacent.

[0067] For the sake of distinction, the quantum bit structure in the quantum chip is generally referred to as a physical bit, and the object bit operated in the quantum circuit is referred to as a logical bit. The initial mapping relationship between the logical bit and the physical bit refers to the relationship in which the bits correspond to each other between the logical bit and the physical bit.

[0068] For example, for a segment of initial quantum program CNOT(q[0], q[1]) << CNOT(q[2], q[4]) << CNOT(q[0], q[2]) << CNOT(q[2], q[4]) << CNOT(q[1], q[3]), the logical bits operated thereon are q[0], q[1], q[2], q[3], and q[4], and the initial mapping relationship between the logical bit and the physical bit can be set as q[0] corresponding to Q[0], q[1] corresponding to Q[1], q[2] corresponding to Q[2], q[3] corresponding to Q[3], and q[4] corresponding to Q[4], and the like.

[0069] S202: Determine the execution timing of the initial quantum program.

[0070] Specifically, the timing refers to the time sequence in which a single quantum logic gate is executed, and determining the execution timing of the initial quantum program includes:

[0071] S2021: Obtain a quantum circuit corresponding to the initial quantum program.

[0072] For example, as shown in FIG. 2, Figure 4 Figure 4 FIG. 2 is a schematic diagram of a quantum circuit corresponding to an initial quantum program according to an embodiment of the present application. The quantum circuit corresponds to a segment of initial quantum program CNOT(q[0], q[1]) << CNOT(q[2], q[4]) << CNOT(q[0], q[2]) << CNOT(q[2], q[4]) << CNOT(q[1], q[3]).

[0073] S2022: Traverse the quantum circuit, and set the execution timing of the first rule logic gate set of the first timing of each quantum bit as a priority execution timing, and set the execution timing of the second rule logic gate set of the first timing of each quantum bit as a sub-priority execution timing. ​

[0074] For example, the quantum circuit shown in Figure 4 is traversed, where the first-timed logical gate is CNOT(q[0], q[1]), the second-timed logical gate is CNOT(q[2], q[4]), the third-timed logical gate is CNOT(q[0], q[2]), and the fourth-timed logical gate is CNOT(q[2], q[4]). Thus, the first-timed logical gate set of each quantum bit is CNOT(q[0], q[1]) and CNOT(q[2], q[4]), where CNOT(q[0], q[1]) meets the characteristics of the first rule logical gate and its execution time is set as the priority execution time; and CNOT(q[2], q[4]) meets the characteristics of the second rule logical gate and its execution time is set as the sub-priority execution time.

[0075] S2023: deleting the logical gate whose execution time division is completed, and continuing to perform the step of setting the execution time of the first-timed first rule logical gate set of each quantum bit as the priority execution time and setting the execution time of the first-timed second rule logical gate set of each quantum bit as the sub-priority execution time until the execution time division of the quantum circuit logical gate is completed.

[0076] For example, the above example is continued, and the logical gate whose execution time division is completed is deleted, i.e., CNOT(q[0], q[1]) and CNOT(q[2], q[4]) are deleted, at this time, the first-timed logical gate is CNOT(q[0], q[2]), the second-timed logical gate is CNOT(q[2], q[4]), and the third-timed logical gate is CNOT(q[1], q[3]), at this time, the step of setting the execution time of the first-timed first rule logical gate set of each quantum bit as the priority execution time and setting the execution time of the first-timed second rule logical gate set of each quantum bit as the sub-priority execution time is continued to be performed, thus, CNOT(q[0], q[2]), CNOT(q[2], q[4]), and CNOT(q[1], q[3]) are all set as the sub-priority execution time, and the execution time division is completed.

[0077] It should be noted that the initial quantum program can include single-bit quantum logic gates, two-bit quantum logic gates and multi-bit quantum logic gates, but before determining the execution order of the initial quantum program logic gate set, the multi-bit quantum logic gate needs to be first converted into a combination of single-bit quantum logic gates and two-bit quantum logic gates. Since the single-bit quantum logic gate can directly map the logical bit to the physical bit, the single-bit quantum logic gate obtained after conversion and the single quantum logic gate originally existing in the quantum program to be executed before conversion can be deleted (or preferentially executed), and then based on the two-bit quantum logic gate obtained after conversion and the two-bit quantum logic gate originally existing in the initial quantum program before conversion, the execution time sequence of the logic gate set of the initial quantum program is determined. Here, in order to facilitate the description, the above example is only exemplified by a quantum circuit containing two-bit quantum logic gates.

[0078] S203: According to the topology of the physical bit and the initial mapping relationship, the mapping relationship between the logical bit and the physical bit corresponding to each logic gate is adjusted according to the execution time sequence to obtain a final mapping relationship.

[0079] Specifically, according to the topology of the physical bit, the initial mapping relationship, and the execution time sequence, each logic gate is forward traversed and the physical bit mapped by each logic gate under the previous mapping relationship is adjusted, the previous mapping relationship is adjusted, until the forward traversal according to the execution time sequence is completed, and a target forward mapping relationship is obtained.

[0080] For example, according to the topology of the physical bit, the initial mapping relationship, and the execution time sequence, each logic gate is forward traversed and the physical bit mapped by each logic gate under the previous mapping relationship is adjusted, the previous mapping relationship is adjusted, until the forward traversal according to the execution time sequence is completed, and a target forward mapping relationship is obtained. Figure 3The topology of the physical bits, the initial mapping relationship q[0] corresponds to Q[0], q[1] corresponds to Q[1], q[2] corresponds to Q[2], q[3] corresponds to Q[3], q[4] corresponds to Q[4], and the execution time sequence is traversed in a forward direction CNOT(q[0], q[1]), CNOT(q[2], q[4]), CNOT(q[0], q[2]), CNOT(q[2], q[4]), CNOT(q[1], q[3]). First, CNOT(q[0], q[1]) is traversed in a forward direction according to the execution time sequence, and since the logical bits are adjacent, the current mapping relationship does not change; when traversing to CNOT(q[2], q[4]), in one possible solution: by inserting a SWAP logic gate between Q[4] and Q[0], and then inserting a SWAP logic gate between Q[0] and Q[1], the logical bit q[4] is mapped to the physical bit Q[1], so that CNOT(q[2], q[4]) can be executed, and the mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[2]--Q[2], q[3]--Q[3], q[4]--Q[1]; continue to traverse to CNOT(q[0], q[2]), based on the current mapping relationship, a SWAP logic gate can be inserted between Q[2] and Q[3] to map the logical bit q[2] to the physical bit Q[3], so that CNOT(q[0], q[2]) can be executed, and the mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[3]--Q[2], q[2]--Q[3], q[4]--Q[1]; continue to traverse to CNOT(q[2], q[4]), based on the current mapping relationship, a SWAP logic gate can be inserted between Q[2] and Q[3] to map the logical bit q[2] to the physical bit Q[2], so that CNOT(q[2], q[4]) can be executed, and the mapping relationship at this time is q[0]--Q[4], q[1]--Q[0], q[2]--Q[2], q[3]--Q[3], q[4]--Q[1]; continue to traverse to CNOT(q[1], q[3]), based on the current mapping relationship, a SWAP logic gate can be inserted between Q[2] and Q[3], and then a SWAP logic gate can be inserted between Q[1] and Q[2] to map the logical bit q[3] to the physical bit Q[1], so that CNOT(q[1], q[3]) can be executed, and the target forward mapping relationship obtained at this time is q[0]--Q[4], q[1]--Q[0], q[4]--Q[2], q[2]--Q[3], q[3]--Q[1].

[0081] According to the target forward mapping relationship, each logical gate is traversed in reverse according to the execution time sequence, and the physical bit mapped by each logical gate under the previous mapping relationship is adjusted, the previous mapping relationship is adjusted until a target reverse mapping relationship obtained after the reverse traversal according to the execution time sequence is completed is taken as the final mapping relationship.

[0082] According to the above example, the target forward mapping relationship is q[0]--Q[4], q[1]--Q[0], q[4]--Q[2], q[2]--Q[3], q[3]--Q[1], the CNOT(q[1], q[3]), CNOT(q[2], q[4]), CNOT(q[0], q[2]), CNOT(q[2], q[4]) and CNOT(q[0], q[1]) are traversed in reverse according to the execution time sequence, the physical bit mapped by each logical gate under the previous mapping relationship is adjusted, such as adjusting the physical bit mapped by CNOT(q[1], q[3]) under the current target forward mapping relationship, then adjusting the previous mapping relationship, that is, the current target forward mapping relationship, and continuing to adjust the physical bit mapped by each logical gate under the previous mapping relationship, until the target reverse mapping relationship obtained after the reverse traversal according to the execution time sequence is completed, that is: q[0]--Q[4], q[1]--Q[0], q[4]--Q[2], q[2]--Q[3], q[3]--Q[1], is taken as the final mapping relationship.

[0083] S204: According to the final mapping relationship, a to-be-mapped quantum program equivalent to the initial quantum program is constructed, so that the number of SWAP quantum logic gates in the to-be-mapped quantum program is minimized.

[0084] Specifically, according to the final mapping relationship, the SWAP quantum logic gate corresponding to each logical gate generated according to the execution time sequence is inserted into the corresponding position in the quantum logic gate set, and the quantum program obtained after the insertion is determined as the to-be-mapped quantum program equivalent to the initial quantum program.

[0085] Exemplarily, the SWAP quantum logic gate corresponding to each logical gate generated according to the execution time sequence is inserted into the corresponding position in the quantum logic gate set. Referring to Figure 5 , Figure 5The schematic diagram of the to-be-mapped quantum program equivalent to the initial quantum program provided by the embodiment of the present application is obtained by inserting a SWAP logic gate between Q[4] and Q[0], and then inserting a SWAP logic gate between Q[0] and Q[1], so as to map the logical bit q[4] to the physical bit Q[1]. The logical bit q[2] is mapped to the physical bit Q[3] by inserting a SWAP logic gate between Q[2] and Q[3]. The logical bit q[2] is mapped to the physical bit Q[2] by inserting a SWAP logic gate between Q[2] and Q[3]. The logical bit q[2] is mapped to the physical bit Q[2] by inserting a SWAP logic gate between Q[2] and Q[3], and then inserting a SWAP logic gate between Q[1] and Q[2], so as to obtain the to-be-mapped quantum program equivalent to the initial quantum program, so as to minimize the number of SWAP quantum logic gates in the to-be-mapped quantum program. The black dots in the figure represent the control bits of the CNOT gate, the "+" in the black circle represents the target bit of the CNOT gate, and the two "X"s are connected by a vertical line, which represents the schematic diagram of the SWAP logic gate.

[0086] It should be noted that there are many schemes for introducing SWAP logic gates between two non-adjacent bits, but the fidelity, noise and the like of each scheme are different. Only by selecting a scheme with fewer introduced SWAP logic gates and high fidelity can the execution accuracy of the to-be-executed quantum circuit be effectively ensured, and if the logical bits with less operation are mapped to the physical bits with shorter decoherence time during the mapping process, the physical bit resource utilization can be maximized, and the operation accuracy of the quantum circuit is also improved. Therefore, by selecting a scheme with high fidelity, fewer introduced SWAP logic gates, and mapping logical bits with less operation to physical bits with shorter decoherence time, the execution accuracy of the quantum circuit can be effectively ensured.

[0087] Compared with the prior art, the present application first acquires the topology of the physical bits in the quantum chip, the initial quantum program, the logical gate set of the initial quantum program, and the initial mapping relationship between the logical bits and the physical bits, determines the execution time sequence of the logical gate set of the initial quantum program, adjusts the mapping relationship between the logical bits and the physical bits corresponding to each logical gate according to the topology of the physical bits and the initial mapping relationship according to the execution time sequence, obtains the final mapping relationship, and constructs a to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship, so as to minimize the number of SWAP quantum logic gates in the to-be-mapped quantum program, solve the problem of the influence of the added SWAP gate on the operation of the entire quantum circuit, and improve the resource utilization rate of the entire quantum chip.

[0088] Referring to Figure 6 , Figure 6 The structure schematic diagram of the device for constructing the to-be-mapped quantum program provided by the embodiment of the present application corresponds to the flow shown in Figure 2 , and the device can include:

[0089] The acquisition module 601 is configured to acquire a topology of physical bits in a quantum chip, a set of logical gates of an initial quantum program, and an initial mapping relationship between logical bits and the physical bits.

[0090] The determination module 602 is configured to determine an execution timing of the set of logical gates of the initial quantum program.

[0091] The adjustment module 603 is configured to adjust, according to the topology of the physical bits and the initial mapping relationship, a mapping relationship between logical bits and physical bits corresponding to each logical gate according to the execution timing, to obtain a final mapping relationship.

[0092] The construction module 604 is configured to construct a to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship, so that a number of SWAP quantum logical gates in the to-be-mapped quantum program is minimized.

[0093] Specifically, the determination module comprises:

[0094] The acquisition unit is configured to acquire a quantum circuit corresponding to an initial quantum program.

[0095] The traversal unit is configured to traverse the quantum circuit, set an execution timing of a first set of regular logical gates of each quantum bit at a first timing as a priority execution timing, and set an execution timing of a second set of regular logical gates of each quantum bit at the first timing as a sub-priority execution timing.

[0096] The iteration unit is configured to delete a logical gate whose execution timing division is completed, and continue to execute the step of setting the execution timing of the first set of regular logical gates of each quantum bit at the first timing as the priority execution timing, and setting the execution timing of the second set of regular logical gates of each quantum bit at the first timing as the sub-priority execution timing, until the execution timing division of the logical gate of the quantum circuit is completed.

[0097] Specifically, the adjustment module comprises:

[0098] The first execution unit is configured to forwardly traverse each logical gate according to the topology of the physical bits, the initial mapping relationship, and the execution timing, and adjust a physical bit mapped by the each logical gate under a previous mapping relationship, and adjust the previous mapping relationship, until forward traversal is completed according to the execution timing, to obtain a target forward mapping relationship.

[0099] The second execution unit is configured to backwardly traverse each logical gate according to the target forward mapping relationship and the execution timing, and adjust a physical bit mapped by the each logical gate under a previous mapping relationship, and adjust the previous mapping relationship, until a target backward mapping relationship obtained after backward traversal according to the execution timing is obtained as the final mapping relationship.

[0100] Specifically, the construction module comprises:

[0101] The insertion unit is configured to insert, according to the final mapping relationship, a SWAP quantum logic gate corresponding to each logic gate running according to the execution time sequence into a corresponding position in the set of quantum logic gates, and determine the quantum program obtained after the insertion as the to-be-mapped quantum program equivalent to the initial quantum program.

[0102] Compared with the prior art, the present application first acquires the topology of physical bits in a quantum chip, a set of logic gates of an initial quantum program, and an initial mapping relationship between logic bits and physical bits, determines an execution time sequence of the set of logic gates of the initial quantum program, adjusts the mapping relationship between the logic bits and the physical bits corresponding to each logic gate according to the topology of the physical bits and the initial mapping relationship, obtains a final mapping relationship, and constructs a to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship, so as to minimize the number of SWAP quantum logic gates in the to-be-mapped quantum program, solve the problem of the influence of the increase of SWAP gates on the operation of the entire quantum circuit, and improve the resource utilization rate of the entire quantum chip.

[0103] The embodiment of the present application also provides a storage medium, wherein the storage medium stores a computer program, and the computer program is set to execute the steps in the method embodiment of any one of the above.

[0104] Specifically, in the embodiment, the storage medium can be set to store a computer program for executing the following steps:

[0105] S201: acquiring a topology of physical bits in a quantum chip, a set of logic gates of an initial quantum program, and an initial mapping relationship between logic bits and physical bits;

[0106] S202: determining an execution time sequence of the set of logic gates of the initial quantum program;

[0107] S203: adjusting the mapping relationship between the logic bits and the physical bits corresponding to each logic gate according to the topology of the physical bits and the initial mapping relationship, and obtaining a final mapping relationship according to the execution time sequence;

[0108] S204: constructing a to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship, so as to minimize the number of SWAP quantum logic gates in the to-be-mapped quantum program.

[0109] Specifically, in the embodiment, the storage medium can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various storage media that can store computer programs.

[0110] Compared with the prior art, the application first acquires the topology of physical bits in a quantum chip, a logical gate set of an initial quantum program, and an initial mapping relationship between logical bits and physical bits, determines an execution time sequence of the logical gate set of the initial quantum program, adjusts the mapping relationship between the logical bits and the physical bits corresponding to each logical gate according to the topology of the physical bits and the initial mapping relationship in the execution time sequence, obtains a final mapping relationship, constructs a to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship, so that the number of SWAP quantum logical gates in the to-be-mapped quantum program is minimized, the influence of the increase of the SWAP gate on the operation of the entire quantum circuit is solved, and the resource utilization rate of the entire quantum chip is improved.

[0111] The embodiment of the application further provides an electronic device including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in the method embodiment of any one of the above.

[0112] Specifically, the electronic device can further include a transmission device and an input-output device, wherein the transmission device is connected with the processor, and the input-output device is connected with the processor.

[0113] Specifically, in the embodiment, the processor can be configured to execute the following steps through the computer program:

[0114] S201: acquiring a topology of physical bits in a quantum chip, a logical gate set of an initial quantum program, and an initial mapping relationship between logical bits and physical bits;

[0115] S202: determining an execution time sequence of the logical gate set of the initial quantum program;

[0116] S203: adjusting the mapping relationship between the logical bits and the physical bits corresponding to each logical gate according to the topology of the physical bits and the initial mapping relationship in the execution time sequence, and obtaining a final mapping relationship;

[0117] S204: constructing a to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship, so that the number of SWAP quantum logical gates in the to-be-mapped quantum program is minimized.

[0118] Compared with the prior art, the topology of the physical bits in the quantum chip, the initial quantum program logic gate set and the initial mapping relationship between the logical bits and the physical bits are first acquired, the execution time sequence of the initial quantum program logic gate set is determined, the mapping relationship between the logical bits and the physical bits corresponding to each logic gate is adjusted according to the topology of the physical bits and the initial mapping relationship in the execution time sequence, the final mapping relationship is obtained, the to-be-mapped quantum program equivalent to the initial quantum program is constructed according to the final mapping relationship, so that the number of SWAP quantum logic gates in the to-be-mapped quantum program is minimized, the influence of the increase of the SWAP gate on the operation of the entire quantum circuit is solved, and the resource utilization rate of the entire quantum chip is improved.

[0119] The embodiment of the application further provides a quantum computer operating system, which is constructed according to any one of the method embodiments provided in the embodiment of the application.

[0120] The embodiment of the application further provides a quantum computer, which comprises the quantum computer operating system.

[0121] Compared with the prior art, the topology of the physical bits in the quantum chip, the initial quantum program logic gate set and the initial mapping relationship between the logical bits and the physical bits are first acquired, the execution time sequence of the initial quantum program logic gate set is determined, the mapping relationship between the logical bits and the physical bits corresponding to each logic gate is adjusted according to the topology of the physical bits and the initial mapping relationship in the execution time sequence, the final mapping relationship is obtained, the to-be-mapped quantum program equivalent to the initial quantum program is constructed according to the final mapping relationship, so that the number of SWAP quantum logic gates in the to-be-mapped quantum program is minimized, the influence of the increase of the SWAP gate on the operation of the entire quantum circuit is solved, and the resource utilization rate of the entire quantum chip is improved.

[0122] The above embodiment according to the drawings details the structure, features and effects of the application, and the above description is only the preferred embodiment of the application, but the application is not limited to the drawings shown, any change or modification made according to the concept of the application, or the equivalent embodiment of the equivalent change, as long as it is within the scope of the application.

Claims

1. A method of constructing a quantum program to be mapped, characterized by, The method comprises: acquiring a topology of physical bits in a quantum chip, a logical gate set of an initial quantum program, and an initial mapping relationship between logical bits and physical bits; determining an execution time sequence of the logical gate set of the initial quantum program; forward traversing each logical gate according to the topology of the physical bits, the initial mapping relationship, and the execution time sequence, and adjusting physical bits mapped by each logical gate under a previous mapping relationship, and adjusting the previous mapping relationship until forward traversing is completed according to the execution time sequence, to obtain a target forward mapping relationship; reverse traversing each logical gate according to the target forward mapping relationship and the execution time sequence, and adjusting physical bits mapped by each logical gate under a previous mapping relationship, and adjusting the previous mapping relationship until a target reverse mapping relationship obtained after reverse traversing according to the execution time sequence is completed is taken as a final mapping relationship; constructing a to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship, so that a number of SWAP quantum logical gates in the to-be-mapped quantum program is minimized.

2. The method of claim 1, wherein, The logical gate set of the initial quantum program comprises: a first rule logical gate set, wherein the first rule logical gate set comprises single-bit quantum logical gates and two-bit quantum logical gates adjacent to logical bits; a second rule logical gate set, wherein the second rule logical gate set comprises two-bit quantum logical gates not adjacent to logical bits.

3. The method of claim 2, wherein, The determination of the execution time sequence of the logical gate set of the initial quantum program comprises: acquiring a quantum circuit corresponding to the initial quantum program; traversing the quantum circuit, and setting an execution time sequence of a first rule logical gate set of each quantum bit at a first time sequence as a priority execution time sequence, and setting an execution time sequence of a second rule logical gate set of each quantum bit at the first time sequence as a sub-priority execution time sequence; deleting logical gates whose execution time sequence division is completed, and continuing to perform the step of setting the execution time sequence of the first rule logical gate set of each quantum bit at the first time sequence as the priority execution time sequence, and setting the execution time sequence of the second rule logical gate set of each quantum bit at the first time sequence as the sub-priority execution time sequence, until the execution time sequence division of the logical gates of the quantum circuit is completed.

4. The method of claim 1, wherein, The construction of the to-be-mapped quantum program equivalent to the initial quantum program according to the final mapping relationship comprises: inserting SWAP quantum logical gates corresponding to each logical gate generated according to the execution time sequence into corresponding positions in the quantum logical gate set according to the final mapping relationship, and determining a quantum program obtained after the insertion as the to-be-mapped quantum program equivalent to the initial quantum program.

5. An apparatus for constructing a quantum program to be mapped, the apparatus comprising: The device comprises: an acquisition module configured to acquire a topology of physical bits in a quantum chip, a logical gate set of an initial quantum program, and an initial mapping relationship between logical bits and physical bits; a determination module configured to determine an execution time sequence of the logical gate set of the initial quantum program; The adjusting module is configured to traverse each logic gate in a forward direction according to the topology of physical bits, the initial mapping relationship, and adjust the physical bit mapped by each logic gate under a previous mapping relationship, and adjust the previous mapping relationship until the forward traversal is completed, to obtain a target forward mapping relationship; traverse each logic gate in a reverse direction according to the target forward mapping relationship, adjust the physical bit mapped by each logic gate under a previous mapping relationship, and adjust the previous mapping relationship until a target reverse mapping relationship obtained after the reverse traversal is completed is taken as a final mapping relationship; The constructing module is configured to construct a to-be-mapped quantum program identical to the initial quantum program according to the final mapping relationship, so that the number of SWAP quantum logic gates in the to-be-mapped quantum program is minimized.

6. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to execute the method in any one of claims 1 to 4 when running. 7.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the computer program to execute the method in any one of claims 1 to 4.

8. A quantum computer operating system, characterized by, The quantum computer operating system implements the method in any one of claims 1 to 4 to construct a to-be-mapped quantum program.

9. A quantum computer, characterized by The quantum computer comprises the quantum computer operating system in claim 8. The quantum computer comprises the quantum computer operating system in claim 8.

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