An SFGT memory array and memory chip

Abstract

This application discloses an SFGT memory array and a memory chip. The SFGT memory array includes a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier. The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to a first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines. The reference semi-floating gate array includes multiple second bit lines, each of which is connected to a second input terminal of the sensitive amplifier. When reading data stored in the memory cells of the SFGT memory array, the signal read from the memory cells can be amplified by the sensitive amplifier, which can improve the efficiency of data reading.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to an SFGT storage array and a storage chip. Background Technology

[0002] A semi-floating gate transistor (SFGT) is a transistor that falls between a metal-oxide-semiconductor field-effect transistor (MOSFET) and a floating gate transistor. SFGTs can be used to store data, primarily operating by applying different voltages to the word line and bit line. SFGTs can be integrated into memory arrays, enabling large-scale data storage.

[0003] In the prior art, when reading data stored in the storage cells of the SFGT storage array, the long bit lines of the SFGT storage array result in a relatively weak signal read from the storage cells, which makes the data reading process time-consuming and the data reading efficiency low. Summary of the Invention

[0004] This invention provides an SFGT memory array and a memory chip to solve the technical problem in the prior art that when reading data stored in the memory cells of an SFGT memory array, the signal read from the memory cells is relatively weak due to the long bit lines of the SFGT memory array, resulting in a long data reading process and low data reading efficiency.

[0005] In a first aspect, the present invention provides an SFGT memory array, the SFGT memory array comprising a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier;

[0006] The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to the first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines.

[0007] The reference semi-floating gate array includes multiple second bit lines, each of which is connected to the second input terminal of the sensitive amplifier.

[0008] Optionally, the reference half-floating gate array includes a plurality of reference half-floating gate memory cells and reference word lines. Each of the plurality of second bit lines intersects with the reference word line and is used to operate on the reference half-floating gate memory cell. The reference half-floating gate memory cell is located at the intersection of the second bit line and the reference word line.

[0009] Optionally, the real semi-floating gate array, the reference semi-floating gate array, and the sensitive amplifier correspond one-to-one.

[0010] Optionally, the real semi-floating gate array corresponds to the first reference semi-floating gate array and the second reference semi-floating gate array;

[0011] The odd-numbered first line of the multiple first lines contained in the real semi-floating gate array is connected to the first input terminal of the first sensitive amplifier, and the even-numbered first line of the multiple first lines contained in the real semi-floating gate array is connected to the first input terminal of the second sensitive amplifier.

[0012] Each of the multiple second bit lines included in the first reference semi-floating gate array is connected to the second input terminal of the first sensitive amplifier;

[0013] Each of the multiple second bit lines contained in the second reference semi-floating gate array is connected to the second input terminal of the second sensitive amplifier.

[0014] In a second aspect, the present invention provides a memory chip, comprising: an SFGT memory array, a column decoding module, a row decoding module, and a logic control module;

[0015] The logic control module is connected to the SFGT storage array through the column decoding module and the row decoding module respectively, and is used to write and read the SFGT storage array in units of pages according to the access instructions;

[0016] The SFGT memory array includes a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier;

[0017] The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to the first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines.

[0018] The reference semi-floating gate array includes multiple second bit lines, each of which is connected to the second input terminal of the sensitive amplifier.

[0019] Optionally, the memory chip further includes a circuit module connected to the column decoding module, the row decoding module, and the logic control module, the circuit module being used to provide voltage to the column decoding module, the row decoding module, and the logic control module.

[0020] Optionally, the memory chip further includes a data transmission path, which is connected to the column decoding module and the logic control module.

[0021] Optionally, the memory chip further includes an address input interface, which is connected to the row decoding module and the logic control module.

[0022] Optionally, the memory chip further includes an external interface command decoding circuit, which is connected to the logic control module.

[0023] Optionally, the memory chip further includes an input / output interface connected to the data transmission path.

[0024] As can be seen from the above technical solutions, the SFGT memory array and memory chip provided by the embodiments of the present invention include a real half-floating gate array, a reference half-floating gate array, and a sensitive amplifier. The real half-floating gate array includes multiple real half-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real half-floating gate memory cells. Each of the multiple first bit lines is connected to a first input terminal of the sensitive amplifier. The real half-floating gate memory cells are located at the intersection of the first bit lines and the first word lines. The reference half-floating gate array includes multiple second bit lines, each of which is connected to a second input terminal of the sensitive amplifier. Thus, each of the multiple first bit lines included in the real half-floating gate array is connected to the first input terminal of the sensitive amplifier, and each of the multiple second bit lines included in the reference half-floating gate array is connected to the second input terminal of the sensitive amplifier. When reading data stored in the memory cells of the SFGT memory array, a sensitive amplifier can amplify the signal read from the memory cells. This reduces the time spent reading data and improves the efficiency of data reading. Attached Figure Description

[0025] Figure 1 A schematic diagram of an SFGT storage array provided in an embodiment of this application;

[0026] Figure 2A schematic diagram of another SFGT storage array provided in an embodiment of this application;

[0027] Figure 3 A flowchart illustrating a method for reading data provided in an embodiment of this application;

[0028] Figure 4 A schematic diagram of an SFGT provided for an embodiment of this application;

[0029] Figure 5 An internal structure diagram of a sensitive amplifier SA provided in an embodiment of this application;

[0030] Figure 6 A schematic diagram of a memory chip provided in an embodiment of this application;

[0031] Figure 7 A schematic diagram of a memory core provided in an embodiment of this application;

[0032] Figure 8 A structural diagram of a data reading device provided in an embodiment of this application;

[0033] Figure 9 A schematic diagram illustrating an embodiment of an electronic device provided in this application;

[0034] Figure 10 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided in this application. Detailed Implementation

[0035] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0036] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0037] This invention provides an SFGT memory array, which includes a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier;

[0038] The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to the first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines.

[0039] The reference semi-floating gate array includes multiple second bit lines, each of which is connected to the second input terminal of the sensitive amplifier.

[0040] In a specific embodiment, the SFGT memory array may include a real half-floating gate array, a reference half-floating gate array, and a sensitive amplifier.

[0041] A true semi-floating gate array can include multiple true semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines to form a true semi-floating gate memory cell. The multiple first bit lines and the multiple first word lines can be arranged to intersect for operation on the true semi-floating gate memory cells. Each of the multiple first bit lines is connected to the first input terminal of a sensitive amplifier. The true semi-floating gate memory cells can be located at the intersection of the first bit lines and the first word lines.

[0042] The reference semi-floating gate array can include multiple second bit lines, and each of these second bit lines can be connected to the second input terminal of a sensitive amplifier. Thus, each of the first bit lines in the real semi-floating gate array is connected to the first input terminal of the sensitive amplifier, and each of the second bit lines in the reference semi-floating gate array is connected to the second input terminal of the sensitive amplifier. That is, when reading data stored in a memory cell of the SFGT memory array, the signal read from the memory cell can be amplified by the sensitive amplifier. This reduces the time spent reading data and improves the efficiency of data reading.

[0043] Optionally, the reference half-floating gate array includes a plurality of reference half-floating gate memory cells and reference word lines. Each of the plurality of second bit lines intersects with the reference word line and is used to operate on the reference half-floating gate memory cell. The reference half-floating gate memory cell is located at the intersection of the second bit line and the reference word line.

[0044] In a specific embodiment, the reference half-floating gate array may include multiple reference half-floating gate memory cells and reference word lines. Each of the multiple second bit lines may be configured to intersect with a reference word line for operating on the reference half-floating gate memory cell. The reference half-floating gate memory cell may be located at the intersection of the second bit line and the reference word line.

[0045] Optionally, the real semi-floating gate array, the reference semi-floating gate array, and the sensitive amplifier correspond one-to-one.

[0046] In a specific embodiment, the real semi-floating gate array, the reference semi-floating gate array, and the sensitive amplifier correspond one-to-one. For example... Figure 1 The image shown is a schematic diagram of an SFGT storage array. Figure 1 The diagram shows a total of 8 regions, numbered 1, 2, 3, 4, 5, 6, 7, and 8. In this embodiment, regions numbered 1 and 2 will be used as examples for illustration.

[0047] Region 1 can be a real semi-floating gate array, and region 2 can be a reference semi-floating gate array. In the real semi-floating gate array, the four vertical lines are all first-bit lines, and the three horizontal lines are first-word lines. The intersection of the four vertical first-bit lines and the three horizontal first-word lines forms 12 real semi-floating gate memory cells. Each of the four vertical first-bit lines is connected to the first input terminal of the sense amplifier (SA).

[0048] In the reference semi-floating gate array, the four vertical lines are all second bit lines, and the horizontal line at the bottom of the array is the reference word line. The four vertical second bit lines intersect with the horizontal reference word line to form four reference semi-floating gate memory cells. Each of the four vertical second bit lines is connected to the second input terminal of the SA.

[0049] It should be noted that the real semi-floating gate array and the reference semi-floating gate array can be converted into each other. For example, in Figure 1 In fact, region 2 can also contain three horizontal word lines. If the user selects one of the three horizontal word lines in region 1, then region 1 is the real half-floating gate array, and region 2 is the reference half-floating gate array. If the user selects one of the three horizontal word lines in region 2, then region 2 is the real half-floating gate array, and region 1 is the reference half-floating gate array. That is, the region containing the word line selected by the user is the real half-floating gate array, and the regions of the two inputs connected to the same SA with the real half-floating gate array are the reference half-floating gate array.

[0050] Optionally, the real semi-floating gate array corresponds to the first reference semi-floating gate array and the second reference semi-floating gate array;

[0051] The odd-numbered first line of the multiple first lines contained in the real semi-floating gate array is connected to the first input terminal of the first sensitive amplifier, and the even-numbered first line of the multiple first lines contained in the real semi-floating gate array is connected to the first input terminal of the second sensitive amplifier.

[0052] Each of the multiple second bit lines included in the first reference semi-floating gate array is connected to the second input terminal of the first sensitive amplifier;

[0053] Each of the multiple second bit lines contained in the second reference semi-floating gate array is connected to the second input terminal of the second sensitive amplifier.

[0054] In a specific embodiment, the actual semi-floating gate array can correspond to the first reference semi-floating gate array and the second reference semi-floating gate array. For example... Figure 2 The image shown is a schematic diagram of another type of SFGT storage array. Figure 2 The image shows a total of eight regions, numbered 1, 2, 3, 4, 5, 6, 7, and 8. In this embodiment, regions numbered 1, 2, and 3 will be used as examples. Figure 2 In the diagram, region numbered 2 can be a real semi-floating gate array, region numbered 1 can be a first reference semi-floating gate array, and region numbered 3 can be a second reference semi-floating gate array.

[0055] In a true semi-floating gate array, the eight vertical lines are all first-bit lines, and the three horizontal lines are first-word lines. There are 24 true semi-floating gate memory cells located at the intersections of the eight vertical first-bit lines and the three horizontal first-word lines. The odd-numbered first-bit lines in the true semi-floating gate array are connected to the first input terminal of the first sensitive amplifier. For example, the first-bit lines numbered 1, 3, 5, and 7 in the true semi-floating gate array can be connected to the first input terminal of the first sensitive amplifier. The even-numbered first-bit lines in the true semi-floating gate array are connected to the first input terminal of the second sensitive amplifier. For example, the first-bit lines numbered 2, 4, 6, and 8 in the true semi-floating gate array can be connected to the first input terminal of the second sensitive amplifier.

[0056] In the first reference semi-floating gate array, the four vertical lines are all second bit lines, and the two horizontal lines located at the top and bottom of the first reference semi-floating gate array are reference word lines. Eight reference semi-floating gate memory cells are located at the intersections of the four vertical second bit lines and the two horizontal reference word lines. Each of the multiple second bit lines included in the first reference semi-floating gate array is connected to the second input terminal of the first sensitive amplifier; that is, each of the four second bit lines included in the first reference semi-floating gate array is connected to the second input terminal of the first sensitive amplifier.

[0057] In the second reference semi-floating gate array, four of the eight vertical lines are second bit lines, and the two horizontal lines at the top and bottom of the array are reference word lines. Eight reference semi-floating gate memory cells are located at the intersections of the four vertical second bit lines and the two horizontal reference word lines. Each of the multiple second bit lines in the second reference semi-floating gate array is connected to the second input terminal of the second sensitive amplifier; that is, the four second bit lines in the second reference semi-floating gate array are connected to the second input terminal of the second sensitive amplifier. In this way, the multiple first bit lines in the real semi-floating gate array can be driven by the first and second reference semi-floating gate arrays on both sides (odd and even directions), and the two sensor arrays (SAs) can sense, amplify, and store the data. This reduces coupling effects and lowers the error rate when reading the stored value of the real semi-floating gate memory cell.

[0058] It should be noted that, in Figure 2 In this type of SFGT storage array, the real half-floating gate array and the reference half-floating gate array can be converted into each other. For example, in Figure 2In this context, region 3 can also contain three horizontal word lines. If the user selects one of the three horizontal word lines in region 2, then region 2 is the actual semi-floating grid array, region 1 is the first reference semi-floating grid array, and region 3 is the second reference semi-floating grid array. If the user selects one of the three horizontal word lines in region 3, then region 3 is the actual semi-floating grid array, region 2 is the first reference semi-floating grid array, and region 4 is the second reference semi-floating grid array. In other words, the region containing the word line selected by the user is the actual semi-floating grid array, and the two regions adjacent vertically to this actual semi-floating grid array are the first and second reference semi-floating grid arrays.

[0059] In the prior art, when reading data stored in the storage cells of the SFGT storage array, the long bit lines of the SFGT storage array result in a relatively weak signal read from the storage cells, which makes the data reading process time-consuming and the data reading efficiency low.

[0060] In this application, each of the multiple first bit lines in the real semi-floating gate array is connected to the first input terminal of the sensitive amplifier, and each of the multiple second bit lines in the reference semi-floating gate array is connected to the second input terminal of the sensitive amplifier. That is, when reading data stored in the memory cells of the SFGT memory array, the signal read from the memory cells can be amplified by the sensitive amplifier. This reduces the time consumed in the data reading process and improves the efficiency of data reading.

[0061] As can be seen from the above technical solutions, the SFGT memory array provided by the embodiments of the present invention includes a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier. The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to a first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines. The reference semi-floating gate array includes multiple second bit lines, each of which is connected to a second input terminal of the sensitive amplifier. Thus, each of the multiple first bit lines included in the real semi-floating gate array is connected to the first input terminal of the sensitive amplifier, and each of the multiple second bit lines included in the reference semi-floating gate array is connected to the second input terminal of the sensitive amplifier. When reading data stored in the memory cells of the SFGT memory array, a sensitive amplifier can amplify the signal read from the memory cells. This reduces the time spent reading data and improves the efficiency of data reading.

[0062] See Figure 3 , Figure 3 This is a flowchart of a data reading method provided by the present invention, applied to the SFGT storage array described in the foregoing embodiments. Figure 3 As shown, it includes the following steps:

[0063] Step 301: Obtain the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell through which the first target word line passes, wherein the first target word line is one of the multiple first word lines included in the real semi-floating gate array.

[0064] Step 302: Obtain the second voltage change value of the second target bit line in the reference semi-floating gate array.

[0065] Step 303: Control the sensitive amplifier to amplify the first voltage change value to obtain the first amplified voltage change value, and amplify the second voltage change value to obtain the second amplified voltage change value.

[0066] Step 304: Read the target stored value of the target real semi-floating gate memory cell based on the first amplified voltage change value and the second amplified voltage change value.

[0067] In a specific embodiment, in step 301, with Figure 1Taking regions numbered 1 and 2 as examples, we can obtain the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell through which the first target word line passes. Here, the first target word line is one of the multiple first word lines included in the real semi-floating gate array. For example, we can obtain the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell A through which the uppermost first target word line in region numbered 1 passes. Here, the first target word line is one of the three first word lines included in the real semi-floating gate array.

[0068] In a specific embodiment, in step 302, the second voltage change value of the second target bit line in the reference semi-floating gate array can also be obtained.

[0069] In a specific embodiment, step 302 further includes:

[0070] Obtain the second voltage change value of the second target bit line corresponding to the reference half-floating gate memory cell through which the reference word line passes in the reference half-floating gate array.

[0071] In a specific embodiment, step 302 may further obtain the second voltage change value of the second target bit line corresponding to the reference half-floating gate memory cell through which the reference word line in the reference half-floating gate array passes. For example, the second voltage change value of the second target bit line corresponding to the reference half-floating gate memory cell B through which the reference word line in region number 2 passes may be obtained.

[0072] In a specific embodiment, step 302 further includes:

[0073] The second voltage change value, which has been preset, is read from the sensitive amplifier.

[0074] In a specific embodiment, in step 302, a pre-set second voltage change value can also be read from the sensitive amplifier.

[0075] In a specific embodiment, in step 303, the sensitive amplifier can be controlled to amplify the first voltage change value to obtain the first amplified voltage change value, and to amplify the second voltage change value to obtain the second amplified voltage change value.

[0076] In a specific embodiment, before step 301, the method further includes:

[0077] Receive data read command;

[0078] According to the read data command, select the first target word line and the reference word line;

[0079] The step of obtaining the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell through which the first target word line passes includes:

[0080] After a preset time interval, the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell through which the first target word line passes is obtained.

[0081] like Figure 4 The image shown is a schematic diagram of an SFGT. Figure 4 In a SFGT, there are word lines, bit lines, and ground. The SFGT works by applying different voltages to the word lines and bit lines.

[0082] In practical implementation, a data read command can be received, allowing the selection of the topmost first target word line in region 1 and the reference word line in region 2. This enables the opening of the first target word line and the reference word line selected based on address decoding. After the first target word line is opened, current flows to ground through the SFGT. After a preset time interval, i.e., after a period of discharge, the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell A traversed by the first target word line can be obtained. Thus, the user can select a word line in the real semi-floating gate array according to their needs, thereby enabling the reading of data within the target real semi-floating gate memory cell traversed by that word line. The implementation process is simple, convenient, and fast.

[0083] It should be noted that, according to Q = I × t = C × V, as time changes, ΔQ = I × Δt = C × ΔV. Therefore, after a preset time interval, that is, after a period of discharge, the sensitive amplifier can be controlled to amplify the first voltage change value ΔV1 of the first target bit line to obtain the first amplified voltage change value, and to amplify the second voltage change value ΔV2 of the second target bit line to obtain the second amplified voltage change value.

[0084] In a specific embodiment, in step 304, the target stored value of the target real semi-floating gate memory cell can be read based on the first amplified voltage change value and the second amplified voltage change value.

[0085] Since the capacitance value C1 of the first target bit line is the same as the capacitance value C2 of the second target bit line, the relationship between the magnitudes of the first amplified voltage change and the second amplified voltage change can be used to determine the relationship between the current I1 flowing through the target real semi-floating gate memory cell and the current I2 flowing through the reference semi-floating gate memory cell. Furthermore, the target stored value within the target real semi-floating gate memory cell can be determined based on the relationship between I1 and I2.

[0086] In a specific embodiment, step 304 further includes:

[0087] When the first amplified voltage change value is greater than the second amplified voltage change value, the target stored value of the target real semi-floating gate memory cell is read as the first stored value;

[0088] When the first amplified voltage change value is less than the second amplified voltage change value, the target stored value of the target real semi-floating gate memory cell is read as the second stored value, wherein the first stored value and the second stored value are different.

[0089] If the first amplified voltage change is greater than the second amplified voltage change, it indicates that the current I1 flowing through the target real semi-floating gate memory cell is greater than the current I2 flowing through the reference semi-floating gate memory cell. In this case, the target stored value of the target real semi-floating gate memory cell can be read as the first stored value. For example, the first stored value can be 1.

[0090] If the change in the first amplified voltage is less than the change in the second amplified voltage, it indicates that the current I1 flowing through the target real semi-floating gate memory cell is less than the current I2 flowing through the reference semi-floating gate memory cell. In this case, the target stored value of the target real semi-floating gate memory cell can be read as the second stored value. The first and second stored values ​​are different. For example, the second stored value can be 0. Thus, the target stored value of the target real semi-floating gate memory cell can be determined based on the relationship between the first and second amplified voltage changes, reducing the time spent reading data and improving data reading efficiency.

[0091] It should be noted that after reading the target stored value of the target real semi-floating gate memory cell, all bit line voltages in the SFGT memory array can be switched to low potential. This allows for an erase operation on the selected memory cell in the SFGT memory array, restoring it to its initial state to facilitate the next data writing, i.e., programming operation. The erase operation destroys the original data in the memory cell, and the erased memory cell remains in its original state. Programming operations can also be performed in the SFGT memory array, which involves writing data from the sensitive amplifier into the selected memory cell.

[0092] It should be noted that, as Figure 5 The diagram shown illustrates the internal structure of a sensitive amplifier (SA). The SA_core is the core of the SA's operation, primarily responsible for signal amplification. The multiplexer (MUX) is used for bit line selection. Figure 5 The image also shows the bit line (bl).

[0093] It should be noted that in the existing technology, when reading data stored in the storage cells of the SFGT storage array, the signal read from the storage cell is relatively weak due to the long bit line of the SFGT storage array, which makes the data reading process time-consuming and the data reading efficiency low.

[0094] In this application, a sensitive amplifier can be controlled to amplify the first voltage change value of the first target bit line to obtain a first amplified voltage change value; and amplify the second voltage change value of the second target bit line to obtain a second amplified voltage change value. Then, based on the first and second amplified voltage change values, the target stored value of the target real semi-floating gate memory cell can be read. That is, when reading data stored in a memory cell in the SFGT memory array, the signal read from the memory cell can be amplified by the sensitive amplifier. This can reduce the time consumed in the data reading process and improve the efficiency of data reading.

[0095] As can be seen from the above technical solutions, the present invention provides a method for reading data by obtaining a first voltage change value of a first target bit line corresponding to a target real semi-floating gate memory cell through which a first target word line passes, wherein the first target word line is one of a plurality of first word lines included in the real semi-floating gate array; obtaining a second voltage change value of a second target bit line in the reference semi-floating gate array; controlling a sensitive amplifier to amplify the first voltage change value to obtain a first amplified voltage change value, and amplifying the second voltage change value to obtain a second amplified voltage change value; and reading the target memory value of the target real semi-floating gate memory cell based on the first amplified voltage change value and the second amplified voltage change value. In this way, a sensitive amplifier can be controlled to amplify the first voltage change value of the first target bit line to obtain the first amplified voltage change value; and amplify the second voltage change value of the second target bit line to obtain the second amplified voltage change value. Therefore, the target memory value of the target real semi-floating gate memory cell can be read based on the first amplified voltage change value and the second amplified voltage change value. When reading data stored in the memory cells of the SFGT memory array, a sensitive amplifier can amplify the signal read from the memory cells. This reduces the time spent reading data and improves the efficiency of data reading.

[0096] See Figure 6 , Figure 6 This is a schematic diagram of a memory chip provided by the present invention. The memory chip may include: an SFGT memory array, a column decoding module, a row decoding module, and a logic control module.

[0097] The logic control module is connected to the SFGT storage array through the column decoding module and the row decoding module respectively, and is used to write and read the SFGT storage array in units of pages according to the access instructions;

[0098] The SFGT memory array includes a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier;

[0099] The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to the first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines.

[0100] The reference semi-floating gate array includes multiple second bit lines, each of which is connected to the second input terminal of the sensitive amplifier.

[0101] In this embodiment, the SFGT storage array can be adopted as follows: Figures 1-6 SFGT storage array of any of the embodiments shown.

[0102] like Figure 6 As shown, the memory chip may include an SFGT memory array, a column decoding module (Col_dec), a row decoding module (Row_dec), and a control logic module. The control logic module can be connected to the SFGT memory array through the column decoding module and the row decoding module, respectively, and is used to write and read from the SFGT memory array in units of pages according to access instructions. The structure of the SFGT memory array has been described in detail in the foregoing embodiments and will not be repeated here.

[0103] Optionally, the memory chip further includes a circuit module connected to the column decoding module, the row decoding module, and the logic control module, the circuit module being used to provide voltage to the column decoding module, the row decoding module, and the logic control module.

[0104] like Figure 6 As shown, the memory chip may also include a generator module, which can be connected to the column decoding module, row decoding module, and logic control module. The generator module provides voltage to the column decoding module, row decoding module, and logic control module, while the generator module provides various operating voltages to the memory chip.

[0105] Optionally, the memory chip further includes a data transmission path, which is connected to the column decoding module and the logic control module.

[0106] like Figure 6 As shown, the memory chip may also include a data path, which can be connected to the column decoding module and the logic control module.

[0107] Optionally, the memory chip further includes an address input interface, which is connected to the row decoding module and the logic control module.

[0108] like Figure 6 As shown, the memory chip may also include an address input interface (Add dec), which can be connected to the row decoding module and the logic control module.

[0109] Optionally, the memory chip further includes an external interface command decoding circuit, which is connected to the logic control module.

[0110] like Figure 6 As shown, the memory chip may also include an external interface command decoding circuit (Command dec), which can be connected to the logic control module.

[0111] Optionally, the memory chip further includes an input / output interface connected to the data transmission path.

[0112] like Figure 6 As shown, the memory chip may also include input / output (IO) interfaces, which can be connected to the data transmission path.

[0113] It's important to note that control logic is the control center of a memory chip's operation. It primarily provides various logic and voltage inputs to the chip's core, which is essentially the core of the memory chip. For example... Figure 7 The diagram shows a schematic of a memory chip core. It includes a row decoding module (Row_dec), a column decoding module (Col_dec), and a control logic module that generates various timing control signals. Within the entire SFGT memory array, it contains word line drivers, SA (Search Engine Controller) modules, and more. The word line driver primarily provides driving capability, ensuring the signal isn't too weak even when the word line is at its furthest point. The SA's main function is to amplify small signals to full swing. The Row_dec module selects the corresponding word line based on the input address and then begins the data reading operation. The Col_dec module decodes the input column address.

[0114] As can be seen from the above technical solutions, the memory chip provided in this embodiment of the invention can amplify the signal read from the memory cell using a sensitive amplifier. This can reduce the time consumed in the data reading process and improve the efficiency of data reading.

[0115] See Figure 8 , Figure 8 This is a structural diagram of a data reading device provided by the present invention. Figure 8 As shown, the data reading device 800 includes a first acquisition module 801, a second acquisition module 802, an amplification module 803, and a reading module 804, wherein:

[0116] The first acquisition module 801 is used to acquire the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell through which the first target word line passes, wherein the first target word line is one of the multiple first word lines included in the real semi-floating gate array.

[0117] The second acquisition module 802 is used to acquire the second voltage change value of the second target bit line in the reference semi-floating gate array;

[0118] Amplification module 803 is used to control a sensitive amplifier to amplify the first voltage change value to obtain a first amplified voltage change value, and to amplify the second voltage change value to obtain a second amplified voltage change value;

[0119] The reading module 804 is used to read the target stored value of the target real semi-floating gate memory cell based on the first amplified voltage change value and the second amplified voltage change value.

[0120] The data reading device 800 is capable of... Figure 3 The various processes implemented by the data reading device in the method embodiment will not be described again here to avoid repetition. The data reading device 800 can control a sensitive amplifier to amplify the first voltage change value of the first target bit line to obtain a first amplified voltage change value; and amplify the second voltage change value of the second target bit line to obtain a second amplified voltage change value. Then, based on the first and second amplified voltage change values, the target stored value of the target real semi-floating gate memory cell can be read. That is, when reading data stored in a memory cell in the SFGT memory array, the signal read from the memory cell can be amplified by a sensitive amplifier. This can reduce the time consumed in the data reading process and improve the efficiency of data reading.

[0121] Please see Figure 9 , Figure 9 A schematic diagram illustrating an embodiment of the electronic device provided in this application.

[0122] like Figure 9 As shown, this application provides an electronic device 900, including a memory 910, a processor 920, and a computer program 911 stored in the memory 910 and executable on the processor 920. When the processor 920 executes the computer program 911, it performs the following steps:

[0123] Obtain the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell through which the first target word line passes, wherein the first target word line is one of the multiple first word lines included in the real semi-floating gate array;

[0124] Obtain the second voltage change value of the second target bit line in the reference semi-floating gate array;

[0125] The sensitive amplifier is controlled to amplify the first voltage change value to obtain a first amplified voltage change value, and the second voltage change value is amplified to obtain a second amplified voltage change value;

[0126] Based on the first amplified voltage change value and the second amplified voltage change value, the target stored value of the target real semi-floating gate memory cell is read.

[0127] In practical implementation, when the processor 920 executes the computer program 911, it can achieve... Figure 3 Any of the corresponding implementation methods in the embodiments.

[0128] Since the electronic device described in this embodiment is a device used to implement a data reading device in the embodiments of this application, those skilled in the art can understand the specific implementation method and various variations of the electronic device in this embodiment based on the method described in the embodiments of this application. Therefore, how the electronic device implements the method in the embodiments of this application will not be described in detail here. Any device used by those skilled in the art to implement the method in the embodiments of this application falls within the scope of protection of this application.

[0129] Please see Figure 10 , Figure 10 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided in this application.

[0130] like Figure 10 As shown, this embodiment provides a computer-readable storage medium 1000, on which a computer program 1011 is stored. When the computer program 1011 is executed by a processor, it performs the following steps:

[0131] Obtain the first voltage change value of the first target bit line corresponding to the target real semi-floating gate memory cell through which the first target word line passes, wherein the first target word line is one of the multiple first word lines included in the real semi-floating gate array;

[0132] Obtain the second voltage change value of the second target bit line in the reference semi-floating gate array;

[0133] The sensitive amplifier is controlled to amplify the first voltage change value to obtain a first amplified voltage change value, and the second voltage change value is amplified to obtain a second amplified voltage change value;

[0134] Based on the first amplified voltage change value and the second amplified voltage change value, the target stored value of the target real semi-floating gate memory cell is read.

[0135] In practical implementation, when the computer program 1011 is executed by the processor, it can achieve the following: Figure 3 Any of the corresponding implementation methods in the embodiments.

[0136] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0137] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0138] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0139] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0140] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0141] This application also provides a computer program product, which includes computer software instructions that, when executed on a processing device, cause the processing device to perform actions such as... Figure 3 The flow of the data reading method in the corresponding embodiment.

[0142] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0143] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0144] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0145] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0146] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0147] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0148] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An SFGT storage array, characterized in that, The SFGT memory array includes a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier; The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to the first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines. The reference semi-floating gate array includes multiple second bit lines, each of which is connected to the second input terminal of the sensitive amplifier.

2. The SFGT storage array according to claim 1, characterized in that, The reference semi-floating gate array includes a plurality of reference semi-floating gate memory cells and reference word lines. Each of the plurality of second bit lines intersects with the reference word line and is used to operate on the reference semi-floating gate memory cell. The reference semi-floating gate memory cell is located at the intersection of the second bit line and the reference word line.

3. The SFGT storage array according to claim 2, characterized in that, The real semi-floating gate array, the reference semi-floating gate array, and the sensitive amplifier correspond one-to-one.

4. The SFGT storage array according to claim 2, characterized in that, The real semi-floating gate array corresponds to the first reference semi-floating gate array and the second reference semi-floating gate array; The odd-numbered first line of the multiple first lines contained in the real semi-floating gate array is connected to the first input terminal of the first sensitive amplifier, and the even-numbered first line of the multiple first lines contained in the real semi-floating gate array is connected to the first input terminal of the second sensitive amplifier. Each of the multiple second bit lines included in the first reference semi-floating gate array is connected to the second input terminal of the first sensitive amplifier; Each of the multiple second bit lines contained in the second reference semi-floating gate array is connected to the second input terminal of the second sensitive amplifier.

5. A memory chip, characterized in that, include: SFGT storage array, column decoding module, row decoding module, and logic control module; The logic control module is connected to the SFGT storage array through the column decoding module and the row decoding module respectively, and is used to write and read the SFGT storage array in units of pages according to the access instructions; The SFGT memory array includes a real semi-floating gate array, a reference semi-floating gate array, and a sensitive amplifier; The real semi-floating gate array includes multiple real semi-floating gate memory cells, multiple first bit lines, and multiple first word lines. Each of the multiple first bit lines intersects with each of the multiple first word lines for operating the real semi-floating gate memory cells. Each of the multiple first bit lines is connected to the first input terminal of the sensitive amplifier. The real semi-floating gate memory cells are located at the intersection of the first bit lines and the first word lines. The reference semi-floating gate array includes multiple second bit lines, each of which is connected to the second input terminal of the sensitive amplifier.

6. The memory chip according to claim 5, characterized in that, The memory chip also includes a circuit module connected to the column decoding module, the row decoding module and the logic control module. The circuit module is used to provide voltage to the column decoding module, the row decoding module and the logic control module.

7. The memory chip according to claim 6, characterized in that, The memory chip also includes a data transmission path, which is connected to the column decoding module and the logic control module.

8. The memory chip according to claim 7, characterized in that, The memory chip also includes an address input interface, which is connected to the row decoding module and the logic control module.

9. The memory chip according to claim 8, characterized in that, The memory chip also includes an external interface command decoding circuit, which is connected to the logic control module.

10. The memory chip according to claim 9, characterized in that, The memory chip also includes an input / output interface, which is connected to the data transmission path.

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