Command Clock Gating Implementation with Chip Select Signal Training Indication

Abstract

The present disclosure relates to a command clock gating implementation with chip select signal training indication. Systems and methods for: when a mode register value indicates that synchronization of a command address signal and a clock signal has not occurred, gating the clock signal via a clock gating circuitry at least in part based on the mode register value indicating the synchronization of the command address signal and the clock signal. The clock gating circuitry is configured to gate the clock signal at least in part based on the mode register value and a chip select signal value when the mode register value indicates that the synchronization of the command address signal and the clock signal has occurred.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices, and more particularly, to using registers to indicate chip select clock and / or command address buffer training in a memory device to achieve command clock gating purposes. Background Art

[0002] A semiconductor device (e.g., a memory device) may employ command clock gating to enable or disable an internal clock of the memory device based on the validity of a command. When a chip select signal is detected as logic low, the memory device may detect that a valid command is being transmitted to and / or indicated in a command address buffer. However, due to the topology of the memory device, the chip select clock signal may be unknown before the relationship between the internal clock signal and the chip select signal is established.

[0003] Embodiments of the present disclosure may relate to solving one or more of the problems set forth above. Summary of the Invention

[0004] In one aspect, the present disclosure provides a memory device including: a clock gating circuitry configured to receive a clock signal from a host device, wherein the clock gating circuitry includes: a first portion of the circuitry configured to gate the clock signal at least in part based on a mode register value indicating synchronization of a command address signal and the clock signal; and a second portion of the circuitry configured to gate the clock signal at least in part based on the mode register value and a chip select signal value.

[0005] In another aspect, the present disclosure provides a method including: receiving a clock signal from a host device at a clock gating circuitry of a memory device; gating the clock signal at least in part based on a mode register value indicating synchronization of a command address signal and the clock signal via the clock gating circuitry when the mode register value indicates that synchronization of the command address signal and the clock signal has not occurred; and gating the clock signal at least in part based on the mode register value and a chip select signal value via the clock gating circuitry when the mode register value indicates that synchronization of the command address signal and the clock signal has occurred.

[0006] In yet another aspect, the present disclosure provides a system that includes: a command decoder; a clock gating circuitry configured to receive a clock signal from a host device, wherein the clock gating circuitry is configured to: propagate the clock signal to the command decoder when a mode register value indicates that synchronization of a command address signal and the clock signal has not occurred; propagate the clock signal to the command decoder when the mode register value indicates that synchronization of the command address signal and the clock signal has occurred and a corresponding chip select signal is asserted; and block propagation of the clock signal to the command decoder when the mode register value indicates that synchronization of the command address signal and the clock signal has occurred but the corresponding chip select signal is not asserted. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 6 is a simplified block diagram illustrating some features of a memory device in accordance with an embodiment of the present disclosure;

[0008] Figure 2 FIG. 10 is a timing diagram illustrating training of a chip select signal in accordance with an embodiment of the present disclosure;

[0009] Figure 3 FIG. 14 is a timing diagram illustrating training of a command address signal in accordance with an embodiment of the present disclosure;

[0010] Figure 4 FIG. 18 is a schematic diagram of a command clock gating circuitry for gating an internal clock signal with a chip select signal in accordance with an embodiment of the present disclosure;

[0011] Figure 5 FIG. 22 is a schematic diagram of a flip-flop for gating a command address signal and using an internal clock signal in accordance with an embodiment of the present disclosure; and

[0012] Figure 6 FIG. 26 is a simplified block diagram of a command decoder for receiving and decoding a multi-purpose command in accordance with an embodiment of the present disclosure Figure 1 of. DETAILED DESCRIPTION

[0013] One or more specific embodiments will be described below. For the sake of concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and enterprise-related constraints, which may vary from one implementation to another. In addition, it should be understood that such development work may be complex and time-consuming, but for those skilled in the art who benefit from the present disclosure, these are routine tasks in design, construction, and manufacturing.

[0014] A memory device may employ command clock gating to enable or disable an internal clock of the memory device based on the validity of a command. The command clock gating may use a chip select signal to gate the internal clock of the memory device. That is, the internal clock of the memory device may be cut off until a valid command is detected. However, the topology of the memory device may prevent advance knowledge of the timing specification of the chip select signal. That is, the topology of the memory device may cause an internal clock signal to arrive from a host device and start switching out of sync with the chip select signal in the memory device before the chip select signal arrives at a clock gating circuitry.

[0015] Accordingly, the chip select signal may not be available to gate the internal clock signal until a relationship (e.g., synchronization) between the internal clock signal and the chip select clock signal is established, and the internal clock may run at full speed to ensure full capture of one or more valid commands in a command address buffer. Once the relationship is established, the chip select signal is considered trained (e.g., synchronized with the internal clock signal), and the internal clock may be correctly gated with the chip select signal.

[0016] In addition, due to the topology of the memory device described above, a command address buffer may undergo training to synchronize command address signals with the internal clock signal. However, there is currently no indication that the chip select clock and / or the command address signals are trained. Thus, an improved system for indicating a training state of the chip select clock and / or the command address signals is needed.

[0017] Keeping the foregoing in mind, Figure 1 FIG. is a simplified block diagram illustrating some features of a memory device 10. According to one embodiment, the memory device 10 may be a fifth generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) device. Compared with previous generations of DDR SDRAM, various features of the DDR5 SDRAM allow for reduced power consumption, increased bandwidth, and increased storage capacity. The memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a number of memory banks 12. The memory banks 12 may be, for example, DDR5 SDRAM memory banks. The memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on dual in-line memory modules (DIMMs). Each DIMM may include a number of SDRAM memory chips (e.g., eight or sixteen memory chips). Each SDRAM memory chip may include one or more memory banks 12.

[0018] For DDR5, the memory banks 12 can be arranged to form bank groups. For example, a memory die may include sixteen memory banks 12 for eight-gigabyte (8 Gb) DDR5 SDRAM. The memory banks 12 can be arranged into eight bank groups, each bank group including two memory banks. For sixteen-gigabyte (16 Gb) DDR5 SDRAM, the memory die may include thirty-two memory banks 12 arranged into eight bank groups, each bank group including, for example, four memory banks 12.

[0019] Depending on the application and design of the overall system, various other configurations, organizations, and sizes of the memory banks 12 on the memory device 10 can be utilized. In one embodiment, each memory bank 12 includes a bank control block 22 that controls the execution of commands to and from the memory bank 12 for performing various functions in the memory device 10, such as decoding, timing control, data control, and any combination thereof.

[0020] The command interface 14 of the memory device 10 is configured to receive and transmit several signals (e.g., signal 15). Signal 15 can be received from a host device (not shown), such as a processor or a controller. The processor or controller can provide various signals 15 to the memory device 10 to facilitate the transfer and reception of data to be written to or read from the memory device 10.

[0021] As should be appreciated, the command interface 14 can include several circuits, such as a clock input circuit 21 and a command address input circuit 23, for example, to ensure proper handling of signal 15. The command interface 14 can receive one or more clock signals from an external device. Generally, double data rate (DDR) memories utilize a differential pair of system clock signals, referred to herein as the true clock signal 16 (Clk_t) and the complementary clock signal 17 (Clk_c). The positive clock edge of DDR refers to the point at which the rising true clock signal Clk_t 16 crosses the falling complementary clock signal Clk_c 17. The negative clock edge indicates the transition of the falling true clock signal Clk_t 16 and the rising of the complementary clock signal Clk_c 17. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal. Data can be transferred or received on both the positive and negative clock edges.

[0022] The clock input circuit 21 receives a true clock signal (Clk_t 16) and a complementary clock signal (Clk_c 17), and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) circuit 30. The DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 20 and serves as a timing signal for determining the output timing of the read data. In some embodiments, as discussed below, the clock input circuit 21 may include circuitry that splits the clock signal into multiple (e.g., four) phases. The clock input circuit 21 may also include a phase detection circuit for detecting which phase receives the first pulse when pulse sets occur too frequently so that the clock input circuit 21 can reset between pulses.

[0023] The internal clock signal / phase CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to the command decoder 32. The command decoder 32 may receive a command signal from the command bus 38 and may decode the command signal to provide various internal commands. For example, the command decoder 32 may provide the command signal to the DLL circuit 30 via the bus 40 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK may be used to time data, for example, via the I / O interface 20.

[0024] In addition, the command decoder 32 may decode incoming commands such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to a particular memory bank 12 corresponding to the command via the bus path 42. As should be appreciated, the memory device 10 may include various other decoders, such as a row decoder and a column decoder, to facilitate access to the memory bank 12.

[0025] The command decoder 32 may include a clock gating circuitry 35. In some embodiments, the clock gating circuitry 35 may be included in other locations within the memory device 10 (e.g., the DLL circuit 30). The clock gating circuitry 35 may employ command clock gating to enable or disable the internal clock based on the validity of the command.

[0026] Memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, command / address bus 38 may be a 14-bit bus for accommodating command / address signals 19 (CA). Clock signals (Clk_t 16 and Clk_c 17) are used to time the command / address signals into command interface 14. Command interface 14 may include command address input circuit 23, which is configured to receive and transmit commands through command decoder 32 to provide access to memory bank 12. Additionally, command interface 14 may receive chip select signal 18 (CS_n). CS_n signal 18 may also be regarded as an incoming clock signal. CS_n signal 18 enables memory device 10 to process commands on incoming CA signal 19 bus. Access to a specific memory bank 12 within memory device 10 is encoded in the CA signal 19 on the bus.

[0027] Additionally, command interface 14 may be configured to receive several other command signals. For example, a command / address on die termination (CA_ODT) signal may be provided on the die pads to facilitate proper impedance matching within memory device 10. For example, during power-up, a reset command (RESET_n) may be used to reset command interface 14, status registers, state machines, etc. Command interface 14 may also receive a command / address inversion (CAI) signal, which may be provided to invert the state of CA signal 19 on command / address bus 38, for example, depending on the command / address routing of a particular memory device 10. A mirror (MIR) signal may also be provided to facilitate the mirroring function. Based on the configuration of multiple memory devices (such as memory device 10) in a particular application, the MIR signal may be used to multiplex signals such that the signals can be swapped to achieve a specific routing of the signals to memory device 10. Various signals may also be provided to facilitate testing of memory device 10, such as a test enable (TEN) signal. For example, the TEN signal may be used to place memory device 10 into a test mode for connectivity testing.

[0028] Command interface 14 may also be used to provide a warning signal (ALERT_n) to the system processor or controller for a detectable error. For example, the warning signal (ALERT_n) may be transmitted from memory device 10 in the event of a detected cyclic redundancy check (CRC) error. Other warning signals may also be generated. Additionally, the bus and pins used to transmit the warning signal (ALERT_n) from memory device 10 may be used as input pins during some operations, such as the connectivity test mode performed using the TEN signal as described above.

[0029] Using the commands and timing signals 15 discussed above, data can be sent to and received from the memory device 10 by transmitting and receiving data signals 44 via the I / O interface 20. More specifically, data can be sent to or retrieved from the memory bank 12 through a data path 46 that includes a plurality of bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For a particular memory device, such as a DDR5 SDRAM memory device, the I / O signals can be divided into upper and lower bytes. For example, for a x16 memory device, the I / O signals can be divided into upper I / O signals and lower I / O signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to the upper and lower bytes of the data signal, respectively.

[0030] To allow for higher data rates within the memory device 10, some memory devices, such as DDR memory devices, may utilize data strobe signals, commonly referred to as DQS signals. The DQS signal is driven by an external processor or controller that is transmitting data (e.g., for a write command) or by the memory device 10 itself (e.g., for a read command). For a read command, the DQS signal is effectively an additional data output (DQ) signal with a predefined pattern. For a write command, the DQS signal can be used as a clock signal to capture the corresponding input data. Similar to the clock signals (Clk_t 16 and Clk_c 17), the DQS signal can be provided as a differential pair (DQS_t and DQS_c) of data strobe signals to provide differential pair signaling during both reads and writes. For some memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into upper and lower data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c) corresponding to the upper and lower bytes of the data being sent to and received from the memory device 10, respectively.

[0031] An impedance (ZQ) calibration signal can also be provided to the memory device 10 through the I / O interface 20. The ZQ calibration signal can be provided to a reference pin and is used to tune the output driver and ODT values by adjusting the pull-up and pull-down resistors of the memory device 10 over changes in process, voltage, and temperature (PVT) values. Since the PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin to adjust the resistance to calibrate the input impedance to a known value. As should be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the drive strength of the internal ODT and I / O pins.

[0032] In addition, a loopback signal (LOOPBACK) can be provided to the memory device 10 through the I / O interface 20. The loopback signal can be used during a test or debug phase to set the memory device 10 in a mode in which signals are looped back to the memory device 10 through the same pins. For example, the loopback signal can be used to set the memory device 10 to test the data output (DQ) of the memory device 10. The loopback can include both data and strobe, or may include only data pins. This is generally intended to monitor the data captured by the memory device 10 at the I / O interface 20.

[0033] As should be appreciated, various other components such as a power supply circuit (for receiving external VDD and VSS signals), a mode register (for defining various modes of programmable operations and configurations), a read / write amplifier (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 10) can also be incorporated into the memory device 10. Thus, it should be understood that the Figure 1 block diagram is provided to highlight some functional features of the memory device 10 to assist in the subsequent detailed description.

[0034] As discussed above, the CS_n signal 18 enables the memory device 10 to process commands on the incoming CA signal 19 bus. Before the CS_n signal 18 is trained (e.g., synchronized with the internal clock signal), the CS_n signal 18 is unpredictable, and the timing specification of the CS_n signal 18 is unknown. Additionally, the CA signal 19 may initially not be trained to be synchronized with the internal clock signal.

[0035] Keeping the foregoing in mind, Figure 2 FIG. 50 is a timing diagram of an embodiment of the training of the CS_n signal 18. The CA signal 19 bus can transmit a multi-purpose command (MPC) 52. The MPC 52 can include a decoded command that instructs the memory device 10 to start the training of the CS_n signal 18. The MPC 52 can be supplied by a host device. The host device can be any system or device that communicates with the memory device 10.

[0036] However, the CS_n signal 18 can be de-asserted to ensure that the memory device 10 receives the MPC 52, as illustrated by the pulse 54. One or more regions 55 on either side of the CS_n signal 18 represent the unpredictability of the CS_n signal 18. During the pulse 54, the CS_n signal 18 is unknown to the memory device 10, and the pulse 54 is merely a representation that the CS_n signal 18 is de-asserted at any particular point during the relevant clock cycle of the Clk_t16 signal.

[0037] Since the timing specification of the CS_n signal 18 may be unknown prior to the training of the CS_n signal 18, the CS_n signal 18 is de-asserted (e.g., set to logic low) for a specific number of cycles to ensure the capture of the MPC 52 from the CA signal 19 bus. Additionally, once the CS_n signal 18 is asserted (e.g., set to logic high) after the pulse 54, the CA signal 19 may continue to be asserted due to the unknown relationship between the CS_n signal 18 and the Clk_t 16 signal to ensure the capture of the command supplied by the CA signal 19 bus.

[0038] The CMD signal 56 may indicate the current command that has been decoded from the current or previous CA signal 19 at and / or in the memory device 10. That is, the CMD signal 56 may indicate when the memory device 10 begins to execute any given command supplied by the CA signal 19 bus. When the CS_n signal 18 is asserted, the CMD signal 56 may execute a "deselect" command (DES). As discussed above, the CS_n signal 18 may be de-asserted for two or more cycles to verify that the CS_n signal 18 is properly de-asserted. After the two or more cycles for verification, the CS_n signal 18 may be used to center the CMD signal 56 to decode the MPC 52 from the CA signal 19 bus.

[0039] To train the CS_n signal 18, a host device, such as a processor or a controller, may continuously provide a switching signal for the CS_n signal 18, as illustrated by one or more pulses 58. The host device may detect the high level and the low level of the CS_n signal 18 after a time point during the switching of the CS_n signal 18 and shift the CS_n signal 18 relative to the Clk_t signal 16. The host device may set a mode register to indicate when the CS_n signal 18 is trained. In some embodiments, the host device may use any unused mode register available in the memory device 10. That is, the host device may set the mode register to asserted when the CS_n signal 18 is trained and set the mode register to de-asserted in other cases. In some embodiments, the asserted value may indicate a value of logic high, and the de-asserted value may indicate a value of logic low. In other embodiments, inverted logic may be implemented, and the asserted value may indicate a value of logic low. Additionally, the logic circuits described herein may be modified to reflect the state of the logic (e.g., the inverted state or the non-inverted state of the logic). In some embodiments, the host device may train the CA signal 19 before setting the mode register to indicate the training of the CS_n signal 18. Thus, the host device may set the mode register to indicate that the CS_n signal 18 and the CA signal 19 are trained. The training of the CS_n signal 18 may exit after the capture of the MPC 52 to exit the CS_n signal 18 training.

[0040] Keeping the foregoing in mind, Figure 3 FIG. 70 is a timing diagram of an embodiment of training for the CA signal 19. As discussed above, the CA signal 19 can be trained and synchronized with the Clk_t signal 16. The CA signal 19 bus can carry an MPC 52 to indicate to the memory device 10 to start training the CA signal 19. Similar to Figure 2 , the CS_n signal 18 signal can be de-asserted to ensure that the memory device 10 receives the MPC 52 for CA signal 19 training, as illustrated by the pulse 72. In some embodiments, the pulse 72 can be during the same time range as the pulse 54. In some embodiments, the CA signal 19 training can be performed separately at a different time point from the CS_n signal 18 training. In other embodiments, the CA signal 19 training can occur after or simultaneously with the training of the CS_n signal 18.

[0041] During the CA signal 19 training, one or more iterations of the MPC 52 on the CA signal 19 bus can be transmitted to the memory device 10. The memory device 10 can capture one or more sample values of the CA signal 19 from the CA signal 19 bus, as illustrated by one or more pulses 74. The memory device 10 can capture each sample value at the rising edge of the Clk_t 16 signal. In some embodiments, the memory device 10 can capture one or more sample values while the CS_n signal 18 is asserted. The memory device 10 can perform one or more logical operations on the one or more sample values. By way of example, the memory device 10 can perform an XOR operation on each of the sample values to determine an output value. The memory device can transmit the output value as a DQ value based on whether the sampled value matches an expected value. The host device can expect a specific output value as the DQ value from the memory device 10. Once the XOR operation on one or more sample values of the CA signal 19 is recorded, the CS_n signal 18 is completed, and the host device can record the relationship between the CA signal 19 and the internal clock. The host device can set the mode register to an asserted value to indicate the training of the CS_n signal 18 and / or the CA signal 19 based on the output value received from the memory device 10 as the DQ value.

[0042] As described above, the clock gating circuitry 35 can utilize the CS_n signal 18 to gate an internal clock signal (CLK) based on Clk_t 16 and / or Clk_c 17. Keeping the foregoing in mind, Figure 4 FIG. is a schematic diagram of the clock gating circuitry 35 for gating the internal clock signal (CLK) with the CS_n signal 18. The clock gating circuitry 35 can be implemented in the command decoder 32 and / or external to the command decoder 32 in another part of the memory device 10.

[0043] The CS_n signal 18 is transmitted into the flip-flop 82. An internal clock signal (e.g., the CLK signal) is transmitted as the clock input 104 for the flip-flop 82. It should be noted that the CLK signal 104 is switching at a rate based on the specification of the internal clock of the memory device 10. When the CS_n signal 18 and the CLK signal 104 are asserted, the flip-flop 82 shifts the CS_n signal 18 by one clock cycle. The output 105 of the flip-flop 82 is transmitted as an input to the NAND gate 84.

[0044] As discussed above, one or more mode registers may indicate when the CS_n signal 18 and / or the CA signal 19 are synchronized with the CLK signal 104. The value of the mode register may be represented as the signal Single_cycle 106. The Single_cycle signal 106 is transmitted into the NAND gate 84. When the Single_cycle signal 106 is asserted, the CS_n signal 18 and / or the CA signal 19 have been trained. The CLK signal 104 is transmitted into the NAND gate 84.

[0045] When the Single_cycle signal 106, the CLK signal 104, and the output 105 are each asserted, the NAND gate 84 outputs a de-asserted value to the inverter 86. That is, when any of the Single_cycle signal 106, the CLK signal 104, and the output 105 is de-asserted, the NAND gate 84 may output an asserted value to the inverter 86. The inverter 86 transmits the inverted output of the NAND gate 84 to the OR gate 88. In other words, when the Single_cycle signal 106, the CLK signal 104, and the latched CS_n signal 18 are all asserted, the NAND gate 84 and the inverter 86 act as an AND gate that asserts a value to the OR gate 88. Otherwise, the output of the inverter 86 is de-asserted. Thus, when the Single_cycle signal 106 is asserted and the latched CS_n signal 18 is asserted, the output of the inverter 86 to the OR gate is the CLK signal 104. In some embodiments, the NAND gate 84 and the inverter 86 may be replaced with an AND gate.

[0046] In addition, the Single_cycle signal 106 is additionally transmitted to the inverter 90. The inverter 90 inverts the Single_cycle signal 106 and transmits it to the NAND gate 92. When the CLK signal 104 is asserted and the output of the inverter 90 is asserted (when the CS_n signal 18 and / or the CA signal 19 have not been trained), the NAND gate 92 transmits a de-asserted value to the inverter 94. That is, the Single_cycle signal 106 can effectively gate the CLK signal 104 at the NAND gate 92. Otherwise, the NAND gate 92 transmits an asserted value to the inverter 94. The inverter 94 transmits the inverted output of the NAND gate 92 to the OR gate 88. In other words, when the Single_cycle signal 106 is de-asserted and the CLK signal 104 is asserted, the NAND gate 92 and the inverter 94 act as an AND gate that asserts a value to the OR gate 88. Otherwise, the output of the inverter 94 is de-asserted. Therefore, when the Single_cycle signal 106 is de-asserted, the output from the inverter 94 to the OR gate is the CLK signal 104. In some embodiments, the NAND gate 92 and the inverter 94 can be replaced with an AND gate.

[0047] When the Single_cycle signal 106 is de-asserted, the top portion 116 provides the CLK signal 104 to the OR gate 88, and when the Single_cycle signal 106 is asserted and the latched version of the CS_n signal 18 is asserted, the bottom portion 118 can transmit the CLK signal 104 to the OR gate 88. Otherwise, the CLK signal 104 stops propagating to the OR gate 88. The OR gate 88 can transmit the CLK_CMD signal 114. The CLK_CMD signal 114 can represent a gated CLK signal 104 or a free-running CLK signal 104 based on the values of the CS_n signal 18 and / or the Single_cycle signal 106.

[0048] The synchronizer 101 can shift the CS_n signal 18 by one or more clock cycles when the CS_n signal 18 is asserted. That is, the CS_n signal 18 is transmitted as a data input to the flip-flop 96. The CLK signal 104 is transmitted as a clock input to the flip-flop 96, the flip-flop 98, and the flip-flop 100. The synchronizer 101 can include the flip-flops 96, 98, and 100 to shift the CS_n signal 18 by at least three clock cycles. In the illustrated embodiment, the CS_n signal 18 can be de-asserted in at least 3 cycles. The flip-flop 96 receives the CS_n signal 18 at its data input and the CLK signal 104 at its clock input. The flip-flop 96 outputs the CS_Q1 signal 108 as a shifted version of the CS_n signal 18. The flip-flop 98 receives the CS_Q1 signal 108 at its data input and the CLK signal 104 at its clock input. The flip-flop 98 outputs the CS_Q2 signal 110 as a shifted version of the CS_Q1 signal 108. The flip-flop 100 receives the CS_Q2 signal 110 at its data input and the CLK signal 104 at its clock input. The flip-flop 100 outputs the CS_Q3 signal 112 as a shifted version of the CS_Q2 signal 110. In other words, the synchronizer 101 shifts the CS_n signal 18 to provide different delayed versions of CS_n for the memory device 10.

[0049] Figure 5 Schematic diagram of the flip-flop 120 for using the CLK_CMD signal 114 to capture the CA signal 19. The CLK_CMD signal 114 is transmitted by the clock gating circuitry 35 to latch the corresponding CA bits in the flip-flop 120. The bits of the CA signal 19 are transmitted to the corresponding data inputs of the corresponding flip-flops 120. It should be understood that the flip-flop 120 can represent one or more flip-flops, where each flip-flop corresponds to one bit of the CA signal 19 bus. Thus, each of the flip-flops 120 can hold a bit of the CA signal 19.

[0050] The CAQ signal 124 can represent the bits of the CA signal 19 latched into the corresponding flip-flops 120. Thus, the CAQ signal 124 is shifted from the CA signal 19 by one clock cycle. The flip-flop 120 transmits the CAQ signal to the command decoder 32. Although the illustrated embodiment shows the CA signal 19 and the CAQ signal 124 having 13 bits, some embodiments can include fewer or more bits than 13 bits.

[0051] The command decoder 32 can receive the CAQ signal 124 and decode the valid commands from the CAQ signal 124. Keeping the foregoing in mind, Figure 6 Simplified block diagram of the command decoder 32 for illustrating receiving commands and decoding them. As Figure 1As described, command decoder 32 may receive a command (e.g., MPC) and decode the command to perform various operations.

[0052] Command decoder 32 may receive CAQ signal 124 from flip-flop 120. To decode CAQ signal 124, command decoder 32 may use CS_Q1 signal 108 or CS_Q3 signal input 110 based on the value of Single_cycle signal 106. That is, when Single_cycle signal 106 is logic high, command decoder 32 may use CS_Q1 signal 108 to decode incoming commands on CAQ signal 124. When Single_cycle signal 106 is logic low, command decoder 32 may use CS_Q3 signal 112 to decode incoming MPC commands in CAQ signal 124. Command decoder 32 may use CLK_CMD signal 114 as an internal clock signal for decoding commands.

[0053] Command decoder 32 transmits decoded command signal MPC_CMD 132 to MPC circuitry 130. MPC circuitry 130 also receives CAQ signal 124 from flip-flop 120. MPC circuitry 130 uses MPC_CMD signal 132 from command decoder 32 and CAQ signal 124 to cause one or more commands to be executed. For example, MPC circuitry 130 may use CS_Train_Start signal 134 and / or CA_Train_Start signal 136 to initiate training of CS_n signal 18 and / or CA signal 19 based on MPC_CMD signal 132 and CAQ signal 124.

[0054] By adopting the techniques described in this disclosure, the systems described herein may utilize clock gating after an indication that a chip select signal (CS_n signal 18) and / or a command address signal (CA signal 19) is synchronized with an internal clock signal (CLK). Clock gating circuitry 35 may gate CLK signal 104 with CS_n signal 18 based on a training indication (e.g., Single_cycle signal 106) of the training of CS_n signal 18 and / or CA signal 19. However, when not trained, clock gating circuitry 35 allows CLK signal 104 to run freely to ensure capture of valid commands in the CA signal 19 bus.

[0055] Although only certain features of the present disclosure are illustrated and described herein, many modifications and changes will occur to those skilled in the art. For example, the signal polarity for assertion may be inverted for at least some signals where a logic low is an assertion and a logic high is a de-assertion. Accordingly, it is understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the embodiments described herein.

[0056] The technology presented and claimed herein is referenced and applied to substantial objects and specific instances of a practical nature, which substantially improve the art in a demonstrable manner and are thus not abstract, intangible, or purely theoretical. Further, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing][function]... " or "step for [performing][function]... ", such elements are intended to be construed in accordance with 35 U.S.C. 112(f). However, for any claim that contains elements designated in any other manner, such elements are not intended to be construed in accordance with 35 U.S.C. 112(f).

Claims

1. A memory device, comprising: A clock gating circuitry configured to receive a clock signal from a host device, wherein the clock gating circuitry includes: A first portion of the circuitry configured to gate the clock signal at least in part based on a mode register value indicating synchronization of a command address signal with the clock signal, wherein gating the clock signal in the first portion includes allowing the clock signal to pass through the first portion when the mode register value indicates that the command address signal is not yet synchronized with the clock signal; and A second portion of the circuitry configured to gate the clock signal at least in part based on the mode register value and a chip select signal value.

2. The memory device according to claim 1, wherein gating the clock signal in the first portion includes stopping propagation of the clock signal through the first portion when the mode register value indicates that synchronization of the command address signal with the clock signal has occurred.

3. The memory device according to claim 1, wherein gating the clock signal in the second portion includes allowing the clock signal to pass through the second portion when the mode register value indicates that synchronization of the command address signal with the clock signal has occurred.

4. The memory device according to claim 1, wherein gating the clock signal in the second portion includes stopping propagation of the clock signal through the second portion when the mode register value indicates that the command address signal is not yet synchronized with the clock signal.

5. The memory device according to claim 1, wherein the clock gating circuitry includes a synchronizer, wherein the synchronizer shifts the chip select signal by at least three clock cycles as a first shifted chip select signal.

6. The memory device according to claim 5, comprising a command decoder, wherein the command decoder is configured to: Receive the mode register value; When the mode register value indicates that synchronization of the command address signal with the clock signal has occurred, decode an incoming command using a second shifted chip select signal, wherein the second shifted chip select signal is shifted in the synchronizer by fewer clock cycles than the first shifted chip select signal is shifted in the synchronizer; and When the mode register value indicates that synchronization of the command address signal with the clock signal has not occurred, decode the incoming command using a shifted chip select signal.

7. The memory device according to claim 6, comprising a latch configured to receive the command address signal and latch the command address signal using a gated clock signal, wherein the command decoder is configured to decode the incoming command using the latched command address signal.

8. The memory device according to claim 7, wherein the command decoder is configured to decode a command using the latched command address signal and transmit the decoded command to an MPC circuitry.

9. The memory device according to claim 8, wherein the MPC circuitry is configured to: receive the decoded command; receive the latched command address signal; and perform one or more commands based at least on the decoded command and the latched command address signal.

10. The memory device according to claim 6, wherein the clock gating circuitry is implemented in the command decoder.

11. The memory device according to claim 1, wherein the mode register value is set by the host device.

12. The memory device according to claim 1, wherein the memory device is configured to synchronize the chip select signal with the clock signal before the synchronization of the command address signal and the clock signal.

13. The memory device according to claim 1, wherein the mode register value indicates the synchronization of the chip select signal, the command address signal, or both with the clock signal.

14. A method for a memory device, the method comprising: receiving a clock signal from a host device at a clock gating circuitry of the memory device; gating the clock signal via the clock gating circuitry at least in part based on the mode register value indicating synchronization of a command address signal and the clock signal when the mode register value indicates that the synchronization of the command address signal and the clock signal has not occurred; and gating the clock signal via the clock gating circuitry at least in part based on the mode register value and a chip select signal value when the mode register value indicates that the synchronization of the command address signal and the clock signal has occurred, wherein gating the clock signal at least in part based on the mode register value indicating non - synchronization of the command address signal and the clock signal is performed in a first part of the clock gating circuitry, and gating the clock signal at least in part based on the chip select signal value and the mode register value indicating synchronization of the command address signal and the clock signal is performed in a second part of the clock gating circuitry.

15. The method according to claim 14, which includes shifting the command address signal by at least one clock cycle via a set of flip - flops.

16. The method according to claim 14, which includes: synchronizing the chip select signal with the clock signal before the mode register value indicates that the synchronization of the chip select signal and the clock signal has occurred; and synchronizing the command address signal with the clock signal before setting the mode register value to indicate that the synchronization of the command address signal and the clock signal has occurred.

17. The method according to claim 16, wherein the chip select signal is synchronized with the clock signal before the command address signal is synchronized with the clock signal.

18. A memory system, comprising: a command decoder; a clock gating circuitry configured to receive a clock signal from a host device, wherein the clock gating circuitry is configured to: When the mode register value indicates that the synchronization of the command address signal and the clock signal has not occurred, propagate the clock signal to the command decoder; When the mode register value indicates that the synchronization of the command address signal and the clock signal has occurred and the corresponding chip select signal is asserted, propagate the clock signal to the command decoder; and When the mode register value indicates that the synchronization of the command address signal and the clock signal has occurred but the corresponding chip select signal is de-asserted, prevent the propagation of the clock signal to the command decoder.

19. The memory system according to claim 18, wherein the clock gating circuitry includes a first portion of the circuitry configured to propagate the clock signal to the command decoder when the mode register value indicates that the synchronization of the command address signal and the clock signal has not occurred, and to prevent the propagation of the clock signal to the command decoder via the first portion when the mode register value indicates that the synchronization of the command address signal and the clock signal has occurred.

20. The memory system according to claim 19, wherein the clock gating circuitry includes a second portion of the circuitry configured to propagate the clock signal when the mode register value indicates that the synchronization of the command address signal and the clock signal has occurred and the corresponding chip select signal is asserted, and to prevent the propagation of the clock signal via the second portion when the corresponding chip select signal is not asserted.

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