Memory device, computing device, and method for in-memory computation

Abstract

Embodiments of the present application provide a memory device, a computing device and a method for in-memory computing. The memory device includes an in-memory computing macro and a clock generation circuit. The in-memory computing macro is configured to perform in-memory computation based on a first clock signal. The clock generation circuit is arranged within the in-memory computing macro and is configured to generate the first clock signal. The frequency of the first clock signal is modified according to a condition of the in-memory computing macro to cause the first clock signal to comply with an operating speed of the in-memory computation.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a memory device, a computing device and a method for in-memory computing. BACKGROUND

[0002] The present disclosure generally relates to memory arrays used in data processing, such as multiply-accumulate operations. A compute-in-memory (“CIM” or in-memory computing) system stores information in a random access memory (RAM) of a computer and performs computations at the memory cell level, rather than moving large data between the RAM and data storage units for each computation step. The compute-in-memory system allows real-time analysis of data, as the data stored in the RAM can be accessed quickly, so that reporting and decision making can be faster in machine learning applications. SUMMARY

[0003] According to an aspect of embodiments of the present application, there is provided a memory device, comprising: a compute-in-memory macro configured to perform in-memory computation based on a first clock signal; and a clock generation circuit arranged within the compute-in-memory macro and configured to generate the first clock signal, wherein a frequency of the first clock signal is modified according to a condition of the compute-in-memory macro to cause the first clock signal to comply with an operating speed of the in-memory computation.

[0004] According to an aspect of embodiments of the present application, there is provided a computing device, comprising: a memory array comprising a plurality of memory cells for storing data of a multiply-accumulate operation; a clock generation circuit configured to generate a first clock signal for performing the multiply-accumulate operation, wherein a frequency of the first clock signal is determined based on a process-voltage-temperature (PVT) condition to comply with an operating speed of the multiply-accumulate operation; an input buffer circuit configured to receive input data from an input channel and output the input data to the memory array; and an output buffer circuit configured to receive output data generated by the multiply-accumulate operation from the memory array and output the output data to an output channel.

[0005] According to an aspect of embodiments of the present application, there is provided a method for in-memory computation, comprising: tracking a process-voltage-temperature condition of a compute-in-memory macro for performing a multiply-accumulate operation; generating a first clock signal and adjusting a frequency of the first clock signal based on the process-voltage-temperature condition to comply with an operating speed of the multiply-accumulate operation; and sending input data to the compute-in-memory macro through an input buffer circuit and receiving output data from the compute-in-memory macro based on the first clock signal through an output buffer circuit. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present application can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be emphasized that various components are not necessarily drawn to scale and the dimensions of the various components can be arbitrarily increased or decreased for the sake of clarity. In fact, the dimensions can be arbitrarily increased or decreased for the sake of clarity in discussion.

[0007] Figure 1 is a schematic diagram of an exemplary memory device according to some embodiments of the disclosure.

[0008] Figure 2 is a diagram of an exemplary CIM macro according to some embodiments of the disclosure.

[0009] Figure 3 is a diagram illustrating exemplary operation of a clock generation circuit according to some embodiments of the disclosure.

[0010] Figure 4 is a diagram illustrating exemplary clock generation circuitry of a CIM macro according to some embodiments of the disclosure. Figure 2

[0011] Figure 5 is a block diagram illustrating an exemplary memory array of Figure 2

[0012] Figure 6 is a schematic diagram of an exemplary memory cell according to some embodiments of the disclosure.

[0013] Figure 7 is a diagram illustrating exemplary communication between a CIM macro and an input buffer circuit according to some embodiments of the disclosure.

[0014] Figure 8 is a diagram illustrating exemplary communication between a CIM macro and an output buffer circuit according to some embodiments of the disclosure.

[0015] Figure 9 is a diagram illustrating exemplary communication between a CIM macro, an input buffer circuit, and an output buffer circuit according to some embodiments of the disclosure.

[0016] Figure 10 is a flowchart of a method for in-memory computing according to some embodiments of the disclosure. DETAILED DESCRIPTION

[0017] ​​The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the application can refer to a number and / or letter throughout the various examples. This repetition is for simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] The terms used in this specification generally have their ordinary meanings in the art, and in the specific context of the particular claim in which the term is used. The use of any and all examples, or exemplary language (e.g., "for instance") provided herein, is intended merely to better illuminate the application and does not pose a limitation on the scope of the disclosure or any exemplary language. No language is intended to cause a limitation of the scope of the application. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

[0019] Although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in different use or operation environments. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0021] In this document, the term "coupled" can also be called "electrically coupled", and the term "connected" can be called "electrically connected". "Coupled" and "connected" can also be used to indicate that two or more elements cooperate or interact with each other.

[0022] Various embodiments of the present disclosure will be described with respect to embodiments in a particular context, namely compute-in-memory (“CIM”) applications. One example of a CIM application is a multiply-accumulate (“MAC”) operation. In a MAC operation, numbers in an input array (e.g., a row) are multiplied or “weighted” by numbers (e.g., weights) in respective elements of another array (e.g., a column), and the products are added by an accumulator in some (accumulation) to compute an output sum. This operation is mathematically similar to the dot product of two vectors (i.e., a scalar product). In a dot product operation, the dot product of two vectors is defined as the sum of the products of pairs of components, where the components of the two vectors are multiplied in pairs.

[0023] Figure 1 is a schematic diagram of a memory device 100 in accordance with some embodiments of the present disclosure. In some embodiments, the memory device 100 can be used as a computing device to perform compute-in-memory. As shown, the memory device 100 includes a CIM macro 110, an input buffer circuit 120 coupled with the CIM macro 110, and an output buffer circuit 130 coupled with the CIM macro 110. In some embodiments, the input buffer circuit 120 and the output buffer circuit 130 can be implemented as static random access memory (SRAM) cells. A clock generation circuit 140 is disposed within the CIM macro 110 and is configured to generate one or more clock signals for performing compute-in-memory. Figure 1

[0024] In some embodiments, the CIM macro 110 can be an SRAM macro. In an SRAM device, data can be written to and read from each SRAM cell via one or more bit lines (“BLs”) when one or more access transistors in the SRAM cell are activated by an enable signal from one or more word lines (“WLs”). Although an SRAM macro is used as an example in the present disclosure, it should be understood that other types of memory are within the scope of various embodiments. Figure 1 The CIM macro 110 can be a CIM device configured to perform various compute-in-memory operations, such as multiply-accumulate (MAC) operations. For example, the memory device 100 can receive an input signal and multiply numbers indicated by the input signal by respective weights stored in memory cells in the CIM macro 110. The CIM macro 110 can then add the products by an accumulator to obtain an output signal indicating an output sum. Specifically, in an SRAM-based CIM design, a plurality of word lines associated with a column of SRAM cells can be turned on to discharge a common bit line, such as a read bit line (“RBL”), to implement a 1-bit MAC operation.

[0025] ​The MAC operation is a primary computation used in chip-level artificial intelligence (AI) for training and manipulating neural networks. In some AI systems, such as artificial neural networks, an array of data (i.e., numbers) is weighted using multiple columns of weights. The weighting performed on each column generates its own output sum. Therefore, an AI system can generate an output array of sums from an input array of data (i.e., numbers) multiplied by the weights in a matrix of multiple columns of weights. In other words, an AI system can map inputs to outputs based on a set of weights. A similar operation is employed in some applications, such as multi-bit convolutional neural networks (“CNNs”). When an AI system trains a neural network, the network can use various algorithms to update the weights used in the MAC operation to develop an appropriate set of weights that allows the neural network to correctly classify the data.

[0026] In some embodiments, input buffer circuit 120 may store input data received from external circuitry (e.g., input feature maps to be processed) and provide the stored input data to CIM macro 110 for computation. CIM macro 110 stores weight values ​​for MAC computation, and using the input data provided by input buffer circuit 120, the memory array and logic circuitry within CIM macro 110 perform multiplication and accumulation to obtain the computation result. Therefore, the output data obtained after computation can be provided to and stored in output buffer circuit 130. Output buffer circuit 130 can then communicate with external circuitry (e.g., main memory) and send the final computation output to the external circuitry.

[0027] Figure 2 This is a diagram of an exemplary CIM macro 110 according to some embodiments of this disclosure. (See diagram for example.) Figure 2 As shown, the CIM macro 110 includes one or more CIM memory arrays 210, one or more control circuits 220 with clock generation circuitry 140, and drive circuits 230, 240. In some embodiments, the CIM memory array 210 may include multiple memory segments. Each memory segment may include a memory bank. Storage cells in the memory bank are arranged in rows and columns. Therefore, the storage cells in the memory segments and memory array 210 are also arranged in rows and columns.

[0028] The one or more control circuits 220 can include global control circuits and local control circuits for controlling memory operations in the one or more CIM memory arrays 210. For example, the global control circuits can provide row addresses, column address pre-decoding, clocking, and other signals used in the CIM macro 110. The global control circuits can also communicate with input-output (I / O) circuits to control data transfer between the one or more CIM memory arrays 210 and external circuits. For example, the one or more control circuits 220 can generate a column select signal based on a clock signal and an address of a storage cell to be read to select a column in the one or more CIM memory arrays 210 to be pre-charged or to be read.

[0029] In some embodiments, each driver circuit 230 includes an input activation driver and an SRAM word line (WL) driver. For example, the input activation driver can provide inputs from the input buffer circuit 120 into the CIM memory array 210, and the SRAM word line (WL) driver can provide a word line signal to a corresponding word line of the one or more CIM memory arrays 210. For example, the inputs can be fed into the CIM memory array 210 simultaneously in a MSB-first bit-serial manner.

[0030] In some embodiments, the driver circuit 240 includes an SRAM read / write circuit configured to communicate with a corresponding storage cell within the CIM memory array 210 to perform a read or write operation to update a weight value stored in the CIM memory. The CIM macro 110 can also include other circuit elements, such as decoders, or other input-output (I / O) circuits for transferring data between the storage cells in the respective CIM memory array 210 and external circuits outside of the CIM macro 110.

[0031] When the CIM macro 110 performs the MAC operation, the operation speed of the MAC operation is sensitive to variations in PVT (process, voltage, and temperature) conditions, which can introduce inaccuracies or errors in the accumulation function in the MAC operation. For example, when the CIM macro 110 operates in different voltage conditions, the MAC operation speed can be faster at a higher voltage than at a lower voltage. Similarly, when the CIM macro 110 operates in different temperature conditions, the MAC operation speed can be faster at a higher temperature than at a lower temperature. In addition, unexpected dynamic voltage (IR) drops can also affect the operation speed of the MAC operation. Thus, the MAC operation speed can be slower when the CIM macro 110 performs the MAC operation at a low power supply.

[0032] When the MAC operation speed is lower than the clock frequency in the CIM macro 110 that performs the MAC operation, the CIM macro 110 cannot correctly perform the accumulation function, resulting in MAC operation errors. In various embodiments of the present disclosure, the clock generation circuit 140 within the control circuit 220 can provide an internal clock having a frequency that is automatically dynamically adjustable and modifiable according to PVT (process, voltage, and temperature) conditions of the CIM macro 110 to prevent errors. The CIM macro 110 performs in-memory computation based on the internal clock generated by the clock generation circuit 140. For example, the CIM macro 110 can exchange data with external circuits based on the internal clock.

[0033] Figure 3 is a diagram illustrating an exemplary operation of the clock generation circuit 140 according to some embodiments of the present disclosure. As shown, the clock generation circuit 140 in the CIM macro 110 is configured to generate a clock signal CLK1 for the MAC operation, such that the CIM macro 110 performs the MAC operation according to the clock signal CLK1. For example, the CIM macro 110 can receive input data 104 from the input buffer circuit 120 according to the clock signal CLK1, and provide output data 106 to the output buffer circuit 130 according to the clock signal CLK1. Figure 3

[0034] In some embodiments, the frequency of the clock signal CLK1 can be modified according to conditions (e.g., PVT conditions) of the CIM macro 110 to cause the clock signal CLK1 to comply with the operation speed of the MAC operation. Specifically, the frequency of the clock signal CLK1 can be associated with one or more PVT conditions of the CIM macro 110 to ensure that the frequency of the clock signal CLK1 is within a desired range corresponding to the MAC operation speed. In some embodiments, the frequency of the clock signal CLK1 is equal to or less than the MAC operation speed. For example, the clock generation circuit 140 can include PVT-dependent components, such as NMOS or PMOS transistors. Propagation delays caused by the PVT-dependent components within the clock generation circuit 140 depend on PVT variations. Thus, signals passing through the PVT-dependent components are automatically adjusted in response to different PVT conditions or unexpected power IR drops, implementing a clock throttle such that the clock generation circuit 140 outputs the clock signal CLK1 that complies with the MAC operation speed.

[0035] ​With the above clock adjustment, the clock generation circuit 140 can track the environment (e.g., voltage and temperature) and process of the CIM macro 110 using PVT-dependent components to allow efficient data transfer to or from the CIM macro 110 and achieve dynamic clocking. More specifically, the clock generation circuit 140 can adjust the generated clock signal CLK1 in response to changes in the environmental conditions (e.g., voltage and temperature) and process. With this dynamic clock signal CLK1, the CIM macro is able to perform MAC operations accordingly to maximize operational performance under different operating conditions.

[0036] In comparison, without the dynamic clocking function of the clock generation circuit 140, the MAC operations can only operate according to a fixed clock signal based on worst-case scenarios, which can be different from the actual operating conditions. As a result, without the clock generation circuit 140 generating the dynamic clock signal CLK1, the MAC operations and data transfer are less efficient.

[0037] Figure 4 is in accordance with some embodiments of the present disclosure Figure 2 FIG. 1 illustrates an exemplary configuration of a clock generation circuit 140 in accordance with some embodiments of the present disclosure. As shown in FIG. 1, the clock generation circuit 140 is configured to receive an enable signal EN and a clock signal CLK1 from an output node of the clock generation circuit 140. The clock generation circuit 140 is configured to generate a dynamic clock signal CLK1 based on the enable signal EN and the clock signal CLK1 from the output node of the clock generation circuit 140. Figure 4 As shown in FIG. 2, in some embodiments, the clock generation circuit 140 includes a NAND (not AND) logic circuit 410 and a delay line circuit 420. The NAND logic circuit 410 performs a NAND operation based on the enable signal EN and the clock signal CLK1 fed back from the output node of the clock generation circuit 140 to output a gate output signal S1 to the delay line circuit 420. The delay line circuit 420 is configured to receive the gate output signal S1 and modify the gate output signal S1 to generate the clock signal CLK1 by delaying the gate output signal S1.

[0038] In some embodiments, the delay line circuit 420 includes a plurality of delay elements (e.g., buffers) B1, B2,..., Bn coupled in series with each other. Each of the delay elements B1, B2,..., Bn is configured to delay an output of its input signal and output the delayed signal to the next stage. Thus, the first delay element B1 in the series receives the gate output signal S1, and the nth delay element Bn in the series outputs the clock signal CLK1, which is a delayed signal in response to the gate output signal S1. The delay elements B1, B2,..., Bn in the delay line circuit 420 include PVT-dependent components, such as NMOS transistors or PMOS transistors, that provide a delay associated with PVT conditions. Thus, the propagation delay of the delay elements B1, B2,..., Bn depends on PVT variations. Since the clock generation circuit 140 is integrated within the CIM macro 110, the generated clock signal CLK1 is compliant with the computation performed by the CIM macro 110. For example, the number of delay elements B1, B2,..., Bn can be associated with the number of stages of the CIM macro 110. Thus, the clock signal CLK1 for the MAC operation is delayed to make the clock signal CLK1 compliant with the MAC operation speed that depends on PVT conditions or unexpected power IR drops.

[0039] Specifically, when the enable signal EN received at one input of the NAND logic circuit 410 is disabled (e.g., at a logic low), the gate output signal S1 at the output of the NAND logic circuit 410 becomes a logic high (e.g., 1) regardless of the other input. Thus, the clock signal CLK1, which is a signal delayed by the delay line circuit 420, also becomes a logic high (e.g., 1) to reach a steady state.

[0040] When the enable signal EN is enabled (e.g., transitions to a logic high), the gate output signal S1 at the output of the NAND logic circuit 410 transitions to a logic low (e.g., 0) in response to both the enable signal EN and the feedback clock signal CLK1 being high. After a delay period, the clock signal CLK1 also transitions to a logic low (e.g., 0). The clock signal CLK1 transitioning to the logic low triggers the NAND logic circuit 410 to output the gate output signal S1 as a logic high (e.g., 1). Thus, after another delay period, the clock signal CLK1 again transitions from the logic low to the logic high, triggering another cycle. Thus, when the enable signal EN is enabled, the clock generation circuit 140 generates the periodic clock signal CLK1.

[0041] In summary, clock generation circuit 140 generates a clock signal CLK1 corresponding to one or more process-voltage-temperature (PVT) conditions, such as process conditions, voltage conditions, temperature conditions, power supply IR drop conditions, or any combination thereof. Clock generation circuit 140 can adjust the frequency of clock signal CLK1 in response to the PVT conditions of CIM macro 110 and provide the dynamically modified clock signal CLK1 to input buffer circuit 120 and output buffer circuit 130 for performing MAC operations. Therefore, clock generation circuit 140 is configured to provide sufficient delay for low-speed operation or low-frequency signals and relatively small delay for high-speed operation under different environmental conditions (e.g., voltage and temperature) and process conditions, allowing memory device 100 to optimize performance, provide efficient data transfer, and ensure correct execution of MAC operations.

[0042] Figure 5 The illustrations are of some embodiments according to this disclosure. Figure 2 A block diagram illustrating an exemplary configuration of the CIM memory array 210. (See diagram for reference.) Figure 5 As shown, the memory array 210 has multiple rows and columns of sub-CIM cells 510. In some embodiments, the memory array 210 includes 64 columns to provide 64 sections and outputs, and the sub-CIM cells 510 in the same column are respectively coupled to 256 input lines to receive input data. Figure 5 In some embodiments, each sub-CIM unit 510 includes an SRAM unit 512 for storing data (e.g., corresponding weights) for multiply-accumulate operations, and a bitwise multiplier 514 for performing the multiplication operations. In some embodiments, an SRAM unit can be implemented using a 6T (6 transistors) based SRAM memory unit, and its associated multiplier 514 can be implemented using a 4T based NOR (or NOT) gate configured to perform bitwise multiplication. The outputs of the sub-CIM units 510 in the same column are provided to a parallel adder tree 520 and a partial sum accumulator 530 for performing accumulation operations.

[0043] In the following paragraphs, the structure and circuitry of the sub-CIM unit 510, associated with the corresponding row i and the corresponding column j, are described as examples, along with the operation of the corresponding signal lines. Figure 5As shown, for a sub-CIM unit 510[i,j], the storage unit 512 is connected to a word line WL[i] associated with row i and bit line BL[j] and a bar bit line BLB[j] associated with column j. When activated by a signal on the word line WL[i], the storage unit 512 can be configured to input a binary signal (0 or 1) indicative of a weight (“W”) based on the values of the bit line BL[j] and the bar bit line BLB[j] and update the weight accordingly. For example, the weights can be pre-computed or updated by an AI algorithm and written into the storage unit 512 for MAC computation.

[0044] The multiplier 514 receives the inverse weight value (e.g., WB[i,j]) from the storage unit 512 and the inverse input value from the associated inverse input line IN_B[i]. Thus, the value output by the multiplier 514 is determined by the data from the input line and the weight stored in the storage unit 512. When the signal on the input line IN[i] is logic high (“1”) (i.e., the inverse input line IN_B[i] is 0), the output of the multiplier 514 is the inverse value of the inverse weight value (i.e., the weight value) (e.g., WB[i,j]). When the signal on the input line IN[i] is logic low (“0”) (i.e., the inverse input line IN_B[i] is 1), a “0” is output regardless of the weight stored in the storage unit 512. Thus, the output of the multiplier 514 is the product of the input signal and the weight stored in the storage unit 512, which can be given by Table 1 below:

[0045] Table 1

[0046] enter Weight Output 0 0 0 0 1 0 1 0 0 1 1 1

[0047] For example, in some embodiments, 256 sub-CIM units 510 in the same column are configured to perform 256 multiplications based on input data and corresponding weights, respectively, in one cycle. As shown in FIG. 5, the 256 sub-CIM units 510 are configured to perform 256 multiplications in one cycle. Figure 5 As shown, in one sub-CIM unit 510, the multiplier 514 is electrically connected to a corresponding inverse input line (“IN_B”) to receive input data and multiply the input data with a corresponding weight stored in the associated SRAM unit 512 coupled to the multiplier 514. The sub-CIM unit 510 sends the multiplication result to the adder tree 520 to generate a partial sum. After four cycles, the partial sum accumulator 530 is configured to accumulate the partial sum of each cycle in a pipelined manner to complete the accumulation. The partial sum accumulator 530 can output the final result to the output buffer circuit 230.

[0048] When using a multiply-accumulate system as a model for AI applications, the CIM macro 110 can provide a set of input data (i.e., numbers) to the current model via input line IN[i]. The input data is processed by multiplying each input by its corresponding weight stored in memory array 210 and summing the multiplications to obtain output data. The output data is then compared to a target output voltage or desired output voltage. If the output data is not close enough to the desired value, the model system is adjusted and the process is repeated until the output data is sufficiently close to the desired value. For example, the CIM macro 110 can include a two-dimensional array of elements arranged in rows and columns, each element storing weights, and capable of receiving inputs and generating an output that is the arithmetic product of the inputs and the stored weights. The model system can provide each input to a row of elements and sum the outputs of each column of elements.

[0049] Because neural networks can have various topologies and bit-width precision, the memory device 100 with a CIM structure can support different neural networks using multiple macros (parallel, serial, or 2D arrays). For example, three cascaded CIM memory arrays 210 can support convolution operations with 3×3 filters having 64 channels. Furthermore, weight updates can be performed concurrently with each MAC operation.

[0050] Figure 6 This is a schematic diagram of an exemplary storage cell 512 according to some embodiments of the present disclosure. In some embodiments, storage cell 512 is a six-transistor (6T) single-port (SP) SRAM memory cell, which can be used to implement Figure 5 The storage cell 512 is shown. In some other embodiments, the storage cell 512 employs multiple transistors other than six. For example, in some other embodiments, the storage cell 512 can be implemented using 8T SRAM bit cells, 10T SRAM bit cells, or any other type of memory cell. Figure 6 The 6T SRAM cell 512 illustrated in the figure is exemplary and used to explain features, but is not intended to limit the embodiments of this disclosure.

[0051] like Figure 6 As shown, storage cell 512 includes a pair of cross-coupled inverters 610, and access transistors 620 and 630 (also referred to as transmission gates or transmission transistors). The pair of cross-coupled inverters 610 includes two p-type metal-oxide-semiconductor (PMOS) transistors 612 and 614 and two n-type metal-oxide-semiconductor (NMOS) transistors 616 and 618. The source terminals of the PMOS transistors 612 and 614 are electrically connected to the power supply voltage (V). DDTerminals. The drain terminals of PMOS transistors 612 and 614 are electrically connected to the drain terminals of NMOS transistors 616 and 618 at corresponding nodes 640 and 650, respectively. In some embodiments, Figure 5 The multiplier 514 in the memory is electrically coupled to node 650 and receives the inverse weight value from node 650 of the storage unit 512.

[0052] The source terminals of NMOS transistors 616 and 618 are electrically connected to the reference node. For example... Figure 6 As shown, in some embodiments, the reference node is essentially equal to a logic low signal. For example, the reference node can be essentially equal to the ground voltage (V). SS The gate terminal of PMOS transistor 612 is electrically connected to the gate terminal of NMOS transistor 616 and the respective source / drain terminals of NMOS transistor 618 and PMOS transistor 614. Similarly, the gate terminal of PMOS transistor 614 is electrically connected to the gate terminal of NMOS transistor 618 and the respective source / drain terminals of NMOS transistor 616 and PMOS transistor 612.

[0053] PMOS transistors 612 and 614 can be referred to as pull-up transistors, and NMOS transistors 616 and 618 can be referred to as pull-down transistors. Specifically, PMOS transistors 612 and 614 are configured to pull the voltage potential towards the supply voltage V. DD NMOS transistors 616 and 618 are configured to pull a voltage potential toward a reference node (e.g., ground voltage V). SS ).

[0054] Access transistor 620 is configured to selectively connect the cross-coupled inverter 610 to bit line BL. Access transistor 630 is configured to selectively connect the cross-coupled inverter 610 to the inverted bit line BLB. Both access transistors 620 and 630 are configured to be activated based on a signal on word line WL. Figure 6 As shown, in some embodiments, access transistors 620 and 630 may be NMOS transistors having gate terminals electrically connected to word line WL, but this disclosure is not limited thereto. In other embodiments, access transistors 620 and 630 may be implemented by PMOS transistors.

[0055] for Figure 6The storage cell 512 has NMOS transistors for accessing transistors 620 and 630, and the storage cell 512 is connected to the bit line BL or the inverted bit line BLB via a logic high signal at the gate terminal of access transistor 620 or access transistor 630. Conversely, if the storage cell 512 alternatively includes PMOS transistors for accessing transistors 620 and 630, the storage cell 512 is connected to the bit line BL or the inverted bit line BLB via a logic low signal at the gate terminal of access transistor 620 or access transistor 630.

[0056] In various embodiments, storage cell 512 may have any suitable physical structure. For example, but not limited to, transistors 612, 614, 616, 618, 620 and 630 in storage cell 512 may include three-dimensional gate structures, such as fin field-effect transistors (FinFETs).

[0057] Figure 7 This is a diagram illustrating exemplary communication between a CIM macro 110 and an input buffer circuit 120 according to some embodiments of the present disclosure. Figure 7 As shown, in some embodiments, the input buffer circuit 120 is configured to receive input data 102 from one or more external circuits via the input channel 710 of the memory device 100, and output the received input data 104 to the CIM macro 110 for performing MAC operations. For example, the input data 102 may first be transferred or retrieved into the input buffer circuit 120 based on a write clock signal. Then, in response to a read command based on a read clock signal provided to the input buffer circuit 120, the retrieved data stored in the input buffer circuit 120 is correspondingly provided from the input buffer circuit 120 to the CIM macro 110.

[0058] In some embodiments, the input buffer circuit 120 may be a first-in-first-out (FIFO) buffer, but this disclosure is not limited thereto. In some embodiments, the input buffer circuit 120 receives two different clock signals to enable data transfer between the input channel 710 and the CIM macro 110. For example, the input buffer circuit 120 may receive input data 102 based on the system clock signal CLK2 and output input data 104 to the CIM macro 110 according to the clock signal CLK1. In some embodiments, the internal clock signal CLK1 and the system clock signal CLK2 for the CIM macro 110 may be asynchronous clock signals. Alternatively, the input buffer circuit 120 may be an asynchronous FIFO that uses the system clock signal CLK2 as the write clock signal and uses the internal clock signal CLK1 as the read clock signal, which is asynchronous with the write clock signal. Therefore, the input buffer circuit 120 inputs data from the input channel 710 according to the write clock signal and outputs data to the CIM macro 110 according to the read clock signal.

[0059] In some embodiments, the input buffer circuit 120 can be part of the input interface of the memory device 100. For example, the input interface of the memory device 100 can further include digital counters and drivers. Each counter is configured to output a number of pulses in one counting period. The number of pulses corresponds to the number at the input of the counter. For example, an input of 00002 (i.e., 0 10 ) generates 0 pulses, an input of 00102 (i.e., 2 10 ) generates 2 pulses, an input of 11112 (i.e., 15 10 ) generates 15 pulses, and so on. In other words, in some embodiments, the number of pulses represents the decimal representation of a 4-bit binary number at the input of the counter. The driver corresponding to the counter is configured to drive the corresponding read word line of the memory device 100 according to the pulses output from the counter accordingly.

[0060] Figure 8 is a diagram illustrating exemplary communication between the CIM macro 110 and the output buffer circuit 130 according to some embodiments of the present disclosure. As shown in Figure 8 , in some embodiments, the output buffer circuit 130 is configured to receive the output data 106 output from the CIM macro 110 and output the received output data 108 to one or more external circuits in communication with the output channel 810 through the output channel 810.

[0061] In some embodiments, similar to the input buffer circuit 120 in Figure 7 , the output buffer circuit 130 can also be a first-in-first-out (FIFO) buffer, but the present invention is not limited thereto. In some embodiments, the output buffer circuit 130 also receives two different clock signals to enable data transfer between the output channel 810 and the CIM macro 110. For example, the output buffer circuit 130 can receive the output data 106 from the CIM macro 110 based on an internal clock signal CLK1 for the CIM macro 110 and output the output data 108 to the output channel 810 based on a system clock signal CLK2, which is an asynchronous clock signal with respect to the internal clock signal CLK1. In other words, the output buffer circuit 130 can be an asynchronous FIFO that uses the internal clock signal CLK1 as a write clock signal and uses the system clock signal CLK2 as a read clock signal that is asynchronous with the write clock signal, so the output buffer circuit 130 inputs data from the CIM macro 110 according to the write clock signal and outputs data to the output channel 810 according to the read clock signal.

[0062] Figure 9is a diagram illustrating exemplary communication between a CIM macro 110, an input buffer circuit 120, and an output buffer circuit 130, in accordance with some embodiments of the present disclosure. As shown, in some embodiments, the input buffer circuit 120 and the output buffer circuit 130 can receive input data 102 from an input channel 710 and output output data 108 to an output channel 810, respectively, based on a same system clock signal CLK2. A clock generation circuit 140 communicates with the input buffer circuit 120 and the output buffer circuit 130 and generates a clock signal CLK1, such that the input buffer circuit 120 and the output buffer circuit 130 can transmit input data 104 and output data 106 of the CIM macro 110 based on the same clock signal CLK1. It can be appreciated that, Figure 9 , Figure 7 , Figure 8 , Figure 9 The input buffer circuit 120 and the output buffer circuit 130 shown in

[0063] Figure 10 is a flowchart of a method 1000 for in-memory computing, in accordance with some embodiments of the present disclosure. It should be understood that additional operations can be performed before, during, and / or after the method 1000 depicted in Figure 10 may be performed by the memory device 100 illustrated in embodiments of Figures 1 to 9 , but the present disclosure is not limited thereto.

[0064] In operation 1010, process-voltage-temperature (PVT) dependent components (e.g., NMOS transistors and / or PMOS transistors within a delay line circuit 420 in Figure 2 ) within a clock generation circuit (e.g., the clock generation circuit 140 in Figure 4 ) track one or more process-voltage-temperature conditions of a memory-in-compute macro (e.g., the CIM macro in Figure 1 ) for performing multiply-accumulate operations.

[0065] In operation 1020, the clock generation circuit generates a first clock signal (e.g., the clock signal CLK1 in Figure 3 ) and adjusts a frequency of the first clock signal based on the one or more process-voltage-temperature conditions to comply with an operational speed of the multiply-accumulate operations. In some embodiments, a logic circuit in the clock generation circuit performs a NAND operation based on an enable signal and the first clock signal to output a first gate output signal, and a delay line circuit after the logic circuit delays the first gate output signal to generate the first clock signal.

[0066] In operation 1030, an input buffer circuit (e.g., the input buffer circuit 120 in Figure 1In operation 1030, the input buffer circuit receives input data based on the first clock signal (e.g., clock signal CLK1 in FIG. 1) from the input channel and then provides the input data stored in the input buffer circuit to the CIM macro. In some embodiments, the output buffer circuit outputs the stored output data to the output channel based on the second clock signal (e.g., clock signal CLK2 in FIG. 1). The first clock signal and the second clock signal are asynchronous clock signals.

[0067] In some embodiments, the input buffer circuit receives the input data based on a second clock signal (e.g., clock signal CLK2 in FIG. 1) from the input channel and then provides the input data stored in the input buffer circuit to the CIM macro. In some embodiments, the output buffer circuit outputs the stored output data to the output channel based on the second clock signal. The first clock signal and the second clock signal are asynchronous clock signals. Figure 9

[0068] By the above operations, a method for in-memory computing can be performed to process the MAC operation in the CIM macro with the clock generation circuit for generating the internal clock signal corresponding to the dynamic adjustment of the PVT condition. Therefore, the adaptive clock provided by the clock generation circuit can optimize the operation performance and avoid the MAC operation error due to the PVT variation, which improves the data transmission between the CIM macro and the external circuit and also improves the overall device performance.

[0069] In some embodiments, a memory device is disclosed, which includes a CIM macro configured to perform in-memory computing based on a first clock signal, and a clock generation circuit arranged within the in-memory computing macro and configured to generate the first clock signal. The frequency of the first clock signal is modified according to the condition of the in-memory computing macro to cause the first clock signal to comply with the operation speed of the in-memory computing.

[0070] In some embodiments, the condition of the in-memory computing macro includes a process-voltage-temperature (PVT) condition.

[0071] In some embodiments, the clock generation circuit includes one or more process-voltage-temperature (PVT) condition dependent components configured to provide a delay associated with the PVT condition.

[0072] In some embodiments, the clock generation circuit includes a logic circuit configured to perform a NAND operation based on an enable signal and the first clock signal to output a first gate output signal, and a delay line circuit electrically coupled to the logic circuit and configured to generate the first clock signal by delaying the first gate output signal.

[0073] ​In some embodiments, the delay line circuit includes a plurality of delay elements coupled in series with each other, where a first delay element in the series receives the first gate output signal and a last delay element in the series outputs the first clock signal.

[0074] In some embodiments, the memory device further includes: an input buffer circuit coupled to the in-memory compute macro and configured to receive input data based on a second clock signal from an input channel and output the input data in the in-memory compute macro based on the first clock signal.

[0075] In some embodiments, the input buffer circuit includes a first-in-first-out buffer.

[0076] In some embodiments, the first clock signal and the second clock signal are asynchronous clock signals.

[0077] In some embodiments, the memory device further includes: an output buffer circuit coupled to the in-memory compute macro and configured to receive output data based on the first clock signal from the in-memory compute macro and output the output data to an output channel based on a second clock signal.

[0078] In some embodiments, the output buffer circuit includes a first-in-first-out buffer.

[0079] In some embodiments, the first clock signal and the second clock signal are asynchronous clock signals.

[0080] In some embodiments, a computing device is disclosed, the computing device including: a memory array including a plurality of memory cells to store data for a multiply- accumulate operation; a clock generation circuit configured to generate a first clock signal for performing the multiply-accumulate operation; an input buffer circuit configured to receive input data from an input channel and output the input data to the memory array; and an output buffer circuit configured to receive output data generated by the multiply-accumulate operation from the memory array and output the output data to an output channel. A frequency of the first clock signal is determined based on process-voltage-temperature (PVT) conditions to comply with an operational speed of the multiply-accumulate operation.

[0081] In some embodiments, the frequency of the first clock signal is less than or equal to the operational speed.

[0082] In some embodiments, the clock generation circuit includes a delay line circuit, the delay line circuit including one or more PVT-dependent components.

[0083] In some embodiments, the clock generation circuit includes a logic circuit configured to perform a NAND operation based on the enable signal and the first clock signal to output a NAND gate output signal, and a plurality of delay elements coupled in series with each other, wherein a first delay element in the series receives the NAND gate output signal and a last delay element in the series outputs the first clock signal.

[0084] In some embodiments, the input buffer circuit is configured to receive the input data based on a second clock signal and output the input data based on the first clock signal for performing the multiply-accumulate operation, and the output buffer circuit is configured to receive the output data from the multiply-accumulate operation based on the first clock signal and output the output data based on the second clock signal, the first clock signal and the second clock signal being asynchronous clock signals.

[0085] In some embodiments, a method for in-memory computing is also disclosed, including tracking a process-voltage-temperature condition of an in-memory computing macro for performing a multiply-accumulate operation, generating a first clock signal and adjusting a frequency of the first clock signal based on the process-voltage-temperature condition to comply with an operating speed of the multiply-accumulate operation, sending input data to the in-memory computing macro through an input buffer circuit and receiving output data from the in-memory computing macro through an output buffer circuit based on the first clock signal.

[0086] In some embodiments, generating the first clock signal includes performing a NAND operation by a logic circuit based on the enable signal and the first clock signal to output a first gate output signal, and delaying the first gate output signal by a delay line circuit to generate the first clock signal.

[0087] In some embodiments, the above method further includes receiving the input data by the input buffer circuit based on a second clock signal from an input channel, wherein the first clock signal and the second clock signal are asynchronous clock signals.

[0088] In some embodiments, the above method further includes outputting the output data received by the output buffer circuit to an output channel based on a second clock signal.

[0089] The foregoing summarizes features of several embodiments in order that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same goals and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: The macro is computed in memory and configured to perform in-memory computations based on a first clock signal. as well as A clock generation circuit is arranged within the computation macro in the memory and configured to generate the first clock signal, wherein the frequency of the first clock signal is modified according to the conditions of the computation macro in the memory so that the first clock signal conforms to the operating speed of the computation within the memory. The clock generation circuit includes: The logic circuit is configured to perform a NAND operation based on an enable signal and a first clock signal to output a first gate output signal; and A delay line circuit is electrically coupled to the logic circuit and configured to generate the first clock signal by delaying the output signal of the first gate.

2. The memory device according to claim 1, wherein, The conditions for calculating macros in the memory include process-voltage-temperature conditions.

3. The memory device according to claim 1, wherein, The clock generation circuit includes one or more process-voltage-temperature condition-related components configured to provide a delay associated with process-voltage-temperature conditions.

4. The memory device according to claim 1, wherein, The delay line circuit includes multiple buffers coupled in series with each other.

5. The memory device according to claim 1, wherein, The delay line circuit includes multiple delay elements coupled in series with each other, wherein the first delay element in the series receives the first gate output signal and the last delay element in the series outputs the first clock signal.

6. The memory device according to claim 1, further comprising: An input buffer circuit is coupled to the computation macro in the memory and configured to receive input data based on a second clock signal from the input channel, and to output the input data in the computation macro in the memory based on a first clock signal.

7. The memory device according to claim 6, wherein, The input buffer circuit includes a first-in-first-out buffer.

8. The memory device according to claim 6, wherein, The first clock signal and the second clock signal are asynchronous clock signals.

9. The memory device according to claim 1, further comprising: An output buffer circuit is coupled to a computation macro in the memory and configured to receive output data based on a first clock signal from the computation macro in the memory, and to output the output data to an output channel based on a second clock signal.

10. The memory device according to claim 9, wherein, The output buffer circuit includes a first-in-first-out buffer.

11. The memory device according to claim 9, wherein, The first clock signal and the second clock signal are asynchronous clock signals.

12. A computing device, comprising: A memory array comprising multiple memory cells for storing data for multiplication-accumulation operations; A clock generation circuit is configured to generate a first clock signal for performing the multiplication-accumulation operation, wherein the frequency of the first clock signal is determined based on process-voltage-temperature conditions to match the operating speed of the multiplication-accumulation operation; An input buffer circuit is configured to receive input data from an input channel and output the input data to the memory array; and An output buffer circuit is configured to receive output data generated by the multiplication-accumulation operation from the memory array and output the output data to an output channel. The clock generation circuit includes: The logic circuit is configured to perform a NAND operation based on an enable signal and a first clock signal to output a NAND gate output signal; and Multiple delay elements are connected in series and coupled to each other, wherein the first delay element in the series receives the output signal of the NAND gate and the last delay element in the series outputs the first clock signal.

13. The computing device according to claim 12, wherein, The frequency of the first clock signal is less than or equal to the operating speed.

14. The computing device according to claim 12, wherein, The clock generation circuit includes a delay line circuit, which includes one or more process-voltage-temperature related components.

15. The computing device according to claim 12, wherein, The delay element is a buffer.

16. The computing device of claim 12, wherein: The input buffer circuit is configured to receive input data based on a second clock signal and output the input data based on a first clock signal used to perform the multiplication-accumulation operation. as well as The output buffer circuit is configured to receive the output data obtained by the multiplication and accumulation operation based on the first clock signal and to output the output data based on the second clock signal, wherein the first clock signal and the second clock signal are asynchronous clock signals.

17. A method for in-memory computation, comprising: Track the process-voltage-temperature conditions in memory used to perform the computational macros for the multiply-accumulate operation; A first clock signal is generated, and the frequency of the first clock signal is adjusted based on the process-voltage-temperature conditions to match the operating speed of the multiplication-accumulation operation; as well as Input data is sent to the computation macro in the memory via an input buffer circuit, and output data from the computation macro in the memory is received from the memory based on the first clock signal via an output buffer circuit. Generating the first clock signal includes: The logic circuit performs a NAND operation based on the enable signal and the first clock signal to output a first gate output signal; and The first gate output signal is delayed by a delay line circuit to generate the first clock signal.

18. The method according to claim 17, wherein, The delay line circuit includes multiple buffers coupled in series with each other.

19. The method of claim 17, further comprising: The input data is received by the input buffer circuit based on a second clock signal from the input channel, wherein the first clock signal and the second clock signal are asynchronous clock signals.

20. The method of claim 19, further comprising: The output data received through the output buffer circuit is output to the output channel based on the second clock signal.

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