A method for removing a gate hard mask layer

Abstract

The removing method of the gate hard mask layer of the application, before removing the oxide hard mask layer of the gate, covers the oxide hard mask layer and the active region by forming an organic insulating layer with high filling capacity, adopts the etching back process to etch to the oxide hard mask layer being exposed, covers the photoresist layer on the oxide hard mask layer and the organic insulating layer, makes the photoresist layer and the organic insulating layer tend to be planarized, exposes the oxide hard mask layer by exposing and developing, then removes the oxide hard mask layer above the gate by the dry etching or wet etching process, and finally removes the photoresist layer and the organic insulating layer above the active region. The application makes the first gate not to produce the hole, eliminates the possibility of damaging the active region due to the different thickness of the organic insulating layer caused by the different pattern density on the substrate, and does not produce the hard mask residue in the process of etching the oxide hard mask layer, improves the reliability and yield of the device product.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and particularly to a method for removing a gate hard mask layer. BACKGROUND

[0002] In a semiconductor manufacturing process, according to the requirements of different device functions, there are high-density active regions and low-density active regions in the same device. In the region with low-density active regions, the spacing between adjacent gates is large, so that when the photoresist is filled in the process of gate hard mask etching, a load effect occurs.

[0003] In order to solve the load effect existing in the process of removing the gate hard mask, the current conventional method is to etch the photoresist directly. However, due to the load effect, the heights of the photoresist on the high-density active regions and the low-density active regions are inconsistent. After etching to expose the gate hard mask, the removal of the gate hard mask may damage the active regions. Another method is to first perform photoetching, exposure and development to remove the photoresist above the high-density active regions, and then perform etching on the remaining photoresist with high selectivity until the gate hard mask is exposed, and then remove the gate hard mask. However, in the region with high-density active regions, the spacing between adjacent gates is small, so that when the photoresist is filled in the process of gate hard mask etching, the photoresist is not uniformly filled and holes are generated. Due to the existence of holes in the high-density active regions, the active regions may be damaged or some hard mask residues may be generated in the process of hard mask etching, thereby reducing the yield of the manufactured devices.

[0004] Therefore, it is necessary to find a method for removing the gate hard mask layer while protecting the active regions from damage and without generating hard mask residues, thereby improving the yield of the manufactured devices. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for removing a gate hard mask layer, which solves the problems that the active regions are easily damaged and hard mask residues are generated in the prior art when removing the gate hard mask layer.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for removing a gate hard mask layer, which comprises the following steps:

[0007] A semiconductor substrate with a semiconductor substrate, a gate and an active region is provided, and a first hard mask layer and a second hard mask layer are formed on the gate from bottom to top, the gate includes a first gate and a second gate, wherein the first gate has a first spacing therebetween, the second gate has a second spacing therebetween, and the first spacing is smaller than the second spacing.

[0008] forming an organic insulating layer on the semiconductor substrate, the organic insulating layer being higher than the second hard mask layer and covering the active region, the first gate and the second gate;

[0009] removing part of the organic insulating layer to expose the second hard mask layer;

[0010] forming a photoresist layer on the remaining organic insulating layer, the photoresist layer covering the second hard mask layer and the organic insulating layer and forming a planarization surface;

[0011] removing the photoresist layer on the second hard mask layer to expose the top surface of the second hard mask layer;

[0012] using the photoresist layer as a mask, etching to remove the second hard mask layer to expose the first hard mask layer.

[0013] Optionally, after removing the second hard mask layer, the method further comprises the step of removing the photoresist layer and the organic insulating layer on the active region.

[0014] Optionally, the height of the second gate is equal to the height of the first gate, and the width of the first gate is smaller than the width of the second gate.

[0015] Optionally, the thickness of the organic insulating layer at the first interval is greater than the thickness of the organic insulating layer at the second interval.

[0016] Optionally, the first hard mask layer is a silicon nitride hard mask layer, and the second hard mask layer is an oxide hard mask layer.

[0017] Optionally, the process of forming the organic insulating layer adopts a spin coating process.

[0018] Optionally, the process of removing the organic insulating layer adopts an etching back process.

[0019] Optionally, after forming the photoresist layer, the method further comprises the steps of exposing and developing the photoresist layer.

[0020] Optionally, the process of removing the second hard mask layer adopts a dry etching process, a wet etching process or a chemical mechanical polishing process.

[0021] Optionally, the method for removing the gate hard mask layer is suitable for processes with a technical node of 40 nanometers or less.

[0022] As described above, the removing method of the gate hard mask layer of the present application, before removing the oxide hard mask layer on the top of the gate, a layer of organic insulating layer with high filling capacity is formed by adding a step of spin coating process to replace the photoresist layer in the prior art, covering the active area between the oxide hard mask layer on the gate and the gate, first etching to the oxide hard mask layer exposed by using the etch-back process, then covering the photoresist layer on the oxide hard mask layer and the organic insulating layer, so that the photoresist layer and the organic insulating layer on the substrate have the same height, then exposing the oxide hard mask layer by exposure and development, then removing the oxide hard mask layer on the gate by dry etching or wet etching process, and finally removing the photoresist layer and the organic insulating layer on the active area. The present application makes it impossible to produce holes in the first interval between the first gate, eliminates the possibility of damage to the active area caused by the different thicknesses of the organic insulating layer due to different pattern densities on the substrate, and does not produce hard mask residues during the etching of the oxide hard mask layer, thereby improving the reliability and yield of the device product. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The flowchart shows the removing method of the gate hard mask layer of the present application.

[0024] Figures 2 to 8 The structure diagram of each step of the removing method of the gate hard mask layer of the present application.

[0025] Element number explanation

[0026] 101 semiconductor substrate

[0027] 102 first gate

[0028] 103 second gate

[0029] 104 second hard mask layer

[0030] 1041 top surface of the second hard mask layer

[0031] 105 first hard mask layer

[0032] 106 trench structure

[0033] 107 organic insulating layer

[0034] 108 photoresist layer

[0035] D1 first interval

[0036] D2 second interval

[0037] S1-S6 steps DETAILED DESCRIPTION

[0038] Following, the present application is described in detail by specific embodiments. Other advantages and effects of the present application can be easily understood by those skilled in the art from the description. The present application can also be implemented or applied by other different specific embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0039] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other orientations of the device in use or operation in addition to the orientations depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0040] It should be understood that the use of "first", "second", etc. words to define parts is only for the convenience of distinguishing the above-mentioned parts, and the above-mentioned words have no special meaning unless otherwise stated, and therefore cannot be understood as a limitation on the scope of protection of the present application.

[0041] Please refer to Figures 1 to 8 . It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change, and the component layout pattern can also be more complex.

[0042] Referring to Figure 1 , a flowchart of a method for removing a gate hard mask layer is shown, as shown in Figure 1 , the method comprises the steps of:

[0043] S1: providing a semiconductor substrate with a semiconductor substrate 101, a gate and an active region, and a first hard mask layer 105 and a second hard mask layer 104 are formed on the gate from bottom to top, the gate includes a first gate 102 and a second gate 103, wherein the first gate 102 has a first spacing D1 between them, the second gate 103 has a second spacing D2 between them, and the first spacing D1 is less than the second spacing D2;

[0044] S2: forming an organic insulating layer 107 on the semiconductor substrate 101, the organic insulating layer 107 is higher than the second hard mask layer 104 and covers the active region, the first gate 102 and the second gate 103;

[0045] S3: removing part of the organic insulating layer 107 to expose the second hard mask layer 104;

[0046] S4: forming a photoresist layer 108 on the remaining organic insulating layer 107, the photoresist layer 108 covering the second hard mask layer 104 and the organic insulating layer 107 to form a planarization surface;

[0047] S5: removing the photoresist layer 108 above the second hard mask layer 104 to expose the top surface 1041 of the second hard mask layer 104;

[0048] S6: etching to remove the second hard mask layer 104 to expose the first hard mask layer 105 with the photoresist layer 108 as a mask.

[0049] The method for removing the gate hard mask layer will be further described below in combination with the accompanying drawings, and the specific process is as follows:

[0050] In step S1, referring to Figure 1 and Figure 2 , a semiconductor substrate 101, gates and active regions are provided, and the gates are formed with a first hard mask layer 105 and a second hard mask layer 104 stacked from bottom to top, the gates include first gates 102 and second gates 103, wherein the first gates 102 have a first interval D1, the second gates 103 have a second interval D2, and the first interval D1 is smaller than the second interval D2.

[0051] Specifically, as shown in Figure 2 , the first gates 102 and the second gates 103 are formed on the semiconductor substrate 101, wherein the first gates 102 have a first interval D1, the second gates 103 have a second interval D2, and the first interval D1 is smaller than the second interval D2, first side walls and second side walls are sequentially arranged on the left and right sides of the first gates 102 and the second gates 103, and the first hard mask layer 105 and the second hard mask layer 104 are formed on the first gates 102 and the second gates 103 and stacked from bottom to top.

[0052] Optionally, in the embodiment of the present application, the semiconductor substrate 101 is a single crystal silicon substrate. A trench structure 106 is formed in the semiconductor substrate 102, which separates the semiconductor substrate 101 into a first gate 102 part and a second gate 103 part. Active regions are also formed between the gates, which are respectively located in the first interval D1 and the second interval D2. For simplicity, the active regions are omitted in the figure.

[0053] Optionally, the height of the second gate 103 is equal to the height of the first gate 102, and the width of the first gate 102 is less than the width of the second gate 103.

[0054] Optionally, in the embodiment, the first hard mask layer 105 is a silicon nitride hard mask layer, and the second hard mask layer 104 is an oxide hard mask layer and is located on the first hard mask layer 105. The first hard mask layer 105 and the second hard mask layer 104 are preferably grown by a CVD, PECVD, LPCVD, or ALD process to have a high step coverage.

[0055] Optionally, the preparation process of the semiconductor substrate 101 and the gate structure in the step is known to those skilled in the art, and will not be described in detail herein. In addition, the application point of the present application is the removal method of the subsequent oxide hard mask layer, and therefore, the semiconductor substrate obtained by any prior art in the step is within the protection scope of the present application.

[0056] In step S2, referring to Figure 1 and Figure 3 , an organic insulating layer 107 is formed on the semiconductor substrate 101, the organic insulating layer 107 is higher than the second hard mask layer 104 and covers the active region, the first gate 102, and the second gate 103.

[0057] Optionally, the process of forming the organic insulating layer 107 adopts a spin coating process.

[0058] Specifically, the organic insulating layer 107 adopts an SOC spin coating process, the SOC spin coating process has a good hole filling capacity, and the organic insulating layer 107 also has a strong filling capacity, so that no small holes appear between the first gates 102, and the organic insulating layer 107 can be removed more conveniently in the subsequent process.

[0059] Optionally, in the embodiment of the present application, as shown in Figure 3 , the organic insulating layer 107 is higher than the second hard mask layer 104, and in order to better protect the active region between the gates from being damaged in the subsequent oxide hard mask layer removal process, the organic insulating layer 107 also fills above the active region between the gates. When the filling amount of the organic insulating layer 107 is the same, due to the load effect caused by the large second spacing D2 between the second gates 103, the thickness of the organic insulating layer 107 on the region of the second gate 103 is less than the thickness of the organic insulating layer 107 on the region of the first gate 102.

[0060] In step S3, referring to Figure 1 and Figure 4, part of the organic insulating layer 107 is removed to expose the top surface 1041 of the second hard mask layer 104.

[0061] Optionally, part of the organic insulating layer 107 is removed by an etch-back process, and the etch-back process is terminated at the top surface 1041 of the second hard mask layer 104 above the first gate 102 and the second gate 103, so as to expose the second hard mask layer 104.

[0062] Specifically, as shown in Figure 4 , in the embodiment of the present application, the etch-back process is non-selective and etches the organic insulating layer 107 at the same speed. Due to the existence of the load effect, the height of the organic insulating layer 107 in the region of the second gate 103 is still lower than the height of the organic insulating layer 107 in the region of the first gate 102 after the step of etch-back process is completed.

[0063] In step S4, referring to Figure 1 and Figure 5 , a photoresist layer 108 is formed above the remaining organic insulating layer 107, and the photoresist layer 108 covers the second hard mask layer 104 and the organic insulating layer 107 to form a planar surface.

[0064] Optionally, a photoresist layer 108 is formed above the remaining organic insulating layer 107 and the second hard mask layer 104, and the photoresist layer 108 covers the second hard mask layer 104 and the organic insulating layer 107, so that the influence of the load effect can be weakened. Therefore, after the photoresist layer 108 is formed, the photoresist layer 108 and the organic insulating layer 107 on the first gate 102 region and the second gate 103 region will tend to be planarized.

[0065] Specifically, after the photoresist layer 108 is formed above the second hard mask layer 104 and the organic insulating layer 107, a planarization process can be performed on the photoresist layer to obtain a planar surface.

[0066] In step S5, referring to Figure 1 and Figure 6 , the photoresist layer 108 above the second hard mask layer 104 is removed to expose the top surface 1041 of the second hard mask layer 104.

[0067] Specifically, the photoresist layer 108 can be exposed and developed to expose the top surface 1041 of the second hard mask layer 104.

[0068] In step S6, referring to Figure 1 and Figure 7 , the second hard mask layer 104 is etched and removed to expose the first hard mask layer 105 with the photoresist layer 108 as a mask.

[0069] Specifically, as shown in Figure 7 the second hard mask layer 104 above the first gate 102 and the second gate 103 is etched to expose the first hard mask layer 105.

[0070] Optionally, as shown in Figure 8 after the second hard mask layer 104 is removed, the remaining photoresist layer 108 and the organic insulating layer 107 on the active region are also removed.

[0071] Specifically, after the first hard mask layer 105 is exposed, a process of removing the photoresist layer 108 and the organic insulating layer 107 is needed, and the remaining photoresist layer 108 is removed by ashing or peeling, and the remaining organic insulating layer 107 is removed by etching back.

[0072] The method for removing the gate hard mask layer in the semiconductor process is suitable for processes with a technical node of less than 40 nanometers.

[0073] In summary, before the oxide hard mask layer on the top of the gate is removed, an organic insulating layer with high filling capacity is formed by adding a spin coating process to replace the photoresist layer in the prior art, so as to cover the active region between the oxide hard mask layer on the gate and the gate. The oxide hard mask layer is exposed by etching back, and then a photoresist layer is formed on the oxide hard mask layer and the organic insulating layer, so that the photoresist layer and the organic insulating layer on the substrate are planarized. Then, the oxide hard mask layer is exposed by exposure and development, and then removed by dry etching or wet etching. Finally, the photoresist layer and the organic insulating layer on the active region are removed. The first spacing between the first gate will not produce a small hole, which eliminates the possibility of damage to the active region caused by different thicknesses of the organic insulating layer due to different pattern densities on the substrate, and no hard mask residue is generated during the etching of the oxide hard mask layer, which improves the reliability and yield of the device product. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0074] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for removing a gate hard mask layer, characterized in that, The removing method comprises the following steps: providing a semiconductor substrate with a semiconductor substrate, a gate and an active region, and a first hard mask layer and a second hard mask layer are formed on the gate from bottom to top, and the gate comprises a first gate and a second gate, wherein the first gate has a first interval, the second gate has a second interval, and the first interval is smaller than the second interval; forming an organic insulating layer on the semiconductor substrate, the organic insulating layer is higher than the second hard mask layer and covers the active region, the first gate and the second gate; part of the organic insulating layer is removed to expose the second hard mask layer; a photoresist layer is formed above the remaining organic insulating layer, the photoresist layer covers the second hard mask layer and the organic insulating layer to form a planarization surface; the photoresist layer above the second hard mask layer is removed to expose the top surface of the second hard mask layer; the second hard mask layer is etched to expose the first hard mask layer with the photoresist layer as a mask; the photoresist layer and the organic insulating layer on the active region are removed.

2. The removal method of claim 1, wherein: The height of the second gate is equal to the height of the first gate, and the width of the first gate is smaller than the width of the second gate.

3. The removal method of claim 1, wherein: The thickness of the organic insulating layer at the first interval is greater than the thickness of the organic insulating layer at the second interval.

4. The removal method of claim 1, wherein: The first hard mask layer is a silicon nitride hard mask layer, and the second hard mask layer is an oxide hard mask layer.

5. The removal method of claim 1, wherein: The process of forming the organic insulating layer adopts a spin coating process.

6. The removal method of claim 1, wherein: The process of removing the organic insulating layer adopts an etching back process.

7. The removal method of claim 1, wherein: After forming the photoresist layer, the steps of exposing and developing the photoresist layer are further included.

8. The removal method of claim 1, wherein: The process of removing the second hard mask layer adopts a dry etching process, a wet etching process or a chemical mechanical polishing process.

9. The method of removing a gate hard mask layer according to any one of claims 1 to 8, wherein: It is suitable for processes with a technical node below 40 nanometers.

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