Shielded gate field effect transistor and method of making the same

Abstract

The application provides a shield gate field effect transistor and a preparation method thereof. In the preparation method, the convex part of the shield electrode is oxidized to form a first isolation layer, and an insulating material with fluidity under a predetermined condition is used to fill the gap between the first isolation layer and a second dielectric layer. The method can not only fill the voids with sharp corners in the gap, prevent the formation of an included angle structure at the bottom of the gate electrode, but also compensate for the thickness of the isolation layer, improve the isolation effect between the gate electrode and the shield electrode, and further reduce the leakage current of the device and improve the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a shielded gate field-effect transistor and its fabrication method. Background Technology

[0002] Shielded Gate Trench (SGT) transistors are more advantageous for flexible applications in semiconductor integrated circuits due to their low gate-drain capacitance Cgd, very low on-resistance, and high voltage withstand capability.

[0003] Specifically, in a shielded gate field-effect transistor (SFET), by placing a shielding electrode below the gate electrode, the gate-drain capacitance can be significantly reduced. Furthermore, the drift region of the shielded gate SFET also has a high impurity carrier concentration, which provides additional benefits to the device's breakdown voltage and correspondingly reduces the on-resistance. An isolation layer (IPO) is typically placed between the shielding electrode and the gate electrode to achieve mutual isolation between them.

[0004] In one existing preparation method, for example, reference Figure 1 As shown, the protruding top of the shielding electrode 30 can be directly oxidized to form the isolation layer 40. While this method effectively simplifies the process, the bottom of the oxidized isolation layer 40 is prone to insufficient oxidation, resulting in an insufficient oxide thickness. This leads to sharp corners pointing towards the shielding electrode 30 in the gap between the isolation layer 40 and the trench sidewall (e.g.,...). Figure 1 (As shown in the dashed box in the image). Therefore, when forming the gate electrode 50, please refer to... Figure 2 As shown, the portion of the gate electrode 50 that fills the sharp corner points to the shield electrode 30, and the thickness of the isolation layer 40 between the gate electrode 50 and the shield electrode 30 is small, which increases the reverse gate-source leakage current (IGSSR) of the device and affects the negative high-temperature gate bias (HTGB) of the device, resulting in device reliability issues. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a shielded gate field-effect transistor, so as to reduce the reverse gate-source leakage current of the fabricated device and improve the reliability of the device.

[0006] To address the aforementioned technical problems, the present invention provides a method for fabricating a shielded gate field-effect transistor, comprising: providing a substrate in which a trench is formed, and forming a first dielectric layer on the bottom and sidewalls of the trench; forming a shielding electrode on the first dielectric layer, such that the shielding electrode is lower than the top of the trench; etching the first dielectric layer to remove a portion of the first dielectric layer above the shielding electrode, and making the top of the shielding electrode protrude beyond the top of the etched first dielectric layer; performing an oxidation process to form a second dielectric layer on the sidewalls of the trench above the first dielectric layer, and oxidizing the protrusion of the shielding electrode to form a first isolation layer, wherein a gap exists between the first isolation layer and the second dielectric layer; forming a second isolation layer, wherein the material of the second isolation layer has fluidity under predetermined conditions to at least fill the bottom of the gap; and forming a gate electrode within the trench, the gate electrode being located on the first isolation layer and the second isolation layer.

[0007] Optionally, oxidizing the protrusion of the shielding electrode to form a first isolation layer includes oxidizing the top surface and sidewall of the protrusion of the shielding electrode, wherein the oxidation thickness at the bottom position of the sidewall of the protrusion is less than the oxidation thickness at the top position of the sidewall of the protrusion.

[0008] Optionally, the top of the liquid insulating material filling the gap is not higher than the top of the first insulating layer.

[0009] Optionally, the method for forming the second insulating layer includes: spin-coating a liquid insulating material to at least fill the bottom of the gap, and curing the liquid insulating material to form the second insulating layer.

[0010] Optionally, the liquid insulating material includes a siloxane. The method for curing the liquid insulating material may include annealing under an inert gas atmosphere at a temperature of 400°C-500°C. Furthermore, the method for curing the liquid insulating material may also include annealing under a nitrogen or argon atmosphere.

[0011] The present invention also provides a shielded gate field-effect transistor, comprising: a substrate in which a trench is formed; a first dielectric layer formed at the bottom and sidewalls of the trench; a shielding electrode formed on the first dielectric layer, wherein the top of the shielding electrode protrudes from the first dielectric layer; a second dielectric layer formed on the sidewalls of the trench above the first dielectric layer; a first isolation layer formed on the top surface and sidewalls of the protrusion of the shielding electrode; a second isolation layer filling the gap between the first isolation layer and the second dielectric layer; and a gate electrode filling the trench and located on the first isolation layer and the second isolation layer.

[0012] Optionally, the top surface of the second isolation layer filling the gap is not higher than the top surface of the first isolation layer, and the top surface of the second isolation layer in the gap is a concave arc-shaped surface, and the bottom surface of the gate electrode located at the gap position is correspondingly an arc-shaped bottom surface.

[0013] Optionally, a sharp corner region pointing towards the shielding electrode may be formed at the corner where the first isolation layer and the first dielectric layer are connected, and the second isolation layer fills the sharp corner region.

[0014] In the fabrication method of the shielded gate field-effect transistor provided by this invention, after oxidizing the protrusion of the shielding electrode to form a first isolation layer, a fluid insulating material under predetermined conditions is used to fill the gap between the first isolation layer and the second dielectric layer. This fluid insulating material can effectively fill the bottom of the gap, correspondingly filling the gap bottom in a sharp-angled shape pointing towards the shielding electrode. This not only avoids the formation of a sharp-angle structure at the bottom of the gate electrode but also compensates for the thickness of the isolation layer, improving the isolation effect between the gate electrode and the shielding electrode, reducing the reverse gate-source leakage current (IGSSR) of the device, optimizing the negative high-temperature gate bias (HTGB) of the device, and improving the reliability of the device. Attached Figure Description

[0015] Figures 1-2 This is a schematic diagram of the structure of a shielded gate field-effect transistor during its fabrication process.

[0016] Figure 3 This is a schematic flowchart of a method for fabricating a shielded gate field-effect transistor according to an embodiment of the present invention.

[0017] Figures 4-8 This is a schematic diagram of the shielded gate field-effect transistor in one embodiment of the present invention during its fabrication process.

[0018] The accompanying figure is labeled as follows:

[0019] 30 - Shielding electrode;

[0020] 40 - Isolation layer;

[0021] 50 - Gate electrode;

[0022] 100-substrate;

[0023] 100a - Groove;

[0024] 210 - First dielectric layer;

[0025] 220 - Second dielectric layer;

[0026] 300-Shielded electrode;

[0027] 410 - First isolation layer;

[0028] 420 - Second isolation layer;

[0029] 500 - Gate electrode. Detailed Implementation

[0030] The core idea of ​​this invention is to provide a method for fabricating a shielded gate field-effect transistor. This method can effectively compensate for the sharp-cornered gaps on the side caused by the limitation of the oxidation process of the isolation layer, thereby avoiding the formation of a sharp-cornered part pointing to the shielding electrode at the bottom of the gate electrode. This is beneficial to improve the leakage current phenomenon of the device and improve the reliability of the device.

[0031] For details, please refer to [link / reference]. Figure 3 As shown, the fabrication method of the shielded gate field-effect transistor includes the following steps.

[0032] Step S100: A substrate is provided in which trenches are formed, and a first dielectric layer is formed on the bottom and sidewalls of the trenches.

[0033] Step S200: Form a shielding electrode on the first dielectric layer and make the shielding electrode lower than the top of the trench.

[0034] Step S300: Etch the first dielectric layer to remove the portion of the first dielectric layer above the shielding electrode, and make the top of the shielding electrode protrude from the top of the etched first dielectric layer.

[0035] Step S400: Perform an oxidation process to form a second dielectric layer on the sidewall of the trench above the first dielectric layer, and oxidize the protruding portion of the shielding electrode to form a first isolation layer, with a gap between the first isolation layer and the trench sidewall.

[0036] Step S500: A second isolation layer is formed, wherein the material of the second isolation layer has fluidity under predetermined conditions to at least fill the bottom of the gap.

[0037] Step S600: A gate electrode is formed in the trench, the gate electrode being located on the first isolation layer and the second isolation layer.

[0038] The following combination Figures 4-8 The shielded gate field-effect transistor and its formation method proposed in this invention will be further described in detail with specific embodiments. Figures 4-8This is a schematic diagram of the structure of a shielded gate field-effect transistor in the fabrication process of an embodiment of the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that relative terms such as "above," "below," "top," "bottom," and "over" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described, for example, as being "above" another element would now be below that element.

[0039] In step S100, please refer to the following for details. Figure 4 As shown, a substrate 100 is provided, in which trenches 100a are formed, and a first dielectric layer 210 is formed on the bottom and sidewalls of the trenches 100a.

[0040] Specifically, the method for forming the trench 100a includes, for example, forming a patterned mask layer on the top surface of the substrate 100; and then etching the substrate 100 using the patterned mask layer as a mask to form the trench 100a.

[0041] For details, please refer to the following: Figure 4 As shown, after forming trench 100a, a first dielectric layer 210 can be formed using an oxidation process or a deposition process. The first dielectric layer 210 covers the sidewalls and bottom wall of the trench 100a, and in this step, the first dielectric layer 210 covers the entire inner surface of the trench 100a. The material of the first dielectric layer 210 includes, for example, silicon oxide (SiO2). It should be noted that the thickness of the first dielectric layer 210 can be adjusted according to the voltage withstand requirements of the formed shielded gate field-effect transistor. For example, when the formed shielded gate field-effect transistor is a low-voltage transistor (voltage withstand range, for example, less than 60V), the thickness of the first dielectric layer 210 in the direction perpendicular to the trench sidewall can be less than 2000 angstroms; more specifically, the thickness of the first dielectric layer 210 is, for example, between 800 angstroms and 1500 angstroms.

[0042] In step S200, please refer to the following for details. Figure 4 As shown, a shielding electrode 300 is formed on the first dielectric layer 210, and the shielding electrode 300 is lower than the top of the trench.

[0043] Specifically, after filling the trench 100a with the electrode material of the shielding electrode, a back-etching process can be used to etch the electrode material in the trench to reduce the height of the electrode and form the shielding electrode 300. The material of the shielding electrode 300 includes, for example, polysilicon.

[0044] In step S300, please refer to the following for details. Figure 5 As shown, the first dielectric layer 210 is etched to remove the portion of the first dielectric layer 210 that is above the shielding electrode 300, and to make the top of the shielding electrode 300 protrude from the top of the etched first dielectric layer.

[0045] Specifically, the first dielectric layer 210 can be etched using either a dry etching process or a wet etching process. After removing the portion of the first dielectric layer 210 above the shielding electrode 300, the sidewalls of the upper part of the trench are exposed. In subsequent processes, a second dielectric layer (i.e., the gate dielectric layer) will be formed on the exposed trench sidewalls. To ensure that the first dielectric layer 210 above the shielding electrode can be sufficiently removed, it is typically over-etched so that the top of the etched first dielectric layer 210 is lower than the top of the shielding electrode 300, thus causing the top of the shielding electrode 300 to protrude.

[0046] In this embodiment, after etching the first dielectric layer 210 and before forming the second dielectric layer, the method further includes: oxidizing the exposed sidewalls of the trench 110a to form a sacrificial oxide layer, and then removing the sacrificial oxide layer to repair the etching damage to the trench sidewalls.

[0047] In step S400, please refer to the following for details. Figure 6 As shown, an oxidation process is performed to form a second dielectric layer 220 (i.e., a gate dielectric layer) on the sidewall of the trench 110a above the first dielectric layer 210, and the protrusion of the shielding electrode 300 is oxidized to form a first isolation layer 410, with a gap between the first isolation layer 410 and the trench sidewall.

[0048] In this embodiment, the second dielectric layer 220 and the first insulating layer 410 can be formed simultaneously in the same oxidation process. During the oxidation of the protrusion of the shielding electrode 300, the process includes oxidizing the top surface and sidewalls of the protrusion. The corner where the protrusion of the shielding electrode 300 meets the first dielectric layer 210 is prone to insufficient oxidation, resulting in a thin oxide layer. This causes the oxide thickness at the bottom of the sidewall to be less than the oxide thickness at the top, creating a recessed space towards the shielding electrode 300 in the gap between the first insulating layer 410 and the second dielectric layer 220. For example, in this embodiment, a sharp-angled gap (e.g., a gap pointing towards the shielding electrode 300) is created in the gap between the first insulating layer 410 and the second dielectric layer 220. Figure 6 The sharp-angled area shown in the dashed box is also located at the corner where the first dielectric layer 210 and the first isolation layer 410 are connected.

[0049] In step S500, please refer to the following for details. Figure 7 As shown, a second isolation layer 420 is formed, the material of the second isolation layer 420 having fluidity under predetermined conditions to at least fill the bottom of the gap.

[0050] As described above, a sharp-angled region pointing towards the shielding electrode 300 is formed in the gap between the first isolation layer 410 and the second dielectric layer 220. This sharp-angled region is located at the bottom of the gap. Therefore, the fluid second isolation layer 420 can at least fill the bottom of the gap in its flowing state, correspondingly filling the sharp-angled region. In this way, on the one hand, it can avoid the subsequent gate electrode from filling the sharp-angled region and forming a sharp-angled structure; on the other hand, the filled second isolation layer 420 can also compensate for the thickness of the separator in the sharp-angled region, improving the isolation effect between the gate electrode and the shielding electrode 300.

[0051] In this embodiment, the liquid insulating material filling the gap is not higher than the top of the gap (i.e., not higher than the top of the first insulating layer 410), as long as it is ensured that the liquid insulating material can fill the sharp-cornered gap at the bottom. In addition, since the filling height of the liquid insulating material in the gap is not higher than the top of the gap, the top surface of the second insulating layer 420 formed after the insulating material cures is a concave arc-shaped surface within the gap.

[0052] In a specific example, the method for preparing the second isolation layer 420 includes: spin-coating a liquid insulating material to at least fill the bottom of the gap, and curing the liquid insulating material to form the second isolation layer 420.

[0053] In alternative solutions, the liquid insulating material used includes, for example, siloxane (R...n Si(OH) 4-n Siloxane-based liquid coatings can effectively fill narrow gaps, exhibiting strong filling capacity. During curing, a dehydration reaction occurs, producing a thin film primarily composed of silicon oxide, achieving good electrical isolation. Specifically, a spin-coating process is preferred to apply a siloxane-containing liquid insulating material. This liquid insulating material should at least fill the sharp corner areas at the bottom of the gap. The coating thickness of the siloxane-containing liquid insulating material can be selected according to actual needs, for example, within the range of 200 angstroms to 6000 angstroms. Afterwards, an annealing and curing process is performed, for example, at 400°C-500°C in an inert gas atmosphere, to allow the siloxane to undergo a dehydration reaction to form a solid oxide film (i.e., the second insulating layer 420). The inert gas used includes, for example, nitrogen or argon.

[0054] In step S600, please refer to the following for details. Figure 8 As shown, a gate electrode 500 is formed within the trench 100a, and the gate electrode 500 is located on the first isolation layer 410 and the second isolation layer 420. The gate electrode 500 and the shielding electrode 300 can be formed using the same material, for example, both the gate electrode 500 and the shielding electrode 300 may be made of polycrystalline silicon.

[0055] As described above, the compensation of the second isolation layer 420 ensures that the formed gate electrode 500 does not have a sharp corner structure pointing towards the shielding electrode 300, and facilitates increasing the thickness of the isolation layer at the sharp corners of the gate electrode 500 and the shielding electrode 300. In this embodiment, since the top surface of the second isolation layer 420 within the gap is an arc-shaped surface, the bottom surface of the gate electrode 500 at the gap position is correspondingly made to have an arc-shaped surface.

[0056] Furthermore, after forming the gate electrode 500, the process may further include forming source regions in the substrates on both sides of the trench 100a. Specifically, the source regions may be formed using an ion implantation process.

[0057] Based on the preparation method described above, the following is combined with... Figure 8 The structure of the fabricated shielded gate field-effect transistor is described. For example... Figure 8 As shown, the shielded gate field-effect transistor fabricated includes: a trench formed in a substrate 100; a shielding electrode 300 formed in the lower portion of the trench; a gate electrode 500 formed in the upper portion of the trench; and a first isolation layer 410 and a second isolation layer 420 located between the shielding electrode 300 and the gate electrode 500.

[0058] Furthermore, a first dielectric layer 210 is formed on the bottom and sidewalls of the trench, specifically covering the inner surface of the lower portion of the trench. Additionally, a second dielectric layer 220 (i.e., a gate dielectric layer) is formed on the sidewalls of the upper portion of the trench, the second dielectric layer 220 being located above and connected to the first dielectric layer 210.

[0059] Furthermore, the shielding electrode 300 is formed on the first dielectric layer 210, and the top of the shielding electrode 300 protrudes from the first dielectric layer 210.

[0060] Continue to refer to Figure 8 As shown, a first insulating layer 410 is formed on the top surface and sidewall of the protrusion of the shielding electrode 300. Specifically, the thickness of the first insulating layer 410 at the bottom of the sidewall of the protrusion is less than the thickness of the first insulating layer 410 at the top of the sidewall of the protrusion, thus defining a sharp-angled region at the bottom of the sidewall of the protrusion. That is, the thickness of the first insulating layer 410 at the corner where it connects to the first dielectric layer 210 is smaller, thus forming a sharp-angled region pointing towards the shielding electrode 300 at the corner where the first insulating layer 410 and the first dielectric layer 210 connect.

[0061] Furthermore, the second isolation layer 420 fills the gap between the first isolation layer 410 and the second dielectric layer 220. Specifically, the second isolation layer 420 at least fills the bottom of the gap, thereby filling the sharp corner region located at the bottom of the protruding sidewall, thus forming a sharp corner structure pointing towards the shielding electrode 300. By filling this sharp corner region, not only is it possible to prevent the gate electrode 500 from filling this sharp corner region, so that the gate electrode 500 does not have a sharp corner structure pointing towards the shielding electrode 300, thus improving the leakage current phenomenon of the device; but it can also compensate for the isolation thickness at the bottom of the protruding sidewall, improving the isolation effect between the gate electrode 500 and the shielding electrode 300.

[0062] In this embodiment, the top surface of the second isolation layer 420 filled in the gap is not higher than the top surface of the first isolation layer 410, and the second isolation layer 420 is formed by using a liquid insulating material in a flowing state, so that the top surface of the prepared second isolation layer 420 in the gap can be a concave arc-shaped surface, and the bottom surface of the adjustment gate electrode 500 located in the gap is an arc-shaped bottom surface.

[0063] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0064] It should also be understood that, unless otherwise specified or indicated, the terms "first," "second," "third," etc., used in the specification are merely for distinguishing individual components, elements, steps, etc., and are not for indicating logical or sequential relationships between them. Furthermore, it should be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include a plural basis unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense.

Claims

1. A method for fabricating a shielded gate field-effect transistor, characterized in that, include: A substrate is provided in which trenches are formed, and a first dielectric layer is formed on the bottom and sidewalls of the trenches; A shielding electrode is formed on the first dielectric layer and the shielding electrode is lower than the top of the trench. The material of the shielding electrode includes polycrystalline silicon. The first dielectric layer is etched to remove the portion of the first dielectric layer that is above the shielding electrode, and to make the top of the shielding electrode protrude from the top of the etched first dielectric layer; The sidewalls of the trench above the first dielectric layer and the protrusions of the shielding electrode are oxidized to form a sacrificial oxide layer, and then the sacrificial oxide layer is removed. An oxidation process is performed to form a second dielectric layer on the sidewall of the trench above the first dielectric layer, and the protrusion of the shielding electrode is oxidized to form a first isolation layer, with a gap between the first isolation layer and the second dielectric layer; A second isolation layer is formed, the material of the second isolation layer having fluidity under predetermined conditions to at least fill the bottom of the gap, the second isolation layer exposing the second medium layer covering the sidewall of the trench above the first medium layer; as well as, A gate electrode is formed within the trench, the gate electrode being located on the first isolation layer and the second isolation layer, and the second dielectric layer covering the sidewall of the trench above the first dielectric layer is located between the sidewall of the gate electrode and the substrate.

2. The method for fabricating a shielded gate field-effect transistor as described in claim 1, characterized in that, The top surface of the second isolation layer filling the gap is not higher than the top surface of the first isolation layer.

3. The method for fabricating a shielded gate field-effect transistor as described in claim 2, characterized in that, The top surface of the second isolation layer within the gap is a concave arc-shaped surface, and the bottom surface of the gate electrode located at the gap position is correspondingly an arc-shaped bottom surface.

4. The method for fabricating a shielded gate field-effect transistor as described in claim 1, characterized in that, The method for forming the second insulating layer includes: spin-coating a liquid insulating material to at least fill the bottom of the gap, and curing the liquid insulating material to form the second insulating layer.

5. The method for fabricating a shielded gate field-effect transistor as described in claim 4, characterized in that, The liquid insulating material includes siloxane.

6. The method for fabricating a shielded gate field-effect transistor as described in claim 5, characterized in that, The method for curing the liquid insulating material includes annealing and curing under an inert gas atmosphere at a temperature of 400°C to 500°C.

7. The method for fabricating a shielded gate field-effect transistor as described in claim 5, characterized in that, The method for curing the liquid insulating material includes annealing and curing in a nitrogen or argon atmosphere.

8. A shielded gate field-effect transistor, characterized in that, include: A substrate in which trenches are formed; A first dielectric layer is formed at the bottom and sidewalls of the trench; A shielding electrode is formed on the first dielectric layer, and the top of the shielding electrode protrudes from the first dielectric layer. The material of the shielding electrode includes polycrystalline silicon. A second dielectric layer is formed on the sidewall of the trench above the first dielectric layer; A first isolation layer is formed on the top surface and sidewall of the protrusion of the shielding electrode. The trench is located on the sidewall above the first dielectric layer and the protrusion of the shielding electrode is oxidized before the second dielectric layer and the first isolation layer are formed, and the sacrificial oxide layer formed by oxidation is removed. The first isolation layer and the second dielectric layer are formed in the same oxidation process. A second isolation layer fills the gap between the first isolation layer and the second dielectric layer, and the second isolation layer exposes the second dielectric layer covering the sidewall of the trench above the first dielectric layer; A gate electrode is filled in the trench and located on the first isolation layer and the second isolation layer. The second dielectric layer, which covers the sidewall of the trench above the first dielectric layer, is located between the sidewall of the gate electrode and the substrate.

9. The shielded gate field-effect transistor as described in claim 8, characterized in that, The top surface of the second isolation layer filling the gap is not higher than the top surface of the first isolation layer, and the top surface of the second isolation layer in the gap is a concave arc-shaped surface, and the bottom surface of the gate electrode located in the gap is correspondingly an arc-shaped bottom surface.

10. The shielded gate field-effect transistor as described in claim 8, characterized in that, A sharp corner region pointing towards the shielding electrode is formed at the corner where the first isolation layer and the first dielectric layer are connected, and the second isolation layer fills the sharp corner region.

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