Semiconductor Components and Their Fabrication Methods

Abstract

This invention discloses a semiconductor device and its fabrication method. The method for fabricating the semiconductor device involves first forming a gate dielectric layer on a substrate, then forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer wall next to the gate structure, and simultaneously forming a vent between the gate dielectric layer and the spacer wall, and then forming a source / drain region on both sides of the spacer wall.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a pore between a gate dielectric layer and a spacer wall. Background Technology

[0002] In the current semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as the standard gate fill material. However, as the size of MOS transistors continues to shrink, traditional polysilicon gates suffer from problems such as reduced device performance due to the boron penetration effect and the unavoidable depletion effect. This leads to an increase in the equivalent gate dielectric layer thickness, a decrease in gate capacitance, and consequently, a decline in device drive capability. Therefore, the semiconductor industry is exploring new gate fill materials, such as work function metals, to replace traditional polysilicon gates as control electrodes to match high-k gate dielectric layers.

[0003] However, in the current fabrication process of metal gate transistors, the gate structure and the doped regions on both sides, such as the lightly doped drain or source / drain regions, are often too close, causing problems such as gate-induced drain-leakage (GIDL), which in turn affects device performance. Therefore, how to improve the current fabrication process to solve the above problems is an important issue. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a gate dielectric layer is formed on a substrate, then a gate material layer is formed on the gate dielectric layer, the gate material layer and the gate dielectric layer are patterned to form a gate structure, a portion of the gate dielectric layer is removed, a spacer is formed next to the gate structure, and a vent is simultaneously formed between the gate dielectric layer and the spacer, and then a source / drain region is formed on both sides of the spacer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a gate structure disposed on a substrate, wherein the gate structure includes a gate dielectric layer disposed on the substrate and a gate material layer disposed on the gate dielectric layer. Furthermore, the semiconductor device further includes a spacer wall disposed beside the gate structure and a vent disposed between the gate dielectric layer and the spacer wall. Attached Figure Description

[0006] Figures 1 to 5 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: Fin-like structure

[0010] 16: Gate dielectric layer

[0011] 18: Gate material layer

[0012] 20: Gate structure

[0013] 22: Etching process

[0014] 24: Spacer wall

[0015] 26: Source / Drain Region

[0016] 28: Stomata

[0017] 30: Stomata

[0018] 32: Contact hole etching stop layer

[0019] 34: Interlayer dielectric layer

[0020] 36: High dielectric constant dielectric layer

[0021] 38: Work function metal layer

[0022] 40: Low-resistivity metal layer

[0023] 42: Metal gate

[0024] 44: Hard Mask

[0025] 46: Contact plug Detailed Implementation

[0026] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is first provided, on which a transistor region, such as a PMOS transistor region or an NMOS transistor region, can be defined. The substrate 12 has at least one fin structure 14 and an insulating layer (not shown), wherein the bottom of the fin structure 14 is covered by the insulating layer, such as silicon oxide, to form a shallow trench isolation. It should be noted that although this embodiment uses the fabrication of a non-planar field-effect transistor, such as a fin structure field-effect transistor, as an example, it is not limited thereto. The present invention can also be applied to general planar field-effect transistors, and this embodiment is also within the scope of the present invention.

[0027] According to one embodiment of the present invention, the fin structure 14 is preferably fabricated using sidewall image transfer (SIT) technology. The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0028] In addition, the formation of the fin structure 14 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure. Alternatively, the fin structure may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure. These embodiments of forming fin structures are all within the scope of this invention.

[0029] Next, at least one gate structure 20 or a dummy gate can be formed on the substrate 12. In this embodiment, the gate structure 20 can be fabricated in a manner that meets the requirements of the fabrication process, such as a gate-first fabrication process, a high-k-first fabrication process for the gate-last fabrication process, or a high-k-last fabrication process for the gate-last fabrication process. Taking the high dielectric constant dielectric layer fabrication process of this embodiment as an example, a gate dielectric layer 16 or dielectric layer, a gate electrode layer or gate material layer 18 made of polysilicon and a selective hard mask can be formed sequentially on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etching or successive etching step, part of the gate material layer 18 and part of the gate dielectric layer 16 are removed. Then the patterned photoresist is stripped to form a gate structure 20 composed of the patterned gate dielectric layer 16 and the patterned gate material layer 18 on the substrate 12.

[0030] like Figure 2As shown, an etching process 22 is then performed to remove a portion of the gate dielectric layer 16 without forming any patterned mask. In this embodiment, the formulation of the etching process 22 may include, for example, but not limited to, diluted hydrofluoric acid (dHF), wherein the concentration of the diluted hydrofluoric acid is preferably between 10:1 and 100:1, and the etching process is preferably performed for between 1 minute and 10 minutes. More specifically, if the concentration of the diluted hydrofluoric acid is controlled at 10:1, the etching process time is preferably controlled at about 1 minute, and if the concentration of the diluted hydrofluoric acid is preferably between 100:1, the etching process time is preferably controlled at about 10 minutes. According to a preferred embodiment of the present invention, using the above etching formulation, the present invention can remove only a portion of the gate dielectric layer 16 without removing any gate material layer 18 made of polysilicon, so that the two ends of the gate dielectric layer 16, which were originally aligned with both sides of the gate material layer 18, are slightly reduced inward, and ultimately the overall width of the gate dielectric layer 16 is slightly smaller than the overall width of the gate material layer 18.

[0031] like Figure 3 As shown, at least one spacer 24 is then formed on the sidewall of the gate structure 20. A source / drain region 26 and / or an epitaxial layer (not shown) are formed in the substrate 12 on both sides of the spacer 24, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region 26 and / or the epitaxial layer. It is worth noting that, at the same time as the spacer 24 is formed in this stage, a vent 28 is preferably formed between the originally recessed gate dielectric layer 18 and the spacer. The vent further includes a vent 28 disposed on one side of the gate structure 20, for example, the left side, between the gate dielectric layer 18 and the spacer 24, and another vent 30 disposed on the other side of the gate structure 20, for example, the right side, between the gate dielectric layer 18 and the spacer 24.

[0032] In this embodiment, the spacer wall 24 can be a single spacer wall or a composite spacer wall, for example, it may include a bias spacer wall (not shown) and a main spacer wall (not shown). The main spacer wall and the bias spacer wall may contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source / drain region 26 and the epitaxial layer may contain different dopants or different materials depending on the conductivity type of the transistor being disposed. For example, the source / drain region 26 may contain P-type dopants or N-type dopants, while the epitaxial layer may contain silicon germanide, silicon carbide, or silicon phosphide.

[0033] like Figure 4As shown, a contact hole etch stop layer 32 is then formed on the surface of the fin structure 14, covering the spacer wall 24 and the gate structure 20. An interlayer dielectric layer 34 is then formed on the contact hole etch stop layer 32. A planarization process is then performed, for example, by chemical mechanical polishing to remove part of the interlayer dielectric layer 34 and part of the contact hole etch stop layer 32, exposing the gate material layer 18 made of polysilicon, so that the upper surface of the gate material layer 18 is flush with the upper surface of the interlayer dielectric layer 34.

[0034] A metal gate replacement fabrication process is then performed to convert the gate structure 20 into a metal gate. For example, a selective dry or wet etching process can be performed first, such as using an etching solution like ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 18 to form a groove (not shown) in the interlayer dielectric layer 34. Then, a high-dielectric-constant dielectric layer 36, a work function metal layer 38, and a low-impedance metal layer 40 are sequentially formed within the groove. A planarization process is then performed, for example, using CMP to remove part of the low-impedance metal layer 40, part of the work function metal layer 38, and part of the high-dielectric-constant dielectric layer 36 to form the metal gate 42.

[0035] Subsequently, as Figure 5 As shown, a portion of the low-impedance metal layer 40, a portion of the work function metal layer 38, and a portion of the high-dielectric-constant dielectric layer 36 can be removed to form a groove (not shown). A hard mask 44, made of, for example, silicon nitride, is then filled into the groove, with the upper surface of the hard mask 44 aligned with the upper surface of the interlayer dielectric layer 34. Taking the gate structure fabricated using the high-dielectric-constant dielectric layer fabrication process in this embodiment as an example, the formed metal gate 42 preferably includes a dielectric layer or gate dielectric layer 16, a U-shaped high-dielectric-constant dielectric layer 36, a U-shaped work function metal layer 38, and a low-impedance metal layer 40.

[0036] In this embodiment, the high dielectric constant dielectric layer 36 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0037] The work function metal layer 38 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 38 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 38 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 38 and the low impedance metal layer 40. The material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low impedance metal layer 40 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof.

[0038] A pattern transfer fabrication process can then be performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer 34 next to the metal gate 42 and a portion of the contact hole etching stop layer 32 to form multiple contact holes (not shown) and expose the underlying source / drain regions 26. Then, the desired metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs 46 in each contact hole to electrically connect the source / drain regions 26. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0039] Please refer to again Figure 5 , Figure 5 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 5As shown, the semiconductor device mainly includes a gate structure 20 composed of a metal gate 42 disposed on a substrate 12, a spacer 24 disposed beside the gate structure 20, and source / drain regions 26 disposed on both sides of the spacer 24 in the substrate 12. The gate structure 20 mainly includes a gate dielectric layer 16 and a gate electrode composed of a high dielectric constant dielectric layer 36, a work function metal layer 38, and a low impedance metal layer 40. In this embodiment, a vent is preferably included between the gate dielectric layer 16 and the spacer 24. The vent may specifically include a vent 28 disposed on one side of the gate structure 20, for example, between the gate dielectric layer 18 and the spacer 24 on the left side, and another vent 30 disposed on the other side of the gate structure 20, for example, between the gate dielectric layer 18 and the spacer 24 on the right side.

[0040] In detail, each of the pores 28 and 30 is preferably disposed below the high dielectric constant dielectric layer 36 and / or the work function metal layer 38 in the gate electrode. The edges of each of the pores 28 and 30 are flush with the edge of the gate electrode or the high dielectric constant dielectric layer 36. For example, the outer sidewall of the pore 28 is flush with the left sidewall of the gate electrode, and the outer sidewall of the pore 30 is flush with the right sidewall of the gate electrode. Each pore is surrounded by the fin structure 14, the gate dielectric layer 16, the high dielectric constant dielectric layer 36, and the spacer wall 24.

[0041] Generally, in the fabrication of metal gate transistors, the gate structure and the doped regions on both sides, such as lightly doped drains or source / drain regions, are often too close, leading to problems such as gate-induced drain-leakage (GIDL). To improve this phenomenon, this invention mainly involves an etching process after the gate structure is formed to remove part of the gate dielectric layer, slightly reducing the overall width of the gate dielectric layer inward. Then, spacers are formed on the sidewalls of the gate structure, and pores are simultaneously formed between the gate dielectric layer and the spacers. According to a preferred embodiment of this invention, forming pores on both sides of the gate dielectric layer and directly below the gate electrode composed of polysilicon or metal gates can effectively alleviate or reduce the probability of GIDL and improve device performance.

[0042] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Include: A gate dielectric layer is formed on the substrate; A gate material layer is formed on the gate dielectric layer; The gate material layer and the gate dielectric layer are patterned to form a gate structure; Remove part of the gate dielectric layer; as well as A spacer wall is formed next to the gate structure; A metal gate replacement fabrication process is used to convert the gate structure into a metal gate, which includes a high-dielectric-constant dielectric layer disposed on the gate dielectric layer. The gate dielectric layer and the spacer wall have a pore located directly below the high dielectric constant dielectric layer, exposing the surfaces of the substrate and the gate dielectric layer. The outer sidewall of the pore is flush with the sidewall of the high dielectric constant dielectric layer. The upper part of the substrate includes a first doped region on the first side of the gate dielectric layer that is closest to the gate dielectric layer and a second doped region on the second side of the gate dielectric layer that is closest to the gate dielectric layer relative to the first side. Neither the first doped region nor the second doped region contacts the gate dielectric layer.

2. The method of claim 1, further comprising forming the spacer wall next to the gate structure and forming pores between the gate dielectric layer and the spacer wall.

3. The method of claim 2, wherein the step of forming the pores comprises: A first pore is formed between the gate dielectric layer and the spacer wall on one side of the gate structure; and A second pore is formed between the gate dielectric layer and the spacer wall on the other side of the gate structure.

4. The method of claim 1, wherein the gate dielectric layer comprises silicon oxide.

5. The method of claim 1, wherein the gate material layer comprises polysilicon.

6. The method of claim 1, further comprising forming source / drain regions on both sides of the spacer wall.

7. A semiconductor element characterized by comprising: Include: A gate structure, disposed on a substrate, comprising: A gate dielectric layer is disposed on the substrate; A gate electrode is disposed on the gate dielectric layer, and the gate electrode includes: A high dielectric constant dielectric layer is disposed on the gate dielectric layer; and A work function metal layer is disposed on the high dielectric constant dielectric layer; A spacer wall is disposed beside the gate structure; and A vent is disposed between the gate dielectric layer and the spacer wall, and is located directly below the high dielectric constant dielectric layer, exposing the surfaces of the substrate and the gate dielectric layer. The outer sidewall of the vent is flush with the sidewall of the high dielectric constant dielectric layer. The upper part of the substrate includes a first doped region closest to the gate dielectric layer on the first side of the gate dielectric layer and a second doped region closest to the gate dielectric layer on the second side of the gate dielectric layer relative to the first side. Neither the first doped region nor the second doped region contacts the gate dielectric layer.

8. The semiconductor device of claim 7, further comprising: A first vent is disposed between the gate dielectric layer and the spacer wall on one side of the gate structure; and The second vent is located between the gate dielectric layer and the spacer wall on the other side of the gate structure.

9. The semiconductor device of claim 7, wherein the gate dielectric layer comprises silicon oxide.

10. The semiconductor device of claim 7, wherein the gate electrode comprises a metal gate.

11. The semiconductor device of claim 7, further comprising source / drain regions disposed on both sides of the spacer wall.

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