A method of manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device includes providing a substrate having a first region, a second region, and a third region, forming a first gate oxide layer on the first region, the second region, and the third region, and simultaneously performing an etching process and an infrared processing process to remove the first gate oxide layer on the second region and expose the substrate.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for removing the gate oxide layer using an etching process and an infrared processing process. Background Technology

[0002] In the current semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as the standard gate fill material. However, as the size of MOS transistors continues to shrink, traditional polysilicon gates suffer from problems such as reduced device performance due to the boron penetration effect and the unavoidable depletion effect. This leads to an increase in the equivalent gate dielectric layer thickness, a decrease in gate capacitance, and consequently, a decline in device driving capability. Therefore, the semiconductor industry is exploring new gate fill materials, such as work function metals, to replace traditional polysilicon gates as control electrodes to match high-k gate dielectric layers.

[0003] However, in current metal gate transistor manufacturing processes, especially during the front-end processes of pattern transfer, photolithography, and etching to remove the gate oxide layer on the substrate surface, the accumulation of high charge often prevents the etchant from effectively removing the gate oxide layer, thus affecting the performance of subsequent devices. Therefore, improving current manufacturing processes to solve this problem is an important issue. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first providing a substrate including a first region, a second region and a third region, then forming a first gate oxide layer in the first region, the second region and the third region, and then simultaneously performing an etching process and an infrared processing process to remove the first gate oxide layer on the second region and expose the substrate.

[0005] Generally, when using current pattern transfer or photolithography and etching processes to remove the gate oxide layer on the substrate surface, the accumulation of high charge often prevents the etchant from successfully removing the gate oxide layer. To overcome this drawback, the present invention preferably combines the etching process with an infrared irradiation or treatment process, thereby releasing the accumulated charge and extending the action time of the etchant during the etching process to completely remove the gate oxide layer on the substrate surface and expose the substrate surface. Attached Figure Description

[0006] Figures 1 to 5This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: First Area

[0010] 16: Second Zone

[0011] 18: Third Zone

[0012] 20: Gate oxide layer

[0013] 22: Patterned Mask

[0014] 24: Etching process

[0015] 26: Infrared processing technology

[0016] 28: Gate oxide layer

[0017] 32: Patterned Mask

[0018] 34: Etching process

[0019] 36: Infrared processing manufacturing process

[0020] 38: Gate oxide layer

[0021] 42: Gate material layer

[0022] 44: Gate Structure

[0023] 46: Spacer wall

[0024] 48: Source / Drain Region Detailed Implementation

[0025] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and a first region 14, a second region 16, and a third region 18 are defined on the substrate, wherein each region is intended for subsequent fabrication of gate structures with different threshold voltages. More specifically, the first region 14 includes a core region, the second region 16 is preferably a medium gate region, and the third region 18 includes an input / output region.

[0026] Then, an oxide growth process or more specifically a rapid thermal oxidation (RTO) process is performed to form a gate oxide layer 20 made of silicon oxide in the first region 14, the second region 16, and the third region 18, wherein the thickness of the gate oxide layer 20 made of silicon oxide formed in each region in this stage is preferably between 49 and 51 angstroms or preferably about 50 angstroms.

[0027] Then as Figure 2 As shown, a patterned mask 22, for example a patterned photoresist, is first formed to cover the first region 14 and the third region 18, exposing the gate oxide layer 20 of the second region 16. Then, using the patterned mask 22 as a mask, an etching process 24 and an infrared processing process 26 are simultaneously performed to remove the gate oxide layer 20 on the second region 16. In this embodiment, the formulation used in the etching process 24 preferably includes diluted hydrofluoric acid (dHF), and the etching process 24 preferably takes about 215 seconds.

[0028] Generally, in current pattern transfer fabrication processes, the lower the transmission rate of the patterned photoresist used, the higher the charge will be. The accumulation of high charge during the etching process indirectly prevents etchants such as diluted hydrofluoric acid from successfully removing the gate oxide layer 20 on the surface of the substrate 12. To improve this phenomenon, the present invention preferably combines the aforementioned etching process 24 with an infrared irradiation or treatment process, thereby releasing the accumulated charge and prolonging the action time of the etchant in the etching process 24 to completely remove the gate oxide layer 20 of the second region 16 and expose the surface of the substrate 12.

[0029] It should be noted that since photoresist with low transmittance can lead to charge accumulation, if the transmittance of the patterned mask 22 or the patterned photoresist is less than 7.9% when removing the gate oxide layer 20, an infrared processing fabrication process 26 can be performed to remove the gate oxide layer 20 of the second region 16. Furthermore, the infrared wavelength range used in the infrared processing fabrication process 26 of this embodiment is preferably between 500 nm and 10000 nm, more preferably between 850 nm and 940 nm, or most preferably about 865 nm, but is not limited to this range.

[0030] A detection step can then be selectively performed to confirm whether the gate oxide layer 20 on the second region 16 has been completely removed. According to a preferred embodiment of the present invention, ideally, after the gate oxide layer 20 of the second region 16 is removed by the etching process 24 in this stage, the second region 16 preferably has no gate oxide layer remaining on the surface of the substrate 12, while the first region 14 and the third region 18 still have about 50 angstroms of gate oxide layer 20 on the surface of the substrate 12.

[0031] Subsequently, as Figure 3 As shown, the patterned mask 22 of the first region 14 and the third region 18 is first removed to expose the gate oxide layer 20 of the first region 14 and the third region 18 and the substrate 12 surface of the second region 16. Then, another oxide growth process or, more specifically, a rapid thermal oxidation (RTO) process is performed to form another gate oxide layer 28 made of silicon oxide in the first region 14, the second region 16, and the third region 18. It is worth noting that, since the growth mechanism of the rapid thermal oxidation process generally grows a thinner gate oxide layer in the region where a gate oxide layer is already present and a thicker gate oxide layer grows more quickly in the region where there is no gate oxide layer, the first region 14 and the third region 18, which already have a gate oxide layer 20, will grow a thinner gate oxide layer 28 during this rapid thermal oxidation process, while the second region 16, which originally had no gate oxide layer, will quickly grow a thicker gate oxide layer 28.

[0032] In this embodiment, after the rapid thermal oxidation fabrication process, the overall gate oxide layer thickness of the first region 14 and the third region 18, that is, the total thickness of the gate oxide layer 20 and the gate oxide layer 28, increases from about 50 angstroms to about 54 angstroms, while the overall gate oxide layer 28 thickness of the second region 16 increases to about half of the total gate oxide layer thickness in the first region 14 or the third region 18, for example, about 29 to 30 angstroms or more preferably about 29.5 angstroms.

[0033] Then as Figure 4 As shown, a patterned mask 32 is first formed, for example, a patterned photoresist is used to cover the second region 16 and the third region 18, exposing the gate oxide layer 28 of the first region 14. Then, using the patterned mask 32 as a mask, an etching process 34 and an infrared processing process 36 are simultaneously performed to remove the two gate oxide layers on the first region 14, including the gate oxide layer 28 and the gate oxide layer 20. As described above. Figure 2 The etching process 34 preferably uses a formulation that includes diluted hydrofluoric acid (dHF) and the etching time is preferably about 215 seconds.

[0034] If the transmittance of the patterned mask 22 or the patterned photoresist is less than 75% or more preferably less than 65.4% when removing the two gate oxide layers, including gate oxide layer 28 and gate oxide layer 20, on the first region 14 in this stage, an infrared processing fabrication process 36 can be performed to completely remove the gate oxide layers 20 and 28 of the first region 14. In addition, the infrared wavelength range used in the infrared processing fabrication process 36 in this stage is preferably between 500 nm and 10000 nm, more preferably between 850 and 940 nm or preferably about 865 nm, but is not limited to this.

[0035] Then as Figure 5 As shown, an oxide fabrication process, such as in-situ steam generation (ISSG), can be used to form another gate oxide layer 38 made of silicon oxide in the first region 14, followed by removal of the patterned mask 32 from the second region 16 and the third region 18. However, this order is not limited. According to other embodiments of the present invention, the patterned mask 32 can be removed first, followed by an in-situ steam generation process to form another gate oxide layer 38 made of silicon oxide in the first region 14, the second region 16, and the third region 18. This variation is also within the scope of the present invention. Subsequently, the fabrication processes for gate structures, spacers, and source / drain regions can be performed according to the fabrication process or product requirements.

[0036] For example, the gate structure can be formed by sequentially forming a gate material layer and a selective hard mask (not shown) on the substrate 12 of the first region 14, the second region 16, and the third region 18, including the gate oxide layer 38 of the first region 14, the gate oxide layer 28 of the second region 16, and the gate oxide layer 28 of the third region 18. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process, removing part of the gate material layer and part of the gate oxide layers 20, 28, and 38 in a single etching or sequential etching step. Then, the patterned photoresist is stripped to form a gate structure 44 composed of the patterned gate oxide layer 38 and the patterned gate material layer 42 in the first region 14, a gate structure 44 composed of the patterned gate oxide layer 28 and the patterned gate material layer 42 in the second region 16, and a gate structure 44 composed of the patterned gate oxide layers 20 and 28 and the patterned gate material layer 42 in the third region 18. In this embodiment, the gate material layer 26 may contain polysilicon, but is not limited thereto.

[0037] Then, at least one spacer wall 46 is formed on the sidewall of each gate structure 44. A source / drain region 48 and / or an epitaxial layer (not shown) are formed in the substrate 12 on both sides of the spacer wall 46, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region 48 and / or the epitaxial layer. In this embodiment, the spacer wall 46 can be a single spacer wall or a composite spacer wall. For example, it may include a bias spacer wall (not shown) and a main spacer wall (not shown). The spacer wall 46 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but is not limited thereto. The source / drain region 48 and the epitaxial layer may contain different dopants or different materials depending on the conductivity type of the transistor. For example, the source / drain region 30 may contain P-type dopants or N-type dopants, while the epitaxial layer may contain silicon germanide, silicon carbide, or silicon phosphide.

[0038] Subsequently, depending on the manufacturing process or product requirements, an interlayer dielectric layer can be formed on each gate structure 44. A replacement metal gate (RMG) process can be selectively performed to convert each gate structure 44 into a metal gate, and contact plugs are formed in the interlayer dielectric layer on both sides of each gate structure 44 to connect the source / drain regions 48. Since the conversion of the gate structure into a metal gate and the contact plug processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor device according to the present invention.

[0039] Generally, when using current pattern transfer or photolithography and etching processes to remove the gate oxide layer on the substrate surface, the accumulation of high charge often prevents the etchant from successfully removing the gate oxide layer. To overcome this drawback, the present invention preferably combines the etching process with an infrared irradiation or treatment process, thereby releasing the accumulated charge and extending the action time of the etchant during the etching process to completely remove the gate oxide layer on the substrate surface and expose the substrate surface.

[0040] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: The substrate includes a first region, a second region, and a third region; A first gate oxide layer is formed in the first region, the second region, and the third region; A patterned mask is formed on the first region and the third region, and the patterned mask has a high charge; as well as Simultaneously, etching and infrared processing are performed to remove the first gate oxide layer on the second region and release the accumulated charge.

2. The method of claim 1, further comprising: A second gate oxide layer is formed in the first region, the second region, and the third region; Remove the first gate oxide layer and the second gate oxide layer on the first region; and A third gate oxide layer is formed in the first region.

3. The method of claim 1, further comprising simultaneously performing the etching process and the infrared processing process.

4. The method of claim 1, further comprising performing the etching process and the infrared processing process to completely remove the first gate oxide layer on the second region and expose the substrate.

5. The method of claim 1, further comprising a detection step to confirm the removal of the first gate oxide layer on the second region.

6. The method of claim 1, wherein the first region comprises a core region.

7. The method of claim 1, wherein the third region comprises an input / output area.

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