Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, comprising: providing a substrate, the substrate comprising a first region and a second region, a plurality of dummy gates being formed on the first region and the second region, and a hard mask layer being formed on the dummy gates; forming a second nitride layer to conformingly cover the first region and the second region; opening the second region by lithography; etching to remove the second nitride layer on the top of the first oxide layer of the second region and part of the second nitride layer on the sidewall of the second region; etching to remove the second nitride layer on the top and sidewall of the first oxide layer of the first region and the remaining second nitride layer on the sidewall of the first oxide layer of the second region; forming a second oxide layer to cover the first region and the second region; and performing a polishing process to expose the dummy gates. The application makes the hard mask layer not exist on the dummy gates after the polishing process, is beneficial to the subsequent process, eliminates the process defects, and improves the global uniformity of the process parameters.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of semiconductor device. BACKGROUND

[0002] In the process technology of semiconductor integrated circuit, due to the difference of process flow, when the dummy gate is formed in different regions, the height difference of the hard mask layer on the top of the dummy gate in these regions exists after a series of process flows due to the width difference of the dummy gate in different regions, the hard mask layer includes the nitride layer and the oxide layer on the top of the dummy gate in turn, that is, the thickness difference of the oxide layer leads to the height difference of the top of the hard mask layer. The difference will cause the etching residue of the dummy gate when the dummy gate is etched in the subsequent process, the position of the dummy gate is the position of the subsequently formed metal gate, and the height of the metal gate is affected due to the etching residue of the dummy gate after the formation of the metal gate. SUMMARY

[0003] The purpose of the present application is to provide a preparation method of semiconductor device, so that there is no residual hard mask layer on the dummy gate after the grinding process, which is beneficial to the subsequent process, eliminates the process defects, and improves the global uniformity of the process parameters.

[0004] In order to achieve the above purpose, the present application provides a preparation method of semiconductor device, comprising:

[0005] providing a substrate, the substrate comprising a first region and a second region, a plurality of dummy gates are formed on the first region and the second region, the width of the dummy gate on the first region is smaller than the width of the dummy gate on the second region, and a hard mask layer is formed on the dummy gate, the hard mask layer comprises a first nitride layer and a first oxide layer on the dummy gate in turn;

[0006] forming a second nitride layer conformally covering the first region and the second region;

[0007] forming a patterned photoresist layer covering the first region and the second region to expose the second nitride layer on the dummy gate in the second region;

[0008] etching to remove the second nitride layer on the top of the first oxide layer in the second region and part of the second nitride layer on the sidewall of the first oxide layer in the second region with the patterned photoresist layer as a mask;

[0009] etching to remove the second nitride layer on the top and sidewall of the first oxide layer in the first region and the remaining second nitride layer on the sidewall of the first oxide layer in the second region;

[0010] forming a second oxide layer covering the first region and the second region and covering over the first oxide layer, the first oxide layer and the second oxide layer having the same material;

[0011] performing a grinding process to grind the second oxide layer, the first oxide layer and the first nitride layer to expose the dummy gate.

[0012] Optionally, a thickness of the first oxide layer on the dummy gate on the first region is less than a thickness of the first oxide layer on the dummy gate on the second region.

[0013] Optionally, after the step of etching to remove the second nitride layer on top of the first oxide layer on the second region and a portion of the second nitride layer on the sidewall of the first oxide layer on the second region, the patterned photoresist layer is removed.

[0014] Optionally, the step of etching to remove the second nitride layer on top of and on the sidewall of the first oxide layer on the first region and the remaining second nitride layer on the sidewall of the first oxide layer on the second region comprises:

[0015] forming a fill material layer covering the first region and the second region and covering over the second nitride layer;

[0016] etching to remove a portion of the fill material layer to expose the second nitride layer on the first region and the second nitride layer on the second region;

[0017] etching to remove the second nitride layer on top of and on the sidewall of the first oxide layer on the first region and the remaining second nitride layer on the sidewall of the first oxide layer on the second region; and,

[0018] etching to remove the remaining fill material layer.

[0019] Optionally, the step of etching to remove the second nitride layer on top of and on the sidewall of the first oxide layer on the first region and the remaining second nitride layer on the sidewall of the first oxide layer on the second region is performed by a wet etching process.

[0020] Optionally, the step of forming the second oxide layer covering the first region and the second region is performed by a flowable vapor deposition process.

[0021] Optionally, the first oxide layer and the second oxide layer each comprise silicon oxide.

[0022] Optionally, the grinding process comprises a first grinding process and a second grinding process performed sequentially, and the step of performing a grinding process to grind the second oxide layer, the first oxide layer and the first nitride layer to expose the dummy gate comprises:

[0023] performing a first grinding process to grind the first oxide layer and the second oxide layer to expose a surface of the first nitride layer; and

[0024] performing a second grinding process to grind the second oxide layer, the first nitride layer and the second nitride layer to expose a surface of the dummy gate.

[0025] Optionally, after the second grinding process is performed to grind the second oxide layer, the first oxide layer and the first nitride layer to expose the dummy gate, the method further comprises etching to remove the dummy gate.

[0026] Optionally, after the dummy gate is etched to be removed, the method further comprises forming a metal gate structure in the area where the dummy gate is removed, and the top of the metal gate structure on the first area and the second area is flush.

[0027] In the method for manufacturing the semiconductor device, by etching to remove the second nitride layer on the top of the first oxide layer on the second area and the partial second nitride layer on the sidewall of the second nitride layer, the top of the second nitride layer on the sidewall of the dummy gate on the second area is lower than the top of the first oxide layer, and the height of the second nitride layer on the sidewall of the dummy gate on the second area does not need to be monitored in the subsequent etching; the second nitride layer on the top and the sidewall of the first oxide layer on the first area and the remaining second nitride layer on the sidewall of the first oxide layer on the second area are etched to be removed, so that the top and the sidewall of the first oxide layer on the first area and the second area are exposed; then the second oxide layer is formed to cover the first area and the second area, and the grinding process is performed again. Since the material of the first oxide layer and the second oxide layer is the same and the top and the sidewall of the first oxide layer on the first area and the second area are exposed, the uniformity of the grinding can be ensured, the top of the second nitride layer on the sidewall of the dummy gate is flush with the top of the dummy gate after the grinding process, and there is no residual hard mask layer on the dummy gate, which is beneficial to the subsequent process, eliminates the process defects, and improves the global uniformity of the process parameters. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 a flow chart of the method for manufacturing the semiconductor device;

[0029] Figures 2A-2K a cross-sectional schematic view of corresponding steps in the method for manufacturing the semiconductor device according to an embodiment of the present application.

[0030] wherein, Figures 2A-2K the reference signs in the drawings are as follows:

[0031] 10 - substrate; 11 - first region; 12 - second region; 20 - dummy gate; 31 - first nitrided layer; 32 - second nitrided layer; 41 - first oxidized layer; 42 - second oxidized layer; 50 - patterned photoresist layer; 60 - filling material layer. DETAILED DESCRIPTION

[0032] In the preparation method of the semiconductor device, the width of the dummy gate in different regions is different, which can cause the height difference of the hard mask layer reserved on the top of the dummy gate in these regions after a series of process flows, and the hard mask layer includes the first nitrided layer and the first oxidized layer which are sequentially located on the top of the dummy gate. To improve this problem, the current solution is to form a second nitrided layer covering the dummy gate, then use a photolithography process to open the region of the dummy gate with a larger width, and etch to remove the second nitrided layer on the top of the dummy gate with a larger width; then etch to remove the first oxidized layer and the second nitrided layer on the top of the dummy gate, deposit a second oxidized layer to fill between the dummy gates, and use a grinding process to grind the second oxidized layer, the first nitrided layer and the second nitrided layer to stop on the top of the dummy gate, so as to reduce the height difference of the hard mask layer reserved on the top of the dummy gate in different regions. However, it is not easy to control the height of the second nitrided layer (side wall) of the dummy gate in the current solution, and the second nitrided layer of the dummy gate is prone to be in a convex state after the grinding process, so that the top of the second nitrided layer of the dummy gate is higher than the top of the dummy gate, which is not conducive to the subsequent process.

[0033] Therefore, the present application provides a preparation method of a semiconductor device, which can make the top of the second nitrided layer of the dummy gate sidewall in the second region lower than the top of the first oxidized layer by etching to remove the second nitrided layer on the top of the first oxidized layer and part of the second nitrided layer on the sidewall of the first oxidized layer in the second region, so that the height of the second nitrided layer of the dummy gate sidewall in the second region does not need to be monitored during subsequent etching; etching to remove the second nitrided layer on the top and sidewall of the first oxidized layer in the first region and the remaining second nitrided layer on the sidewall of the first oxidized layer in the second region, so that the top and sidewall of the first oxidized layer in the first region and the second region are exposed; then forming a second oxidized layer covering the first region and the second region and performing a grinding process. Since the material of the first oxidized layer and the second oxidized layer is the same and the top and sidewall of the first oxidized layer in the first region and the second region are exposed, the grinding uniformity can be ensured, so that the top of the second nitrided layer on the dummy gate sidewall is flush with the top of the dummy gate and there is no residual hard mask layer on the dummy gate after the grinding process, which is conducive to the subsequent process, eliminates process defects, and improves the global uniformity of process parameters.

[0034] The specific embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The advantages and features of the present application will become more apparent after a careful reading of the following description with attached drawings. It should be understood that the drawings are not to scale. All use the same reference numerals to indicate the same components throughout the several views of the drawings.

[0035] Figure 1 A flow chart of the method for manufacturing a semiconductor device is provided in this embodiment. Please refer to Figure 1 The present application provides a method for manufacturing a semiconductor device, comprising:

[0036] Step S1: providing a substrate, the substrate comprising a first region and a second region, a plurality of dummy gates are formed on the first region and the second region, the width of the dummy gates on the first region is smaller than the width of the dummy gates on the second region, and a hard mask layer is formed on the dummy gates, the hard mask layer comprising a first nitride layer and a first oxide layer on the dummy gates in sequence;

[0037] Step S2: forming a second nitride layer to conformly cover the first region and the second region;

[0038] Step S3: forming a patterned photoresist layer to cover the first region and the second region, so as to expose the second nitride layer on the dummy gates on the second region;

[0039] Step S4: etching to remove the second nitride layer on the top of the first oxide layer on the second region and the partial second nitride layer on the sidewall of the second nitride layer, with the patterned photoresist layer as a mask;

[0040] Step S5: etching to remove the second nitride layer on the top and sidewall of the first oxide layer on the first region and the remaining second nitride layer on the sidewall of the first oxide layer on the second region;

[0041] Step S6: forming a second oxide layer to cover the first region and the second region, and covering the first oxide layer, the material of the first oxide layer and the second oxide layer being the same;

[0042] Step S7: performing a polishing process to polish the second oxide layer, the first oxide layer and the first nitride layer to expose the dummy gates.

[0043] Figures 2A-2K A cross-sectional schematic view of the corresponding steps in the method for manufacturing a semiconductor device provided in this embodiment is described below in combination with Figures 2A-2K The method for manufacturing a semiconductor device provided in this embodiment is described in detail.

[0044] Please refer to Figure 2A, execute step S1: provide a substrate 10, the material of the substrate 10 can include one or more of silicon, carbon, germanium, gallium and arsenic. The substrate 10 includes a first region 11 and a second region 12, and a plurality of dummy gates 20 are formed on the first region 11 and the second region 12, and the width of the dummy gate 20 on the first region 11 is smaller than the width of the dummy gate 20 on the second region 12. The top of the dummy gate 20 is formed with a hard mask layer, which is reserved when the dummy gate 20 is etched in the previous process, and can be used to protect the topography of the dummy gate 20 when etching the dummy gate 20. The hard mask layer includes a first nitride layer 31 and a first oxide layer 41 which are sequentially located on the dummy gate 20. Since the width of the dummy gate 20 on the first region 11 is smaller than the width of the dummy gate 20 on the second region 12, there is a difference in etching rate when etching the dummy gate 20, resulting in a difference in the thickness of the first oxide layer 41 reserved on the first region 11 and the second region 12, i.e. the thickness of the first oxide layer 41 on the dummy gate 20 on the first region 11 is smaller than the thickness of the first oxide layer 41 on the dummy gate 20 on the second region 12, which means that there is a height difference between the top of the hard mask layer on the dummy gate 20 on the first region 11 and the top of the hard mask layer on the dummy gate 20 on the second region 12.

[0045] Please refer to Figure 2B , execute step S2: form a second nitride layer 32 conformally covering the first region 11 and the second region 12, specifically covering the exposed surface of the substrate 10, the dummy gate 20 and the hard mask layer (the first nitride layer 31 and the first oxide layer 41). In this embodiment, the thickness of the second nitride layer 32 can be the difference between the thickness of the first oxide layer 41 on the dummy gate 20 on the first region 11 and the thickness of the first oxide layer 41 on the dummy gate 20 on the second region 12, but it is not limited thereto, and the thickness of the second nitride layer 32 is determined according to the actual situation.

[0046] Please refer to Figure 2C , execute step S3: form a patterned photoresist layer 50 covering the first region 11 and the second region 12 to expose the second nitride layer 32 on the dummy gate 20 on the second region 12.

[0047] Please continue to refer to Figure 2C and refer to Figure 2D , execute step S4: etch and remove the second nitride layer 32 on the top of the first oxide layer 41 on the second region 12 and part of the second nitride layer 32 on the sidewall thereof using the patterned photoresist layer 50 as a mask to expose the top and part of the sidewall of the first oxide layer 41 on the second region 12 (see Figure 2D ); further, remove the patterned photoresist layer 50 by ashing process.

[0048] The step S5 of etching to remove the second nitride layer on the top and sidewall of the first oxide layer in the first region and the remaining second nitride layer on the sidewall of the first oxide layer in the second region comprises:

[0049] Please refer to Figure 2E A filling material layer 60 is formed to cover the first region 11 and the second region 12 and to cover the second nitride layer 32, and the material of the filling material layer 60 is preferably an organic material.

[0050] Please refer to Figure 2F The filling material layer 60 is etched to expose the second nitride layer 32 on the second region 12 and the second nitride layer 32 on the first region 11, and the remaining filling material layer 60 can protect the surface of the substrate 10 and the second nitride layer 32 on the sidewall of the dummy gate 20 during subsequent etching processes.

[0051] Please refer to Figure 2G The second nitride layer 32 on the top and sidewall of the first oxide layer 41 in the first region 11 and the remaining second nitride layer 32 on the sidewall of the first oxide layer 41 in the second region 12 are etched and removed by a wet etching process.

[0052] Please refer to Figure 2H The remaining filling material layer 60 is etched and removed, and it can be seen from the figure that after the second nitride layer 32 on the top and sidewall of the first oxide layer 41 in the first region 11 and the remaining second nitride layer 32 on the sidewall of the first oxide layer 41 in the second region 12 are etched and removed, the top and sidewall of the first oxide layer 41 in the first region 11 and the second region 12 are completely exposed.

[0053] Please refer to Figure 2I The step S6 is performed: a flowable vapor deposition process is used to form a second oxide layer 42 to cover the first region 11 and the second region 12 and to cover the first oxide layer 41, the materials of the first oxide layer 41 and the second oxide layer 42 are the same, and the materials of the first oxide layer 41 and the second oxide layer 42 both include silicon oxide. In this embodiment, the flowable vapor deposition process has good flowability and can be well filled between the dummy gates 20 to avoid the formation of voids, and the materials of the first oxide layer 41 and the second oxide layer 42 are the same, which is beneficial for subsequent polishing processes.

[0054] The step S7 of performing a polishing process comprises a first polishing process and a second polishing process performed in sequence, and the step of performing a polishing process to polish the second oxide layer, the first oxide layer, and the first nitride layer to expose the dummy gate comprises:

[0055] Please refer to Figure 2I and refer to Figure 2JThe first grinding process is performed to grind the first oxide layer 41 and the second oxide layer 42 to expose the surface of the first nitride layer 31. Since the top and sidewalls of the first oxide layer 41 on the first region 11 and the second region 12 are completely exposed, even if the thickness of the first oxide layer 41 on the virtual gate 20 on the first region 11 is less than the thickness of the first oxide layer 41 on the virtual gate 20 on the second region 12, after the second oxide layer 42 is formed, the film layer on the top of the virtual gate 20 is made of the same material and the grinding rate is the same. Therefore, the uniformity of grinding can be well controlled. After the first grinding process is performed, there is no residual first oxide layer 41 on the first nitride layer 31 on the first region 11 and the second region 12.

[0056] Please continue to refer to this. Figure 2J and reference Figure 2K The second polishing process is performed to polish the second oxide layer 42, the first nitride layer 31, and the second nitride layer 32 to expose the top of the virtual gate 20. Since there is no residual first oxide layer 41 on the first nitride layer 31 on the first region 11 and the second region 12, and the thickness of the first nitride layer 41 is the same, after the second polishing process, there is no residual first nitride layer 31 on the virtual gate 20 on the first region 11 and the second region 12, and the top of the second nitride layer 32 on the sidewall of the virtual gate 20 is flush with the top of the virtual gate 20.

[0057] Furthermore, after the polishing process is completed, the virtual gate is also etched away. Since there is no residual hard mask layer on the top of the virtual gate, and the top of the second nitride layer is flush with the top of the virtual gate, it can be ensured that the virtual gates on the first and second regions are completely etched away, and there will be no etch residue of the virtual gate. Then, a metal gate structure is formed in the region after the virtual gate is removed. Since the virtual gates on the first and second regions are completely etched away, the final height of the metal gate structure can be better controlled after the metal gate structure is formed on the first and second regions.

[0058] In summary, in the semiconductor device fabrication method provided by this invention, by etching away the second nitride layer on top of the first oxide layer and a portion of the second nitride layer on its sidewalls in the second region, the top of the second nitride layer on the virtual gate sidewalls in the second region is lower than the top of the first oxide layer. Therefore, it is not necessary to monitor the height of the second nitride layer on the virtual gate sidewalls in the second region during subsequent etching. Etching away the second nitride layer on top of and sidewalls of the first oxide layer in the first region, as well as the remaining second nitride layer on the sidewalls of the first oxide layer in the second region, exposes the top and sidewalls of the first oxide layer in both the first and second regions. Then, a second oxide layer is formed covering both the first and second regions before a polishing process is performed. Since the first and second oxide layers are made of the same material and the top and sidewalls of the first oxide layer in both regions are exposed, polishing uniformity is ensured. After the polishing process, the top of the second nitride layer on the virtual gate sidewalls is flush with the top of the virtual gate, and there are no residual hard mask layers on the virtual gate. This facilitates subsequent processes, eliminates process defects, and improves the global uniformity of process parameters.

[0059] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, a plurality of dummy gates are formed on the first region and the second region, the width of the dummy gates on the first region is smaller than the width of the dummy gates on the second region, and a hard mask layer is formed on the dummy gates, the hard mask layer including a first nitride layer and a first oxide layer sequentially located on the dummy gates, the thickness of the first oxide layer on the first region is smaller than the thickness of the first oxide layer on the second region. A second nitrided layer is formed to conformally cover the first region and the second region; A patterned photoresist layer is formed to cover the first region and the second region to expose the second nitride layer on the virtual gate on the second region; Using the patterned photoresist layer as a mask, etch away the second nitride layer on top of the first oxide layer and a portion of the second nitride layer on its sidewalls in the second region; Etching removes the second nitride layer on the top and sidewalls of the first oxide layer in the first region and the remaining second nitride layer on the sidewalls of the first oxide layer in the second region; A second oxide layer is formed to cover the first region and the second region, and extends above the first oxide layer. The first oxide layer and the second oxide layer are made of the same material. as well as, A polishing process is performed to polish the second oxide layer, the first oxide layer, and the first nitride layer until the virtual gate is exposed.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After etching away the second nitride layer on top of the first oxide layer and a portion of the second nitride layer on its sidewalls in the second region, the patterned photoresist layer is removed.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The step of etching away the second nitride layer on the top and sidewalls of the first oxide layer on the first region and the remaining second nitride layer on the sidewalls of the first oxide layer on the second region includes: A filler material layer is formed to cover the first region and the second region, and extends above the second nitride layer; Etching removes part of the filler material layer to expose the second nitride layer on the second region and the second nitride layer on the first region; Etching removes the second nitride layer on the top and sidewalls of the first oxide layer in the first region, and the remaining second nitride layer on the sidewalls of the first oxide layer in the second region; and, The remaining filler material layer is removed by etching.

4. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The second nitride layer on the top and sidewalls of the first oxide layer on the first region and the remaining second nitride layer on the sidewalls of the first oxide layer on the second region are removed by wet etching process.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, A second oxide layer is formed by using a fluidized vapor deposition process to cover the first region and the second region.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, Both the first oxide layer and the second oxide layer are made of silicon oxide.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The polishing process includes a first polishing process and a second polishing process executed sequentially. The step of polishing the second oxide layer, the first oxide layer, and the first nitride layer until the virtual gate is exposed includes: A first polishing process is performed to polish the first oxide layer and the second oxide layer to expose the surface of the first nitride layer; and, A second polishing process is performed to polish the second oxide layer, the first nitride layer, and the second nitride layer to expose the surface of the virtual gate.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After performing a polishing process to polish the second oxide layer, the first oxide layer, and the first nitride layer until the dummy gate is exposed, the process further includes etching to remove the dummy gate.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, After etching away the dummy gate, the process further includes forming a metal gate structure in the region where the dummy gate has been removed, with the tops of the metal gate structures in the first and second regions being flush.

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