Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a first sidewall and a second sidewall between the initial gate structure sidewall and the first dielectric layer, the first sidewall being between the initial gate dielectric layer sidewall and the second sidewall; forming a first conductive structure in the first dielectric layer, the first conductive structure being on the substrate surface on both sides of the gate structure; etching the initial gate dielectric layer and the first sidewall to form a first recess between the first conductive structure and the gate layer, the first recess exposing the gate layer sidewall, and forming a gate dielectric layer from the initial gate dielectric layer at the bottom of the gate layer; forming a second dielectric layer on the first dielectric layer and the gate structure surface, the second dielectric layer closing the top of the first recess and forming an air sidewall between the first conductive structure and the gate layer, which is conducive to reducing parasitic capacitance and improving device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly realized by continuously reducing the size of integrated circuit devices to improve its speed. At present, due to the demand for high device density, high performance and low cost, the semiconductor industry has progressed to the nanometer technology node, and the preparation of semiconductor devices is limited by various physical limits.

[0003] With the evolution of the semiconductor technology node, the increase in device density has brought many problems, one of which is the rapidly increasing parasitic capacitance between the metal gate (MG) and the contact hole. Excessive parasitic capacitance can significantly affect the dynamic performance of the device. At present, a low dielectric constant dielectric layer, such as silicon oxide or silicon nitride, is usually used as a sidewall between the metal gate and the contact hole to eliminate this effect.

[0004] However, the problem of excessive parasitic capacitance of semiconductor devices still needs to be improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the problem of excessive parasitic capacitance of semiconductor devices.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a base, a fin portion on the base, and an isolation structure, the isolation structure also being on the sidewall of the fin portion, and the top surface of the isolation structure being lower than the top surface of the fin portion; a first dielectric layer on the substrate and a gate structure in the first dielectric layer, the gate structure crossing the fin portion and being on part of the sidewall and the top surface of the fin portion, the gate structure comprising a gate layer, a gate dielectric layer on the bottom of the gate layer, an air sidewall on the sidewall of the gate layer, and a second sidewall, the air sidewall being between the gate layer and the second sidewall and exposing the sidewall of the gate layer and the second sidewall; a source-drain layer in the fin portion on both sides of the gate structure; a first conductive structure in the first dielectric layer, the first conductive structure being on the surface of the source-drain layer; a second dielectric layer on the surface of the first dielectric layer and the gate structure, the second dielectric layer being on the top of the air sidewall, and the air sidewall also being between the first conductive structure and the gate layer.

[0007] Optionally, the gate dielectric layer further comprises a portion of the initial gate dielectric layer on the sidewall of the gate layer.

[0008] Optionally, the semiconductor structure further comprises a second conductive structure on a surface of the first conductive structure and a third conductive structure on a surface of the gate structure, and the air spacer is between the second conductive structure and the third conductive structure.

[0009] Accordingly, the technical scheme of the present application further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a base, a fin on the base, and an isolation structure on the fin sidewall, and the top surface of the isolation structure being lower than the top surface of the fin; forming a first dielectric layer and an initial gate structure in the first dielectric layer on the substrate, the initial gate structure crossing the fin and being on part of the fin sidewall and top surface, the initial gate structure comprising a gate layer, an initial gate dielectric layer on the sidewall surface and bottom of the gate layer, and a first spacer and a second spacer between the sidewall of the initial gate structure and the first dielectric layer, the first spacer being between the sidewall of the initial gate dielectric layer and the second spacer; forming a first conductive structure in the first dielectric layer, the first conductive structure being on the surface of the substrate on both sides of the gate structure; etching the initial gate dielectric layer and the first spacer to form a first recess between the first conductive structure and the gate layer, the first recess exposing the sidewall of the gate layer, the initial gate dielectric layer at the bottom of the gate layer forming a gate dielectric layer, and the initial gate structure forming a gate structure; forming a second dielectric layer on the surface of the first dielectric layer and the gate structure, the second dielectric layer closing the top of the first recess and forming an air spacer between the first conductive structure and the gate layer.

[0010] Optionally, the gate dielectric layer further comprises part of the initial gate dielectric layer on the sidewall of the gate layer.

[0011] Optionally, the method for forming the first recess comprises: etching the first spacer to a target depth, the remaining first spacer forming a protection layer; and after forming the protection layer, etching the initial gate dielectric layer.

[0012] Optionally, the first conductive structure is located on a surface of a source-drain layer in the substrate on both sides of the gate structure; and the forming method of the first conductive structure, the initial gate structure and the source-drain layer comprises: before forming the first dielectric layer, forming a dummy gate structure on part of the substrate, a first sidewall and a second sidewall located on sidewalls of the dummy gate structure, and the first sidewall is located between the dummy gate structure and the second sidewall, the dummy gate structure spans the fin and is located on part of the sidewalls and the top surface of the fin; forming a source-drain layer in the fin on both sides of the dummy gate structure; after forming the source-drain layer, forming a first dielectric layer on the substrate, the first dielectric layer is located on the sidewalls of the dummy gate structure and exposes the top surface of the dummy gate structure; removing the dummy gate structure to form a gate opening in the first dielectric layer; forming the initial gate dielectric layer and the gate layer located on the surface of the initial gate dielectric layer in the gate opening; forming a first opening in the first dielectric layer, the first opening exposes part of the surface of the source-drain layer; and forming the first conductive structure in the first opening.

[0013] Optionally, before forming the first recess, the method comprises: forming a third dielectric layer on the surface of the first dielectric layer, the initial gate structure and the first conductive structure; forming a second conductive structure in the third dielectric layer, the second conductive structure is located on the surface of the first conductive structure; forming a third conductive structure in the third dielectric layer, the third conductive structure is located on the surface of the gate layer; removing the third dielectric layer to form a second recess, the second recess exposes the top surface of the initial gate dielectric layer and the first sidewall.

[0014] Optionally, the material of the third dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0015] Optionally, before forming the first recess, the method comprises: forming a third dielectric layer on the surface of the first dielectric layer, the initial gate structure and the first conductive structure; forming a second conductive structure in the third dielectric layer, the second conductive structure is located on the surface of the first conductive structure; forming a third conductive structure in the third dielectric layer, the third conductive structure is located on the surface of the gate layer; removing the third dielectric layer to form a second recess, the second recess exposes the top surface of the initial gate dielectric layer and the first sidewall.

[0016] Optionally, the air sidewall is also located between the second conductive structure and the third conductive structure.

[0017] Optionally, the material of the third dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0018] Optionally, the material of the first sidewall is different from the material of the second sidewall.

[0019] Optionally, the material of the second sidewall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride; and the material of the first sidewall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0020] Optionally, the material of the gate dielectric layer comprises a high-K dielectric material; and the material of the gate electrode layer comprises a metal.

[0021] Optionally, the forming process of the second dielectric layer comprises a plasma enhanced chemical vapor deposition process.

[0022] Optionally, the material of the second dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0023] Optionally, the first recess has a depth-to-width ratio ranging from 2:1 to 10:1.

[0024] Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:

[0025] In the forming method of the semiconductor structure provided by the technical scheme, the initial gate dielectric layer and the first sidewall are etched, a first recess is formed between the first conductive structure and the gate electrode layer, the first recess exposes the sidewall of the gate electrode layer, the gate dielectric layer is formed from the initial gate dielectric layer at the bottom of the gate electrode layer, the initial gate dielectric layer at the sidewall of the gate electrode layer is removed, and the parasitic capacitance between the gate electrode layer and the first conductive structure is reduced; on the other hand, the second dielectric layer is formed on the surface of the first dielectric layer and the gate electrode structure, the second dielectric layer seals the top of the first recess, an air sidewall is formed between the first conductive structure and the gate electrode layer, the air sidewall has a smaller dielectric constant and is used for isolating the gate electrode layer from the first conductive structure, the parasitic capacitance between the gate electrode layer and the first conductive structure is reduced, and the performance of the device is improved.

[0026] Further, the first sidewall is etched to a target depth, and the remaining first sidewall forms a protective layer, which is used to protect the subsequently formed gate dielectric layer from being damaged in the etching process, thereby improving the gate leakage current of the formed device and improving the performance of the device.

[0027] Further, the material of the first sidewall is different from the material of the second sidewall, and the second sidewall is used to protect the first dielectric layer from being damaged in the etching process, thereby improving the performance stability of the formed device.

[0028] The semiconductor structure provided by the technical scheme has the following advantages: the gate structure comprises a gate layer and a gate dielectric layer located at the bottom of the gate layer, and the sidewall of the gate layer of the semiconductor structure is free of the gate dielectric layer, thereby reducing the parasitic capacitance between the gate layer and the first conductive structure; on the other hand, the air side wall is also located between the first conductive structure and the gate layer, and the air side wall has a small dielectric constant and is used for isolating the gate layer from the first conductive structure, thereby reducing the parasitic capacitance between the gate layer and the first conductive structure and improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a sectional structure schematic diagram of a semiconductor structure;

[0030] Figures 2 to 4 is a structure schematic diagram of each step of a forming method of the semiconductor structure of an embodiment of the present application;

[0031] Figures 5 to 8 is a structure schematic diagram of each step of a forming method of the semiconductor structure of another embodiment of the present application;

[0032] Figures 9 to 13 is a structure schematic diagram of each step of a forming method of the semiconductor structure of still another embodiment of the present application. DETAILED DESCRIPTION

[0033] As described in the background, the problem of excessive parasitic capacitance of the existing semiconductor device still needs to be improved. Now, a semiconductor structure is described and analyzed.

[0034] It should be noted that the "surface", "upper", in the specification are used to describe the relative position relationship in space, and are not limited to whether they are in direct contact.

[0035] Figure 1 is a sectional structure schematic diagram of a semiconductor structure.

[0036] Please refer to Figure 1 , the semiconductor structure comprises: a substrate 100; a gate structure located on part of the substrate 100, the gate structure comprising a gate layer 101; a source-drain region 102 located in the substrate 100 on both sides of the gate structure; a dielectric layer 103 located on the substrate 100, the dielectric layer 103 being located on the top and sidewall of the gate structure 102; a conductive plug 104 located in the dielectric layer 103, the conductive plug 104 being located on the source-drain region 102.

[0037] The material of the gate layer 101 is metal. The gate layer 101 is formed by a metal replacement gate process. The gate layer 101 and the substrate 100 are separated by a gate dielectric layer 105 formed by high-K dielectric material, which is used to improve the leakage current of the gate structure and the reliability of the formed device. With the development of integrated circuits, the feature size of the semiconductor structure is getting smaller and smaller, and the distance between the conductive plug 104 and the gate structure is also getting smaller and smaller, so the parasitic capacitance between the conductive plug 104 and the gate structure is getting larger and larger. The gate structure also includes a sidewall 106 of the sidewall of the gate layer 101. In order to reduce the parasitic capacitance, the sidewall 106 is usually made of low-K dielectric material to reduce the influence of the parasitic capacitance.

[0038] However, due to the limitation of the metal replacement gate process, the gate dielectric layer 105 is also formed on the sidewall of the gate layer 101. Since the gate dielectric layer 105 is made of high-K dielectric material, the gate dielectric layer 105 will increase the parasitic capacitance, which will affect the performance of the semiconductor structure. In another embodiment, an air sidewall is used to replace the sidewall, that is, the performance of the air sidewall with smaller dielectric constant is used to reduce the influence of the parasitic capacitance. However, since the gate structure is formed by the metal replacement gate process, the sidewall of the gate layer inevitably introduces the gate dielectric layer. The existence of the gate dielectric layer limits the further reduction of the parasitic capacitance.

[0039] In order to solve the above problems, the present application provides a semiconductor structure forming method. The initial gate dielectric layer and the first sidewall are etched, a first recess is formed between the first conductive structure and the gate layer, the first recess exposes the sidewall of the gate layer, the gate dielectric layer is formed by the initial gate dielectric layer at the bottom of the gate layer, the initial gate dielectric layer of the sidewall of the gate layer is removed, and the parasitic capacitance between the gate layer and the first conductive structure is reduced. On the other hand, a second dielectric layer is formed on the first dielectric layer and the surface of the gate structure, the second dielectric layer seals the top of the first recess, an air sidewall is formed between the first conductive structure and the gate layer, the air sidewall has smaller dielectric constant, which is used to isolate the gate layer and the first conductive structure, and can reduce the parasitic capacitance between the gate layer and the first conductive structure, thereby improving the performance of the device.

[0040] In order to make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0041] Figures 2 to 4 is a structure schematic diagram of each step of the semiconductor structure forming method of an embodiment of the present application.

[0042] Please refer to Figure 2A substrate 201 is provided, which includes a base (not labeled in the figure), a fin (not labeled in the figure) on the base, and an isolation structure (not labeled in the figure) on the fin sidewall, and the top surface of the isolation structure is lower than the top surface of the fin.

[0043] In the embodiment, the material of the base is silicon.

[0044] In other embodiments, the material of the base includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0045] In the embodiment, the material of the fin is silicon. In other embodiments, the material of the fin can include silicon or germanium silicon, or a combination of one or both.

[0046] Subsequently, a first dielectric layer and an initial gate structure in the first dielectric layer are formed on the substrate, the initial gate structure crosses the fin and is located on part of the fin sidewall and top surface, the initial gate structure includes a gate layer, an initial gate dielectric layer on the sidewall surface and bottom of the gate layer, and a first sidewall and a second sidewall between the sidewall of the initial gate structure and the first dielectric layer, the first sidewall is between the sidewall of the initial gate dielectric layer and the second sidewall; a first conductive structure is formed in the first dielectric layer, and the first conductive structure is located on the substrate surface on both sides of the gate structure.

[0047] Specifically, the first conductive structure is located on the source / drain layer surface in the substrate on both sides of the gate structure. The formation method of the first conductive structure, the initial gate structure, and the source / drain layer, please continue to refer to Figure 2 , and refer to Figure 3 .

[0048] Please continue to refer to Figure 2Before forming the first dielectric layer (not shown in the figure), a dummy gate structure (not shown in the figure) is formed on part of the substrate 201, a first sidewall 204 and a second sidewall 207 are formed on sidewalls of the dummy gate structure, and the first sidewall 204 is between the dummy gate structure and the second sidewall 207. The dummy gate structure spans the fin and is on part of the sidewalls and top surface of the fin. A source-drain layer 206 is formed in the fin on both sides of the dummy gate structure. After forming the source-drain layer 206, a first dielectric layer (not shown in the figure) is formed on the substrate 201, and the first dielectric layer is on sidewalls of the dummy gate structure and exposes the top surface of the dummy gate structure. The dummy gate structure is removed, and a gate opening (not shown in the figure) is formed in the first dielectric layer. The initial gate dielectric layer 203 and the gate electrode layer 202 on the surface of the initial gate dielectric layer are formed in the gate opening. A first opening (not shown in the figure) is formed in the first dielectric layer, and the first opening exposes part of the surface of the source-drain layer 206. The first conductive structure 205 is formed in the first opening.

[0049] The method for forming the source-drain layer 206 includes: forming a trench (not shown in the figure) in the fin on both sides of the dummy gate structure by taking the dummy gate structure as a mask. The source-drain layer 206 is formed in the trench. Specifically, the process of forming the trench also takes the first sidewall 204 and the second sidewall 207 as masks.

[0050] The material of the initial gate dielectric layer 203 includes a high-K dielectric material. The high-K dielectric material has a dielectric constant greater than 3.9, and the high-K dielectric material includes hafnium oxide. In this embodiment, the material of the initial gate dielectric layer 203 is hafnium oxide. The initial gate dielectric layer 203 is used to form a gate dielectric layer.

[0051] The material of the gate electrode layer 202 includes a metal, and the metal includes copper, aluminum, or tungsten. In this embodiment, the material of the gate electrode layer 202 is tungsten.

[0052] The material of the first sidewall 204 is different from the material of the second sidewall 207. The second sidewall 207 is used to protect the interlayer dielectric layer 201 from being damaged by etching during the etching process of the first sidewall 204. During the subsequent etching process of the first sidewall 204, an etching process with a relatively large selectivity of the first sidewall 204 to the second sidewall 207 can be used to reduce the etching damage to the second sidewall 207.

[0053] The material of the second sidewall 207 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second sidewall 207 is silicon nitride.

[0054] The material of the first sidewall 204 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first sidewall 204 is silicon oxide.

[0055] The source-drain layer 206 has doped ions, which are of N-type or P-type; the N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron-fluorine ions, or indium ions.

[0056] Please refer to Figure 3 The initial gate dielectric layer 203 and the first sidewall 204 are etched to form a first recess 208 between the first conductive structure 205 and the gate layer 202, which exposes the sidewall of the gate layer 202, and the initial gate dielectric layer 203 at the bottom of the gate layer 202 forms a gate dielectric layer 209, and the initial gate structure forms a gate structure.

[0057] The depth-to-width ratio of the first recess 208 ranges from 2:1 to 10:1.

[0058] The initial gate dielectric layer 203 is etched to remove the initial gate dielectric layer 203 on the sidewall of the gate layer 202, thereby reducing the parasitic capacitance between the gate layer 202 and the first conductive structure 205.

[0059] In this embodiment, the gate dielectric layer 209 also includes a portion of the initial gate dielectric layer on the sidewall of the gate layer 202. The first sidewall 204 is etched to form a protective layer 210. The protective layer 210 retains a small amount of the initial gate dielectric layer 203 on the sidewall of the gate layer 202 to reduce the damage to the gate dielectric layer 209 caused by over-etching, thereby improving the performance of the gate dielectric layer 209.

[0060] In this embodiment, the initial gate dielectric layer 203 and the first sidewall 204 can be etched in the same process. Specifically, the material of the initial gate dielectric layer 203 is hafnium oxide, and the material of the first sidewall 204 is silicon oxide, which can be etched by a hydrofluoric acid solution to form the first recess 208.

[0061] In another embodiment, the first sidewall can be etched first, and then the initial gate dielectric layer can be etched.

[0062] Please refer to Figure 4 A second dielectric layer 211 is formed on the surface of the first dielectric layer and the gate structure, which seals the top of the first recess 208 and forms an air sidewall 212 between the first conductive structure 205 and the gate layer 202.

[0063] Specifically, the second dielectric layer 211 is also located on top surfaces of the second sidewall 207 and the first conductive structure 205.

[0064] The forming process of the second dielectric layer 211 includes a plasma enhanced chemical vapor deposition process.

[0065] In the embodiment, the process parameters for forming the second dielectric layer 211 include: the reaction gas includes a mixed gas of silane, nitrogen, oxygen and nitrous oxide; the gas flow ranges from 10 standard milliliters per minute to 30000 standard milliliters per minute; the pressure ranges from 0.5 Torr to 20 Torr; and the power ranges from 100 watts to 2000 watts. The reaction gas of the deposition process can be preferentially deposited on top of the first recess 208, so as to seal the first recess 208 into a sealed cavity 212.

[0066] The material of the second dielectric layer 211 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0067] So far, the air sidewall 212 is formed between the first conductive structure 205 and the gate layer 202, the air sidewall 212 has a small dielectric constant, is used for isolating the gate layer 202 from the first conductive structure 205, can reduce the parasitic capacitance between the gate layer 202 and the first conductive structure 205, and thus improves the performance of the device.

[0068] Figures 5 to 8 is a structure schematic diagram of each step of a forming method of a semiconductor structure of another embodiment of the present application.

[0069] Please continue to refer to Figure 2 on the basis of Figure 5 Before forming the first recess, a third dielectric layer 301 is formed on the first dielectric layer, the initial gate structure and the surface of the first conductive structure 205; and a second recess 302 is formed in the third dielectric layer 301, and the second recess 302 exposes the top surface of the initial gate dielectric layer 203 and the first sidewall 204.

[0070] Specifically, the third dielectric layer 301 is also located on top surfaces of the first sidewall 204 and the second sidewall 207.

[0071] The material of the third dielectric layer 301 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0072] The second groove 302 is used to expose the initial gate dielectric layer 203 and the top surface of the first sidewall 204, so as to facilitate subsequent etching of the initial gate dielectric layer 203 and the first sidewall 204. Meanwhile, the third dielectric layer 301 can protect the surface of the gate structure and the first conductive structure 205 during the etching process.

[0073] Subsequently, the initial gate dielectric layer 203 and the first sidewall 204 are etched to form a first groove between the first conductive structure 205 and the gate layer 202, and the first groove exposes the sidewall of the gate layer 202, so that the initial gate dielectric layer at the bottom of the gate layer 202 forms a gate dielectric layer.

[0074] In this embodiment, the first groove is formed by a two-step etching process, i.e., the first sidewall 204 is etched first, and then the initial gate dielectric layer 203 is etched. In other embodiments, the initial gate dielectric layer and the first sidewall can be etched and removed in the same process.

[0075] In this embodiment, the method for forming the first groove is described in detail in Figures 6 to 7 .

[0076] Please refer to Figure 6 , the first sidewall 204 is etched to a target depth, and the remaining first sidewall 204 forms a protection layer 303.

[0077] In this embodiment, the material of the first sidewall 204 is silicon nitride. In this embodiment, the material of the second sidewall 207 is silicon carbon nitride. In order to avoid the influence of the etching process of the first sidewall 204 on the second sidewall 207, a process with a large selectivity ratio for the first sidewall 204 and the second sidewall 207 can be selected during the etching process of the first sidewall 204. In this embodiment, the first sidewall 204 can be etched by using a phosphoric acid solution.

[0078] The protection layer 303 is used to protect the subsequently formed gate dielectric layer from damage during the etching process, which is beneficial to improve the gate leakage current of the formed device and improve the performance of the device.

[0079] Please refer to Figure 7 , after the formation of the protection layer 303, the initial gate dielectric layer 203 is etched.

[0080] In this embodiment, the material of the initial gate dielectric layer 203 is hafnium oxide. The initial gate dielectric layer 203 can be etched by using a hydrofluoric acid solution.

[0081] Etching the initial gate dielectric layer 203 and the first sidewall 204, a first recess 304 is formed between the first conductive structure 205 and the gate layer 202, the first recess 304 exposes the sidewall of the gate layer 202, the initial gate dielectric layer 203 at the bottom of the gate layer 202 forms a gate dielectric layer 305, and the initial gate structure forms a gate structure.

[0082] The first recess 304 is subsequently used to form an air sidewall.

[0083] Etching the initial gate dielectric layer 203 removes the initial gate dielectric layer 203 on the sidewall of the gate layer 202, reducing the parasitic capacitance between the gate layer 202 and the first conductive structure 205.

[0084] Please refer to Figure 8 A second dielectric layer 305 is formed on the surface of the first dielectric layer and the gate structure, the second dielectric layer 305 seals the top of the first recess 304, and an air sidewall 306 is formed between the first conductive structure 205 and the gate layer 202.

[0085] Specifically, the second dielectric layer 305 is also located in the second recess 302.

[0086] The material of the second dielectric layer 305 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0087] So far, the air sidewall 306 is formed between the first conductive structure 205 and the gate layer 202, which has a smaller dielectric constant and is used to isolate the gate layer 202 from the first conductive structure 205, thereby reducing the parasitic capacitance between the gate layer 202 and the first conductive structure 205 and improving the performance of the device.

[0088] Figures 9 to 13 is a structure diagram of each step of the method for forming a semiconductor structure according to another embodiment of the present application.

[0089] Please refer to Figure 2 on the basis of Figure 9 Before forming the first recess, a third dielectric layer 401 is formed on the surface of the first dielectric layer, the initial gate structure, and the first conductive structure 205.

[0090] Specifically, the third dielectric layer 401 is also located on the top surface of the first sidewall 204 and the second sidewall 207.

[0091] The material of the third dielectric layer 401 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0092] Referring to Figure 10 A second conductive structure 402 is formed in the third dielectric layer 401 and located on the surface of the first conductive structure 205. A third conductive structure 403 is formed in the third dielectric layer 401 and located on the surface of the gate layer 202.

[0093] Referring to Figure 11 The third dielectric layer 401 is removed to form a second recess 404, which exposes the top surface of the initial gate dielectric layer 203 and the first sidewall 204.

[0094] The second recess 404 exposes the top surface of the initial gate dielectric layer 203 and the first sidewall 204, which prepares for subsequent etching of the initial gate dielectric layer 203 and the first sidewall 204.

[0095] Referring to Figure 12 The initial gate dielectric layer 203 and the first sidewall 204 are etched to form a first recess 405 between the first conductive structure 205 and the gate layer 202, which exposes the sidewall of the gate layer 202. The initial gate dielectric layer 203 at the bottom of the gate layer 202 forms a gate dielectric layer 406, and the initial gate structure forms a gate structure.

[0096] The depth-to-width ratio of the first recess 208 ranges from 2:1 to 10:1.

[0097] In this embodiment, the initial gate dielectric layer 203 and the first sidewall 204 can be etched and removed in the same process. Specifically, the material of the initial gate dielectric layer 203 is hafnium oxide, and the material of the first sidewall 204 is silicon oxide. Hydrofluoric acid solution can be used for etching to form the first recess 208.

[0098] In another embodiment, the first sidewall can be etched first, and then the initial gate dielectric layer can be etched.

[0099] Referring to Figure 13 A second dielectric layer 408 is formed on the surface of the first dielectric layer and the gate structure, which seals the top of the first recess 405 and forms an air sidewall 409 between the first conductive structure 205 and the gate layer 202.

[0100] In this embodiment, the second dielectric layer 408 is also located in the second recess 404.

[0101] In this embodiment, the air sidewall 409 is also located between the second conductive structure 402 and the third conductive structure 403.

[0102] At this point, the air side wall 409 is formed between the first conductive structure 205 and the gate layer 202, which has a small dielectric constant for isolating the gate layer 202 from the first conductive structure 205, and can reduce the parasitic capacitance between the gate layer 202 and the first conductive structure 205, thereby improving the performance of the device.

[0103] Correspondingly, an embodiment of the present application also provides a semiconductor structure formed by the above method, please continue to refer to Figure 13 , the substrate 201 includes a base (not labeled in the figure), a fin (not labeled in the figure) on the base, and an isolation structure (not labeled in the figure) on the fin side wall, and the top surface of the isolation structure is lower than the top surface of the fin; a first dielectric layer (not labeled in the figure) on the substrate 201 and a gate structure in the first dielectric layer, the gate structure spans the fin, and is located on part of the fin side wall and the top surface, the gate structure includes a gate layer 202, a gate dielectric layer 407 at the bottom of the gate layer, an air side wall 409 and a second side wall 207 on the side wall of the gate layer 202, the air side wall 409 is located between the gate layer 202 and the second side wall 207, and the side wall of the gate layer 202 and the second side wall 207 are exposed; a source-drain layer 206 in the fin on both sides of the gate structure; a first conductive structure 205 in the first dielectric layer, the first conductive structure 205 is located on the surface of the source-drain layer 206; a second dielectric layer 408 on the surface of the first dielectric layer and the gate structure, the second dielectric layer 408 is located on the top of the air side wall 409, and the air side wall 409 is also located between the first conductive structure 205 and the gate layer 202.

[0104] The gate structure includes a gate layer 202 and a gate dielectric layer 407 at the bottom of the gate layer 202, and the side wall of the gate layer 202 of the semiconductor structure has no gate dielectric layer, thereby reducing the parasitic capacitance between the gate layer 202 and the first conductive structure 205; on the other hand, the air side wall 409 has a small dielectric constant for isolating the gate layer 202 from the first conductive structure 205, which can reduce the parasitic capacitance between the gate layer 202 and the first conductive structure 205, thereby improving the performance of the device.

[0105] In this embodiment, the gate dielectric layer 407 also includes a part of the initial gate dielectric layer on the side wall of the gate layer 202. In another embodiment, the side wall of the gate layer 202 has no initial gate dielectric layer. The side wall of the gate layer of the semiconductor structure has no gate dielectric layer or only a small amount of initial gate dielectric layer, thereby reducing the parasitic capacitance between the gate layer and the first conductive structure.

[0106] In this embodiment, the semiconductor structure further comprises a second conductive structure 402 on the surface of the first conductive structure 205 and a third conductive structure 403 on the surface of the gate layer 202, and the air spacer 409 is further between the second conductive structure 402 and the third conductive structure 403.

[0107] Although the present application has been disclosed with reference to the above embodiments, it is not intended to limit the present application. Any modifications and changes can be made by any person skilled in the art without departing from the spirit and scope of the present application. The scope of protection of the present application should be defined by the appended claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate comprising a base, a fin on the base, and an isolation structure on the fin sidewall, the isolation structure top surface being lower than the fin top surface; a first dielectric layer on the substrate and a gate structure in the first dielectric layer, the gate structure spanning the fin and being on part of the fin sidewall and top surface, the gate structure comprising a gate layer, a gate dielectric layer on the gate layer bottom, the gate dielectric layer further comprising part of the initial gate dielectric layer on the gate layer sidewall, an air spacer on the gate layer sidewall with a second spacer between the gate layer and the second spacer, the air spacer exposing the gate layer sidewall and the second spacer; a protective layer on the air spacer bottom and between the gate dielectric layer and the second spacer, the protective layer material being different from the second spacer material; a source-drain layer in the fin on both sides of the gate structure; a first conductive structure in the first dielectric layer, the first conductive structure being on the source-drain layer surface; a second dielectric layer on the first dielectric layer and the gate structure surface, the second dielectric layer being on the air spacer top, and the air spacer being further between the first conductive structure and the gate layer.

2. The semiconductor structure of claim 1, wherein, Further comprising a second conductive structure on the first conductive structure surface and a third conductive structure on the gate layer surface, the air spacer being further between the second conductive structure and the third conductive structure.

3. A method of forming a semiconductor structure, characterized by, Comprising: providing a substrate comprising a base, a fin on the base, and an isolation structure on the fin sidewall, the isolation structure top surface being lower than the fin top surface; forming a first dielectric layer on the substrate and an initial gate structure in the first dielectric layer, the initial gate structure spanning the fin and being on part of the fin sidewall and top surface, the initial gate structure comprising a gate layer, an initial gate dielectric layer on the gate layer sidewall surface and bottom, and a first spacer and a second spacer between the initial gate structure sidewall and the first dielectric layer, the first spacer being between the initial gate dielectric layer sidewall and the second spacer, the first spacer material being different from the second spacer material; forming a first conductive structure in the first dielectric layer, the first conductive structure being on the substrate surface on both sides of the gate structure; etching the initial gate dielectric layer and the first spacer to a target depth, forming a first recess between the first conductive structure and the gate layer, the first recess exposing the gate layer sidewall, a protective layer being formed by the remaining first spacer, a gate dielectric layer being formed by the initial gate dielectric layer on the gate layer bottom and part of the initial gate dielectric layer on the gate layer sidewall, and a gate structure being formed by the initial gate structure; forming a second dielectric layer on the first dielectric layer and the gate structure surface, the second dielectric layer closing the first recess top, and forming an air spacer between the first conductive structure and the gate layer.

4. The method of forming a semiconductor structure of claim 3, wherein, After the protective layer is formed, the initial gate dielectric layer is etched.

5. The method of forming a semiconductor structure of claim 3, wherein, The first conductive structure is located on the surface of the source-drain layer in the substrate on both sides of the gate structure; the forming method of the first conductive structure, the initial gate structure and the source-drain layer comprises: before the first dielectric layer is formed, a dummy gate structure, a first sidewall located on the sidewall of the dummy gate structure and a second sidewall are formed on part of the substrate, the first sidewall is located between the dummy gate structure and the second sidewall, the dummy gate structure spans the fin and is located on part of the sidewall and the top surface of the fin; a source-drain layer is formed in the fin on both sides of the dummy gate structure; after the source-drain layer is formed, a first dielectric layer is formed on the substrate, the first dielectric layer is located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate structure; the dummy gate structure is removed to form a gate opening in the first dielectric layer; the initial gate dielectric layer and the gate layer located on the surface of the initial gate dielectric layer are formed in the gate opening; a first opening is formed in the first dielectric layer, the first opening exposes part of the surface of the source-drain layer; the first conductive structure is formed in the first opening.

6. The method of forming a semiconductor structure of claim 5, wherein, Before the first recess is formed, it comprises: forming a third dielectric layer on the surface of the first dielectric layer, the initial gate structure and the first conductive structure; forming a second recess in the third dielectric layer, the second recess exposes the top surface of the initial gate dielectric layer and the first sidewall.

7. The method of forming a semiconductor structure of claim 6, wherein, The material of the third dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

8. The method of forming a semiconductor structure of claim 5, wherein, Before the first recess is formed, it comprises: forming a third dielectric layer on the surface of the first dielectric layer, the initial gate structure and the first conductive structure; forming a second conductive structure in the third dielectric layer, the second conductive structure is located on the surface of the first conductive structure; forming a third conductive structure in the third dielectric layer, the third conductive structure is located on the surface of the gate layer; removing the third dielectric layer to form a second recess, the second recess exposes the top surface of the initial gate dielectric layer and the first sidewall.

9. The method of forming a semiconductor structure of claim 8, wherein, The air sidewall is also located between the second conductive structure and the third conductive structure.

10. The method of forming a semiconductor structure of claim 8, wherein, The material of the third dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

11. The method of forming a semiconductor structure of claim 3, wherein, The material of the second sidewall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride; the material of the first sidewall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

12. The method of forming a semiconductor structure of claim 3, wherein, The material of the gate dielectric layer comprises a high-K dielectric material; the material of the gate layer comprises a metal.

13. The method of forming a semiconductor structure of claim 3, wherein, The forming process of the second dielectric layer comprises a plasma enhanced chemical vapor deposition process.

14. The method of forming a semiconductor structure of claim 13, wherein, The material of the second dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

15. The method of forming a semiconductor structure of claim 3, wherein, The aspect ratio of the first recess ranges from 2:1 to 10:1.

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