A single-ended input differential output burst-mode transimpedance amplifier front-end circuit

Abstract

This invention relates to a front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier. It includes: a first high-speed inverting amplifier unit and a feedback resistor Rf, used to convert a high-speed input current signal into a high-speed voltage signal; a high-speed non-inverting amplifier unit, connected to the voltage output terminal of the first high-speed inverting amplifier unit and used to provide the first output voltage signal in the differential output signal; a second high-speed inverting amplifier unit, used to invert the phase of the output signal of the first high-speed inverting amplifier unit and provide the second output voltage signal in the differential output signal; and a differential output DC voltage monitoring and feedback control unit (21), used to detect the DC quantity and amplitude difference between the first and second output voltage signals and thereby make the DC quantity and amplitude of the first and second output voltage signals converge. Fast burst response can be achieved without requiring a matching RESET signal from the OLT optical module.

Description

TECHNICAL FIELD

[0001] The present application relates to the fields of semiconductor integrated circuit technology and optical communication technology, in particular to a single-ended input and differential output burst-mode transimpedance amplifier front-end circuit. BACKGROUND

[0002] At present, the home broadband has completely entered the optical fiber era of hundreds of Mbps from the Kbps rate copper wire era. With the rise of new broadband services in the future, the domestic optical access network (Optcial Access Network) will step from the current 10G G / EPON to the next generation 50G PON, and the evolution and upgrade of the communication network will also increase the single rate of the optical module from 10G to 25G / 50G rate level. At the same time, the optical receiving and transmitting optical / electric chips used in the optical module also need to be updated in rate.

[0003] In the optical access network, the downstream service data is transmitted in a broadcast continuous form; and the upstream service data is transmitted in a time division multiplexing burst mode. For the optical signal receiving electric chip (such as a transimpedance amplifier TIA) on the OLT (optical line terminal) side, since the transmission signal is an upstream burst signal (a plurality of ONUs transmit the upstream signal in a time division manner), the transimpedance amplifier TIA is required to quickly respond to the upstream burst signal, that is, a burst-mode transimpedance amplifier (BM-TIA, Burst-Mode Transimpedance Amplifier), and the burst response time thereof generally needs to be less than 1us to avoid the influence of different ONU upstream signals on each other and the occurrence of data transmission faults. However, the current burst-mode transimpedance amplifier product cannot meet the burst response time requirement when working independently without the coordination of an external control signal.

[0004] In the related art, before the arrival of each burst signal data packet, an OLT optical module internal MCU provides a RESET signal to control the transimpedance amplifier to quickly complete the reset operation, thereby reducing the burst response time of the burst-mode transimpedance amplifier to meet the requirement. In view of the case that the burst response time of the current burst-mode transimpedance amplifier product is too large when working independently, how to avoid the OLT optical module to provide a matching RESET signal while realizing the fast burst response function is a technical problem to be solved by the present application. SUMMARY

[0005] The embodiment of the present application provides a single-ended input and differential output burst-mode transimpedance amplifier front-end circuit, which has solved the above technical problems.

[0006] In one aspect, the present application provides a single-ended input and differential output burst-mode trans-impedance amplifier front-end circuit, characterized in that it comprises:

[0007] a first high-speed inverting amplification unit and a feedback resistor Rf for converting a high-speed input current signal into a high-speed voltage signal;

[0008] a high-speed non-inverting amplification unit in communication with the voltage output end of the first high-speed inverting amplification unit and for providing a first output voltage signal in a differential output signal;

[0009] a second high-speed inverting amplification unit for inverting the phase of the output signal of the first high-speed inverting amplification unit and providing a second output voltage signal in the differential output signal;

[0010] a differential output DC voltage monitoring and feedback control unit (21) for detecting the DC amount and amplitude difference of the first output voltage signal and the second output voltage signal and outputting a feedback signal accordingly;

[0011] the feedback signal is used to adjust the DC amount and voltage amplitude of the first output voltage signal and the second output voltage signal through multiple negative feedback loops so that the DC amount and voltage amplitude of the first output voltage signal and the second output voltage signal are both converged.

[0012] In some embodiments, the first high-speed inverting amplification unit comprises a transistor Q (21), a transistor Q (22), a resistor R (21), a resistor R (22), an NMOS tube MN (21), and a bias current source Ibias (21);

[0013] the base of the transistor Q (21) is connected to the input port IN and the drain of the NMOS tube MN (22), the emitter is grounded, and the collector is connected to the first port of the resistor R (21) and the base of the transistor Q (22);

[0014] the emitter of the transistor Q (22) is connected to the second port of the feedback resistor Rf and the current source port of the bias current source Ibias (21), and the collector is connected to the first port of the resistor R (22); the emitter of the transistor Q (22) is the voltage output end of the first high-speed inverting amplification unit;

[0015] the second port of the resistor R (21) and the second port of the resistor R (22) are both connected to a voltage source VCC1, the first port of the feedback resistor Rf is connected to the input port IN, and the other port of the bias current source Ibias (21) is grounded;

[0016] the source of the NMOS tube MN (21) is grounded.

[0017] In some embodiments, the high-speed in-phase amplifier unit includes a high-speed diode SBD (21) and a resistor R (23);

[0018] The anode of the high-speed diode SBD (21) is the first output voltage port mTIAoutp in the differential output voltage port, and is connected to the first port of the resistor R (23) and the inverting input port inn of the differential output DC voltage monitoring and feedback control unit (21);

[0019] The cathode of the high-speed diode SBD(21) is the voltage input terminal of the high-speed non-inverting amplifier unit, which is connected to the voltage output terminal of the first high-speed inverting amplifier unit.

[0020] The second port of the resistor R (23) is connected to the source of the NMOS transistor M (23).

[0021] In some embodiments, the second high-speed inverting amplifier unit includes:

[0022] Transistor Q(23), resistor R(24), resistor R(25), NMOS transistor MN(22), high-speed diode SBD(22) and high-speed diode SBD(23);

[0023] The base of the transistor Q(23) is the voltage input terminal of the second high-speed inverting amplifier unit, and it is connected to the voltage output terminal of the first high-speed inverting amplifier unit.

[0024] The collector of the transistor Q (23) is the second output voltage port mTIAoutn in the differential output voltage port, and is connected to the first port of the resistor R (24) and the non-inverting input port inp of the differential output DC voltage monitoring and feedback control unit (21). The emitter of the transistor Q (23) is connected to the first port of the resistor R (25) and the drain of the NMOS transistor MN (22).

[0025] The second port of the resistor R (24) is connected to the cathode of the high-speed diode SBD (22);

[0026] The anode of the high-speed diode SBD(22) is connected to the cathode of the high-speed diode SBD(23);

[0027] The anode of the high-speed diode SBD(23) is connected to the source of the NMOS transistor M(23);

[0028] The second port of the resistor R(25) is grounded;

[0029] The source of the NMOS transistor MN(22) is grounded.

[0030] In some embodiments, the differential output DC voltage monitoring and feedback control unit (21) forms a first negative feedback loop for the first output voltage signal and the second output voltage signal together with a low-pass filter, an NMOS transistor MN (21), a first high-speed inverting amplifier unit, the feedback resistor Rf, the high-speed non-inverting amplifier unit and the second high-speed inverting amplifier unit;

[0031] The differential output DC voltage monitoring and feedback control unit (21), together with the low-pass filter, the NMOS transistor MN (22), the high-speed in-phase amplifier unit and the second high-speed in-phase amplifier unit, form a second negative feedback loop for the first output voltage signal and the second output voltage signal;

[0032] The first negative feedback loop and the second negative feedback loop are used to adjust the DC values ​​of the first output voltage signal and the second output voltage signal according to the feedback signal so that the DC values ​​of the first output voltage signal and the second output voltage signal are similar.

[0033] In some embodiments, a low-pass filter (21), an NMOS transistor MN (21), and an NMOS transistor MN (22) are also included;

[0034] The first output port of the differential output DC voltage monitoring and feedback control unit (21) is connected to the input of the low-pass filter (21);

[0035] The output of the low-pass filter (21) is the feedback control voltage VFB1, which is connected to the gate of NMOS transistor MN (21) and the gate of NMOS transistor MN (22).

[0036] In some embodiments, the differential output DC voltage monitoring and feedback control unit (21), the ultra-low bandwidth low-pass filter (22), the monitoring and digital feedback control and locking unit (21), and the digital adjustable regulator (21) form a third negative feedback loop for the first output voltage signal and the second output voltage signal. The third negative feedback loop is used to adjust the DC quantity of the first output voltage signal and the second output voltage signal according to the feedback signal so that the DC quantity of the first output voltage signal and the second output voltage signal converges.

[0037] The 3dB bandwidth of the ultra-low bandwidth low-pass filter (22) is less than 10kHz;

[0038] The monitoring and digital feedback control and locking unit (21) is used to monitor the analog input voltage signal and convert the analog input voltage signal into a multi-bit digital output voltage signal according to the detection result;

[0039] The digitally adjustable regulator (21) finely adjusts its stable output DC voltage value using a multi-bit digital control voltage signal.

[0040] In some embodiments, it also includes an ultra-low bandwidth low-pass filter (22), a monitoring and digital feedback control and lockout unit (21), and a digitally adjustable regulator (21);

[0041] The second output port of the differential output DC voltage monitoring and feedback control unit (21) is connected to the input of the ultra-low bandwidth low-pass filter (22);

[0042] The output of the ultra-low bandwidth low-pass filter (22) is connected to the analog voltage signal VFB2, which is connected to the input of the monitoring and digital feedback control and locking unit (21).

[0043] The output of the monitoring and digital feedback control and locking unit (21) consists of four digital control voltage signals VFBreg1, VFBreg2, VFBreg3 and VFBreg4, and the four digital control voltage signals are respectively connected to the gates of the four MOS switches MN (211), MN (212), MN (213) and MN (214) inside the digital adjustable regulator (21).

[0044] In some embodiments, the differential output DC voltage monitoring and feedback control unit (21) forms a fourth negative feedback loop in the second high-speed inverting amplifier unit through a low-pass filter, a resistor and an NMOS transistor, and the fourth negative feedback loop is used to adjust the voltage amplitude of the second output voltage signal according to the feedback signal so that the voltage amplitude of the first output voltage signal and the second output voltage signal are similar.

[0045] In some embodiments, a resistor R (31), an NMOS transistor MN (31), and a low-pass filter M (23) are also included;

[0046] The first port of the resistor R (31) is connected to the base of the transistor Q (21) and the source or drain of the NMOS transistor MN (31), and its second port is connected to the collector of the transistor Q (21) and the drain or source of the NMOS transistor MN (31).

[0047] The third output port of the differential output DC voltage monitoring and feedback control unit (21) outputs a feedback control voltage VFB3 through the low-pass filter M (23). The feedback control voltage VFB3 is used to adjust the resistance value of the NMOS transistor MN (31) and the resistance value of the parallel unit composed of the resistor R (31) and the NMOS transistor MN (31) so that the voltage amplitude of the first output voltage signal and the second output voltage signal tend to be the same.

[0048] This invention provides a front-end circuit for a single-ended input differential output burst-mode transimpedance amplifier. It converts the input current signal into a pair of differential output voltage signals, transforming the current single-ended input single-ended output transimpedance amplifier front-end circuit structure into a single-ended input differential output transimpedance amplifier front-end circuit structure. Compared to current transimpedance amplifier structures, the circuit structure using the proposed single-ended input differential output burst-mode transimpedance amplifier front-end circuit not only achieves rapid burst response capability in its own structure, but its differential output voltage can also quickly follow changes in the input current in real time, eliminating the need for a matching RESET signal from the OLT optical module. Furthermore, it eliminates the need for a low-pass filter circuit and a single-ended to differential converter circuit, simplifying the transimpedance amplifier circuit structure and reducing its power consumption. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the transimpedance amplifier circuit structure in related technologies;

[0051] Figure 2 for Figure 1 The simulation results of the transimpedance amplifier circuit shown are illustrated in the diagram.

[0052] Figure 3 This is a schematic diagram of the front-end circuit of a single-ended input differential output burst mode transimpedance amplifier proposed in this invention.

[0053] Figure 4 This is a schematic diagram of the front-end circuit of a single-ended input differential output burst mode transimpedance amplifier proposed in this invention.

[0054] Figure 5 This is a schematic diagram of a transimpedance amplifier circuit structure that employs the single-ended input differential output burst mode transimpedance amplifier front-end circuit proposed in this invention.

[0055] Figure 6 yes Figure 5 The transimpedance amplifier shown uses Figure 2 The diagram shows the simulation results of the front-end circuit of a single-ended input differential output burst mode transimpedance amplifier.

[0056] Figure 7 yes Figure 5 The transimpedance amplifier shown uses Figure 3The diagram shows the simulation results of the front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] like Figure 1 As shown, a common transimpedance amplifier circuit typically includes a transimpedance amplifier front-end circuit, a low-pass filter composed of R11 and C11, a single-ended to differential amplifier, a differential amplifier, an output buffer stage, and a DC offset correction circuit. The transimpedance amplifier front-end circuit is a single-ended input, single-ended output structure, converting the input photocurrent signal IN into an output voltage signal OUTfront. The low-pass filter composed of R11 and C11 performs low-pass filtering on the OUTfront signal and outputs an average signal OUTfrontavg. The single-ended to differential amplifier converts a pair of input signals OUTfront and OUTfrontavg into a pair of differential output voltage signals. The differential amplifier amplifies the differential voltage signals output from the single-ended to differential amplifier. The output buffer stage performs impedance matching with external circuitry and outputs a pair of differential voltage signals OUTP and OUTN.

[0059] like Figure 2 As shown, Figure 1 The diagram shows a simulation result of a common transimpedance amplifier circuit. In this circuit, / R1 / PLUS represents the input current signal of the transimpedance amplifier, which is a burst signal with no signal for an initial period, followed by a longer period of random data signal. / OUTfront (solid line) represents the output port signal of the transimpedance amplifier's front-end circuit. / OUTfrontavg (dashed line) represents the average signal after low-pass filtering of the output port signal of the transimpedance amplifier's front-end circuit. / OUTP (dashed line) and / OUTN (solid line) represent a pair of differential output signals of the transimpedance amplifier. Figure 2It can be seen that after the arrival of a random data signal, / OUTfrontavg changes relatively slowly towards the mean of / OUTfront, taking approximately 500ns to approximately reach the mean state of / OUTfront. This slow process causes the pair of differential output signals / OUTP and / OUTN of the transimpedance amplifier to also take approximately 500ns to reach a stable state. This is also the reason for the relatively long burst response time of current burst-type transimpedance amplifiers.

[0060] like Figure 3 As shown, this embodiment of the invention provides a front-end circuit for a single-ended input differential output burst-mode transimpedance amplifier, which includes:

[0061] The first high-speed inverting amplifier unit and the feedback resistor Rf are used to convert the high-speed input current signal into a high-speed voltage signal.

[0062] A high-speed in-phase amplifier unit is connected to the voltage output terminal of the first high-speed in-phase amplifier unit and is used to provide the first output voltage signal in the differential output signal;

[0063] The second high-speed inverting amplifier unit is used to invert the phase of the output signal of the first high-speed inverting amplifier unit and provide a second output voltage signal in the differential output signal.

[0064] The differential output DC voltage monitoring and feedback control unit 21 is used to detect the DC quantity and amplitude difference between the first output voltage signal and the second output voltage signal and output a feedback signal accordingly.

[0065] The feedback signal is used to adjust the DC quantity and amplitude of the first output voltage signal and the second output voltage signal through multiple negative feedback loops so that the DC quantity and amplitude of the first output voltage signal and the second output voltage signal are similar.

[0066] This embodiment converts the input current signal into a pair of differential output voltage signals, transforming the current single-ended input, single-ended output transimpedance amplifier front-end circuit structure into a single-ended input, differential output transimpedance amplifier front-end circuit structure. Compared to the current transimpedance amplifier structure, the circuit structure of the single-ended input, differential output, burst-mode transimpedance amplifier front-end circuit proposed in this invention not only achieves fast burst response capability in its own structure, but its differential output voltage can also quickly follow the changes in input current in real time, eliminating the need for a matching RESET signal from the OLT optical module to complete the fast burst response. Furthermore, it eliminates the need for a low-pass filter circuit and a single-ended to differential converter circuit, simplifying the transimpedance amplifier circuit structure and reducing the power consumption of the transimpedance amplifier.

[0067] In some embodiments, the first high-speed inverting amplifier unit includes transistor Q21, transistor Q22, resistor R21, resistor R22, NMOS transistor MN21, and bias current source Ibias21;

[0068] The base of transistor Q21 is connected to both the input port IN and the drain of NMOS transistor MN22, its emitter is grounded, and its collector is connected to the first port of resistor R21 and the base of transistor Q22.

[0069] The emitter of transistor Q22 is connected to the second port of feedback resistor Rf and the current source port of bias current source Ibias21, and its collector is connected to the first port of resistor R22; the emitter of transistor Q22 is the voltage output terminal of the first high-speed inverting amplifier unit.

[0070] The second port of resistor R21 and the second port of resistor R22 are both connected to voltage source VCC1, the first port of feedback resistor Rf is connected to input port IN, and the other port of bias current source Ibias21 is grounded.

[0071] The source of the NMOS transistor MN21 is grounded.

[0072] It is understandable that the emitter of transistor Q22 is the voltage output terminal of the first high-speed inverting amplifier unit; the cathode of high-speed diode SBD21 is the voltage input terminal of the high-speed non-inverting amplifier unit, which is connected to the voltage output terminal of the first high-speed inverting amplifier unit (the emitter of transistor Q22).

[0073] In some embodiments, the high-speed non-inverting amplifier unit includes a high-speed diode SBD21 and a resistor R23;

[0074] The anode of the high-speed diode SBD21 is the first output voltage port mTIAoutp in the differential output voltage port, and is connected to the first port of the resistor R23 and the inverting input port inn of the differential output DC voltage monitoring and feedback control unit 21;

[0075] The cathode of the high-speed diode SBD21 is the voltage input terminal of the high-speed non-inverting amplifier unit, which is connected to the voltage output terminal of the first high-speed inverting amplifier unit.

[0076] The second port of resistor R23 is connected to the source of NMOS transistor M23.

[0077] In some embodiments, the second high-speed inverting amplifier unit includes:

[0078] Transistor Q23, resistor R24, resistor R25, NMOS transistor MN22, high-speed diode SBD22 and high-speed diode SBD23;

[0079] The base of the transistor Q23 is the voltage input terminal of the second high-speed inverting amplifier unit, and it is connected to the voltage output terminal of the first high-speed inverting amplifier unit.

[0080] The collector of transistor Q23 is the second output voltage port mTIAoutn in the differential output voltage port, and is connected to the first port of resistor R24 ​​and the non-inverting input port inp of the differential output DC voltage monitoring and feedback control unit 21. The emitter of transistor Q23 is connected to the first port of resistor R25 and the drain of NMOS transistor MN22.

[0081] The second port of the resistor R24 ​​is connected to the cathode of the high-speed diode SBD22;

[0082] The anode of the high-speed diode SBD22 is connected to the cathode of the high-speed diode SBD23;

[0083] The anode of the high-speed diode SBD23 is connected to the source of the NMOS transistor M23;

[0084] The second port of resistor R25 is grounded;

[0085] The source of the NMOS transistor MN22 is grounded;

[0086] In some embodiments, the differential output DC voltage monitoring and feedback control unit 21, together with the low-pass filter, NMOS transistor MN21, first high-speed inverting amplifier unit, feedback resistor Rf, high-speed non-inverting amplifier unit and second high-speed inverting amplifier unit, forms a first negative feedback loop for the first output voltage signal and the second output voltage signal.

[0087] The differential output DC voltage monitoring and feedback control unit 21, together with the low-pass filter, NMOS transistor MN22, the high-speed non-inverting amplifier unit, and the second high-speed inverting amplifier unit, forms a second negative feedback loop for the first output voltage signal and the second output voltage signal;

[0088] The first negative feedback loop and the second negative feedback loop are used to adjust the DC values ​​of the first output voltage signal and the second output voltage signal according to the feedback signal so that the DC values ​​of the first output voltage signal and the second output voltage signal are similar.

[0089] In some embodiments, a front-end circuit of a single-ended input differential output burst mode transimpedance amplifier further includes a low-pass filter 21, an NMOS transistor MN21, and an NMOS transistor MN22;

[0090] The first output port of the differential output DC voltage monitoring and feedback control unit 21 is connected to the input terminal of the low-pass filter 21;

[0091] The output of the low-pass filter 21 is the feedback control voltage VFB1, which is simultaneously connected to the gate of NMOS transistor MN21 and the gate of NMOS transistor MN22.

[0092] In some embodiments, the differential output DC voltage monitoring and feedback control unit 21, the ultra-low bandwidth low-pass filter 22, the monitoring and digital feedback control and locking unit 21, and the digital adjustable regulator 21 form a third negative feedback loop for the first output voltage signal and the second output voltage signal. The third negative feedback loop is used to adjust the DC quantity of the first output voltage signal and the second output voltage signal according to the feedback signal so that the DC quantity of the first output voltage signal and the second output voltage signal converges.

[0093] The 3dB bandwidth of the ultra-low bandwidth low-pass filter 22 is less than 10kHz.

[0094] The monitoring and digital feedback control and locking unit 21 is used to monitor the analog input voltage signal and convert the analog input voltage signal into a multi-bit digital output voltage signal according to the detection result.

[0095] The digitally adjustable voltage regulator 21 uses a multi-bit digital control voltage signal to finely adjust its stable output DC voltage value.

[0096] In some embodiments, a single-ended input differential output burst-mode transimpedance amplifier front-end circuit also includes an ultra-low bandwidth low-pass filter 22, a monitoring and digital feedback control and lock-in unit 21, and a digitally adjustable regulator 21.

[0097] The second output port of the differential output DC voltage monitoring and feedback control unit 21 is connected to the input terminal of the ultra-low bandwidth low-pass filter 22;

[0098] The output of the ultra-low bandwidth low-pass filter 22, analog voltage signal VFB2, is connected to the input of the monitoring and digital feedback control and locking unit 21.

[0099] The output of the monitoring and digital feedback control and locking unit 21 consists of four digital control voltage signals VFBreg1, VFBreg2, VFBreg3 and VFBreg4, and the four digital control voltage signals are respectively connected to the gates of the four MOS switches MN211, MN212, MN213 and MN214 inside the digital adjustable regulator 21.

[0100] Understandably, the monitoring and digital feedback control and locking unit 21 monitors the analog voltage signal VFB2 and converts the detection result of VFB2 into four digital signals VFBreg1, VFBreg2, VFBreg3 and VFBreg4. These four digital signals VFBreg1, VFBreg2, VFBreg3 and VFBreg4 are then output to the digital adjustable regulator 21. The digital adjustable regulator 21 adjusts the output voltage (the output terminal is connected to the gate of the NMOS transistor MN23) according to the four input digital signals VFBreg1, VFBreg2, VFBreg3 and VFBreg4.

[0101] In some embodiments, the differential output DC voltage monitoring and feedback control unit 21 forms a fourth negative feedback loop in the second high-speed inverting amplifier unit through a low-pass filter, a resistor and an NMOS transistor, and the fourth negative feedback loop is used to adjust the voltage amplitude of the second output voltage signal according to the feedback signal so that the voltage amplitude of the first output voltage signal and the second output voltage signal are similar.

[0102] In some embodiments, a front-end circuit for a single-ended input differential output burst-mode transimpedance amplifier is characterized by further including a resistor R31, an NMOS transistor MN31, and a low-pass filter M23.

[0103] The first port of resistor R31 is connected to the base of transistor Q21 and the source or drain of NMOS transistor MN31, and its second port is connected to the collector of transistor Q21 and the drain or source of NMOS transistor MN31.

[0104] The third output port of the differential output DC voltage monitoring and feedback control unit 21 outputs a feedback control voltage VFB3 through the low-pass filter M23. The feedback control voltage VFB3 is used to adjust the resistance value of the NMOS transistor MN31 and the resistance value of the parallel unit composed of the resistor R31 and the NMOS transistor MN31, so that the voltage amplitude of the first output voltage signal and the second output voltage signal tend to be the same.

[0105] like Figure 3As shown in a specific embodiment, the front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier proposed in this invention includes: transistors Q21, Q22, and Q23; resistors R21, R22, R23, R24, and R25; high-speed diodes SBD21, SBD22, and SBD23; NMOS transistors MN21, MN22, and MN23; bias current source Ibias21; differential output DC voltage monitoring and feedback control unit 21; low-pass filter 21; ultra-low bandwidth low-pass filter 22; monitoring and digital feedback control and lock-in unit 21; bandgap reference 21; and digitally adjustable regulator 21 (containing resistors R210, R211, R212, R213, and R214, and NMOS transistors MN211, MN212, MN213, and MN214).

[0106] The connection methods for each device are as follows: the input port IN is connected to the base of transistor Q21, the first port of feedback resistor Rf, and the drain of NMOS transistor MN21; the emitter of transistor Q21 is grounded; the collector of transistor Q21 is connected to the first port of resistor R21 and the base of transistor Q22; the second port of resistor R21 is connected to voltage source VCC1; the emitter of transistor Q22 is connected to the second port of feedback resistor Rf, the current source port of bias current source Ibias21, the base of transistor Q23, and the cathode of high-speed diode SBD21; the transistor... The collector of transistor Q22 is connected to the first port of resistor R22; the second port of resistor R22 is connected to voltage source VCC1; the other port of bias current source Ibias21 is grounded; the source of NMOS transistor MN21 is grounded; the anode of high-speed diode SBD21 is the first output voltage port mTIAoutp of a pair of differential output voltage ports, which is connected to the inverting input port inn of differential output DC voltage monitoring and feedback control unit 21 of resistor R23; the cathode of high-speed diode SBD21 is connected to the emitter of transistor Q22; resistor R... The second port of transistor Q23 is connected to the source of NMOS transistor M23; the collector of transistor Q23 is the second output voltage port mTIAoutn in a pair of differential output voltage ports, which is connected to the first port of resistor R24 ​​and the non-inverting input port inp of the differential output DC voltage monitoring and feedback control unit 21; the base of transistor Q23 is connected to the emitter of transistor Q22; the second port of resistor R24 ​​is connected to the cathode of high-speed diode SBD22; the anode of high-speed diode SBD22 is connected to the cathode of high-speed diode SBD23; high-speed diode SBD2... The anode of transistor 3 is connected to the source of NMOS transistor M23; the emitter of transistor Q23 is connected to the first port of resistor R25 and the drain of NMOS transistor MN22; the second port of resistor R25 is grounded; the source of NMOS transistor MN21 is grounded; the source of NMOS transistor MN22 is grounded; the first output port of differential output DC voltage monitoring and feedback control unit 21 is connected to the input of low-pass filter 21, and the output of low-pass filter 21 is the feedback control voltage VFB1, which is simultaneously connected to the gate of NMOS transistor MN21 and the gate of NMOS transistor MN22. The second output port of the differential output DC voltage monitoring and feedback control unit 21 is connected to the input of the ultra-low bandwidth low-pass filter 22. The output of the ultra-low bandwidth low-pass filter 22, VFB2, is connected to the input of the monitoring and digital feedback control and locking unit 21. The output of the monitoring and digital feedback control and locking unit 21 consists of four digital control voltage signals, VFBreg1, VFBreg2, VFBreg3, and VFBreg4, which are 4-bit digital output voltage signals. These four digital control voltage signals are connected to the gates of the four MOS switches MN211, MN212, MN213, and MN214 inside the digital adjustable regulator 21, respectively.Inside the digital adjustable regulator 21, the two ends of resistor R211 are connected to the source and drain of MOS switch MN211, the two ends of resistor R212 are connected to the source and drain of MOS switch MN212, the two ends of resistor R213 are connected to the source and drain of MOS switch MN213, and the two ends of resistor R214 are connected to the source and drain of MOS switch MN214. The drain of MN211 is connected to the source of MN212, the drain of MN212 is connected to the source of MN213, and the drain of MN213 is connected to the source of MN212. The first port of resistor R211 is simultaneously connected to the source of MN211, the first port of resistor R210, and the source of NMOS transistor MN23. The second port of resistor R210 is grounded. The second port of resistor R214 is simultaneously connected to the drain of MOS switch MN214 and the gate of NMOS transistor MN23. The output terminal VBG of bandgap reference 21 is connected to the input reference voltage port of digital adjustable regulator 21.

[0107] Preferably, such as Figure 3 The high-speed diodes SBD21, SBD22 and SBD23 shown can also be Schottky diodes, or they can be high-speed diodes formed by shorting the base and collector of an NPN transistor, shorting the gate and drain of an NMOS transistor, or other similar structures.

[0108] In this embodiment, transistors Q21 and Q22, resistors R21 and R22, NMOS transistor MN21, and bias current source Ibias21 form the first high-speed inverting amplifier unit; transistor Q23, resistors R24 and R25, NMOS transistor MN22, and high-speed diodes SBD22 and SBD23 form the second high-speed inverting amplifier unit; the first high-speed inverting amplifier unit and feedback resistor Rf work together to convert the high-speed input current signal into a high-speed voltage signal; the high-speed diode SBD21 and resistor R23 function to implement a high-speed non-inverting amplifier unit and provide the first output voltage signal mTIAoutp in a pair of differential output signals; the second high-speed inverting amplifier unit inverts the phase of the output signal of the first high-speed inverting amplifier unit and provides the second output voltage signal mTIAoutn in a pair of differential output signals.

[0109] Understandably, the differential output DC voltage monitoring and feedback control unit 21 in this embodiment has two main functions: First, it compares the difference between the DC quantity of the differential output signal mTIAoutp and the DC quantity of mTIAoutn, and outputs a first feedback signal based on the magnitude of the detected difference between the DC quantities of the differential signals mTIAoutp and mTIAoutn. This feedback signal is then passed through a low-pass filter 21 to obtain a first feedback control voltage signal VFB1, which adjusts the gate voltage of NMOS transistor MN21 and the gate voltage of NMOS transistor MN22, thereby adjusting the current and drain voltage of NMOS transistors MN21 and MN22. This adjustment is then achieved through a first high-speed inverting amplifier unit, a high-speed non-inverting amplifier unit, and a second high-speed inverting amplifier unit to form a... Two negative feedback loops are used for the differential signals mTIAoutp and mTIAoutn (the first negative feedback loop consists of a differential output DC voltage monitoring and feedback control unit 21, a low-pass filter 21, an NMOS transistor MN21, a first high-speed inverting amplifier unit and a feedback resistor Rf, a high-speed non-inverting amplifier unit and a second high-speed inverting amplifier unit; the second negative feedback loop consists of a differential output DC voltage monitoring and feedback control unit 21, a low-pass filter 21, an NMOS transistor MN22, a high-speed non-inverting amplifier unit and a second high-speed inverting amplifier unit), to adjust the DC current of mTIAoutp and mTIAoutn, and ultimately maintain the DC current of mTIAoutp and mTIAoutn in a state of approximately equal value.Secondly, based on the result of detecting and comparing the DC difference between the differential signals mTIAoutp and mTIAoutn, a second feedback signal is output. This feedback signal is then passed through an ultra-low bandwidth low-pass filter 22 to output a feedback control voltage signal VFB2. This is then converted into four digital control voltage signals VFBreg1, VFBreg2, VFBreg3, and VFBreg4 (4-bit digital control voltage signals) by the monitoring and digital feedback control and locking unit 21. Simultaneously, after a period of comparison, the monitoring and digital feedback control and locking unit 21 locks the four digital control voltage signals VFBreg1, VFBreg2, VFBreg3, and VFBreg4 into a fixed state. The four digital control voltage signals VFBreg1, VFBreg2, VFBreg3, and VFBreg4 output by the control and locking unit 21 control the on / off states of the four MOS switches MN211, MN212, MN213, and MN214 inside the digital adjustable voltage regulator 21, thereby adjusting the total resistance of the four resistors R211, R212, R213, and R214 connected in series inside the digital adjustable voltage regulator 21. This, in turn, adjusts the source voltage of the NMOS transistor M23, and further adjusts the DC values ​​of the differential signals mTIAoutp and mTIAoutn, ultimately achieving the goal of maintaining the DC values ​​of the differential signals mTIAoutp and mTIAoutn approximately equal.

[0110] The 3dB bandwidth of the ultra-low bandwidth low-pass filter 22 is less than 10kHz.

[0111] The digital adjustable voltage regulator 21 can output multiple stable DC voltages. The number of stable DC voltages that can be output is determined by the number of digital control voltage signals designed internally. For example, the number corresponding to 4 (4 bit) digital control voltage signals is 2*2*2*2-1=15, which can achieve the purpose of finely adjusting its stable output DC voltage value.

[0112] In one specific embodiment, considering Figure 3 The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier can effectively convert the input current signal IN into a pair of differential output voltage signals mTIAoutp and mTIAoutn. However, a significant difference may exist in the amplitudes of the mTIAoutp and mTIAoutn voltage signals. To address this, a solution is proposed... Figure 4 This diagram illustrates the front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier. It is related to... Figure 3The difference in the front-end circuit structure of the single-ended input differential output burst mode transimpedance amplifier shown is that: a resistor R31, an NMOS transistor MN31, a low-pass filter M23, and a third output port of the differential output DC voltage monitoring and feedback control unit 21 are added; the first port of resistor R31 is connected to the base of transistor Q21 and the source (or drain) of NMOS transistor MN31, and the second port of resistor R31 is connected to the collector of transistor Q21 and the drain (or source) of NMOS transistor MN31; the function of resistor R31 and NMOS transistor MN31 is to form a negative feedback loop in the second high-speed inverting amplifier unit composed of transistor Q23, resistors R24 and R25, high-speed diodes SBD22 and SBD23, and NMOS transistor MN22. The third output port of the differential output DC voltage monitoring and feedback control unit 21 outputs a feedback control voltage VFB3 through a low-pass filter M23. This voltage VFB3 adjusts the resistance value of NMOS transistor MN31 and the resistance value of the parallel unit composed of resistor R31 and NMOS transistor MN31, thereby adjusting the voltage gain of the second high-speed inverting amplifier unit. This, in turn, adjusts the amplitude of the voltage signal at the output terminal mTIAoutn, ultimately achieving the goal of maintaining approximately equal amplitudes for the differential signals mTIAoutp and mTIAoutn. That is, Figure 4 The single-ended input differential output burst mode transimpedance amplifier front-end circuit structure shown can simultaneously maintain the DC quantity of the differential signal mTIAoutp and the DC quantity of mTIAoutn approximately equal, as well as maintain the voltage signal amplitudes of the differential signals mTIAoutp and mTIAoutn approximately equal, thereby achieving the purpose of outputting a fully differential signal.

[0113] like Figure 5 As shown, this embodiment of the invention also provides a transimpedance amplifier circuit structure employing the single-ended input differential output burst mode transimpedance amplifier front-end circuit proposed in this invention, which includes a single-ended input differential output burst mode transimpedance amplifier front-end circuit, a differential amplifier, an output buffer stage, and a DC offset correction circuit. Figure 1 The significant difference between the common transimpedance amplifier circuit structures shown is that the transimpedance amplifier using the single-ended input differential output burst mode transimpedance amplifier front-end circuit proposed in this invention not only eliminates the need for a low-pass filter and a single-ended to differential amplifier, but also enables a fast response to burst signals.

[0114] like Figure 6 As shown in (a), Figure 4 The transimpedance amplifier shown uses Figure 2The diagram shows the simulation results of the front-end circuit of a single-ended input differential output burst mode transimpedance amplifier, with a duration of 1.1µs. Here, / R1 / PLUS is the input current signal of the transimpedance amplifier, which is a burst signal; there is no signal for an initial period, followed by a longer period of random data signal. / I0 / I0 / mTIAoutp (dashed line signal) and / I0 / I0 / mTIAoutn (solid line signal) are a pair of differential output voltage signals from the front-end circuit of the single-ended input differential output burst mode transimpedance amplifier. / OUTP (dashed line signal) and / OUTN (solid line signal) are a pair of differential output voltage signals from the transimpedance amplifier. Figure 6 (a) It can be seen that: / R1 / PLUS has no signal during the initial time, then it is a pseudo-random data signal, and after the pseudo-random data signal ends, it is no signal again; when / R1 / PLUS is in a no-signal state, / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn as well as / OUTP and / OUTN are also in a no-signal state; when / R1 / PLUS changes to a pseudo-random data signal state, / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn as well as / OUTP and / OUTN also quickly change to a pseudo-random data signal state.

[0115] Figure 6 (b) is to Figure 6 The simulation results shown in (a) only show the results for the 0 to 150 ns time period. As can be seen from 6(b), the initial no-signal duration of / R1 / PLUS is about 50 ns; the burst response speeds of / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn as well as / OUTP and / OUTN are very fast (response time is less than the order of ns), and they change in real time following the signal state of / R1 / PLUS; / I0 / I0 / mTIAoutn changes in phase with / R1 / PLUS, and / I0 / I0 / mTIAoutp changes out of phase with / R1 / PLUS.

[0116] Figure 6 (c) is to Figure 6The simulation results shown in (a) only display the results for the period from 950ns to 1.1us. As can be seen from 6(c), the steady-state of the / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn, as well as the / OUTP and / OUTN signals during the period from 950ns to 1.05us is basically the same as the steady-state during the period from 50ns to 150ns. After the pseudo-random data signal ends and / R1 / PLUS enters the no-signal state, the / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn, as well as the / OUTP and / OUTN signals, all quickly follow / R1 / PLUS into the no-signal state (response time is less than the order of ns). This confirms that the process of / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn, as well as / OUTP and / OUTN, changing rapidly with the state of / R1 / PLUS is stable.

[0117] Figure 6 The simulation results also reflect a phenomenon: there is a large difference in the signal amplitudes of / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn. The signal amplitude of / I0 / I0 / mTIAoutp is about 40mV, while the signal amplitude of / I0 / I0 / mTIAoutn is about 200mV.

[0118] like Figure 7 As shown in (a), Figure 5 The transimpedance amplifier shown uses Figure 4 The simulation results of the front-end circuit of the single-ended input differential output burst mode transimpedance amplifier are shown in the figure, with a duration of 1.1us; Figure 7 (b) is to Figure 6 The simulation results shown in (a) only display the results for the 0 to 150 ns time period. Figure 7 From (a) and 7(b), we can see that: Figure 4 The structure shown significantly reduces the signal amplitude of / I0 / I0 / mTIAoutn (solid line signal), decreasing the signal amplitude of / I0 / I0 / mTIAoutn from... Figure 6 The voltage decreased from approximately 200mV to approximately 60mV, reaching a level roughly equivalent to the signal amplitude of / I0 / I0 / mTIAoutp (the dashed line signal). That is, Figure 4 The added negative feedback structure can maintain the voltage amplitudes of the differential output signals / I0 / I0 / mTIAoutp and / I0 / I0 / mTIAoutn approximately equal, thus achieving the purpose of fully differential output.

[0119] In summary, the single-ended input differential output burst-mode transimpedance amplifier front-end circuit proposed in this invention not only innovatively transforms the current single-ended input single-ended output transimpedance amplifier front-end circuit structure into a single-ended input differential output transimpedance amplifier front-end circuit structure, but also possesses fast burst response capability. Furthermore, compared to current transimpedance amplifier structures, the circuit structure employing the single-ended input differential output burst-mode transimpedance amplifier front-end circuit proposed in this invention not only achieves fast burst response capability in its own structure, but its differential output voltages OUTP and OUTN can also rapidly follow the changes in input current / R1 / PLUS in real time, eliminating the need for a matching RESET signal from the OLT optical module. Moreover, it eliminates the need for a low-pass filter circuit and a single-ended to differential converter circuit, simplifying the transimpedance amplifier circuit structure and reducing the power consumption of the transimpedance amplifier.

[0120] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer-readable storage media (or non-transitory media) and communication media (or transient media).

[0121] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0122] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A front-end circuit for a single-ended input differential output burst-mode transimpedance amplifier, characterized in that, It includes: The first high-speed inverting amplifier unit and the feedback resistor Rf are used to convert the high-speed input current signal into a high-speed voltage signal. A high-speed in-phase amplifier unit is connected to the voltage output terminal of the first high-speed in-phase amplifier unit and is used to provide the first output voltage signal in the differential output signal. The second high-speed inverting amplifier unit is used to invert the phase of the output signal of the first high-speed inverting amplifier unit and provide a second output voltage signal in the differential output signal. Differential output DC voltage monitoring and feedback control unit (21) is used to detect the DC quantity and amplitude difference between the first output voltage signal and the second output voltage signal and output a feedback signal accordingly; The feedback signal is used to adjust the DC quantity and voltage amplitude of the first output voltage signal and the second output voltage signal through multiple negative feedback loops so that the DC quantity and voltage amplitude of the first output voltage signal and the second output voltage signal are similar. The first high-speed inverting amplifier unit includes transistor Q (21), transistor Q (22), resistor R (21), resistor R (22), NMOS transistor MN (21) and bias current source Ibias (21). The base of the transistor Q (21) is connected to both the input port IN and the drain of the NMOS transistor MN (22), its emitter is grounded, and its collector is connected to the first port of the resistor R (21) and the base of the transistor Q (22). The emitter of the transistor Q (22) is connected to the second port of the feedback resistor Rf and the current source port of the bias current source Ibias (21), and its collector is connected to the first port of the resistor R (22); the emitter of the transistor Q (22) is the voltage output terminal of the first high-speed inverting amplifier unit. The second port of the resistor R (21) and the second port of the resistor R (22) are both connected to the voltage source VCC1, the first port of the feedback resistor Rf is connected to the input port IN, and the other port of the bias current source Ibias (21) is grounded. The source of the NMOS transistor MN (21) is grounded; The second high-speed inverting amplifier unit includes: Transistor Q (23), resistor R (24), resistor R (25), NMOS transistor MN (22), high-speed diode SBD (22) and high-speed diode SBD (23); The base of the transistor Q (23) is the voltage input terminal of the second high-speed inverting amplifier unit, and it is connected to the voltage output terminal of the first high-speed inverting amplifier unit. The collector of the transistor Q (23) is the second output voltage port mTIAoutn in the differential output voltage port, and is connected to the first port of the resistor R (24) and the non-inverting input port inp of the differential output DC voltage monitoring and feedback control unit (21). The emitter of the transistor Q (23) is connected to the first port of the resistor R (25) and the drain of the NMOS transistor MN (22). The second port of the resistor R (24) is connected to the cathode of the high-speed diode SBD (22); The anode of the high-speed diode SBD (22) is connected to the cathode of the high-speed diode SBD (23); The anode of the high-speed diode SBD (23) is connected to the source of the NMOS transistor M (23); The second port of the resistor R (25) is grounded; The source of the NMOS transistor MN (22) is grounded.

2. The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier as described in claim 1, characterized in that, The high-speed in-phase amplifier unit includes a high-speed diode SBD (21) and a resistor R (23). The anode of the high-speed diode SBD (21) is the first output voltage port mTIAoutp in the differential output voltage port, and is connected to the first port of the resistor R (23) and the inverting input port inn of the differential output DC voltage monitoring and feedback control unit (21); The cathode of the high-speed diode SBD (21) is the voltage input terminal of the high-speed non-inverting amplifier unit, which is connected to the voltage output terminal of the first high-speed inverting amplifier unit. The second port of the resistor R (23) is connected to the source of the NMOS transistor M (23).

3. The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier as described in claim 1, characterized in that, The differential output DC voltage monitoring and feedback control unit (21), together with the low-pass filter, NMOS transistor MN (21), first high-speed inverting amplifier unit, feedback resistor Rf, high-speed non-inverting amplifier unit and second high-speed inverting amplifier unit, form a first negative feedback loop for the first output voltage signal and the second output voltage signal; The differential output DC voltage monitoring and feedback control unit (21), together with the low-pass filter, the NMOS transistor MN (22), the high-speed in-phase amplifier unit and the second high-speed in-phase amplifier unit, form a second negative feedback loop for the first output voltage signal and the second output voltage signal; The first negative feedback loop and the second negative feedback loop are used to adjust the DC values ​​of the first output voltage signal and the second output voltage signal according to the feedback signal so that the DC values ​​of the first output voltage signal and the second output voltage signal are similar.

4. The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier as described in claim 3, characterized in that, It also includes a low-pass filter (21), an NMOS transistor MN (21), and an NMOS transistor MN (22). The first output port of the differential output DC voltage monitoring and feedback control unit (21) is connected to the input of the low-pass filter (21); The output of the low-pass filter (21) is the feedback control voltage VFB1, which is connected to the gate of NMOS transistor MN (21) and the gate of NMOS transistor MN (22).

5. The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier as described in claim 1, characterized in that, The differential output DC voltage monitoring and feedback control unit (21), the ultra-low bandwidth low-pass filter (22), the monitoring and digital feedback control and locking unit (21), and the digital adjustable regulator (21) form a third negative feedback loop for the first output voltage signal and the second output voltage signal. The third negative feedback loop is used to adjust the DC quantity of the first output voltage signal and the second output voltage signal according to the feedback signal so that the DC quantity of the first output voltage signal and the second output voltage signal tends to be the same. The 3dB bandwidth of the ultra-low bandwidth low-pass filter (22) is less than 10kHz; The monitoring and digital feedback control and locking unit (21) is used to monitor the analog input voltage signal and convert the analog input voltage signal into a multi-bit digital output voltage signal according to the detection result; The digitally adjustable regulator (21) finely adjusts its stable output DC voltage value using a multi-bit digital control voltage signal.

6. The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier as described in claim 5, characterized in that, It also includes an ultra-low bandwidth low-pass filter (22), a monitoring and digital feedback control and lockout unit (21), and a digitally adjustable regulator (21). The second output port of the differential output DC voltage monitoring and feedback control unit (21) is connected to the input of the ultra-low bandwidth low-pass filter (22); The output of the ultra-low bandwidth low-pass filter (22) is connected to the analog voltage signal VFB2, which is connected to the input of the monitoring and digital feedback control and locking unit (21). The output of the monitoring and digital feedback control and locking unit (21) consists of four digital control voltage signals VFBreg1, VFBreg2, VFBreg3 and VFBreg4, and the four digital control voltage signals are respectively connected to the gates of the four MOS switches MN (211), MN (212), MN (213) and MN (214) inside the digital adjustable regulator (21).

7. The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier as described in claim 1, characterized in that, The differential output DC voltage monitoring and feedback control unit (21) forms a fourth negative feedback loop in the second high-speed inverting amplifier unit through a low-pass filter, a resistor and an NMOS transistor, and the fourth negative feedback loop is used to adjust the voltage amplitude of the second output voltage signal according to the feedback signal so that the voltage amplitude of the first output voltage signal and the second output voltage signal are similar.

8. The front-end circuit of a single-ended input differential output burst-mode transimpedance amplifier as described in claim 7, characterized in that, It also includes resistor R (31), NMOS transistor MN (31) and low-pass filter M (23); The first port of the resistor R (31) is connected to the base of the transistor Q (21) and the source or drain of the NMOS transistor MN (31), and its second port is connected to the collector of the transistor Q (21) and the drain or source of the NMOS transistor MN (31). The third output port of the differential output DC voltage monitoring and feedback control unit (21) outputs a feedback control voltage VFB3 through the low-pass filter M (23). The feedback control voltage VFB3 is used to adjust the resistance value of the NMOS transistor MN (31) and the resistance value of the parallel unit composed of the resistor R (31) and the NMOS transistor MN (31) so that the voltage amplitude of the first output voltage signal and the second output voltage signal tend to be the same.

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