A narrow pulse based power line time synchronization device

Abstract

The application discloses a kind of power line time synchronization devices based on narrow pulse, by constructing time encoding, then the corresponding control signal of processing end generates to control the output of narrow pulse signal and whether to produce the pulse train loaded with time encoding transmission on power line, finally amplify, isolated and coupled to transmission on power line.Simultaneously, by coupling, isolation, pulse detection obtains the pulse train sent by opposite end.Thus, by sending time and receiving time time count value, the time difference Δt in second can be obtained, the processing end of A end, B end is combined according to the time of opposite end received with oneself time, and the time in second is synchronized, and then combined with time difference Δt to synchronize the time in second.The application designs a kind of new power line transmission time encoding based on narrow pulse, and utilizes high-stable pulse and bidirectional time comparison method to carry out power line time synchronization, and designs a set of hardware system based on this, overcomes the limitation of power line bad channel, and improves the precision of power line time synchronization.

Description

Technical Field

[0001] This invention belongs to the field of time synchronization technology, and more specifically, relates to a device for achieving time synchronization on power lines using high-voltage pulse technology, namely a power line time synchronization device based on narrow pulses. Background Technology

[0002] Time is inextricably linked to human production and daily life, and is one of the most important physical concepts. The development of modern science requires precise measurement of physical quantities, and time is one of the fundamental physical parameters with the highest measurement accuracy in scientific research, engineering technology, and other fields. By utilizing precise time measurement, we can measure other important physical quantities, such as high-precision distance measurement.

[0003] For example, no matter how sophisticated a timekeeping device is, it cannot achieve perfect time synchronization. The problem of time synchronization is to use various technologies and methods to make the "clocks" at several locations keep as consistent as possible. More broadly, the problem of time synchronization is also the problem of time transmission. Time transmission technology has a long history and a wide range of methods. After the invention of radio communication in 1900, the United States, France, and Germany successively developed shortwave radio time synchronization. With the continuous development of technology, wired cables, fiber optic transmission, and satellite time synchronization methods have emerged. Microwave transmission transmits time synchronization signals through the atmosphere, wired cable transmission transmits time synchronization signals through electrical wires, and fiber optic transmission technology transmits time synchronization signals through fiber optic channels.

[0004] 1. Satellite two-way time transfer

[0005] Two-way Satellite Time and Frequency Transfer (TWSTFT) is currently a relatively high-precision long-distance time transfer method. Due to its symmetrical transmission path, propagation delays along the link can be almost completely canceled out. The principle of TWSTFT is as follows: Figure 1 As shown, the two ground observation stations calculate the time difference between the two locations by measuring the time when the other's signal arrives at the local location after being relayed by the communication satellite and the time when the signal is transmitted. Then, by subtracting the clock differences obtained by each station, the clock difference between the two ground observation stations can be obtained.

[0006]

[0007] In the formula, TIC(A) and TIC(B) are the readings of the time counter; A and B are the clock times of the two stations, and d xx To delay the spread.

[0008] Subtracting the two equations and rearranging the terms, we get:

[0009]

[0010] It can be seen that the ionospheric delay and tropospheric delay in the formula can be completely canceled out, as can the delay from satellite relay. Therefore, the TWSTFT method eliminates most of the errors and can achieve very high accuracy. Currently, the accuracy of TWSTFT can reach 500–750 ps, ​​and the stability can reach 200 ps.

[0011] 2. Power line spread spectrum communication synchronization technology

[0012] Power lines, also known as transmission lines, have a wide distribution. In recent years, new direct time synchronization methods have been proposed for some commonly used channels, such as power line networks. This method uses existing power lines as channels to transmit time, eliminating the need for additional channels. The time synchronization equipment only needs to be connected to the power line network to achieve time signal transmission. This method is an excellent choice for situations where building fiber optic networks is inconvenient or where satellite signals cannot provide coverage, offering an effective time synchronization solution for certain application scenarios (such as underground equipment or facilities).

[0013] Spread spectrum communication refers to extending the spectrum of a baseband signal into a very wide frequency band for transmission. The most basic principle is derived from Shannon's theorem: C = ωlog₂(1 + P / N), where C is the transmission rate, ω is the bandwidth, P is the signal power, and N is the noise power. With a constant transmission rate, increasing the bandwidth reduces the required signal-to-noise ratio.

[0014] Based on the method of spectrum spread in spread spectrum communication, existing spread spectrum communication systems can be divided into the following categories, which will be introduced separately below.

[0015] Direct sequence spread spectrum (DSSS) spreads the spectrum by multiplying the transmitted signal with a high-rate spreading code sequence at the transmitter and then despreading the received signal with the same spreading code sequence at the receiver to recover the original information.

[0016] Frequency hopping spread spectrum refers to using a specific code sequence to select the carrier frequency of the transmitted signal. It is a multi-frequency frequency shift keying modulation method, in which the carrier frequency of the frequency hopping spread spectrum system changes continuously. Simple frequency shift keying modulation methods generally only have a few frequencies, such as 2FSK, while a real frequency hopping spread spectrum system can have dozens or even tens of thousands of frequencies depending on the choice of spreading code, thus expanding the spectrum.

[0017] As the name suggests, time-hopping spread spectrum transmits signals discontinuously along the time axis, but rather in a constantly hopping manner. The time axis is divided into many time slots, and each time slot is further divided into many time slices. Not every time slice within a single time slot needs to transmit a signal; whether or not a signal is transmitted is determined by the spreading code. The signal is confined to a very narrow time slice for transmission, resulting in a very short transmission time and a significantly broadened frequency spectrum.

[0018] Wideband linear frequency modulation (LFM) transmitted signals are called LFM signals. Their instantaneous frequency changes linearly over a wide range, resulting in a broad bandwidth. This spread spectrum modulation method is primarily used in radar. Besides the spread spectrum methods mentioned above, various methods can be combined to form hybrid spread spectrum.

[0019] The synchronization technologies described above have the following main problems: While satellite-based time synchronization is widely applicable and technically mature, it cannot be achieved in certain special scenarios, such as locations where satellite signals are unavailable (e.g., underground facilities). Time synchronization using conventional power line carrier communication techniques (such as the power line spread spectrum synchronization technology described above) is limited by the poor channel conditions and methods of power lines, and therefore cannot achieve high accuracy. Summary of the Invention

[0020] The purpose of this invention is to overcome the shortcomings of the prior art and provide a power line time synchronization device based on narrow pulses. This device uses high-voltage pulses and bidirectional time comparison to achieve power line time synchronization, thereby overcoming the limitations of poor power line channels and achieving higher accuracy.

[0021] To achieve the above-mentioned objectives, the present invention provides a narrow-pulse power line time synchronization device, comprising two power system time synchronization devices located at different locations, namely, end A and end B;

[0022] The feature is that each power system time synchronization device includes a processing end, a transmitting end, and a receiving end, wherein:

[0023] The processing end is used to generate control signals with time encoding. The time encoding is one frame per second. Each frame consists of a time slice, and each time slice consists of multiple symbols. The duration of each symbol is 10ms. A pulse in each symbol represents logic "1", and no pulse represents logic "0".

[0024] The time slice includes a frame header, seconds units digit, seconds tens digit, minutes units digit, minutes tens digit, hours units digit, hours tens digit, day units digit, day tens digit, month units digit, month tens digit, year units digit, year tens digit, and a frame trailer. The frame header is marked with 8 code characters "FF" as the start marker, and the frame trailer is marked with 8 code characters "AA" as the end marker. The remaining time slices each contain 4 code characters, and the time encoding order is low-order bits first and high-order bits last.

[0025] The transmitting end consists of a pulse synthesis module, an isolator, and a coupler;

[0026] In the pulse synthesis module, firstly, the pulse generation module generates two completely identical pulse signals, which are then fed into the narrow delay module and the wide delay module for delay, respectively, outputting two completely identical pulse signals except for a very short phase difference. Then, the synthesis circuit generates a narrow pulse signal through the very short phase difference between the two pulses, and the waveform of the pulse is processed and edge compressed by the waveform conditioning module to generate a fast-edge, 10ns narrow pulse signal. Then, the switching module is controlled by the input control signal at the processing terminal, and the output of the narrow pulse signal is controlled to generate a pulse train loaded with time code that is transmitted on the power line. Finally, the amplifier circuit amplifies the amplitude of the pulse train to make it suitable for transmission on the power line, and the amplified pulse train is output to the isolator.

[0027] In the isolator, the pulse train is isolated and then sent to the coupler, where it is coupled to the power line;

[0028] Accordingly, the receiving end consists of a coupler, an isolator, and a pulse detection module;

[0029] The coupler couples the pulse train from the power line at the other end, and after isolation by the isolator, it is sent to the pulse detection module.

[0030] In the pulse detection module, the peak detection module uses capacitor charging to detect peak values. After detecting the peak value (i.e., the pulse of the pulse train), it holds the value. The voltage obtained from the peak detection is sent to the comparison module. The comparison module has a preset threshold. If the voltage exceeds the threshold, it is considered that a pulse has been detected, and a TTL level is output and sent to the FPGA module. Before the next pulse of the pulse train arrives, the capacitor of the peak detection module is discharged, and the voltage obtained from the peak detection is lower than the threshold. The comparison module outputs a 0 level. When the next pulse of the pulse train arrives, the TTL level is output again. The above process is repeated to obtain a pulse train loaded with time encoding.

[0031] The processing unit processes the pulse train loaded with time code to obtain the time code;

[0032] End A and End B respectively transmit pulse trains loaded with their own time codes through their respective processing end, transmitting end, and receiving end, and receive pulse trains loaded with the other end's time codes, and then decode the other end's time.

[0033] Both ends A and B have counters. The counter starts counting when it sends a time-coded pulse train and stops counting when it receives a time-coded pulse train from the other end. This results in a count value T at end A. AB The count value T is obtained at end B. BA Thus, the time difference Δt between end B and end A is obtained:

[0034]

[0035] Where, τ AB Let τ be the propagation delay from point A to point B. BA Let τ be the path propagation delay from point B to point A, and τ be the path propagation delay. AB =τ BA Specific values ​​are ignored;

[0036] τ TB τ RB For the hardware latency of the B-end transmitting and receiving equipment, τ TA τ RA The hardware delays of the transmitting and receiving devices at end A can be obtained through pre-calibration.

[0037] The processing ends at A and B synchronize the second time based on the received time from the other end and their own time, and then synchronize the time within the second by combining the time difference Δt.

[0038] The objective of this invention is achieved as follows.

[0039] This invention relates to a narrow-pulse power line time synchronization device. It constructs a time code, and then the processing end generates corresponding control signals to control whether the narrow pulse signal is output, thus generating a pulse train loaded with the time code to be transmitted on the power line. Finally, the pulse train is amplified, isolated, and coupled onto the power line for transmission. Simultaneously, the pulse train sent from the other end is obtained through coupling, isolation, and pulse detection. Thus, by using the time count values ​​of the sending and receiving times, the time difference Δt within a second can be obtained. The processing ends at points A and B synchronize the second time based on the received time from the other end and their own time, and then synchronize the time within the second based on the time difference Δt. This invention designs a novel narrow-pulse-based power line transmission time code, utilizes highly stable pulses and a bidirectional time comparison method for power line time synchronization, and designs a hardware system based on this, overcoming the limitations of poor power line channel conditions and improving the accuracy of power line time synchronization. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the principle of two-way time transfer via satellite in existing technology;

[0041] Figure 2 This is a schematic block diagram illustrating the principle of a specific embodiment of the power line time synchronization device based on narrow pulses of the present invention;

[0042] Figure 3 yes Figure 2 The diagram shown is a schematic block diagram of one specific implementation of the pulse synthesis module.

[0043] Figure 4 yes Figure 3 The diagram shows a synthesis circuit that synthesizes narrow pulse signals.

[0044] Figure 5 yes Figure 2 The waveform diagrams for each test point in the pulse synthesis module are shown below.

[0045] Figure 6 This is a schematic diagram of the structure of a pulse train, i.e., a code element, loaded with time encoding;

[0046] Figure 7 yes Figure 2 The waveform diagram of a specific example of a pulse train with time encoding output from the pulse synthesis module is shown.

[0047] Figure 8 yes Figure 2 The diagram shows a schematic block diagram of one specific implementation of the pulse detection module.

[0048] Figure 9 yes Figure 2 The waveform diagram of each test point in the pulse detection module is shown below.

[0049] Figure 10 This is a schematic diagram illustrating the principle of obtaining the time difference Δt through bidirectional time comparison. Detailed Implementation

[0050] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0051] Figure 2 This is a schematic block diagram illustrating the principle of a specific embodiment of the power line time synchronization device based on narrow pulses of the present invention.

[0052] In this embodiment, as Figure 2 As shown, the present invention is a power line time synchronization device based on narrow pulses, which includes two power system time synchronization devices located at different locations, namely end A and end B.

[0053] Each power system time synchronization device includes a processing terminal 1, a transmitting terminal 2, a receiving terminal 3, and a counter 4, wherein:

[0054] Processing terminal 1 is used to generate control signals with time encoding. The time encoding is one frame per second. Each frame consists of a time slice, and each time slice consists of multiple symbols. The duration of each symbol is 10ms. A pulse in each symbol represents logic "1", and no pulse represents logic "0".

[0055] The time slice includes a frame header, seconds units digit, seconds tens digit, minutes units digit, minutes tens digit, hours units digit, hours tens digit, day units digit, day tens digit, month units digit, month tens digit, year units digit, year tens digit, and a frame trailer. The frame header is marked with 8 bits "FF" as the start marker, and the frame trailer is marked with 8 bits "AA" as the end marker. The remaining time slices each contain 4 bits, with the least significant bit first and the most significant bit last. There is a blank period after the time slice, containing no data, primarily used to pad the time to 1 second.

[0056] The transmitter 2 consists of a pulse synthesis module 201, an isolator 202, and a coupler 203.

[0057] In the pulse synthesis module 201, such as Figure 3 As shown, firstly, the pulse generation module 201 generates two completely identical pulse signals, which are then fed into the narrow delay module and the wide delay module for delay, respectively. The output consists of two completely identical pulse signals, Signal 1 and Signal 2, except for a very short phase difference, labeled ①. Then, as... Figure 4 As shown, the synthesis circuit generates a narrow pulse signal (marked as ②) through the extremely short phase difference between two pulses, and processes the waveform and compresses the edges of the pulse through the waveform conditioning module to generate a fast-edge, 10ns narrow pulse signal (marked as ③).

[0058] Then, the switching module is controlled by inputting control signals through the processing terminal. By controlling whether the narrow pulse signal is output, a pulse train loaded with time code is generated for transmission on the power line, marked as ④. Finally, the amplifier circuit amplifies the amplitude of the pulse train to make it suitable for transmission on the power line. The amplified pulse train, marked as ⑤, is output to the isolator.

[0059] The waveform diagrams of each test point in the pulse synthesis module are shown below. Figure 5 As shown. In this embodiment, as Figure 6 As shown, a time-coded pulse train is loaded, with a symbol duration of 10ms and a narrow pulse width of 10ns. Figure 7 The time indicated is 11:52:44 on December 14, 2022.

[0060] As shown in Figure 2, in isolator 202, the pulse train is isolated and then sent to coupler 203, which couples it to the power line.

[0061] Accordingly, such as Figure 2 As shown, the receiving end consists of a coupler 301, an isolator 302, and a pulse detection module 303.

[0062] Coupler 301 couples the pulse train from the power line at the other end, and after isolation by isolator 302, it is sent to pulse detection module 303.

[0063] In the pulse detection module 303, such as Figure 8 As shown, the peak detection module uses capacitor charging to detect the peak of the pulse train (marked as ①). After detecting the peak, i.e. the pulse of the pulse train, it is held. The voltage obtained by peak detection (marked as ②) is sent to the comparison module. The comparison module has a preset threshold. If it exceeds the threshold, it is considered that a pulse has been detected, and the TTL level (marked as ③) is output and sent to the FPGA module.

[0064] like Figure 9 As shown, before the next pulse of the pulse train arrives, the capacitor of the peak detection module is discharged, the voltage obtained by peak detection is lower than the threshold, and the comparison module outputs a 0 level. When the next pulse of the pulse train arrives, it outputs a TTL level again. The above process is repeated to obtain a pulse train loaded with time encoding.

[0065] Processing terminal 1 processes the pulse train loaded with time code to obtain the time code;

[0066] like Figure 2 As shown, ends A and B transmit pulse trains loaded with their own time codes through their respective processing end 1, transmitting end 2, and receiving end 3, and receive pulse trains loaded with the other end's time codes, and then decode the other end's time.

[0067] like Figure 2 As shown, both end A and end B have a counter 4. The counter starts counting when it sends a pulse train loaded with time encoding, and stops counting when it receives a pulse train loaded with time encoding from the other end. This results in a count value T at end A. AB The count value T is obtained at end B. BA Thus, the time difference Δt between end B and end A is obtained:

[0068]

[0069] Where, τ AB Let τ be the propagation delay from point A to point B. AB Let τ be the path propagation delay from point A to point B, and τ be the path propagation delay. AB =τ BA Specific numerical values ​​are ignored.

[0070] τ TB τ RB For the hardware latency of the B-end transmitting and receiving equipment, τ TA τ RA The hardware delays of the transmitting and receiving devices at end A can be obtained through pre-calibration.

[0071] In this embodiment, the start counting is defined as starting counting when the rising edge of the first bit of the transmitted frame header is received, and the stop counting is defined as stopping counting when the rising edge of the first bit of the transmitted frame header is received from the other end.

[0072] like Figure 10 As shown, Δt is the time difference between B and A, and the hardware delays of the transmitting and receiving devices at A and B are τ, respectively. TA τ RA and τ TB τ RB The propagation delay from point A to point B is τ. AB The propagation delay from point B to point A is τ. BA Since the paths are the same, only the propagation directions are opposite, τ can be considered as... AB =τ BA This gives us the count value T at terminal A. AB :

[0073] T AB =τ TB +τ BA +τ RA +Δt

[0074] The count value T is obtained at point B. BA :

[0075] T BA =τ TA +τ AB +τ RB -Δt

[0076] Solving the equations simultaneously, we get:

[0077]

[0078] Because the bidirectional propagation paths at both ends A and B are the same, i.e., τ AB =τ BA Furthermore, we obtain:

[0079]

[0080] Finally, processing terminals 1 of terminals A and B synchronize the second time based on the received time from the other end and their own time, and then synchronize the time within the second by combining the time difference Δt.

[0081] This invention uses narrow pulse transmission time coding and bidirectional time comparison method for power line time synchronization, which overcomes the limitations of poor power line channels and improves the accuracy of power line time synchronization.

[0082] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A power line time synchronization device based on narrow pulse, comprising two power system time synchronization devices located at different locations, namely end A and end B; Its features are, Each power system time synchronization device includes a processing end, a transmitting end, and a receiving end, wherein: The processing end is used to generate control signals with time encoding. The time encoding is one frame per second. Each frame consists of a time slice, and each time slice consists of multiple symbols. The duration of each symbol is 10ms. A pulse in each symbol represents logic "1", and no pulse represents logic "0". The time slice includes a frame header, seconds units digit, seconds tens digit, minutes units digit, minutes tens digit, hours units digit, hours tens digit, day units digit, day tens digit, month units digit, month tens digit, year units digit, year tens digit, and a frame trailer. The frame header is marked with 8 code characters "FF" as the start marker, and the frame trailer is marked with 8 code characters "AA" as the end marker. The remaining time slices each contain 4 code characters, and the time encoding order is low-order bits first and high-order bits last. The transmitting end consists of a pulse synthesis module, an isolator, and a coupler; In the pulse synthesis module, firstly, the pulse generation module generates two completely identical pulse signals, which are then fed into the narrow delay module and the wide delay module for delay, respectively, outputting two completely identical pulse signals except for a very short phase difference. Then, the synthesis circuit generates a narrow pulse signal through the very short phase difference between the two pulses, and the waveform of the pulse is processed and edge compressed by the waveform conditioning module to generate a fast-edge, 10ns narrow pulse signal. Then, the switching module is controlled by the input control signal at the processing terminal, and the output of the narrow pulse signal is controlled to generate a pulse train loaded with time code that is transmitted on the power line. Finally, the amplifier circuit amplifies the amplitude of the pulse train to make it suitable for transmission on the power line, and the amplified pulse train is output to the isolator. In the isolator, the pulse train is isolated and then sent to the coupler, where it is coupled to the power line; Accordingly, the receiving end consists of a coupler, an isolator, and a pulse detection module; The coupler couples the pulse train from the power line at the other end, and after isolation by the isolator, it is sent to the pulse detection module. In the pulse detection module, the peak detection module uses capacitor charging to detect peak values. After detecting the peak value (i.e., the pulse of the pulse train), it holds the value. The voltage obtained from the peak detection is sent to the comparison module. The comparison module has a preset threshold. If the voltage exceeds the threshold, it is considered that a pulse has been detected, and a TTL level is output and sent to the FPGA module. Before the next pulse of the pulse train arrives, the capacitor of the peak detection module is discharged, and the voltage obtained from the peak detection is lower than the threshold. The comparison module outputs a 0 level. When the next pulse of the pulse train arrives, the TTL level is output again. The above process is repeated to obtain a pulse train loaded with time encoding. The processing unit processes the pulse train loaded with time code to obtain the time code; End A and End B respectively transmit pulse trains loaded with their own time codes through their respective processing end, transmitting end, and receiving end, and receive pulse trains loaded with the other end's time codes, and then decode the other end's time. Both ends A and B have counters. Each counter starts counting when it sends a time-coded pulse train and stops counting when it receives a time-coded pulse train from the other end. The counting begins when the first rising edge of the first frame header is sent and stops when the first rising edge of the first frame header is received from the other end. This results in a count value T at end A. AB The count value T is obtained at end B. BA Thus, the time difference Δt between end B and end A is obtained: ； Where, τ AB Let τ be the propagation delay from point A to point B. BA Let τ be the path propagation delay from point B to point A, and τ be the path propagation delay. AB =τ BA Specific values ​​are ignored; τ TB τ RB For the hardware latency of the B-end transmitting and receiving equipment, τ TA τ RA The hardware delays of the transmitting and receiving devices at end A can be obtained through pre-calibration. The processing ends at A and B synchronize the second time based on the received time from the other end and their own time, and then synchronize the time within the second by combining the time difference Δt.

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